[U-Boot] [PATCH v2 00/12] Go to common initdram() on 85xx-based boards
This patch series consists of a bunch of cleanups that allow us to use a common initdram() on all of the non-corenet 85xx-based boards. Also, switch to using phys_size_t to represent the size of memory returned.
Most of these patches are just code rearranges or renaming things to get a common scheme in place. There are also lots of cleanups - the various initdram() implementations had a variety of issues that I have hopefully fixed.
This is a large patch series, and I've had to hack on a bunch of different boards that I know nothing about, so I'd appreciate any review commentary. I have tested this on 8572DS and confirmed that the results of a MAKEALL powerpc are the same before and after this series.
Changes from V1: - Removed prints from initdram() as suggested by Peter - Changed spacing of 36-bit DRAM size warning messages to better line up after the removal of the excess prints from initdram() - Switched sdram_init() to be a weak function - renamed sdram_init() to lbc_sdram_init()
Diffstat below.
Cheers, Becky
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 + arch/powerpc/cpu/mpc85xx/cpu.c | 51 ++++++++++++++++ arch/powerpc/cpu/mpc85xx/tlb.c | 6 ++- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 5 +- arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 10 +++ arch/powerpc/include/asm/fsl_ddr_sdram.h | 13 ++++ arch/powerpc/include/asm/fsl_lbc.h | 4 + board/atum8548/atum8548.c | 25 +-------- board/freescale/mpc8536ds/mpc8536ds.c | 21 ------- board/freescale/mpc8540ads/mpc8540ads.c | 56 +----------------- board/freescale/mpc8540ads/tlb.c | 19 ------ board/freescale/mpc8541cds/mpc8541cds.c | 46 +-------------- board/freescale/mpc8544ds/mpc8544ds.c | 17 ------ board/freescale/mpc8548cds/mpc8548cds.c | 41 +------------- board/freescale/mpc8555cds/mpc8555cds.c | 48 +--------------- board/freescale/mpc8560ads/mpc8560ads.c | 56 +----------------- board/freescale/mpc8560ads/tlb.c | 19 ------ board/freescale/mpc8568mds/mpc8568mds.c | 41 +------------- board/freescale/mpc8569mds/mpc8569mds.c | 36 ------------ board/freescale/mpc8572ds/mpc8572ds.c | 19 ------ board/freescale/p1022ds/p1022ds.c | 13 ---- board/freescale/p1_p2_rdb/ddr.c | 15 +----- board/freescale/p2020ds/p2020ds.c | 34 ++--------- board/mpc8540eval/mpc8540eval.c | 52 +--------------- board/pm854/law.c | 5 +- board/pm854/pm854.c | 62 +------------------- board/pm854/tlb.c | 18 +----- board/pm856/law.c | 5 +- board/pm856/pm856.c | 57 +------------------ board/pm856/tlb.c | 18 +----- board/sbc8548/sbc8548.c | 48 +--------------- board/sbc8548/tlb.c | 34 ++++------- board/sbc8560/sbc8560.c | 93 +----------------------------- board/socrates/sdram.c | 15 +----- board/stx/stxgp3/stxgp3.c | 32 ---------- board/stx/stxssa/stxssa.c | 33 ----------- board/tqc/tqm85xx/sdram.c | 70 +++++++---------------- board/tqc/tqm85xx/tlb.c | 47 --------------- board/xes/common/Makefile | 2 - board/xes/common/fsl_8xxx_ddr.c | 46 --------------- board/xes/xpedite517x/xpedite517x.c | 13 ++++ doc/README.mpc85xxads | 4 +- include/configs/MPC8536DS.h | 1 - include/configs/MPC8540EVAL.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 7 -- include/configs/MPC8572DS.h | 1 - include/configs/P1_P2_RDB.h | 1 - include/configs/PM854.h | 8 +-- include/configs/PM856.h | 8 +-- include/configs/SBC8540.h | 2 +- include/configs/TQM85xx.h | 6 ++- include/configs/sbc8560.h | 2 +- include/configs/stxgp3.h | 2 +- include/configs/stxssa.h | 1 - 56 files changed, 186 insertions(+), 1110 deletions(-)
Modeled after the MPC8540DS code; this will allow us to use a common initdram() once that is available. There should be no functional change.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/mpc8540eval/mpc8540eval.c | 64 +++++++++++++++++++++----------------- 1 files changed, 35 insertions(+), 29 deletions(-)
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 054d644..f1ab360 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -64,41 +64,15 @@ int checkboard (void) return (0); }
-phys_size_t initdram (int board_type) +void sdram_init(void) { - long dram_size = 0; - -#if !defined(CONFIG_RAM_AS_FLASH) +#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; -#endif -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif
-#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0;
- /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - return dram_size; -#endif - -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ get_sys_info(&sysinfo); /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) { @@ -132,6 +106,38 @@ phys_size_t initdram (int board_type) lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("sync"); #endif +} + +phys_size_t initdram(int board_type) +{ + long dram_size = 0; + +#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + +#if defined(CONFIG_DDR_DLL) + uint temp_ddrdll = 0; + + /* Work around to stabilize DDR DLL */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + dram_size = fixed_sdram(); +#endif + +#if defined(CONFIG_SYS_RAMBOOT) + return dram_size; +#endif + + sdram_init();
#if defined(CONFIG_DDR_ECC) {
Also, change this code to use phys_size_t instead of long int. Using common naming for this function will enable us to use the common initdram() for 85xx going forward. Other than the type change, this is just a code rearrange.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/tqc/tqm85xx/sdram.c | 37 +++++++++++++++++++++++-------------- 1 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 503c5e5..260cd1c 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -65,6 +65,7 @@ sdram_conf_t ddr_cs_conf[] = { #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
int cas_latency (void); +static phys_size_t sdram_setup(int);
/* * Autodetect onboard DDR SDRAM on 85xx platforms @@ -73,7 +74,26 @@ int cas_latency (void); * so this should be extended for other future boards * using this routine! */ -long int sdram_setup (int casl) +phys_size_t fixed_sdram(void) +{ + int casl = 0; + phys_size_t dram_size = 0; + + casl = cas_latency(); + dram_size = sdram_setup(casl); + if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { + /* + * Try again with default CAS latency + */ + printf("Problem with CAS lantency, using default CL %d/10!\n", + CONFIG_DDR_DEFAULT_CL); + dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); + puts(" "); + } + return dram_size; +} + +static phys_size_t sdram_setup(int casl) { int i; volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); @@ -376,8 +396,7 @@ long int sdram_setup (int casl)
phys_size_t initdram (int board_type) { - long dram_size = 0; - int casl; + phys_size_t dram_size = 0;
#if defined(CONFIG_DDR_DLL) /* @@ -407,17 +426,7 @@ phys_size_t initdram (int board_type) } #endif
- casl = cas_latency (); - dram_size = sdram_setup (casl); - if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { - /* - * Try again with default CAS latency - */ - printf ("Problem with CAS lantency, using default CL %d/10!\n", - CONFIG_DDR_DEFAULT_CL); - dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL); - puts (" "); - } + dram_size = fixed_sdram();
return dram_size; }
Some platforms might want to override the default wimge=0 for DDR. Add CONFIG_DDR_TLB_WIMGE for those platforms to use. This will initially only be used by TQM85xx, but could be useful for other boards or testing going forward.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/tlb.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index e3a71ae..513aaaa 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -250,10 +250,14 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { int i; unsigned int tlb_size; + unsigned int wimge = 0; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; u64 size, memsize = (u64)memsize_in_meg << 20;
+#ifdef CONFIG_DDR_TLB_WIMGE + wimge = CONFIG_DDR_TLB_WIMGE; +#endif size = min(memsize, CONFIG_MAX_MEM_MAPPED);
/* Convert (4^max) kB to (2^max) bytes */ @@ -277,7 +281,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) tlb_size = (camsize - 10) / 2;
set_tlb(1, ram_tlb_address, p_addr, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, wimge, 0, ram_tlb_index, tlb_size, 1);
size -= 1ULL << camsize;
This will help us go to a fixed initdram() for all 85xx boards going forward. sdram_setup() had an argument that it didn't need, since the value was #defined.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/socrates/sdram.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 029ba02..ef897b2 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -39,7 +39,7 @@ * so this should be extended for other future boards * using this routine! */ -long int sdram_setup(int casl) +long int fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -85,7 +85,7 @@ phys_size_t initdram (int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else - dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); + dram_size = fixed_sdram(); #endif return dram_size; }
This isn't used - delete it.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- include/configs/MPC8569MDS.h | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9620fd0..e64277e 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -263,12 +263,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #endif
-/* - * SDRAM on the LocalBus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
As far as I can tell, this board doesn't actually configure the LBC for SDRAM. I've renamed this to avoid confusion (and to make the initdram() cleanup easier later.)
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/pm854/law.c | 5 ++--- board/pm854/tlb.c | 4 ++-- include/configs/PM854.h | 6 +----- 3 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/board/pm854/law.c b/board/pm854/law.c index ac21d7a..bea9259 100644 --- a/board/pm854/law.c +++ b/board/pm854/law.c @@ -35,7 +35,7 @@ * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf000_0000 0xf7ff_ffff LBC 128M * 0xf800_0000 0xf80f_ffff BCSR 1M * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M * @@ -49,8 +49,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index 5e74e2d..dadb75c 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -93,9 +93,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM + * 0xf000_0000 64M LBC */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1),
diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 1e2089f..39283b2 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -123,11 +123,7 @@ #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
-/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ +#define CONFIG_SYS_LBC_BASE 0xf0000000 /* Localbus */
#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */ #define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */
This board does not actually configure anything for SDRAM - change the name to avoid confusion and make it easier to go to a common initdram going forward.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/pm856/law.c | 5 ++--- board/pm856/tlb.c | 4 ++-- include/configs/PM856.h | 6 +----- 3 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/board/pm856/law.c b/board/pm856/law.c index ac21d7a..bea9259 100644 --- a/board/pm856/law.c +++ b/board/pm856/law.c @@ -35,7 +35,7 @@ * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf000_0000 0xf7ff_ffff LBC 128M * 0xf800_0000 0xf80f_ffff BCSR 1M * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M * @@ -49,8 +49,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index 5e74e2d..dadb75c 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -93,9 +93,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM + * 0xf000_0000 64M LBC */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1),
diff --git a/include/configs/PM856.h b/include/configs/PM856.h index d3e8f41..dbce6c4 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -125,11 +125,7 @@ #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
-/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ +#define CONFIG_SYS_LBC_BASE 0xf0000000 /* Localbus */
#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ #define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */
Neither of these parts should have the erratum this is meant to work around. Delete it.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - 2 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 281918b..7817fba 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -82,7 +82,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index e64277e..2395cb2 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -122,7 +122,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c
The ATUM8548 board didn't appear to set up any tlbs in the fixed_sdram case; this patch fixes that.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/cpu.c | 51 ++++++++++++++++ arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 10 +++ arch/powerpc/include/asm/fsl_ddr_sdram.h | 13 ++++ arch/powerpc/include/asm/fsl_lbc.h | 4 + board/atum8548/atum8548.c | 25 +-------- board/freescale/mpc8536ds/mpc8536ds.c | 21 ------- board/freescale/mpc8540ads/mpc8540ads.c | 52 +---------------- board/freescale/mpc8540ads/tlb.c | 19 ------ board/freescale/mpc8541cds/mpc8541cds.c | 43 -------------- board/freescale/mpc8544ds/mpc8544ds.c | 17 ------ board/freescale/mpc8548cds/mpc8548cds.c | 38 ------------ board/freescale/mpc8555cds/mpc8555cds.c | 45 -------------- board/freescale/mpc8560ads/mpc8560ads.c | 52 +---------------- board/freescale/mpc8560ads/tlb.c | 19 ------ board/freescale/mpc8568mds/mpc8568mds.c | 38 ------------ board/freescale/mpc8569mds/mpc8569mds.c | 36 ------------ board/freescale/mpc8572ds/mpc8572ds.c | 19 ------ board/freescale/p1022ds/p1022ds.c | 13 ---- board/freescale/p1_p2_rdb/ddr.c | 15 +----- board/freescale/p2020ds/p2020ds.c | 34 ++--------- board/mpc8540eval/mpc8540eval.c | 52 +---------------- board/pm854/pm854.c | 62 +------------------- board/pm854/tlb.c | 14 ----- board/pm856/pm856.c | 57 +------------------ board/pm856/tlb.c | 14 ----- board/sbc8548/sbc8548.c | 45 +-------------- board/sbc8548/tlb.c | 34 ++++------- board/sbc8560/sbc8560.c | 93 +----------------------------- board/socrates/sdram.c | 15 +----- board/stx/stxgp3/stxgp3.c | 32 ---------- board/stx/stxssa/stxssa.c | 33 ----------- board/tqc/tqm85xx/sdram.c | 37 ------------ board/tqc/tqm85xx/tlb.c | 47 --------------- board/xes/common/Makefile | 2 - board/xes/common/fsl_8xxx_ddr.c | 46 --------------- board/xes/xpedite517x/xpedite517x.c | 13 ++++ include/configs/TQM85xx.h | 4 + 37 files changed, 124 insertions(+), 1040 deletions(-) delete mode 100644 board/xes/common/fsl_8xxx_ddr.c
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index fc5d951..b58a1a7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -34,6 +34,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include <asm/fsl_lbc.h> #include <post.h> #include <asm/processor.h> #include <asm/fsl_ddr_sdram.h> @@ -286,6 +287,56 @@ void mpc85xx_reginfo(void) print_lbc_regs(); }
+/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + +#if defined(CONFIG_DDR_DLL) + { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int x = 10; + unsigned int i; + + /* + * Work around to stabilize DDR DLL + */ + out_be32(&gur->ddrdllcr, 0x81000000); + asm("sync;isync;msync"); + udelay(200); + while (in_be32(&gur->ddrdllcr) != 0x81000100) { + setbits_be32(&gur->devdisr, 0x00010000); + for (i = 0; i < x; i++) + ; + clrbits_be32(&gur->devdisr, 0x00010000); + x++; + } + } +#endif + +#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) + dram_size = fsl_ddr_sdram(); +#else + dram_size = fixed_sdram(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* Some boards also have sdram on the lbc */ + sdram_init(); + + return dram_size; +} +#endif + #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index fcef40c..10fcd24 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -9,6 +9,16 @@ #include <common.h> #include <asm/fsl_lbc.h>
+#ifdef CONFIG_MPC85xx +/* Boards should provide their own version of this if they use lbc sdram */ +void __sdram_init(void) +{ + /* Do nothing */ +} +void sdram_init(void) __attribute__((weak, alias("__sdram_init"))); +#endif + + void print_lbc_regs(void) { int i; diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 17d4b31..8ceae18 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -214,6 +214,19 @@ typedef struct memctl_options_s {
extern phys_size_t fsl_ddr_sdram(void);
+/* + * The 85xx boards have a common prototype for fixed_sdram so put the + * declaration here. + */ +#ifdef CONFIG_MPC85xx +extern phys_size_t fixed_sdram(void); +#endif + +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + + typedef struct fixed_ddr_parm{ int min_freq; int max_freq; diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 82d24ab..fcf3371 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -16,6 +16,10 @@ #include <config.h> #include <common.h>
+#ifdef CONFIG_MPC85xx +void sdram_init(void); +#endif + /* BR - Base Registers */ #define BR0 0x5000 /* Register offset to immr */ diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 9403e4b..d719292 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -37,8 +37,6 @@ #include <libfdt.h> #include <fdt_support.h>
-long int fixed_sdram(void); - int board_early_init_f (void) { return 0; @@ -67,7 +65,7 @@ int checkboard (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -96,27 +94,6 @@ long int fixed_sdram (void) } #endif /* !defined(CONFIG_SPD_EEPROM) */
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_SPD_EEPROM) - puts("fsl_ddr_sdram\n"); - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - puts("fixed_sdram\n"); - dram_size = fixed_sdram (); -#endif - - puts(" DDR: "); - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram(void) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index cf92ba1..ee5b668 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -42,8 +42,6 @@
#include "../common/sgmii_riser.h"
-phys_size_t fixed_sdram(void); - int board_early_init_f (void) { #ifdef CONFIG_MMC @@ -98,25 +96,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #if !defined(CONFIG_SPD_EEPROM) /* * Fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index d354a26..deab811 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -39,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
int checkboard (void) { @@ -61,54 +59,6 @@ int checkboard (void) return 0; }
- -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* - * Work around to stabilize DDR DLL - */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * Initialize SDRAM. - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -232,7 +182,7 @@ sdram_init(void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index a9925d5..adcc0ad 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_64M, 1), -#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 59ec604..59df2bd 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -42,7 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void);
/* * I/O Port configuration table @@ -242,48 +241,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 31c3fad..35d81db 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -67,23 +67,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 14c902c..230cbd1 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -41,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void); -void sdram_init(void);
int checkboard (void) { @@ -74,43 +73,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index edaba26..5fe7f13 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -40,7 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void);
/* * I/O Port configuration table @@ -240,50 +239,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 1761431..38f59d1 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -44,8 +44,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
/* @@ -266,54 +264,6 @@ int checkboard (void) return 0; }
- -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* - * Work around to stabilize DDR DLL - */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * Initialize SDRAM. - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -437,7 +387,7 @@ sdram_init(void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index a9925d5..adcc0ad 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_64M, 1), -#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index d74fcac..ee4c807 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -100,7 +100,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { };
void local_bus_init(void); -void sdram_init(void);
int board_early_init_f (void) { @@ -137,43 +136,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index dc0884e..12a417c 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -44,8 +44,6 @@ #include "../common/pq-mds-pib.h" #endif
-phys_size_t fixed_sdram(void); - const qe_iop_conf_t qe_iop_conf_tab[] = { /* QE_MUX_MDC */ {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ @@ -244,40 +242,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - volatile ccsr_gur_t *gur = - (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - out_be32(&gur->ddrdllcr, 0x81000000); - udelay(200); -#endif - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 120f35c..796aacf 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -38,8 +38,6 @@
#include "../common/sgmii_riser.h"
-long int fixed_sdram(void); - int checkboard (void) { u8 vboot; @@ -73,23 +71,6 @@ int checkboard (void) return 0; }
-phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -}
#if !defined(CONFIG_SPD_EEPROM) /* diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 7cb549b..e3e8300 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -76,19 +76,6 @@ int checkboard(void) return 0; }
-phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing....\n"); - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000; - - puts(" DDR: "); - return dram_size; -} - #define CONFIG_TFP410_I2C_ADDR 0x38
/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 15b46b0..e54fde2 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -239,19 +239,6 @@ phys_size_t fixed_sdram (void)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1); return ddr_size; } - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - dram_size = fixed_sdram(); - set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts("DDR: "); - return dram_size; -} diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index b05ef98..7ad8544 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -43,8 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t fixed_sdram(void); - int checkboard(void) { u8 sw; @@ -69,31 +67,6 @@ int checkboard(void) return 0; }
-phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - -#ifdef CONFIG_DDR_SPD - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - dram_size, - LAW_TRGT_IF_DDR) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - }; -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #if !defined(CONFIG_DDR_SPD) /* * Fixed sdram init -- doesn't use serial presence detect. @@ -169,6 +142,13 @@ phys_size_t fixed_sdram(void) udelay(500); #endif
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE * 1024 * 1024, + LAW_TRGT_IF_DDR) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index f1ab360..63a0035 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -31,8 +31,6 @@ #include <asm/fsl_ddr_sdram.h> #include <spd_sdram.h>
-long int fixed_sdram (void); - int board_pre_init (void) { #if defined(CONFIG_PCI) @@ -108,54 +106,6 @@ void sdram_init(void) #endif }
-phys_size_t initdram(int board_type) -{ - long dram_size = 0; - -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif - -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - return dram_size; -#endif - - sdram_init(); - -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); - - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } -#endif - - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { @@ -194,7 +144,7 @@ int testdram (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 0b8ea81..bbaf4fd 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -34,14 +34,7 @@ #include <asm/fsl_ddr_sdram.h> #include <spd_sdram.h>
-#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void); -
int board_early_init_f (void) { @@ -73,59 +66,6 @@ int checkboard (void) return 0; }
- -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) - { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; i<x; i++) - ; - gur->devdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_DDR_ECC) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -225,7 +165,7 @@ int testdram (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index dadb75c..482eb38 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -98,20 +98,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_256M, 1), -#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 4e059b0..3791216 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -41,7 +41,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -long int fixed_sdram(void);
/* * I/O Port configuration table @@ -228,60 +227,6 @@ int checkboard (void) }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) - { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; i<x; i++) - ; - gur->devdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_DDR_ECC) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -380,7 +325,7 @@ int testdram (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index dadb75c..482eb38 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -98,20 +98,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_256M, 1), -#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 272428f..2d24890 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -42,8 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram (void);
int board_early_init_f (void) { @@ -68,47 +66,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - out_be32(&gur->ddrdllcr, 0x81000000); - asm("sync;isync;msync"); - udelay(200); - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ @@ -267,7 +224,7 @@ testdram(void) * fixed_sdram init -- doesn't use serial presence detect. * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 38bdeb3..bb4c052 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -65,44 +65,34 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 1, BOOKE_PAGESZ_1G, 1),
/* - * TLB 2: 256M Cacheable, non-guarded - * 0x0 256M DDR SDRAM - */ -#if !defined(CONFIG_SPD_EEPROM) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 2, BOOKE_PAGESZ_256M, 1), -#endif - - /* - * TLB 3: 64M Non-cacheable, guarded + * TLB 2: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR * 0xe2000000 8M PCI1 IO * 0xe2800000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_64M, 1), + 0, 2, BOOKE_PAGESZ_64M, 1),
/* - * TLB 4: 64M Cacheable, non-guarded + * TLB 3: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 4, BOOKE_PAGESZ_64M, 1), + 0, 3, BOOKE_PAGESZ_64M, 1),
/* - * TLB 5: 64M Cacheable, non-guarded + * TLB 4: 64M Cacheable, non-guarded * 0xf4000000 64M LBC SDRAM Second half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_64M, 1), + 0, 4, BOOKE_PAGESZ_64M, 1),
/* - * TLB 6: 16M Cacheable, non-guarded + * TLB 5: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -110,24 +100,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), + 0, 5, BOOKE_PAGESZ_16M, 1),
/* - * TLB 7: 4M Non-cacheable, guarded + * TLB 6: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_4M, 1), + 0, 6, BOOKE_PAGESZ_4M, 1),
/* - * TLB 8: 4M Non-cacheable, guarded + * TLB 7: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 7, BOOKE_PAGESZ_4M, 1),
};
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 77abde5..53278d3 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -38,8 +38,6 @@ #include <libfdt.h> #include <fdt_support.h>
-long int fixed_sdram (void); - /* * I/O Port configuration table * @@ -263,95 +261,6 @@ int checkboard (void) }
-phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - sys_info_t sysinfo; - uint temp_lbcdll = 0; -#endif -#endif /* 0 */ -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */ - get_sys_info(&sysinfo); - /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; - } else { -#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */ - lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */ -#endif - lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; - udelay(200); - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; - asm("sync;isync;msync"); - } - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */ - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; - asm("sync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - asm("sync"); - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("sync"); -#endif -#endif - -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); - - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } -#endif - - return dram_size; -} - - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { @@ -390,7 +299,7 @@ int testdram (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) {
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index ef897b2..c8235f4 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -39,7 +39,7 @@ * so this should be extended for other future boards * using this routine! */ -long int fixed_sdram(void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -77,19 +77,6 @@ long int fixed_sdram(void) } #endif
-phys_size_t initdram (int board_type) -{ - long dram_size = 0; -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index 25d5211..63068a5 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -40,8 +40,6 @@ #include <spd_sdram.h> #include <miiphy.h>
-long int fixed_sdram (void); - /* * I/O Port configuration table * @@ -277,36 +275,6 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); }
-phys_size_t -initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) - /* Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - return dram_size; -} -
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 1e0acab..a630cc8 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -41,8 +41,6 @@ #include <miiphy.h> #include <netdev.h>
-long int fixed_sdram (void); - /* * I/O Port configuration table * @@ -294,37 +292,6 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); }
-phys_size_t -initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) - /* Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - return dram_size; -} - - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 260cd1c..b2d3185 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -394,43 +394,6 @@ static phys_size_t sdram_setup(int casl) return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; }
-phys_size_t initdram (int board_type) -{ - phys_size_t dram_size = 0; - -#if defined(CONFIG_DDR_DLL) - /* - * This DLL-Override only used on TQM8540 and TQM8560 - */ - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int i, x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm ("sync; isync; msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) { - gur->devdisr = gur->devdisr | 0x00010000; - asm ("sync; isync; msync"); - for (i = 0; i < x; i++) - ; - gur->devdisr = gur->devdisr & 0xfff7ffff; - asm ("sync; isync; msync"); - x++; - } - } -#endif - - dram_size = fixed_sdram(); - - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 75dd348..f9f8cc9 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -120,36 +120,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), - -#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE) - /* - * TLB 7+8: 2G DDR, cache enabled - * 0x00000000 2G DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_1G, 1), - - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1), -#else - /* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), -#endif #ifdef CONFIG_PCIE1 /* * TLB 9: 16M Non-cacheable, guarded @@ -228,23 +198,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 7, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 8+9: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 9, BOOKE_PAGESZ_256M, 1), - #ifdef CONFIG_PCIE1 /* * TLB 10: 16M Non-cacheable, guarded diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 7604f62..39d105f 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -33,8 +33,6 @@ COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o -COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o -COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_ddr.c b/board/xes/common/fsl_8xxx_ddr.c deleted file mode 100644 index 81ee70d..0000000 --- a/board/xes/common/fsl_8xxx_ddr.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/mmu.h> - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = fsl_ddr_sdram(); - -#ifdef CONFIG_MPC85xx - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Initialize and enable DDR ECC */ - ddr_enable_ecc(dram_size); -#endif - - return dram_size; -} diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index 0f7fa6c..572a908 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -22,6 +22,7 @@
#include <common.h> #include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> #include <asm/mmu.h> #include <asm/io.h> #include <fdt_support.h> @@ -71,6 +72,18 @@ int board_early_init_r(void) return 0; }
+phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = fsl_ddr_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Initialize and enable DDR ECC */ + ddr_enable_ecc(dram_size); +#endif + + return dram_size; +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 890d6d9..d8f43d7 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -147,6 +147,10 @@ * DDR Setup */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#if defined(CONFIG_TQM_BIGFLASH) || \ + (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE)) +#define CONFIG_DDR_TLB_WIMGE (MAS2_I | MAS2_G) +#endif #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_TQM8548_AG #define CONFIG_VERY_BIG_RAM
This config option is for an erratum workaround; rename it to be more clear. Also, drop it from config files don't need it and were undefining it.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- doc/README.mpc85xxads | 4 ++-- include/configs/MPC8536DS.h | 1 - include/configs/MPC8540EVAL.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8572DS.h | 1 - include/configs/P1_P2_RDB.h | 1 - include/configs/PM854.h | 2 +- include/configs/PM856.h | 2 +- include/configs/SBC8540.h | 2 +- include/configs/TQM85xx.h | 2 +- include/configs/sbc8560.h | 2 +- include/configs/stxgp3.h | 2 +- include/configs/stxssa.h | 1 - 15 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index d73f3d7..2d32532 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -47,6 +47,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) + puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); +#endif return 0; }
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index b58a1a7..38ff234 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -293,7 +293,7 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size = 0;
-#if defined(CONFIG_DDR_DLL) +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); unsigned int x = 10; diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index 046f981..d059a97 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -144,8 +144,8 @@ Updated 13-July-2004 Jon Loeliger also manual config the DDR after undef this definition. CONFIG_DDR_ECC only for ECC DDR module - CONFIG_DDR_DLL DLL fix on some ADS boards needed for more - stability. + CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN DLL fix on some ADS boards needed + for more stability. CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0.
Other than the above definitions, the rest in the config files are diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 5c5be0c..b644ae1 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -145,7 +145,6 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#undef CONFIG_DDR_DLL
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index a968949..073241b 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -122,7 +122,7 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b221a5c..e5ac3a9 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -89,7 +89,7 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 1ee95ae..708f05b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -99,7 +99,6 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#undef CONFIG_DDR_DLL
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index a21afb7..7edbd36 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -146,7 +146,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_DLL
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 39283b2..559dcfa 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -96,7 +96,7 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_FSL_DMA /* use DMA to init DDR ECC */
diff --git a/include/configs/PM856.h b/include/configs/PM856.h index dbce6c4..5727ec8 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -98,7 +98,7 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_FSL_DMA /* use DMA to init DDR ECC */
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index fd9bacc..72559c0 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -118,7 +118,7 @@ #undef CONFIG_DDR_SPD
#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #endif
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d8f43d7..1368a48 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -162,7 +162,7 @@
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) /* TQM8540 & 8560 need DLL-override */ -#define CONFIG_DDR_DLL /* DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 101c5d9..435b148 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -116,7 +116,7 @@ #undef CONFIG_DDR_SPD
#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #endif
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index c2497ad..fc3881d 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -123,7 +123,7 @@ #undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 996120a..d5dd94f 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -135,7 +135,6 @@ #undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
sdram_init() is used to initialize sdram on the lbc. Rename it accordingly.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 4 ++-- arch/powerpc/include/asm/fsl_lbc.h | 2 +- board/freescale/mpc8540ads/mpc8540ads.c | 4 +--- board/freescale/mpc8541cds/mpc8541cds.c | 3 +-- board/freescale/mpc8548cds/mpc8548cds.c | 3 +-- board/freescale/mpc8555cds/mpc8555cds.c | 3 +-- board/freescale/mpc8560ads/mpc8560ads.c | 4 +--- board/freescale/mpc8568mds/mpc8568mds.c | 3 +-- board/sbc8548/sbc8548.c | 3 +-- 10 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 38ff234..8126ef0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -331,7 +331,7 @@ phys_size_t initdram(int board_type) #endif
/* Some boards also have sdram on the lbc */ - sdram_init(); + lbc_sdram_init();
return dram_size; } diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 10fcd24..6f401e7 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -11,11 +11,11 @@
#ifdef CONFIG_MPC85xx /* Boards should provide their own version of this if they use lbc sdram */ -void __sdram_init(void) +void __lbc_sdram_init(void) { /* Do nothing */ } -void sdram_init(void) __attribute__((weak, alias("__sdram_init"))); +void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init"))); #endif
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index fcf3371..c504732 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -17,7 +17,7 @@ #include <common.h>
#ifdef CONFIG_MPC85xx -void sdram_init(void); +void lbc_sdram_init(void); #endif
/* BR - Base Registers diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index deab811..9eeb134 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -122,9 +122,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ - -void -sdram_init(void) +void lbc_sdram_init(void) { volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 59df2bd..3ee666f 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -291,8 +291,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ -void -sdram_init(void) +void lbc_sdram_init(void) { #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 230cbd1..51c59df 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -110,8 +110,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ -void -sdram_init(void) +void lbc_sdram_init(void) { #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 5fe7f13..02df6ae 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -289,8 +289,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ -void -sdram_init(void) +void lbc_sdram_init(void) { #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 38f59d1..0a87d62 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -327,9 +327,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ - -void -sdram_init(void) +void lbc_sdram_init(void) { volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index ee4c807..490bb44 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -170,8 +170,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ -void -sdram_init(void) +void lbc_sdram_init(void) { #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 2d24890..b729eb4 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -103,8 +103,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ -void -sdram_init(void) +void lbc_sdram_init(void) { #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
Add spaces to cause the informational prints to line up with the ones from init_func_ram() in board.c. Output now looks like this:
.... DRAM: Detected 4096 MB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT 2 GiB (DDR2, 64-bit, CL=5, ECC off) ....
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 6d582e9..e3888ff 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -469,8 +469,9 @@ phys_size_t fsl_ddr_sdram(void) /* Check for 4G or more. Bad. */ if (total_memory >= (1ull << 32)) { printf("Detected %lld MB of memory\n", total_memory >> 20); - printf("This U-Boot only supports < 4G of DDR\n"); - printf("You could rebuild it with CONFIG_PHYS_64BIT\n"); + printf(" This U-Boot only supports < 4G of DDR\n"); + printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); + printf(" "); /* re-align to match init_func_ram print */ total_memory = CONFIG_MAX_MEM_MAPPED; } #endif
On Mon, Dec 13, 2010 at 4:06 PM, Becky Bruce beckyb@kernel.crashing.org wrote:
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Â Most of the initdram() functions were identical, with 2 common differences:
- DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. Â I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner.
- Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale errata document. Â It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. Â This seems bad.
Having #1 and #2 each as standalone commits might have been useful as extra bisection points, in the event that anyone runs into problems -- but I suspect that is a lot of respin work, and hopefully Things Just Work for most people.
The only other thing I noticed was that...
+/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +phys_size_t initdram(int board_type) +{
- phys_size_t dram_size = 0;
+#if defined(CONFIG_DDR_DLL)
- {
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- unsigned int x = 10;
- unsigned int i;
- /*
- * Work around to stabilize DDR DLL
- */
- out_be32(&gur->ddrdllcr, 0x81000000);
- asm("sync;isync;msync");
- udelay(200);
- while (in_be32(&gur->ddrdllcr) != 0x81000100) {
- setbits_be32(&gur->devdisr, 0x00010000);
- for (i = 0; i < x; i++)
- ;
- clrbits_be32(&gur->devdisr, 0x00010000);
- x++;
- }
- }
+#endif
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
- dram_size = fsl_ddr_sdram();
+#else
- dram_size = fixed_sdram();
+#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
+#endif
...right here, the 8540EVAL board bailed out if RAMBOOT was set, thus bypassing sdram_init. So this won't strictly match the old behaviour on at least that board. Maybe it makes sense to just gut the rest of the RAMBOOT code (if any) from boards that were doing this, since I believe it isn't really a globally supported (or at least encouraged) u-boot feature?
I'm not anywhere near the office at the moment, but later in the week I'll see if I can find a board (or two?) to test on.
Paul.
- /* Some boards also have sdram on the lbc */
- sdram_init();
- return dram_size;
+} +#endif
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index fcef40c..10fcd24 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -9,6 +9,16 @@ Â #include <common.h> Â #include <asm/fsl_lbc.h>
+#ifdef CONFIG_MPC85xx +/* Boards should provide their own version of this if they use lbc sdram */ +void __sdram_init(void) +{
- /* Do nothing */
+} +void sdram_init(void) __attribute__((weak, alias("__sdram_init"))); +#endif
void print_lbc_regs(void) Â { Â Â Â Â int i; diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 17d4b31..8ceae18 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -214,6 +214,19 @@ typedef struct memctl_options_s {
extern phys_size_t fsl_ddr_sdram(void);
+/*
- The 85xx boards have a common prototype for fixed_sdram so put the
- declaration here.
- */
+#ifdef CONFIG_MPC85xx +extern phys_size_t fixed_sdram(void); +#endif
+#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif
typedef struct fixed_ddr_parm{ Â Â Â Â int min_freq; Â Â Â Â int max_freq; diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 82d24ab..fcf3371 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -16,6 +16,10 @@ Â #include <config.h> Â #include <common.h>
+#ifdef CONFIG_MPC85xx +void sdram_init(void); +#endif
/* BR - Base Registers  */  #define BR0               0x5000      /* Register offset to immr */ diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 9403e4b..d719292 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -37,8 +37,6 @@  #include <libfdt.h>  #include <fdt_support.h>
-long int fixed_sdram(void);
int board_early_init_f (void) Â { Â Â Â Â return 0; @@ -67,7 +65,7 @@ int checkboard (void) Â /************************************************************************* Â * Â fixed sdram init -- doesn't use serial presence detect. Â ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) Â { Â Â Â Â volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -96,27 +94,6 @@ long int fixed_sdram (void) Â } Â #endif /* !defined(CONFIG_SPD_EEPROM) */
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_SPD_EEPROM)
- puts("fsl_ddr_sdram\n");
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- puts("fixed_sdram\n");
- dram_size = fixed_sdram ();
-#endif
- puts(" Â Â DDR: ");
- return dram_size;
-}
#if defined(CONFIG_SYS_DRAM_TEST)  int  testdram(void) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index cf92ba1..ee5b668 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -42,8 +42,6 @@
#include "../common/sgmii_riser.h"
-phys_size_t fixed_sdram(void);
int board_early_init_f (void) Â { Â #ifdef CONFIG_MMC @@ -98,25 +96,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t -initdram(int board_type) -{
- phys_size_t dram_size = 0;
- puts("Initializing....");
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
- puts(" Â Â DDR: ");
- return dram_size;
-}
#if !defined(CONFIG_SPD_EEPROM) Â /* Â * Fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index d354a26..deab811 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -39,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); Â #endif
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
int checkboard (void) Â { @@ -61,54 +59,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint temp_ddrdll = 0;
- /*
- * Work around to stabilize DDR DLL
- */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram();
-#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- /*
- * Initialize SDRAM.
- */
- sdram_init();
- puts(" Â Â DDR: ");
- return dram_size;
-}
/*  * Initialize Local Bus  */ @@ -232,7 +182,7 @@ sdram_init(void)  /*************************************************************************  *  fixed sdram init -- doesn't use serial presence detect.  ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void)  {  #ifndef CONFIG_SYS_RAMBOOT     volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index a9925d5..adcc0ad 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = {     SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,            MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,            0, 7, BOOKE_PAGESZ_16K, 1),
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 8, 9: Â Â 128M Â Â DDR
- * 0x00000000 Â 64M Â Â DDR System memory
- * 0x04000000 Â 64M Â Â DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
-#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_64M, 1),
-#endif  };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 59ec604..59df2bd 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -42,7 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); Â #endif
void local_bus_init(void); -void sdram_init(void);
/* Â * I/O Port configuration table @@ -242,48 +241,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Â Â Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- /*
- * SDRAM Initialization
- */
- sdram_init();
- puts(" Â Â DDR: ");
- return dram_size;
-}
/*  * Initialize Local Bus  */ diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 31c3fad..35d81db 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -67,23 +67,6 @@ int checkboard (void)     return 0;  }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
- puts(" Â Â DDR: ");
- return dram_size;
-}
#ifdef CONFIG_PCI1 Â static struct pci_controller pci1_hose; Â #endif diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 14c902c..230cbd1 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -41,7 +41,6 @@ Â DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void); -void sdram_init(void);
int checkboard (void) Â { @@ -74,43 +73,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Â Â Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
- /*
- * SDRAM Initialization
- */
- sdram_init();
- puts(" Â Â DDR: ");
- return dram_size;
-}
/*  * Initialize Local Bus  */ diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index edaba26..5fe7f13 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -40,7 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);  #endif
void local_bus_init(void); -void sdram_init(void);
/* Â * I/O Port configuration table @@ -240,50 +239,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Â Â Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- /*
- * SDRAM Initialization
- */
- sdram_init();
- puts(" Â Â DDR: ");
- return dram_size;
-}
/*  * Initialize Local Bus  */ diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 1761431..38f59d1 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -44,8 +44,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
/* @@ -266,54 +264,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint temp_ddrdll = 0;
- /*
- * Work around to stabilize DDR DLL
- */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram();
-#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- /*
- * Initialize SDRAM.
- */
- sdram_init();
- puts(" Â Â DDR: ");
- return dram_size;
-}
/*  * Initialize Local Bus  */ @@ -437,7 +387,7 @@ sdram_init(void)  /*************************************************************************  *  fixed sdram init -- doesn't use serial presence detect.  ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void)  {  #ifndef CONFIG_SYS_RAMBOOT     volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index a9925d5..adcc0ad 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = {     SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,            MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,            0, 7, BOOKE_PAGESZ_16K, 1),
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 8, 9: Â Â 128M Â Â DDR
- * 0x00000000 Â 64M Â Â DDR System memory
- * 0x04000000 Â 64M Â Â DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
-#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_64M, 1),
-#endif  };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index d74fcac..ee4c807 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -100,7 +100,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { Â };
void local_bus_init(void); -void sdram_init(void);
int board_early_init_f (void) Â { @@ -137,43 +136,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Â Â Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
- /*
- * SDRAM Initialization
- */
- sdram_init();
- puts(" Â Â DDR: ");
- return dram_size;
-}
/*  * Initialize Local Bus  */ diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index dc0884e..12a417c 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -44,8 +44,6 @@  #include "../common/pq-mds-pib.h"  #endif
-phys_size_t fixed_sdram(void);
const qe_iop_conf_t qe_iop_conf_tab[] = { Â Â Â Â /* QE_MUX_MDC */ Â Â Â Â {2, Â 31, 1, 0, 1}, /* QE_MUX_MDC Â Â Â Â Â Â Â */ @@ -244,40 +242,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL)
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Â Â Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
- volatile ccsr_gur_t *gur =
- (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- out_be32(&gur->ddrdllcr, 0x81000000);
- udelay(200);
-#endif
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
- puts(" Â Â DDR: ");
- return dram_size;
-}
#if !defined(CONFIG_SPD_EEPROM) Â phys_size_t fixed_sdram(void) Â { diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 120f35c..796aacf 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -38,8 +38,6 @@
#include "../common/sgmii_riser.h"
-long int fixed_sdram(void);
int checkboard (void) Â { Â Â Â Â u8 vboot; @@ -73,23 +71,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t initdram(int board_type) -{
- phys_size_t dram_size = 0;
- puts("Initializing....");
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
- puts(" Â Â DDR: ");
- return dram_size;
-}
#if !defined(CONFIG_SPD_EEPROM) Â /* diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 7cb549b..e3e8300 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -76,19 +76,6 @@ int checkboard(void) Â Â Â Â return 0; Â }
-phys_size_t initdram(int board_type) -{
- phys_size_t dram_size = 0;
- puts("Initializing....\n");
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
- puts(" Â Â DDR: ");
- return dram_size;
-}
#define CONFIG_TFP410_I2C_ADDR 0x38
/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 15b46b0..e54fde2 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -239,19 +239,6 @@ phys_size_t fixed_sdram (void)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
- set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
return ddr_size; Â }
-phys_size_t initdram(int board_type) -{
- phys_size_t dram_size = 0;
- dram_size = fixed_sdram();
- set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
- puts("DDR: ");
- return dram_size;
-} diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index b05ef98..7ad8544 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -43,8 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t fixed_sdram(void);
int checkboard(void) Â { Â Â Â Â u8 sw; @@ -69,31 +67,6 @@ int checkboard(void) Â Â Â Â return 0; Â }
-phys_size_t initdram(int board_type) -{
- phys_size_t dram_size = 0;
- puts("Initializing....");
-#ifdef CONFIG_DDR_SPD
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- dram_size,
- LAW_TRGT_IF_DDR) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
- puts(" Â Â DDR: ");
- return dram_size;
-}
#if !defined(CONFIG_DDR_SPD) Â /* Â * Fixed sdram init -- doesn't use serial presence detect. @@ -169,6 +142,13 @@ phys_size_t fixed_sdram(void) Â Â Â Â udelay(500); Â #endif
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
- LAW_TRGT_IF_DDR) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; Â }
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index f1ab360..63a0035 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -31,8 +31,6 @@ Â #include <asm/fsl_ddr_sdram.h> Â #include <spd_sdram.h>
-long int fixed_sdram (void);
int board_pre_init (void)  {  #if defined(CONFIG_PCI) @@ -108,54 +106,6 @@ void sdram_init(void)  #endif  }
-phys_size_t initdram(int board_type) -{
- long dram_size = 0;
-#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif
-#if defined(CONFIG_DDR_DLL)
- uint temp_ddrdll = 0;
- /* Work around to stabilize DDR DLL */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
-#endif
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram();
-#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- return dram_size;
-#endif
- sdram_init();
-#if defined(CONFIG_DDR_ECC)
- {
- /* Initialize all of memory for ECC, then
- * enable errors */
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
- /* Enable errors for ECC */
- ddr->err_disable = 0x00000000;
- asm("sync;isync;msync");
- }
-#endif
- return dram_size;
-}
#if defined(CONFIG_SYS_DRAM_TEST) Â int testdram (void) Â { @@ -194,7 +144,7 @@ int testdram (void) Â /************************************************************************* Â * Â fixed sdram init -- doesn't use serial presence detect. Â ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) Â { Â #ifndef CONFIG_SYS_RAMBOOT Â Â Â Â volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 0b8ea81..bbaf4fd 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -34,14 +34,7 @@ Â #include <asm/fsl_ddr_sdram.h> Â #include <spd_sdram.h>
-#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
int board_early_init_f (void) Â { @@ -73,59 +66,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int i,x;
- x = 10;
- /*
- * Work around to stabilize DDR DLL
- */
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay (200);
- while (gur->ddrdllcr != 0x81000100)
- {
- gur->devdisr = gur->devdisr | 0x00010000;
- asm("sync;isync;msync");
- for (i=0; i<x; i++)
- ;
- gur->devdisr = gur->devdisr & 0xfff7ffff;
- asm("sync;isync;msync");
- x++;
- }
- }
-#endif
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram ();
-#endif
-#if defined(CONFIG_DDR_ECC)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- puts(" Â Â DDR: ");
- return dram_size;
-}
/*  * Initialize Local Bus  */ @@ -225,7 +165,7 @@ int testdram (void)  /*************************************************************************  *  fixed sdram init -- doesn't use serial presence detect.  ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void)  {  #ifndef CONFIG_SYS_RAMBOOT     volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index dadb75c..482eb38 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -98,20 +98,6 @@ struct fsl_e_tlb_entry tlb_table[] = {     SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE,            MAS3_SX|MAS3_SW|MAS3_SR, 0,            0, 6, BOOKE_PAGESZ_64M, 1),
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 7: Â Â Â 256M Â Â DDR
- * 0x00000000 Â 256M Â Â DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_256M, 1),
-#endif  };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 4e059b0..3791216 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -41,7 +41,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); Â #endif
void local_bus_init(void); -long int fixed_sdram(void);
/* Â * I/O Port configuration table @@ -228,60 +227,6 @@ int checkboard (void) Â }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int i,x;
- x = 10;
- /*
- * Work around to stabilize DDR DLL
- */
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay (200);
- while (gur->ddrdllcr != 0x81000100)
- {
- gur->devdisr = gur->devdisr | 0x00010000;
- asm("sync;isync;msync");
- for (i=0; i<x; i++)
- ;
- gur->devdisr = gur->devdisr & 0xfff7ffff;
- asm("sync;isync;msync");
- x++;
- }
- }
-#endif
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram ();
-#endif
-#if defined(CONFIG_DDR_ECC)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- puts(" Â Â DDR: ");
- return dram_size;
-}
/*  * Initialize Local Bus  */ @@ -380,7 +325,7 @@ int testdram (void)  /*************************************************************************  *  fixed sdram init -- doesn't use serial presence detect.  ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void)  {  #ifndef CONFIG_SYS_RAMBOOT     volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index dadb75c..482eb38 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -98,20 +98,6 @@ struct fsl_e_tlb_entry tlb_table[] = {     SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE,            MAS3_SX|MAS3_SW|MAS3_SR, 0,            0, 6, BOOKE_PAGESZ_64M, 1),
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 7: Â Â Â 256M Â Â DDR
- * 0x00000000 Â 256M Â Â DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_256M, 1),
-#endif  };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 272428f..2d24890 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -42,8 +42,6 @@ Â DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram (void);
int board_early_init_f (void) Â { @@ -68,47 +66,6 @@ int checkboard (void) Â Â Â Â return 0; Â }
-phys_size_t -initdram(int board_type) -{
- long dram_size = 0;
- puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Â Â Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- out_be32(&gur->ddrdllcr, 0x81000000);
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram ();
-#endif
- /*
- * SDRAM Initialization
- */
- sdram_init();
- puts(" Â Â DDR: ");
- return dram_size;
-}
/*  * Initialize Local Bus  */ @@ -267,7 +224,7 @@ testdram(void)  *  fixed_sdram init -- doesn't use serial presence detect.  *  assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.  ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void)  {     volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 38bdeb3..bb4c052 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -65,44 +65,34 @@ struct fsl_e_tlb_entry tlb_table[] = { Â Â Â Â Â Â Â Â Â Â Â 0, 1, BOOKE_PAGESZ_1G, 1),
/*
- * TLB 2: Â Â Â 256M Cacheable, non-guarded
- * 0x0 Â Â Â Â Â 256M DDR SDRAM
- */
-#if !defined(CONFIG_SPD_EEPROM)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-#endif
- /*
- * TLB 3: Â Â Â 64M Â Â Non-cacheable, guarded
- * TLB 2: Â Â Â 64M Â Â Non-cacheable, guarded
* 0xe0000000 Â 1M Â Â Â CCSRBAR Â Â Â Â * 0xe2000000 Â 8M Â Â Â PCI1 IO Â Â Â Â * 0xe2800000 Â 8M Â Â Â PCIe IO Â Â Â Â */ Â Â Â Â SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, Â Â Â Â Â Â Â Â Â Â Â MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_64M, 1),
- 0, 2, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 4: Â Â Â 64M Â Â Cacheable, non-guarded
- * TLB 3: Â Â Â 64M Â Â Cacheable, non-guarded
* 0xf0000000  64M   LBC SDRAM First half     */     SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,            MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 4, BOOKE_PAGESZ_64M, 1),
- 0, 3, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 5: Â Â Â 64M Â Â Cacheable, non-guarded
- * TLB 4: Â Â Â 64M Â Â Cacheable, non-guarded
* 0xf4000000  64M   LBC SDRAM Second half     */     SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,            CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,            MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_64M, 1),
- 0, 4, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 6: Â Â Â 16M Â Â Cacheable, non-guarded
- * TLB 5: Â Â Â 16M Â Â Cacheable, non-guarded
* 0xf8000000  1M    7-segment LED display     * 0xf8100000  1M    User switches     * 0xf8300000  1M    Board revision @@ -110,24 +100,24 @@ struct fsl_e_tlb_entry tlb_table[] = {     */     SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,            MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
- 0, 5, BOOKE_PAGESZ_16M, 1),
/*
- * TLB 7: Â Â Â 4M Â Â Â Non-cacheable, guarded
- * TLB 6: Â Â Â 4M Â Â Â Non-cacheable, guarded
* 0xfb800000 Â 4M Â Â Â 1st 4MB block of 64MB user FLASH Â Â Â Â */ Â Â Â Â SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, Â Â Â Â Â Â Â Â Â Â Â MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4M, 1),
- 0, 6, BOOKE_PAGESZ_4M, 1),
/*
- * TLB 8: Â Â Â 4M Â Â Â Non-cacheable, guarded
- * TLB 7: Â Â Â 4M Â Â Â Non-cacheable, guarded
* 0xfbc00000 Â 4M Â Â Â 2nd 4MB block of 64MB user FLASH Â Â Â Â */ Â Â Â Â SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, Â Â Â Â Â Â Â Â Â Â Â CONFIG_SYS_ALT_FLASH + 0x400000, Â Â Â Â Â Â Â Â Â Â Â MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4M, 1),
- 0, 7, BOOKE_PAGESZ_4M, 1),
};
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 77abde5..53278d3 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -38,8 +38,6 @@ Â #include <libfdt.h> Â #include <fdt_support.h>
-long int fixed_sdram (void);
/*  * I/O Port configuration table  * @@ -263,95 +261,6 @@ int checkboard (void)  }
-phys_size_t initdram (int board_type) -{
- long dram_size = 0;
-#if 0 -#if !defined(CONFIG_RAM_AS_FLASH)
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- sys_info_t sysinfo;
- uint temp_lbcdll = 0;
-#endif -#endif /* 0 */ -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif -#if defined(CONFIG_DDR_DLL)
- uint temp_ddrdll = 0;
- /* Work around to stabilize DDR DLL */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
-#endif
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram ();
-#endif
-#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
- get_sys_info(&sysinfo);
- /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
- if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
- lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
- } else {
-#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
- lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
-#endif
- lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
- udelay(200);
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
- asm("sync;isync;msync");
- }
- set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
- set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
- asm("sync");
- (unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
- asm("sync");
- (unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
- asm("sync");
- (unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
- asm("sync");
- (unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
- asm("sync");
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- asm("sync");
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- asm("sync");
-#endif -#endif
-#if defined(CONFIG_DDR_ECC)
- {
- /* Initialize all of memory for ECC, then
- * enable errors */
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
- /* Enable errors for ECC */
- ddr->err_disable = 0x00000000;
- asm("sync;isync;msync");
- }
-#endif
- return dram_size;
-}
#if defined(CONFIG_SYS_DRAM_TEST) Â int testdram (void) Â { @@ -390,7 +299,7 @@ int testdram (void) Â /************************************************************************* Â * Â fixed sdram init -- doesn't use serial presence detect. Â ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) Â {
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index ef897b2..c8235f4 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -39,7 +39,7 @@  *    so this should be extended for other future boards  *    using this routine!  */ -long int fixed_sdram(void) +phys_size_t fixed_sdram(void)  {     volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -77,19 +77,6 @@ long int fixed_sdram(void) Â } Â #endif
-phys_size_t initdram (int board_type) -{
- long dram_size = 0;
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram();
-#endif
- return dram_size;
-}
#if defined(CONFIG_SYS_DRAM_TEST) Â int testdram (void) Â { diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index 25d5211..63068a5 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -40,8 +40,6 @@ Â #include <spd_sdram.h> Â #include <miiphy.h>
-long int fixed_sdram (void);
/*  * I/O Port configuration table  * @@ -277,36 +275,6 @@ show_activity(int flag)     next_led_update += (get_tbclk() / 4);  }
-phys_size_t -initdram (int board_type) -{
- long dram_size = 0;
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint temp_ddrdll = 0;
- /* Work around to stabilize DDR DLL */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC)
- /* Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- return dram_size;
-}
#if defined(CONFIG_SYS_DRAM_TEST) Â int testdram (void) diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 1e0acab..a630cc8 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -41,8 +41,6 @@ Â #include <miiphy.h> Â #include <netdev.h>
-long int fixed_sdram (void);
/*  * I/O Port configuration table  * @@ -294,37 +292,6 @@ show_activity(int flag)     next_led_update += (get_tbclk() / 4);  }
-phys_size_t -initdram (int board_type) -{
- long dram_size = 0;
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint temp_ddrdll = 0;
- /* Work around to stabilize DDR DLL */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC)
- /* Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- return dram_size;
-}
#if defined(CONFIG_SYS_DRAM_TEST) Â int testdram (void) Â { diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 260cd1c..b2d3185 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -394,43 +394,6 @@ static phys_size_t sdram_setup(int casl) Â Â Â Â return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; Â }
-phys_size_t initdram (int board_type) -{
- phys_size_t dram_size = 0;
-#if defined(CONFIG_DDR_DLL)
- /*
- * This DLL-Override only used on TQM8540 and TQM8560
- */
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int i, x;
- x = 10;
- /*
- * Work around to stabilize DDR DLL
- */
- gur->ddrdllcr = 0x81000000;
- asm ("sync; isync; msync");
- udelay (200);
- while (gur->ddrdllcr != 0x81000100) {
- gur->devdisr = gur->devdisr | 0x00010000;
- asm ("sync; isync; msync");
- for (i = 0; i < x; i++)
- ;
- gur->devdisr = gur->devdisr & 0xfff7ffff;
- asm ("sync; isync; msync");
- x++;
- }
- }
-#endif
- dram_size = fixed_sdram();
- return dram_size;
-}
#if defined(CONFIG_SYS_DRAM_TEST) Â int testdram (void) Â { diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 75dd348..f9f8cc9 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -120,36 +120,6 @@ struct fsl_e_tlb_entry tlb_table[] = { Â Â Â Â SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, Â Â Â Â Â Â Â Â Â Â Â MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, Â Â Â Â Â Â Â Â Â Â Â 0, 6, BOOKE_PAGESZ_64M, 1),
-#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
- /*
- * TLB 7+8: Â Â Â 2G Â Â DDR, cache enabled
- * 0x00000000 Â Â 2G Â Â DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_1G, 1),
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#else
- /*
- * TLB 7+8: Â Â 512M Â Â DDR, cache disabled (needed for memory test)
- * 0x00000000 Â 512M Â Â DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 7, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 8, BOOKE_PAGESZ_256M, 1),
-#endif  #ifdef CONFIG_PCIE1     /*     * TLB 9:     16M   Non-cacheable, guarded @@ -228,23 +198,6 @@ struct fsl_e_tlb_entry tlb_table[] = {     SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,            MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,            0, 7, BOOKE_PAGESZ_64M, 1),
- /*
- * TLB 8+9: Â Â 512M Â Â DDR, cache disabled (needed for memory test)
- * 0x00000000 Â 512M Â Â DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 8, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 9, BOOKE_PAGESZ_256M, 1),
#ifdef CONFIG_PCIE1     /*     * TLB 10:    16M   Non-cacheable, guarded diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 7604f62..39d105f 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -33,8 +33,6 @@ COBJS-$(CONFIG_FSL_PCI_INIT)  += fsl_8xxx_pci.o  COBJS-$(CONFIG_MPC8572)         += fsl_8xxx_clk.o  COBJS-$(CONFIG_MPC86xx)         += fsl_8xxx_clk.o  COBJS-$(CONFIG_P2020)      += fsl_8xxx_clk.o -COBJS-$(CONFIG_FSL_DDR2)    += fsl_8xxx_ddr.o -COBJS-$(CONFIG_FSL_DDR3)    += fsl_8xxx_ddr.o  COBJS-$(CONFIG_MPC85xx)         += fsl_8xxx_misc.o board.o  COBJS-$(CONFIG_MPC86xx)         += fsl_8xxx_misc.o board.o  COBJS-$(CONFIG_NAND_ACTL)    += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_ddr.c b/board/xes/common/fsl_8xxx_ddr.c deleted file mode 100644 index 81ee70d..0000000 --- a/board/xes/common/fsl_8xxx_ddr.c +++ /dev/null @@ -1,46 +0,0 @@ -/*
- Copyright 2008 Extreme Engineering Solutions, Inc.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Â Â Â Â See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
-#include <common.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/mmu.h>
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif
-phys_size_t initdram(int board_type) -{
- phys_size_t dram_size = fsl_ddr_sdram();
-#ifdef CONFIG_MPC85xx
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /* Initialize and enable DDR ECC */
- ddr_enable_ecc(dram_size);
-#endif
- return dram_size;
-} diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index 0f7fa6c..572a908 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -22,6 +22,7 @@
#include <common.h> Â #include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> Â #include <asm/mmu.h> Â #include <asm/io.h> Â #include <fdt_support.h> @@ -71,6 +72,18 @@ int board_early_init_r(void) Â Â Â Â return 0; Â }
+phys_size_t initdram(int board_type) +{
- phys_size_t dram_size = fsl_ddr_sdram();
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /* Initialize and enable DDR ECC */
- ddr_enable_ecc(dram_size);
+#endif
- return dram_size;
+}
#if defined(CONFIG_OF_BOARD_SETUP)  void ft_board_setup(void *blob, bd_t *bd)  { diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 890d6d9..d8f43d7 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -147,6 +147,10 @@  * DDR Setup  */  #define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000    /* DDR is system memory */ +#if defined(CONFIG_TQM_BIGFLASH) || \
- (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))
+#define CONFIG_DDR_TLB_WIMGE (MAS2_I | MAS2_G) +#endif  #define CONFIG_SYS_SDRAM_BASE      CONFIG_SYS_DDR_SDRAM_BASE  #ifdef CONFIG_TQM8548_AG  #define CONFIG_VERY_BIG_RAM -- 1.5.6.5
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Dec 13, 2010, at 8:12 PM, Paul Gortmaker wrote:
On Mon, Dec 13, 2010 at 4:06 PM, Becky Bruce beckyb@kernel.crashing.org wrote:
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences:
- DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner.
- Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad.
Having #1 and #2 each as standalone commits might have been useful as extra bisection points, in the event that anyone runs into problems -- but I suspect that is a lot of respin work, and hopefully Things Just Work for most people.
I thought about that, but it turns out that creates a ton of patchery than then just gets whacked out.
The only other thing I noticed was that...
+/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +phys_size_t initdram(int board_type) +{
phys_size_t dram_size = 0;+#if defined(CONFIG_DDR_DLL)
{ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);unsigned int x = 10;unsigned int i;/** Work around to stabilize DDR DLL*/out_be32(&gur->ddrdllcr, 0x81000000);asm("sync;isync;msync");udelay(200);while (in_be32(&gur->ddrdllcr) != 0x81000100) {setbits_be32(&gur->devdisr, 0x00010000);for (i = 0; i < x; i++);clrbits_be32(&gur->devdisr, 0x00010000);x++;}}+#endif
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
dram_size = fsl_ddr_sdram();+#else
dram_size = fixed_sdram();+#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);+#endif
...right here, the 8540EVAL board bailed out if RAMBOOT was set, thus bypassing sdram_init. So this won't strictly match the old behaviour on at least that board. Maybe it makes sense to just gut the rest of the RAMBOOT code (if any) from boards that were doing this, since I believe it isn't really a globally supported (or at least encouraged) u-boot feature?
You are correct, and I missed that one (perils of the huge patchset :). However, I believe Kumar has announced he is deprecating support for that board, and I don't see any other cases of this. Yell if I've missed something else.
-Becky
I'm not anywhere near the office at the moment, but later in the week I'll see if I can find a board (or two?) to test on.
Paul.
/* Some boards also have sdram on the lbc */sdram_init();return dram_size;+} +#endif
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index fcef40c..10fcd24 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -9,6 +9,16 @@ #include <common.h> #include <asm/fsl_lbc.h>
+#ifdef CONFIG_MPC85xx +/* Boards should provide their own version of this if they use lbc sdram */ +void __sdram_init(void) +{
/* Do nothing */+} +void sdram_init(void) __attribute__((weak, alias("__sdram_init"))); +#endif
void print_lbc_regs(void) { int i; diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 17d4b31..8ceae18 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -214,6 +214,19 @@ typedef struct memctl_options_s {
extern phys_size_t fsl_ddr_sdram(void);
+/*
- The 85xx boards have a common prototype for fixed_sdram so put the
- declaration here.
- */
+#ifdef CONFIG_MPC85xx +extern phys_size_t fixed_sdram(void); +#endif
+#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif
typedef struct fixed_ddr_parm{ int min_freq; int max_freq; diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 82d24ab..fcf3371 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -16,6 +16,10 @@ #include <config.h> #include <common.h>
+#ifdef CONFIG_MPC85xx +void sdram_init(void); +#endif
/* BR - Base Registers */ #define BR0 0x5000 /* Register offset to immr */ diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 9403e4b..d719292 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -37,8 +37,6 @@ #include <libfdt.h> #include <fdt_support.h>
-long int fixed_sdram(void);
int board_early_init_f (void) { return 0; @@ -67,7 +65,7 @@ int checkboard (void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -96,27 +94,6 @@ long int fixed_sdram (void) } #endif /* !defined(CONFIG_SPD_EEPROM) */
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_SPD_EEPROM)
puts("fsl_ddr_sdram\n");dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
puts("fixed_sdram\n");dram_size = fixed_sdram ();-#endif
puts(" DDR: ");return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram(void) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index cf92ba1..ee5b668 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -42,8 +42,6 @@
#include "../common/sgmii_riser.h"
-phys_size_t fixed_sdram(void);
int board_early_init_f (void) { #ifdef CONFIG_MMC @@ -98,25 +96,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
phys_size_t dram_size = 0;puts("Initializing....");-#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();-#else
dram_size = fixed_sdram();-#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts(" DDR: ");return dram_size;-}
#if !defined(CONFIG_SPD_EEPROM) /*
- Fixed sdram init -- doesn't use serial presence detect.
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index d354a26..deab811 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -39,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
int checkboard (void) { @@ -61,54 +59,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);uint temp_ddrdll = 0;/** Work around to stabilize DDR DLL*/temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");}-#endif
-#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram();-#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
/** Initialize SDRAM.*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ @@ -232,7 +182,7 @@ sdram_init(void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index a9925d5..adcc0ad 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1),
-#if !defined(CONFIG_SPD_EEPROM)
/** TLB 8, 9: 128M DDR* 0x00000000 64M DDR System memory* 0x04000000 64M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.* Make sure the TLB count at the top of this table is correct.* Likely it needs to be increased by two for these entries.*/-#error("Update the number of table entries in tlb1_entry")
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 8, BOOKE_PAGESZ_64M, 1),SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 9, BOOKE_PAGESZ_64M, 1),-#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 59ec604..59df2bd 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -42,7 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void);
/*
- I/O Port configuration table
@@ -242,48 +241,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay(200);}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
/** SDRAM Initialization*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 31c3fad..35d81db 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -67,23 +67,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts(" DDR: ");return dram_size;-}
#ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 14c902c..230cbd1 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -41,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void); -void sdram_init(void);
int checkboard (void) { @@ -74,43 +73,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay(200);}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;/** SDRAM Initialization*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index edaba26..5fe7f13 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -40,7 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void);
/*
- I/O Port configuration table
@@ -240,50 +239,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay(200);}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
/** SDRAM Initialization*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 1761431..38f59d1 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -44,8 +44,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
/* @@ -266,54 +264,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);uint temp_ddrdll = 0;/** Work around to stabilize DDR DLL*/temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");}-#endif
-#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram();-#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
/** Initialize SDRAM.*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ @@ -437,7 +387,7 @@ sdram_init(void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index a9925d5..adcc0ad 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1),
-#if !defined(CONFIG_SPD_EEPROM)
/** TLB 8, 9: 128M DDR* 0x00000000 64M DDR System memory* 0x04000000 64M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.* Make sure the TLB count at the top of this table is correct.* Likely it needs to be increased by two for these entries.*/-#error("Update the number of table entries in tlb1_entry")
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 8, BOOKE_PAGESZ_64M, 1),SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 9, BOOKE_PAGESZ_64M, 1),-#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index d74fcac..ee4c807 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -100,7 +100,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { };
void local_bus_init(void); -void sdram_init(void);
int board_early_init_f (void) { @@ -137,43 +136,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay(200);}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;/** SDRAM Initialization*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index dc0884e..12a417c 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -44,8 +44,6 @@ #include "../common/pq-mds-pib.h" #endif
-phys_size_t fixed_sdram(void);
const qe_iop_conf_t qe_iop_conf_tab[] = { /* QE_MUX_MDC */ {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ @@ -244,40 +242,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur =(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);out_be32(&gur->ddrdllcr, 0x81000000);udelay(200);-#endif
-#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();-#else
dram_size = fixed_sdram();-#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts(" DDR: ");return dram_size;-}
#if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 120f35c..796aacf 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -38,8 +38,6 @@
#include "../common/sgmii_riser.h"
-long int fixed_sdram(void);
int checkboard (void) { u8 vboot; @@ -73,23 +71,6 @@ int checkboard (void) return 0; }
-phys_size_t initdram(int board_type) -{
phys_size_t dram_size = 0;puts("Initializing....");-#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();-#else
dram_size = fixed_sdram();-#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts(" DDR: ");return dram_size;-}
#if !defined(CONFIG_SPD_EEPROM) /* diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 7cb549b..e3e8300 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -76,19 +76,6 @@ int checkboard(void) return 0; }
-phys_size_t initdram(int board_type) -{
phys_size_t dram_size = 0;puts("Initializing....\n");dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;puts(" DDR: ");return dram_size;-}
#define CONFIG_TFP410_I2C_ADDR 0x38
/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 15b46b0..e54fde2 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -239,19 +239,6 @@ phys_size_t fixed_sdram (void)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1); return ddr_size;}
-phys_size_t initdram(int board_type) -{
phys_size_t dram_size = 0;dram_size = fixed_sdram();set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts("DDR: ");return dram_size;-} diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index b05ef98..7ad8544 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -43,8 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t fixed_sdram(void);
int checkboard(void) { u8 sw; @@ -69,31 +67,6 @@ int checkboard(void) return 0; }
-phys_size_t initdram(int board_type) -{
phys_size_t dram_size = 0;puts("Initializing....");-#ifdef CONFIG_DDR_SPD
dram_size = fsl_ddr_sdram();-#else
dram_size = fixed_sdram();if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,dram_size,LAW_TRGT_IF_DDR) < 0) {printf("ERROR setting Local Access Windows for DDR\n");return 0;};-#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;puts(" DDR: ");return dram_size;-}
#if !defined(CONFIG_DDR_SPD) /*
- Fixed sdram init -- doesn't use serial presence detect.
@@ -169,6 +142,13 @@ phys_size_t fixed_sdram(void) udelay(500); #endif
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,LAW_TRGT_IF_DDR) < 0) {printf("ERROR setting Local Access Windows for DDR\n");return 0;};return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;}
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index f1ab360..63a0035 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -31,8 +31,6 @@ #include <asm/fsl_ddr_sdram.h> #include <spd_sdram.h>
-long int fixed_sdram (void);
int board_pre_init (void) { #if defined(CONFIG_PCI) @@ -108,54 +106,6 @@ void sdram_init(void) #endif }
-phys_size_t initdram(int board_type) -{
long dram_size = 0;-#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);-#endif
-#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;/* Work around to stabilize DDR DLL */temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");-#endif
-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram();-#endif
-#if defined(CONFIG_SYS_RAMBOOT)
return dram_size;-#endif
sdram_init();-#if defined(CONFIG_DDR_ECC)
{/* Initialize all of memory for ECC, then* enable errors */volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);/* Enable errors for ECC */ddr->err_disable = 0x00000000;asm("sync;isync;msync");}-#endif
return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { @@ -194,7 +144,7 @@ int testdram (void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 0b8ea81..bbaf4fd 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -34,14 +34,7 @@ #include <asm/fsl_ddr_sdram.h> #include <spd_sdram.h>
-#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
int board_early_init_f (void) { @@ -73,59 +66,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);int i,x;x = 10;/** Work around to stabilize DDR DLL*/gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay (200);while (gur->ddrdllcr != 0x81000100){gur->devdisr = gur->devdisr | 0x00010000;asm("sync;isync;msync");for (i=0; i<x; i++);gur->devdisr = gur->devdisr & 0xfff7ffff;asm("sync;isync;msync");x++;}}-#endif
-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram ();-#endif
-#if defined(CONFIG_DDR_ECC)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ @@ -225,7 +165,7 @@ int testdram (void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index dadb75c..482eb38 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -98,20 +98,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1),
-#if !defined(CONFIG_SPD_EEPROM)
/** TLB 7: 256M DDR* 0x00000000 256M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.* Make sure the TLB count at the top of this table is correct.* Likely it needs to be increased by two for these entries.*/SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 7, BOOKE_PAGESZ_256M, 1),-#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 4e059b0..3791216 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -41,7 +41,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -long int fixed_sdram(void);
/*
- I/O Port configuration table
@@ -228,60 +227,6 @@ int checkboard (void) }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);int i,x;x = 10;/** Work around to stabilize DDR DLL*/gur->ddrdllcr = 0x81000000;asm("sync;isync;msync");udelay (200);while (gur->ddrdllcr != 0x81000100){gur->devdisr = gur->devdisr | 0x00010000;asm("sync;isync;msync");for (i=0; i<x; i++);gur->devdisr = gur->devdisr & 0xfff7ffff;asm("sync;isync;msync");x++;}}-#endif
-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram ();-#endif
-#if defined(CONFIG_DDR_ECC)
/** Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ @@ -380,7 +325,7 @@ int testdram (void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index dadb75c..482eb38 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -98,20 +98,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1),
-#if !defined(CONFIG_SPD_EEPROM)
/** TLB 7: 256M DDR* 0x00000000 256M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.* Make sure the TLB count at the top of this table is correct.* Likely it needs to be increased by two for these entries.*/SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 7, BOOKE_PAGESZ_256M, 1),-#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 272428f..2d24890 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -42,8 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram (void);
int board_early_init_f (void) { @@ -68,47 +66,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{
long dram_size = 0;puts("Initializing\n");-#if defined(CONFIG_DDR_DLL)
{/** Work around to stabilize DDR DLL MSYNC_IN.* Errata DDR9 seems to have been fixed.* This is now the workaround for Errata DDR11:* Override DLL = 1, Course Adj = 1, Tap Select = 0*/volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);out_be32(&gur->ddrdllcr, 0x81000000);asm("sync;isync;msync");udelay(200);}-#endif
-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram ();-#endif
/** SDRAM Initialization*/sdram_init();puts(" DDR: ");return dram_size;-}
/*
- Initialize Local Bus
*/ @@ -267,7 +224,7 @@ testdram(void)
- fixed_sdram init -- doesn't use serial presence detect.
- assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 38bdeb3..bb4c052 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -65,44 +65,34 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 1, BOOKE_PAGESZ_1G, 1),
/*
* TLB 2: 256M Cacheable, non-guarded* 0x0 256M DDR SDRAM*/-#if !defined(CONFIG_SPD_EEPROM)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 2, BOOKE_PAGESZ_256M, 1),-#endif
/** TLB 3: 64M Non-cacheable, guarded
* TLB 2: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR * 0xe2000000 8M PCI1 IO * 0xe2800000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_64M, 1),
0, 2, BOOKE_PAGESZ_64M, 1), /*
* TLB 4: 64M Cacheable, non-guarded
* TLB 3: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
0, 3, BOOKE_PAGESZ_64M, 1), /*
* TLB 5: 64M Cacheable, non-guarded
* TLB 4: 64M Cacheable, non-guarded * 0xf4000000 64M LBC SDRAM Second half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_64M, 1),
0, 4, BOOKE_PAGESZ_64M, 1), /*
* TLB 6: 16M Cacheable, non-guarded
* TLB 5: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision@@ -110,24 +100,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
0, 5, BOOKE_PAGESZ_16M, 1), /*
* TLB 7: 4M Non-cacheable, guarded
* TLB 6: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4M, 1),
0, 6, BOOKE_PAGESZ_4M, 1), /*
* TLB 8: 4M Non-cacheable, guarded
* TLB 7: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_4M, 1),
0, 7, BOOKE_PAGESZ_4M, 1),};
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 77abde5..53278d3 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -38,8 +38,6 @@ #include <libfdt.h> #include <fdt_support.h>
-long int fixed_sdram (void);
/*
- I/O Port configuration table
@@ -263,95 +261,6 @@ int checkboard (void) }
-phys_size_t initdram (int board_type) -{
long dram_size = 0;-#if 0 -#if !defined(CONFIG_RAM_AS_FLASH)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;sys_info_t sysinfo;uint temp_lbcdll = 0;-#endif -#endif /* 0 */ -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);-#endif -#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;/* Work around to stabilize DDR DLL */temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");-#endif
-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram ();-#endif
-#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
get_sys_info(&sysinfo);/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;} else {-#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */-#endif
lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;udelay(200);temp_lbcdll = gur->lbcdllcr;gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;asm("sync;isync;msync");}set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);lbc->lbcr = CONFIG_SYS_LBC_LBCR;lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;asm("sync");(unsigned int) * (ulong *)0 = 0x000000ff;lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;asm("sync");(unsigned int) * (ulong *)0 = 0x000000ff;lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;asm("sync");(unsigned int) * (ulong *)0 = 0x000000ff;lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;asm("sync");(unsigned int) * (ulong *)0 = 0x000000ff;lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;asm("sync");lbc->lsrt = CONFIG_SYS_LBC_LSRT;asm("sync");lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;asm("sync");-#endif -#endif
-#if defined(CONFIG_DDR_ECC)
{/* Initialize all of memory for ECC, then* enable errors */volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);/* Enable errors for ECC */ddr->err_disable = 0x00000000;asm("sync;isync;msync");}-#endif
return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { @@ -390,7 +299,7 @@ int testdram (void) /*************************************************************************
- fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) {
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index ef897b2..c8235f4 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -39,7 +39,7 @@
so this should be extended for other future boardsusing this routine!*/ -long int fixed_sdram(void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -77,19 +77,6 @@ long int fixed_sdram(void) } #endif
-phys_size_t initdram (int board_type) -{
long dram_size = 0;-#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#else
dram_size = fixed_sdram();-#endif
return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index 25d5211..63068a5 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -40,8 +40,6 @@ #include <spd_sdram.h> #include <miiphy.h>
-long int fixed_sdram (void);
/*
- I/O Port configuration table
@@ -277,36 +275,6 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); }
-phys_size_t -initdram (int board_type) -{
long dram_size = 0;-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);uint temp_ddrdll = 0;/* Work around to stabilize DDR DLL */temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#if defined(CONFIG_DDR_ECC)
/* Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 1e0acab..a630cc8 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -41,8 +41,6 @@ #include <miiphy.h> #include <netdev.h>
-long int fixed_sdram (void);
/*
- I/O Port configuration table
@@ -294,37 +292,6 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); }
-phys_size_t -initdram (int board_type) -{
long dram_size = 0;-#if defined(CONFIG_DDR_DLL)
{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);uint temp_ddrdll = 0;/* Work around to stabilize DDR DLL */temp_ddrdll = gur->ddrdllcr;gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;asm("sync;isync;msync");}-#endif
dram_size = fsl_ddr_sdram();dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#if defined(CONFIG_DDR_ECC)
/* Initialize and enable DDR ECC.*/ddr_enable_ecc(dram_size);-#endif
return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 260cd1c..b2d3185 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -394,43 +394,6 @@ static phys_size_t sdram_setup(int casl) return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; }
-phys_size_t initdram (int board_type) -{
phys_size_t dram_size = 0;-#if defined(CONFIG_DDR_DLL)
/** This DLL-Override only used on TQM8540 and TQM8560*/{volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);int i, x;x = 10;/** Work around to stabilize DDR DLL*/gur->ddrdllcr = 0x81000000;asm ("sync; isync; msync");udelay (200);while (gur->ddrdllcr != 0x81000100) {gur->devdisr = gur->devdisr | 0x00010000;asm ("sync; isync; msync");for (i = 0; i < x; i++);gur->devdisr = gur->devdisr & 0xfff7ffff;asm ("sync; isync; msync");x++;}}-#endif
dram_size = fixed_sdram();return dram_size;-}
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 75dd348..f9f8cc9 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -120,36 +120,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1),
-#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
/** TLB 7+8: 2G DDR, cache enabled* 0x00000000 2G DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.*/SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX | MAS3_SW | MAS3_SR, 0,0, 7, BOOKE_PAGESZ_1G, 1),SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,MAS3_SX | MAS3_SW | MAS3_SR, 0,0, 8, BOOKE_PAGESZ_1G, 1),-#else
/** TLB 7+8: 512M DDR, cache disabled (needed for memory test)* 0x00000000 512M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.*/SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,0, 7, BOOKE_PAGESZ_256M, 1),SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,0, 8, BOOKE_PAGESZ_256M, 1),-#endif #ifdef CONFIG_PCIE1 /* * TLB 9: 16M Non-cacheable, guarded @@ -228,23 +198,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 7, BOOKE_PAGESZ_64M, 1),
/** TLB 8+9: 512M DDR, cache disabled (needed for memory test)* 0x00000000 512M DDR System memory* Without SPD EEPROM configured DDR, this must be setup manually.* Make sure the TLB count at the top of this table is correct.* Likely it needs to be increased by two for these entries.*/SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,0, 8, BOOKE_PAGESZ_256M, 1),SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,0, 9, BOOKE_PAGESZ_256M, 1),#ifdef CONFIG_PCIE1 /* * TLB 10: 16M Non-cacheable, guarded diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 7604f62..39d105f 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -33,8 +33,6 @@ COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o -COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o -COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_ddr.c b/board/xes/common/fsl_8xxx_ddr.c deleted file mode 100644 index 81ee70d..0000000 --- a/board/xes/common/fsl_8xxx_ddr.c +++ /dev/null @@ -1,46 +0,0 @@ -/*
- Copyright 2008 Extreme Engineering Solutions, Inc.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
-#include <common.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/mmu.h>
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif
-phys_size_t initdram(int board_type) -{
phys_size_t dram_size = fsl_ddr_sdram();-#ifdef CONFIG_MPC85xx
dram_size = setup_ddr_tlbs(dram_size / 0x100000);dram_size *= 0x100000;-#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize and enable DDR ECC */ddr_enable_ecc(dram_size);-#endif
return dram_size;-} diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index 0f7fa6c..572a908 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -22,6 +22,7 @@
#include <common.h> #include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> #include <asm/mmu.h> #include <asm/io.h> #include <fdt_support.h> @@ -71,6 +72,18 @@ int board_early_init_r(void) return 0; }
+phys_size_t initdram(int board_type) +{
phys_size_t dram_size = fsl_ddr_sdram();+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize and enable DDR ECC */ddr_enable_ecc(dram_size);+#endif
return dram_size;+}
#if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 890d6d9..d8f43d7 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -147,6 +147,10 @@
- DDR Setup
*/ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#if defined(CONFIG_TQM_BIGFLASH) || \
(!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))+#define CONFIG_DDR_TLB_WIMGE (MAS2_I | MAS2_G) +#endif #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_TQM8548_AG
#define CONFIG_VERY_BIG_RAM
1.5.6.5
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Mon, Dec 13, 2010 at 9:12 PM, Paul Gortmaker paul.gortmaker@windriver.com wrote:
I'm not anywhere near the office at the moment, but later in the week I'll see if I can find a board (or two?) to test on.
Paul.
Seems OK for POST test on an old MPC8540ADS. The info printed for SDRAM kind of interjects itself into the DRAM info, but that is largely cosmetic.
Testing details of the base commit I used to "am" your patches to are below. Feel free to add a Tested-by: from me if you want.
P. -------------------------------------- => reset
U-Boot 2010.12-rc1-00038-g04af960 (Dec 15 2010 - 18:09:59)
CPU: 8540, Version: 2.0, (0x80300020) Core: Unknown, Version: 2.0, (0x80200020) Clock Configuration: CPU0:825 MHz, CCB:330 MHz, DDR:165 MHz (330 MT/s data rate), LBC:82.500 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Board: ADS PCI1: 32 bit, 33 MHz (compiled) I2C: ready DRAM: SDRAM: 64 MiB 256 MiB (DDR1, 64-bit, CL=2.5, ECC off) FLASH: 16 MiB L2: 256 KB already enabled *** Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Net: TSEC0, TSEC1, FEC Hit any key to stop autoboot: 0 =>
--------------------
u-boot$git merge-base master HEAD 0c0892be0d93a5a892b93739c5eb3bf692fed4ff u-boot$git describe v2010.12-rc1-38-g04af960 u-boot$git request-pull master . The following changes since commit 0c0892be0d93a5a892b93739c5eb3bf692fed4ff:
Merge branch 'master' of git://git.denx.de/u-boot-marvell (2010-10-29 22:03:00 +0200)
are available in the git repository at:
. bb-dram
Becky Bruce (12): mpc8540eval: Split initdram() into initdram() and sdram_init() tqm85xx: create fixed_sdram() to do sdram setup mpc85xx/tlb.c: Allow platforms to specify wimge bits socrates: rename sdram_setup fixed_sdram() mpc8569mds: Remove unnecessary CONFIG_SYS_LBC_SDRAM_BASE definition PM854: rename CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_BASE PM856: Rename CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_BASE MPC8568/MPC8569: Remove CONFIG_DDR_DLL define mpc85xx boards: initdram() cleanup/bugfix 85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN mpc85xx: rename sdram_init() lbc_sdram_init() MPC8xxx DDR: align informational prints
On Dec 15, 2010, at 5:25 PM, Paul Gortmaker wrote:
On Mon, Dec 13, 2010 at 9:12 PM, Paul Gortmaker paul.gortmaker@windriver.com wrote:
I'm not anywhere near the office at the moment, but later in the week I'll see if I can find a board (or two?) to test on.
Paul.
Seems OK for POST test on an old MPC8540ADS. The info printed for SDRAM kind of interjects itself into the DRAM info, but that is lar gely cosmetic.
I'll look at making this prettier.... I like pretty.
Testing details of the base commit I used to "am" your patches to are below. Feel free to add a Tested-by: from me if you want.
Thanks! -Becky
P.
=> reset
U-Boot 2010.12-rc1-00038-g04af960 (Dec 15 2010 - 18:09:59)
CPU: 8540, Version: 2.0, (0x80300020) Core: Unknown, Version: 2.0, (0x80200020) Clock Configuration: CPU0:825 MHz, CCB:330 MHz, DDR:165 MHz (330 MT/s data rate), LBC:82.500 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Board: ADS PCI1: 32 bit, 33 MHz (compiled) I2C: ready DRAM: SDRAM: 64 MiB 256 MiB (DDR1, 64-bit, CL=2.5, ECC off) FLASH: 16 MiB L2: 256 KB already enabled *** Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Net: TSEC0, TSEC1, FEC Hit any key to stop autoboot: 0 =>
u-boot$git merge-base master HEAD 0c0892be0d93a5a892b93739c5eb3bf692fed4ff u-boot$git describe v2010.12-rc1-38-g04af960 u-boot$git request-pull master . The following changes since commit 0c0892be0d93a5a892b93739c5eb3bf692fed4ff:
Merge branch 'master' of git://git.denx.de/u-boot-marvell (2010-10-29 22:03:00 +0200)
are available in the git repository at:
. bb-dram
Becky Bruce (12): mpc8540eval: Split initdram() into initdram() and sdram_init() tqm85xx: create fixed_sdram() to do sdram setup mpc85xx/tlb.c: Allow platforms to specify wimge bits socrates: rename sdram_setup fixed_sdram() mpc8569mds: Remove unnecessary CONFIG_SYS_LBC_SDRAM_BASE definition PM854: rename CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_BASE PM856: Rename CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_BASE MPC8568/MPC8569: Remove CONFIG_DDR_DLL define mpc85xx boards: initdram() cleanup/bugfix 85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN mpc85xx: rename sdram_init() lbc_sdram_init() MPC8xxx DDR: align informational prints
On Dec 13, 2010, at 3:06 PM, Becky Bruce wrote:
Neither of these parts should have the erratum this is meant to work around. Delete it.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - 2 files changed, 0 insertions(+), 2 deletions(-)
applied to 85xx next
- k
On Dec 13, 2010, at 3:06 PM, Becky Bruce wrote:
This board does not actually configure anything for SDRAM - change the name to avoid confusion and make it easier to go to a common initdram going forward.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
board/pm856/law.c | 5 ++--- board/pm856/tlb.c | 4 ++-- include/configs/PM856.h | 6 +----- 3 files changed, 5 insertions(+), 10 deletions(-)
drop as I'm killing support for this board.
- k
On Dec 13, 2010, at 3:06 PM, Becky Bruce wrote:
As far as I can tell, this board doesn't actually configure the LBC for SDRAM. I've renamed this to avoid confusion (and to make the initdram() cleanup easier later.)
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
board/pm854/law.c | 5 ++--- board/pm854/tlb.c | 4 ++-- include/configs/PM854.h | 6 +----- 3 files changed, 5 insertions(+), 10 deletions(-)
drop as I'm killing support for this board.
- k
On Dec 13, 2010, at 3:06 PM, Becky Bruce wrote:
This isn't used - delete it.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
include/configs/MPC8569MDS.h | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-)
applied to 85xx next
- k
On Dec 13, 2010, at 3:06 PM, Becky Bruce wrote:
This will help us go to a fixed initdram() for all 85xx boards going forward. sdram_setup() had an argument that it didn't need, since the value was #defined.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
board/socrates/sdram.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
applied to 85xx next
- k
On Dec 13, 2010, at 3:06 PM, Becky Bruce wrote:
Some platforms might want to override the default wimge=0 for DDR. Add CONFIG_DDR_TLB_WIMGE for those platforms to use. This will initially only be used by TQM85xx, but could be useful for other boards or testing going forward.
This should be CONFIG_SYS_DDR_MPC85xx_TLB_WIMGE
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
arch/powerpc/cpu/mpc85xx/tlb.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index e3a71ae..513aaaa 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -250,10 +250,14 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { int i; unsigned int tlb_size;
- unsigned int wimge = 0; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; u64 size, memsize = (u64)memsize_in_meg << 20;
+#ifdef CONFIG_DDR_TLB_WIMGE
- wimge = CONFIG_DDR_TLB_WIMGE;
+#endif size = min(memsize, CONFIG_MAX_MEM_MAPPED);
/* Convert (4^max) kB to (2^max) bytes */ @@ -277,7 +281,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) tlb_size = (camsize - 10) / 2;
set_tlb(1, ram_tlb_address, p_addr,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
MAS3_SX|MAS3_SW|MAS3_SR, wimge, 0, ram_tlb_index, tlb_size, 1);size -= 1ULL << camsize;
-- 1.5.6.5
On Dec 13, 2010, at 3:06 PM, Becky Bruce wrote:
Modeled after the MPC8540DS code; this will allow us to use a common initdram() once that is available. There should be no functional change.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org
board/mpc8540eval/mpc8540eval.c | 64 +++++++++++++++++++++----------------- 1 files changed, 35 insertions(+), 29 deletions(-)
drop as I'm killing support for this board.
- k
participants (3)
-
Becky Bruce -
Kumar Gala -
Paul Gortmaker