From: Stephen Warren swarren@nvidia.com

This file defines pr_fmt(), so the individual error() calls don't need to include the prefix in their format strings. Doing so results in duplicate text in any error messages. Remove the duplication.

Signed-off-by: Stephen Warren swarren@nvidia.com --- v2: New patch. --- arch/arm/mach-tegra/tegra124/xusb-padctl.c | 33 +++++++++++++----------------- 1 file changed, 14 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index 43af883f2c12..ce857b8b05e9 100644 --- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c @@ -220,7 +220,7 @@ static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) u32 value;

if (padctl->enable == 0) { - error("tegra-xusb-padctl: unbalanced enable/disable"); + error("unbalanced enable/disable"); return 0; }

@@ -415,7 +415,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,

len = fdt_count_strings(fdt, node, "nvidia,lanes"); if (len < 0) { - error("tegra-xusb-padctl: failed to parse "nvidia,lanes" property"); + error("failed to parse "nvidia,lanes" property"); return -EINVAL; }

@@ -425,7 +425,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, err = fdt_get_string_index(fdt, node, "nvidia,lanes", i, &group->pins[i]); if (err < 0) { - error("tegra-xusb-padctl: failed to read string from "nvidia,lanes" property"); + error("failed to read string from "nvidia,lanes" property"); return -EINVAL; } } @@ -434,7 +434,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,

err = fdt_get_string(fdt, node, "nvidia,function", &group->func); if (err < 0) { - error("tegra-xusb-padctl: failed to parse "nvidia,func" property"); + error("failed to parse "nvidia,func" property"); return -EINVAL; }

@@ -487,15 +487,14 @@ tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,

lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); if (!lane) { - error("tegra-xusb-padctl: no lane for pin %s", - group->pins[i]); + error("no lane for pin %s", group->pins[i]); continue; }

func = tegra_xusb_padctl_lane_find_function(padctl, lane, group->func); if (func < 0) { - error("tegra-xusb-padctl: function %s invalid for lane %s: %d", + error("function %s invalid for lane %s: %d", group->func, lane->name, func); continue; } @@ -537,8 +536,7 @@ tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,

err = tegra_xusb_padctl_group_apply(padctl, group); if (err < 0) { - error("tegra-xusb-padctl: failed to apply group %s: %d", - group->name, err); + error("failed to apply group %s: %d", group->name, err); continue; } } @@ -564,8 +562,7 @@ tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt, subnode); if (err < 0) { - error("tegra-xusb-padctl: failed to parse group %s", - group->name); + error("failed to parse group %s", group->name); return err; }

@@ -582,7 +579,7 @@ static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,

err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs); if (err < 0) { - error("tegra-xusb-padctl: registers not found"); + error("registers not found"); return err; }

@@ -592,8 +589,8 @@ static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt, subnode); if (err < 0) { - error("tegra-xusb-padctl: failed to parse entry %s: %d", - config->name, err); + error("failed to parse entry %s: %d", config->name, + err); continue; } } @@ -618,7 +615,7 @@ static int process_nodes(const void *fdt, int nodes[], unsigned int count) break;

default: - error("tegra-xusb-padctl: unsupported compatible: %s", + error("unsupported compatible: %s", fdtdec_get_compatible(id)); continue; } @@ -631,8 +628,7 @@ static int process_nodes(const void *fdt, int nodes[], unsigned int count)

err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]); if (err < 0) { - error("tegra-xusb-padctl: failed to parse DT: %d", - err); + error("failed to parse DT: %d", err); continue; }

@@ -641,8 +637,7 @@ static int process_nodes(const void *fdt, int nodes[], unsigned int count)

err = tegra_xusb_padctl_config_apply(padctl, &padctl->config); if (err < 0) { - error("tegra-xusb-padctl: failed to apply pinmux: %d", - err); + error("failed to apply pinmux: %d", err); continue; }

From: Stephen Warren swarren@nvidia.com

A fair amount of the XUSB padctl driver will be common between Tegra124 and Tegra210. To avoid cut/paste between the two chips, create a new file that will contain the common code, and convert the Tegra124 code to use it. This change doesn't move every last piece of code that can/will be shared, but rather concentrates on moving code that can be moved with zero changes, so there are no other diffs mixed in.

Signed-off-by: Stephen Warren swarren@nvidia.com --- v2: Fixed duplicate error() message prefixes. --- arch/arm/mach-tegra/tegra124/Makefile | 1 + arch/arm/mach-tegra/tegra124/xusb-padctl.c | 346 +---------------------------- arch/arm/mach-tegra/xusb-padctl-common.c | 305 +++++++++++++++++++++++++ arch/arm/mach-tegra/xusb-padctl-common.h | 103 +++++++++ 4 files changed, 414 insertions(+), 341 deletions(-) create mode 100644 arch/arm/mach-tegra/xusb-padctl-common.c create mode 100644 arch/arm/mach-tegra/xusb-padctl-common.h

diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index f577f459be0f..c00de6151e2d 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -11,6 +11,7 @@ obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o obj-y += xusb-padctl.o +obj-y += ../xusb-padctl-common.o

ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV7_NONSEC) += psci.o diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index ce857b8b05e9..b3715d8f47bc 100644 --- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -11,6 +11,8 @@ #include <fdtdec.h> #include <malloc.h>

+#include "../xusb-padctl-common.h" + #include <asm/io.h>

#include <asm/arch/clock.h> @@ -83,18 +85,6 @@ static const unsigned int tegra124_pci_functions[] = { TEGRA124_FUNC_RSVD, };

-struct tegra_xusb_padctl_lane { - const char *name; - - unsigned int offset; - unsigned int shift; - unsigned int mask; - unsigned int iddq; - - const unsigned int *funcs; - unsigned int num_funcs; -}; - #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ { \ .name = _name, \ @@ -121,74 +111,6 @@ static const struct tegra_xusb_padctl_lane tegra124_lanes[] = { TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci), };

-struct tegra_xusb_phy_ops { - int (*prepare)(struct tegra_xusb_phy *phy); - int (*enable)(struct tegra_xusb_phy *phy); - int (*disable)(struct tegra_xusb_phy *phy); - int (*unprepare)(struct tegra_xusb_phy *phy); -}; - -struct tegra_xusb_phy { - const struct tegra_xusb_phy_ops *ops; - - struct tegra_xusb_padctl *padctl; -}; - -struct tegra_xusb_padctl_pin { - const struct tegra_xusb_padctl_lane *lane; - - unsigned int func; - int iddq; -}; - -#define MAX_GROUPS 3 -#define MAX_PINS 6 - -struct tegra_xusb_padctl_group { - const char *name; - - const char *pins[MAX_PINS]; - unsigned int num_pins; - - const char *func; - int iddq; -}; - -struct tegra_xusb_padctl_config { - const char *name; - - struct tegra_xusb_padctl_group groups[MAX_GROUPS]; - unsigned int num_groups; -}; - -struct tegra_xusb_padctl { - struct fdt_resource regs; - - unsigned int enable; - - struct tegra_xusb_phy phys[2]; - - const struct tegra_xusb_padctl_lane *lanes; - unsigned int num_lanes; - - const char *const *functions; - unsigned int num_functions; - - struct tegra_xusb_padctl_config config; -}; - -static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, - unsigned long offset) -{ - return readl(padctl->regs.start + offset); -} - -static inline void padctl_writel(struct tegra_xusb_padctl *padctl, - u32 value, unsigned long offset) -{ - writel(value, padctl->regs.start + offset); -} - static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) { u32 value; @@ -380,7 +302,7 @@ static const struct tegra_xusb_phy_ops sata_phy_ops = { .unprepare = phy_unprepare, };

-static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) { +struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) { .phys = { [0] = { .ops = &pcie_phy_ops, @@ -391,214 +313,7 @@ static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) { }, };

-static const struct tegra_xusb_padctl_lane * -tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name) -{ - unsigned int i; - - for (i = 0; i < padctl->num_lanes; i++) - if (strcmp(name, padctl->lanes[i].name) == 0) - return &padctl->lanes[i]; - - return NULL; -} - -static int -tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, - struct tegra_xusb_padctl_group *group, - const void *fdt, int node) -{ - unsigned int i; - int len, err; - - group->name = fdt_get_name(fdt, node, &len); - - len = fdt_count_strings(fdt, node, "nvidia,lanes"); - if (len < 0) { - error("failed to parse "nvidia,lanes" property"); - return -EINVAL; - } - - group->num_pins = len; - - for (i = 0; i < group->num_pins; i++) { - err = fdt_get_string_index(fdt, node, "nvidia,lanes", i, - &group->pins[i]); - if (err < 0) { - error("failed to read string from "nvidia,lanes" property"); - return -EINVAL; - } - } - - group->num_pins = len; - - err = fdt_get_string(fdt, node, "nvidia,function", &group->func); - if (err < 0) { - error("failed to parse "nvidia,func" property"); - return -EINVAL; - } - - group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1); - - return 0; -} - -static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl, - const char *name) -{ - unsigned int i; - - for (i = 0; i < padctl->num_functions; i++) - if (strcmp(name, padctl->functions[i]) == 0) - return i; - - return -ENOENT; -} - -static int -tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl, - const struct tegra_xusb_padctl_lane *lane, - const char *name) -{ - unsigned int i; - int func; - - func = tegra_xusb_padctl_find_function(padctl, name); - if (func < 0) - return func; - - for (i = 0; i < lane->num_funcs; i++) - if (lane->funcs[i] == func) - return i; - - return -ENOENT; -} - -static int -tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl, - const struct tegra_xusb_padctl_group *group) -{ - unsigned int i; - - for (i = 0; i < group->num_pins; i++) { - const struct tegra_xusb_padctl_lane *lane; - unsigned int func; - u32 value; - - lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); - if (!lane) { - error("no lane for pin %s", group->pins[i]); - continue; - } - - func = tegra_xusb_padctl_lane_find_function(padctl, lane, - group->func); - if (func < 0) { - error("function %s invalid for lane %s: %d", - group->func, lane->name, func); - continue; - } - - value = padctl_readl(padctl, lane->offset); - - /* set pin function */ - value &= ~(lane->mask << lane->shift); - value |= func << lane->shift; - - /* - * Set IDDQ if supported on the lane and specified in the - * configuration. - */ - if (lane->iddq > 0 && group->iddq >= 0) { - if (group->iddq != 0) - value &= ~(1 << lane->iddq); - else - value |= 1 << lane->iddq; - } - - padctl_writel(padctl, value, lane->offset); - } - - return 0; -} - -static int -tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, - struct tegra_xusb_padctl_config *config) -{ - unsigned int i; - - for (i = 0; i < config->num_groups; i++) { - const struct tegra_xusb_padctl_group *group; - int err; - - group = &config->groups[i]; - - err = tegra_xusb_padctl_group_apply(padctl, group); - if (err < 0) { - error("failed to apply group %s: %d", group->name, err); - continue; - } - } - - return 0; -} - -static int -tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, - struct tegra_xusb_padctl_config *config, - const void *fdt, int node) -{ - int subnode; - - config->name = fdt_get_name(fdt, node, NULL); - - fdt_for_each_subnode(fdt, subnode, node) { - struct tegra_xusb_padctl_group *group; - int err; - - group = &config->groups[config->num_groups]; - - err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt, - subnode); - if (err < 0) { - error("failed to parse group %s", group->name); - return err; - } - - config->num_groups++; - } - - return 0; -} - -static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, - const void *fdt, int node) -{ - int subnode, err; - - err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs); - if (err < 0) { - error("registers not found"); - return err; - } - - fdt_for_each_subnode(fdt, subnode, node) { - struct tegra_xusb_padctl_config *config = &padctl->config; - - err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt, - subnode); - if (err < 0) { - error("failed to parse entry %s: %d", config->name, - err); - continue; - } - } - - return 0; -} - -static int process_nodes(const void *fdt, int nodes[], unsigned int count) +int process_nodes(const void *fdt, int nodes[], unsigned int count) { unsigned int i;

@@ -648,57 +363,6 @@ static int process_nodes(const void *fdt, int nodes[], unsigned int count) return 0; }

-struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type) -{ - struct tegra_xusb_phy *phy = NULL; - - switch (type) { - case TEGRA_XUSB_PADCTL_PCIE: - phy = &padctl->phys[0]; - phy->padctl = padctl; - break; - - case TEGRA_XUSB_PADCTL_SATA: - phy = &padctl->phys[1]; - phy->padctl = padctl; - break; - } - - return phy; -} - -int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) -{ - if (phy && phy->ops && phy->ops->prepare) - return phy->ops->prepare(phy); - - return phy ? -ENOSYS : -EINVAL; -} - -int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy) -{ - if (phy && phy->ops && phy->ops->enable) - return phy->ops->enable(phy); - - return phy ? -ENOSYS : -EINVAL; -} - -int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy) -{ - if (phy && phy->ops && phy->ops->disable) - return phy->ops->disable(phy); - - return phy ? -ENOSYS : -EINVAL; -} - -int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) -{ - if (phy && phy->ops && phy->ops->unprepare) - return phy->ops->unprepare(phy); - - return phy ? -ENOSYS : -EINVAL; -} - void tegra_xusb_padctl_init(const void *fdt) { int count, nodes[1]; diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c new file mode 100644 index 000000000000..18ad7bfbdc0f --- /dev/null +++ b/arch/arm/mach-tegra/xusb-padctl-common.c @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt + +#include <common.h> +#include <errno.h> + +#include "xusb-padctl-common.h" + +#include <asm/arch/clock.h> + +int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->prepare) + return phy->ops->prepare(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->enable) + return phy->ops->enable(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->disable) + return phy->ops->disable(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->unprepare) + return phy->ops->unprepare(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type) +{ + struct tegra_xusb_phy *phy; + int i; + + for (i = 0; i < padctl.socdata->num_phys; i++) { + phy = &padctl.socdata->phys[i]; + if (phy->type != type) + continue; + return phy; + } + + return NULL; +} + +static const struct tegra_xusb_padctl_lane * +tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name) +{ + unsigned int i; + + for (i = 0; i < padctl->socdata->num_lanes; i++) + if (strcmp(name, padctl->socdata->lanes[i].name) == 0) + return &padctl->socdata->lanes[i]; + + return NULL; +} + +static int +tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, + struct tegra_xusb_padctl_group *group, + const void *fdt, int node) +{ + unsigned int i; + int len, err; + + group->name = fdt_get_name(fdt, node, &len); + + len = fdt_count_strings(fdt, node, "nvidia,lanes"); + if (len < 0) { + error("failed to parse "nvidia,lanes" property"); + return -EINVAL; + } + + group->num_pins = len; + + for (i = 0; i < group->num_pins; i++) { + err = fdt_get_string_index(fdt, node, "nvidia,lanes", i, + &group->pins[i]); + if (err < 0) { + error("failed to read string from "nvidia,lanes" property"); + return -EINVAL; + } + } + + group->num_pins = len; + + err = fdt_get_string(fdt, node, "nvidia,function", &group->func); + if (err < 0) { + error("failed to parse "nvidia,func" property"); + return -EINVAL; + } + + group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1); + + return 0; +} + +static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl, + const char *name) +{ + unsigned int i; + + for (i = 0; i < padctl->socdata->num_functions; i++) + if (strcmp(name, padctl->socdata->functions[i]) == 0) + return i; + + return -ENOENT; +} + +static int +tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl, + const struct tegra_xusb_padctl_lane *lane, + const char *name) +{ + unsigned int i; + int func; + + func = tegra_xusb_padctl_find_function(padctl, name); + if (func < 0) + return func; + + for (i = 0; i < lane->num_funcs; i++) + if (lane->funcs[i] == func) + return i; + + return -ENOENT; +} + +static int +tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl, + const struct tegra_xusb_padctl_group *group) +{ + unsigned int i; + + for (i = 0; i < group->num_pins; i++) { + const struct tegra_xusb_padctl_lane *lane; + unsigned int func; + u32 value; + + lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); + if (!lane) { + error("no lane for pin %s", group->pins[i]); + continue; + } + + func = tegra_xusb_padctl_lane_find_function(padctl, lane, + group->func); + if (func < 0) { + error("function %s invalid for lane %s: %d", + group->func, lane->name, func); + continue; + } + + value = padctl_readl(padctl, lane->offset); + + /* set pin function */ + value &= ~(lane->mask << lane->shift); + value |= func << lane->shift; + + /* + * Set IDDQ if supported on the lane and specified in the + * configuration. + */ + if (lane->iddq > 0 && group->iddq >= 0) { + if (group->iddq != 0) + value &= ~(1 << lane->iddq); + else + value |= 1 << lane->iddq; + } + + padctl_writel(padctl, value, lane->offset); + } + + return 0; +} + +static int +tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, + struct tegra_xusb_padctl_config *config) +{ + unsigned int i; + + for (i = 0; i < config->num_groups; i++) { + const struct tegra_xusb_padctl_group *group; + int err; + + group = &config->groups[i]; + + err = tegra_xusb_padctl_group_apply(padctl, group); + if (err < 0) { + error("failed to apply group %s: %d", + group->name, err); + continue; + } + } + + return 0; +} + +static int +tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, + struct tegra_xusb_padctl_config *config, + const void *fdt, int node) +{ + int subnode; + + config->name = fdt_get_name(fdt, node, NULL); + + fdt_for_each_subnode(fdt, subnode, node) { + struct tegra_xusb_padctl_group *group; + int err; + + group = &config->groups[config->num_groups]; + + err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt, + subnode); + if (err < 0) { + error("failed to parse group %s", group->name); + return err; + } + + config->num_groups++; + } + + return 0; +} + +static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, + const void *fdt, int node) +{ + int subnode, err; + + err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs); + if (err < 0) { + error("registers not found"); + return err; + } + + fdt_for_each_subnode(fdt, subnode, node) { + struct tegra_xusb_padctl_config *config = &padctl->config; + + err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt, + subnode); + if (err < 0) { + error("failed to parse entry %s: %d", + config->name, err); + continue; + } + } + + return 0; +} + +struct tegra_xusb_padctl padctl; + +int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count, + const struct tegra_xusb_padctl_soc *socdata) +{ + unsigned int i; + int err; + + for (i = 0; i < count; i++) { + if (!fdtdec_get_is_enabled(fdt, nodes[i])) + continue; + + padctl.socdata = socdata; + + err = tegra_xusb_padctl_parse_dt(&padctl, fdt, nodes[i]); + if (err < 0) { + error("failed to parse DT: %d", err); + continue; + } + + /* deassert XUSB padctl reset */ + reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0); + + err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config); + if (err < 0) { + error("failed to apply pinmux: %d", err); + continue; + } + + /* only a single instance is supported */ + break; + } + + return 0; +} diff --git a/arch/arm/mach-tegra/xusb-padctl-common.h b/arch/arm/mach-tegra/xusb-padctl-common.h new file mode 100644 index 000000000000..a65b754f6b7d --- /dev/null +++ b/arch/arm/mach-tegra/xusb-padctl-common.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA_XUSB_PADCTL_COMMON_H_ +#define _TEGRA_XUSB_PADCTL_COMMON_H_ + +#include <common.h> +#include <fdtdec.h> + +#include <asm/io.h> +#include <asm/arch-tegra/xusb-padctl.h> + +struct tegra_xusb_padctl_lane { + const char *name; + + unsigned int offset; + unsigned int shift; + unsigned int mask; + unsigned int iddq; + + const unsigned int *funcs; + unsigned int num_funcs; +}; + +struct tegra_xusb_phy_ops { + int (*prepare)(struct tegra_xusb_phy *phy); + int (*enable)(struct tegra_xusb_phy *phy); + int (*disable)(struct tegra_xusb_phy *phy); + int (*unprepare)(struct tegra_xusb_phy *phy); +}; + +struct tegra_xusb_phy { + const struct tegra_xusb_phy_ops *ops; + + struct tegra_xusb_padctl *padctl; +}; + +struct tegra_xusb_padctl_pin { + const struct tegra_xusb_padctl_lane *lane; + + unsigned int func; + int iddq; +}; + +#define MAX_GROUPS 3 +#define MAX_PINS 6 + +struct tegra_xusb_padctl_group { + const char *name; + + const char *pins[MAX_PINS]; + unsigned int num_pins; + + const char *func; + int iddq; +}; + +struct tegra_xusb_padctl_config { + const char *name; + + struct tegra_xusb_padctl_group groups[MAX_GROUPS]; + unsigned int num_groups; +}; + +struct tegra_xusb_padctl { + struct fdt_resource regs; + + unsigned int enable; + + struct tegra_xusb_phy phys[2]; + + const struct tegra_xusb_padctl_lane *lanes; + unsigned int num_lanes; + + const char *const *functions; + unsigned int num_functions; + + struct tegra_xusb_padctl_config config; +}; + +static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, + unsigned long offset) +{ + return readl(padctl->regs.start + offset); +} + +static inline void padctl_writel(struct tegra_xusb_padctl *padctl, + u32 value, unsigned long offset) +{ + writel(value, padctl->regs.start + offset); +} + +extern struct tegra_xusb_padctl *padctl; + +int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, + const void *fdt, int node); +int tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, + struct tegra_xusb_padctl_config *config); + +#endif

From: Stephen Warren swarren@nvidia.com

There are some differences between the Tegra124 and Tegra210 XUSB padctl code. So far, the common XUSB padctl code only supports Tegra124. Add some parameters etc. so that it can work for both chips.

This also allows moving Tegra124's process_nodes() into the common file; something that would have requires edits during the move if done in the previous commit.

Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/tegra124/xusb-padctl.c | 84 +++++++----------------------- arch/arm/mach-tegra/xusb-padctl-common.h | 32 ++++++------ 2 files changed, 34 insertions(+), 82 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index b3715d8f47bc..76af924b948d 100644 --- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c @@ -8,16 +8,9 @@

#include <common.h> #include <errno.h> -#include <fdtdec.h> -#include <malloc.h>

#include "../xusb-padctl-common.h"

-#include <asm/io.h> - -#include <asm/arch/clock.h> -#include <asm/arch-tegra/xusb-padctl.h> - #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>

#define XUSB_PADCTL_ELPG_PROGRAM 0x01c @@ -302,66 +295,27 @@ static const struct tegra_xusb_phy_ops sata_phy_ops = { .unprepare = phy_unprepare, };

-struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) { - .phys = { - [0] = { - .ops = &pcie_phy_ops, - }, - [1] = { - .ops = &sata_phy_ops, - }, +static struct tegra_xusb_phy tegra124_phys[] = { + { + .type = TEGRA_XUSB_PADCTL_PCIE, + .ops = &pcie_phy_ops, + .padctl = &padctl, + }, + { + .type = TEGRA_XUSB_PADCTL_SATA, + .ops = &sata_phy_ops, + .padctl = &padctl, }, };

-int process_nodes(const void *fdt, int nodes[], unsigned int count) -{ - unsigned int i; - - for (i = 0; i < count; i++) { - enum fdt_compat_id id; - int err; - - if (!fdtdec_get_is_enabled(fdt, nodes[i])) - continue; - - id = fdtdec_lookup(fdt, nodes[i]); - switch (id) { - case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL: - break; - - default: - error("unsupported compatible: %s", - fdtdec_get_compatible(id)); - continue; - } - - padctl->num_lanes = ARRAY_SIZE(tegra124_lanes); - padctl->lanes = tegra124_lanes; - - padctl->num_functions = ARRAY_SIZE(tegra124_functions); - padctl->functions = tegra124_functions; - - err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]); - if (err < 0) { - error("failed to parse DT: %d", err); - continue; - } - - /* deassert XUSB padctl reset */ - reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0); - - err = tegra_xusb_padctl_config_apply(padctl, &padctl->config); - if (err < 0) { - error("failed to apply pinmux: %d", err); - continue; - } - - /* only a single instance is supported */ - break; - } - - return 0; -} +static const struct tegra_xusb_padctl_soc tegra124_socdata = { + .lanes = tegra124_lanes, + .num_lanes = ARRAY_SIZE(tegra124_lanes), + .functions = tegra124_functions, + .num_functions = ARRAY_SIZE(tegra124_functions), + .phys = tegra124_phys, + .num_phys = ARRAY_SIZE(tegra124_phys), +};

void tegra_xusb_padctl_init(const void *fdt) { @@ -370,6 +324,6 @@ void tegra_xusb_padctl_init(const void *fdt) count = fdtdec_find_aliases_for_id(fdt, "padctl", COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, nodes, ARRAY_SIZE(nodes)); - if (process_nodes(fdt, nodes, count)) + if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra124_socdata)) return; } diff --git a/arch/arm/mach-tegra/xusb-padctl-common.h b/arch/arm/mach-tegra/xusb-padctl-common.h index a65b754f6b7d..11ecb99b749d 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.h +++ b/arch/arm/mach-tegra/xusb-padctl-common.h @@ -33,8 +33,8 @@ struct tegra_xusb_phy_ops { };

struct tegra_xusb_phy { + unsigned int type; const struct tegra_xusb_phy_ops *ops; - struct tegra_xusb_padctl *padctl; };

@@ -58,6 +58,15 @@ struct tegra_xusb_padctl_group { int iddq; };

+struct tegra_xusb_padctl_soc { + const struct tegra_xusb_padctl_lane *lanes; + unsigned int num_lanes; + const char *const *functions; + unsigned int num_functions; + struct tegra_xusb_phy *phys; + unsigned int num_phys; +}; + struct tegra_xusb_padctl_config { const char *name;

@@ -66,20 +75,13 @@ struct tegra_xusb_padctl_config { };

struct tegra_xusb_padctl { + const struct tegra_xusb_padctl_soc *socdata; + struct tegra_xusb_padctl_config config; struct fdt_resource regs; - unsigned int enable;

- struct tegra_xusb_phy phys[2]; - - const struct tegra_xusb_padctl_lane *lanes; - unsigned int num_lanes; - - const char *const *functions; - unsigned int num_functions; - - struct tegra_xusb_padctl_config config; }; +extern struct tegra_xusb_padctl padctl;

static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, unsigned long offset) @@ -93,11 +95,7 @@ static inline void padctl_writel(struct tegra_xusb_padctl *padctl, writel(value, padctl->regs.start + offset); }

-extern struct tegra_xusb_padctl *padctl; - -int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, - const void *fdt, int node); -int tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, - struct tegra_xusb_padctl_config *config); +int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count, + const struct tegra_xusb_padctl_soc *socdata);

#endif

From: Stephen Warren swarren@nvidia.com

This change simply deletes code from the Tegra210 XUSB padctl driver that is already present in the common XUSB padctl code. Since all the arrays in tegra210_socdata are empty, this update may leave the Tegra210 XUSB padctl driver non-functional at run-time. However, (a) this driver is not used yet so no regression can be observed and (b) the next commit will immediately fix this up.

Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/tegra210/Makefile | 1 + arch/arm/mach-tegra/tegra210/xusb-padctl.c | 173 +++-------------------------- 2 files changed, 16 insertions(+), 158 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile index 1fb8d1ac7483..b6012fc7baac 100644 --- a/arch/arm/mach-tegra/tegra210/Makefile +++ b/arch/arm/mach-tegra/tegra210/Makefile @@ -9,3 +9,4 @@ obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o obj-y += xusb-padctl.o +obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 3c10a96aa396..503354344067 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -8,52 +8,13 @@

#include <common.h> #include <errno.h> -#include <fdtdec.h> -#include <malloc.h>

-#include <asm/io.h> +#include "../xusb-padctl-common.h"

#include <asm/arch/clock.h> -#include <asm/arch-tegra/xusb-padctl.h>

#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>

-struct tegra_xusb_phy_ops { - int (*prepare)(struct tegra_xusb_phy *phy); - int (*enable)(struct tegra_xusb_phy *phy); - int (*disable)(struct tegra_xusb_phy *phy); - int (*unprepare)(struct tegra_xusb_phy *phy); -}; - -struct tegra_xusb_phy { - const struct tegra_xusb_phy_ops *ops; - - struct tegra_xusb_padctl *padctl; -}; - -struct tegra_xusb_padctl { - struct fdt_resource regs; - - unsigned int enable; - - struct tegra_xusb_phy phys[2]; -}; - -static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, - unsigned long offset) -{ - u32 value = readl(padctl->regs.start + offset); - debug("padctl: %08lx > %08x\n", offset, value); - return value; -} - -static inline void padctl_writel(struct tegra_xusb_padctl *padctl, - u32 value, unsigned long offset) -{ - debug("padctl: %08lx < %08x\n", offset, value); - writel(value, padctl->regs.start + offset); -} - #define XUSB_PADCTL_ELPG_PROGRAM 0x024 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31) #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30) @@ -358,120 +319,22 @@ static const struct tegra_xusb_phy_ops pcie_phy_ops = { .unprepare = phy_unprepare, };

-static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) { - .phys = { - [0] = { - .ops = &pcie_phy_ops, - }, +static struct tegra_xusb_phy tegra210_phys[] = { + { + .type = TEGRA_XUSB_PADCTL_PCIE, + .ops = &pcie_phy_ops, + .padctl = &padctl, }, };

-static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, - const void *fdt, int node) -{ - int err; - - err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs); - if (err < 0) { - error("registers not found"); - return err; - } - - debug("regs: %pa-%pa\n", &padctl->regs.start, - &padctl->regs.end); - - return 0; -} - -static int process_nodes(const void *fdt, int nodes[], unsigned int count) -{ - unsigned int i; - int err; - - debug("> %s(fdt=%p, nodes=%p, count=%u)\n", __func__, fdt, nodes, - count); - - for (i = 0; i < count; i++) { - enum fdt_compat_id id; - - if (!fdtdec_get_is_enabled(fdt, nodes[i])) - continue; - - id = fdtdec_lookup(fdt, nodes[i]); - switch (id) { - case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL: - case COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL: - break; - - default: - error("unsupported compatible: %s", - fdtdec_get_compatible(id)); - continue; - } - - err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]); - if (err < 0) { - error("failed to parse DT: %d", - err); - continue; - } - - /* deassert XUSB padctl reset */ - reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0); - - /* only a single instance is supported */ - break; - } - - debug("< %s()\n", __func__); - return 0; -} - -struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type) -{ - struct tegra_xusb_phy *phy = NULL; - - switch (type) { - case TEGRA_XUSB_PADCTL_PCIE: - phy = &padctl->phys[0]; - phy->padctl = padctl; - break; - } - - return phy; -} - -int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) -{ - if (phy && phy->ops && phy->ops->prepare) - return phy->ops->prepare(phy); - - return phy ? -ENOSYS : -EINVAL; -} - -int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy) -{ - if (phy && phy->ops && phy->ops->enable) - return phy->ops->enable(phy); - - return phy ? -ENOSYS : -EINVAL; -} - -int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy) -{ - if (phy && phy->ops && phy->ops->disable) - return phy->ops->disable(phy); - - return phy ? -ENOSYS : -EINVAL; -} - -int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) -{ - if (phy && phy->ops && phy->ops->unprepare) - return phy->ops->unprepare(phy); - - return phy ? -ENOSYS : -EINVAL; -} +static const struct tegra_xusb_padctl_soc tegra210_socdata = { + .lanes = NULL, + .num_lanes = 0, + .functions = NULL, + .num_functions = 0, + .phys = tegra210_phys, + .num_phys = ARRAY_SIZE(tegra210_phys), +};

void tegra_xusb_padctl_init(const void *fdt) { @@ -482,13 +345,7 @@ void tegra_xusb_padctl_init(const void *fdt) count = fdtdec_find_aliases_for_id(fdt, "padctl", COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, nodes, ARRAY_SIZE(nodes)); - if (process_nodes(fdt, nodes, count)) - return; - - count = fdtdec_find_aliases_for_id(fdt, "padctl", - COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, - nodes, ARRAY_SIZE(nodes)); - if (process_nodes(fdt, nodes, count)) + if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata)) return;

debug("< %s()\n", __func__);

From: Stephen Warren swarren@nvidia.com

Add the tables defining which pads and mux options exist in the Tegra210 XUSB padctl hardware.

Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 78 ++++++++++++++++++++++++++++-- arch/arm/mach-tegra/xusb-padctl-common.h | 4 +- 2 files changed, 76 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 503354344067..6022f1614bda 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -15,6 +15,76 @@

#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>

+enum tegra210_function { + TEGRA210_FUNC_SNPS, + TEGRA210_FUNC_XUSB, + TEGRA210_FUNC_UART, + TEGRA210_FUNC_PCIE_X1, + TEGRA210_FUNC_PCIE_X4, + TEGRA210_FUNC_USB3, + TEGRA210_FUNC_SATA, + TEGRA210_FUNC_RSVD, +}; + +static const char *const tegra210_functions[] = { + "snps", + "xusb", + "uart", + "pcie-x1", + "pcie-x4", + "usb3", + "sata", + "rsvd", +}; + +static const unsigned int tegra210_otg_functions[] = { + TEGRA210_FUNC_SNPS, + TEGRA210_FUNC_XUSB, + TEGRA210_FUNC_UART, + TEGRA210_FUNC_RSVD, +}; + +static const unsigned int tegra210_usb_functions[] = { + TEGRA210_FUNC_SNPS, + TEGRA210_FUNC_XUSB, +}; + +static const unsigned int tegra210_pci_functions[] = { + TEGRA210_FUNC_PCIE_X1, + TEGRA210_FUNC_USB3, + TEGRA210_FUNC_SATA, + TEGRA210_FUNC_PCIE_X4, +}; + +#define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ + { \ + .name = _name, \ + .offset = _offset, \ + .shift = _shift, \ + .mask = _mask, \ + .iddq = _iddq, \ + .num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions), \ + .funcs = tegra210_##_funcs##_functions, \ + } + +static const struct tegra_xusb_padctl_lane tegra210_lanes[] = { + TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg), + TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg), + TEGRA210_LANE("otg-2", 0x004, 4, 0x3, 0, otg), + TEGRA210_LANE("otg-3", 0x004, 6, 0x3, 0, otg), + TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg), + TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, 0, usb), + TEGRA210_LANE("hsic-1", 0x004, 15, 0x1, 0, usb), + TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, 1, pci), + TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, 2, pci), + TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, 3, pci), + TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, 4, pci), + TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, 5, pci), + TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, 6, pci), + TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, 7, pci), + TEGRA210_LANE("sata-0", 0x028, 30, 0x3, 8, pci), +}; + #define XUSB_PADCTL_ELPG_PROGRAM 0x024 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31) #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30) @@ -328,10 +398,10 @@ static struct tegra_xusb_phy tegra210_phys[] = { };

static const struct tegra_xusb_padctl_soc tegra210_socdata = { - .lanes = NULL, - .num_lanes = 0, - .functions = NULL, - .num_functions = 0, + .lanes = tegra210_lanes, + .num_lanes = ARRAY_SIZE(tegra210_lanes), + .functions = tegra210_functions, + .num_functions = ARRAY_SIZE(tegra210_functions), .phys = tegra210_phys, .num_phys = ARRAY_SIZE(tegra210_phys), }; diff --git a/arch/arm/mach-tegra/xusb-padctl-common.h b/arch/arm/mach-tegra/xusb-padctl-common.h index 11ecb99b749d..f44790a65004 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.h +++ b/arch/arm/mach-tegra/xusb-padctl-common.h @@ -45,8 +45,8 @@ struct tegra_xusb_padctl_pin { int iddq; };

-#define MAX_GROUPS 3 -#define MAX_PINS 6 +#define MAX_GROUPS 5 +#define MAX_PINS 7

struct tegra_xusb_padctl_group { const char *name;

From: Stephen Warren swarren@nvidia.com

Add code to detect timeouts when waiting for HW events such as PLL lock done. Any errors are logged and trigger an error return code.

Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 6022f1614bda..9ec93e7c4c4c 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -279,7 +279,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) break; } - + if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) { + debug(" timeout\n"); + return -ETIMEDOUT; + } debug(" done\n");

value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); @@ -295,7 +298,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0) break; } - + if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) { + debug(" timeout\n"); + return -ETIMEDOUT; + } debug(" done\n");

value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); @@ -310,7 +316,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS) break; } - + if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) { + debug(" timeout\n"); + return -ETIMEDOUT; + } debug(" done\n");

value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); @@ -326,7 +335,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) break; } - + if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) { + debug(" timeout\n"); + return -ETIMEDOUT; + } debug(" done\n");

value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); @@ -341,7 +353,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0) break; } - + if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) { + debug(" timeout\n"); + return -ETIMEDOUT; + } debug(" done\n");

value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);

On 23 October 2015 at 10:50, Stephen Warren swarren@wwwdotorg.org wrote:

From: Stephen Warren swarren@nvidia.com

A future patch will soon move some of the XUSB padctl code into a common file in arch/arm/mach-tegra. Rename the existing dummy XUSB padctl file to avoid conflicting with that, or being confusing.

Signed-off-by: Stephen Warren swarren@nvidia.com

arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/{xusb-padctl.c => xusb-padctl-dummy.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/mach-tegra/{xusb-padctl.c => xusb-padctl-dummy.c} (100%)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 98431a91f875..2be6ef41fff6 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -23,7 +23,7 @@ obj-y += clock.o obj-y += lowlevel_init.o obj-y += pinmux-common.o obj-y += powergate.o -obj-y += xusb-padctl.o +obj-y += xusb-padctl-dummy.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o diff --git a/arch/arm/mach-tegra/xusb-padctl.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c similarity index 100% rename from arch/arm/mach-tegra/xusb-padctl.c rename to arch/arm/mach-tegra/xusb-padctl-dummy.c -- 1.9.1

Reviewed-by: Simon Glass sjg@chromium.org