[U-Boot] [PATCH 1/2] powerpc/p2040: Add various p2040 specific information
From: Mingkai Hu Mingkai.hu@freescale.com
Add P2040 SoC specific information: * LIODN setup * Portal configuration * etc
Signed-off-by: Mingkai Hu Mingkai.hu@freescale.com Signed-off-by: Roy Zang tie-fei.zang@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/Makefile | 3 + arch/powerpc/cpu/mpc85xx/p2040_ids.c | 103 +++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/p2040_serdes.c | 24 +++++++ 3 files changed, 130 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/p2040_ids.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index d61d34c..37667db 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -64,6 +64,7 @@ COBJS-$(CONFIG_P1024) += ddr-gen3.o COBJS-$(CONFIG_P1025) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P2040) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o @@ -76,6 +77,7 @@ COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments +COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o @@ -107,6 +109,7 @@ COBJS-$(CONFIG_P1024) += p1021_serdes.o COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o +COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/p2040_ids.c b/arch/powerpc/cpu/mpc85xx/p2040_ids.c new file mode 100644 index 0000000..599f09e --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p2040_ids.c @@ -0,0 +1,103 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO( 0, 0, 0, 5), + SET_QP_INFO( 0, 0, 0, 6), + SET_QP_INFO( 0, 0, 0, 7), + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ +}; + +struct liodn_id_table liodn_tbl[] = { + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), + + SET_SDHC_LIODN(1, 64), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 125), + SET_USB_LIODN(2, "fsl-usb2-dr", 126), + + SET_SATA_LIODN(1, 127), + SET_SATA_LIODN(2, 128), + + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + + SET_DMA_LIODN(1, 197), + SET_DMA_LIODN(2, 198), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +}; + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 10), + SET_FMAN_RX_1G_LIODN(1, 1, 11), + SET_FMAN_RX_1G_LIODN(1, 2, 12), + SET_FMAN_RX_1G_LIODN(1, 3, 13), + SET_FMAN_RX_1G_LIODN(1, 4, 14), +}; +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 154), + SET_SEC_RTIC_LIODN_ENTRY(b, 155), + SET_SEC_RTIC_LIODN_ENTRY(c, 156), + SET_SEC_RTIC_LIODN_ENTRY(d, 157), + SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), + SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), +}; + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), +#endif +}; + +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c index a96eff4..83bc82f 100644 --- a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c @@ -36,6 +36,9 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, + [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, NONE, }, [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, NONE, NONE, }, @@ -49,6 +52,12 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, + [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE, + NONE, NONE, NONE, NONE, NONE, }, + [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, + NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, @@ -64,3 +73,18 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
return serdes_cfg_tbl[cfg][lane]; } + +int is_serdes_prtcl_valid(u32 prtcl) +{ + int i; + + if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +}
The P2041 is similar to P2040, however has a 10G port and backside L2
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/Makefile | 3 +++ arch/powerpc/cpu/mpc85xx/p2040_ids.c | 3 +++ arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++ arch/powerpc/include/asm/config_mpc85xx.h | 15 +++++++++++++++ arch/powerpc/include/asm/processor.h | 2 ++ 5 files changed, 25 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 37667db..8a0a8e9 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -65,6 +65,7 @@ COBJS-$(CONFIG_P1025) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P2040) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o @@ -78,6 +79,7 @@ COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o +COBJS-$(CONFIG_PPC_P2041) += p2040_ids.o COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o @@ -110,6 +112,7 @@ COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o +COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/p2040_ids.c b/arch/powerpc/cpu/mpc85xx/p2040_ids.c index 599f09e..be6a381 100644 --- a/arch/powerpc/cpu/mpc85xx/p2040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2040_ids.c @@ -72,6 +72,9 @@ struct liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 2, 12), SET_FMAN_RX_1G_LIODN(1, 3, 13), SET_FMAN_RX_1G_LIODN(1, 4, 14), +#if (CONFIG_SYS_NUM_FM1_10GEC == 1) + SET_FMAN_RX_10G_LIODN(1, 0, 15), +#endif }; #endif
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 39b304a..85ebcc9 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -98,6 +98,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2020, P2020_E, 2), CPU_TYPE_ENTRY(P2040, P2040, 4), CPU_TYPE_ENTRY(P2040, P2040_E, 4), + CPU_TYPE_ENTRY(P2041, P2041, 4), + CPU_TYPE_ENTRY(P2041, P2041_E, 4), CPU_TYPE_ENTRY(P3041, P3041, 4), CPU_TYPE_ENTRY(P3041, P3041_E, 4), CPU_TYPE_ENTRY(P4040, P4040, 4), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 41c2d20..1b440d0 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -269,6 +269,21 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#elif defined(CONFIG_PPC_P2041) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index c5b03b4..9c4651a 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1103,6 +1103,8 @@ #define SVR_P2020_E 0x80EA00 #define SVR_P2040 0x821000 #define SVR_P2040_E 0x821800 +#define SVR_P2041 0x821001 +#define SVR_P2041_E 0x821801 #define SVR_P3041 0x821103 #define SVR_P3041_E 0x821903 #define SVR_P4040 0x820100
On May 13, 2011, at 2:18 AM, Kumar Gala wrote:
The P2041 is similar to P2040, however has a 10G port and backside L2
Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/cpu/mpc85xx/Makefile | 3 +++ arch/powerpc/cpu/mpc85xx/p2040_ids.c | 3 +++ arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++ arch/powerpc/include/asm/config_mpc85xx.h | 15 +++++++++++++++ arch/powerpc/include/asm/processor.h | 2 ++ 5 files changed, 25 insertions(+), 0 deletions(-)
applied to 85xx
- k
On May 13, 2011, at 2:18 AM, Kumar Gala wrote:
From: Mingkai Hu Mingkai.hu@freescale.com
Add P2040 SoC specific information:
- LIODN setup
- Portal configuration
- etc
Signed-off-by: Mingkai Hu Mingkai.hu@freescale.com Signed-off-by: Roy Zang tie-fei.zang@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/cpu/mpc85xx/Makefile | 3 + arch/powerpc/cpu/mpc85xx/p2040_ids.c | 103 +++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/p2040_serdes.c | 24 +++++++ 3 files changed, 130 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/p2040_ids.c
applied to 85xx
- k
participants (1)
-
Kumar Gala