From: Marcel Ziswiler marcel@ziswiler.com

The anadig_reg structure started at the wrong offset (fixed by adding reserved_0x000[4]), was missing some reserved field required for alignment purpose (reserved_0x094[3] between pll4_denom and pll6_ctrl) and further contained a too short reserved field causing further miss- alignment (reserved_0x0C4[7]). Also, rename all the reserved fields and using a memory offset based scheme for.

Discovered and tested by temporarily putting the following debug instrumentation into board_init(): struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl); printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl);

Signed-off-by: Marcel Ziswiler marcel@ziswiler.com [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner stefan@agner.ch --- arch/arm/include/asm/arch-vf610/crm_regs.h | 52 ++++++++++++++++-------------- 1 file changed, 27 insertions(+), 25 deletions(-)

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 85f1fda..2d7a32d 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -55,57 +55,59 @@ struct ccm_reg {

/* Analog components control digital interface (ANADIG) */ struct anadig_reg { + u32 reserved_0x000[4]; u32 pll3_ctrl; - u32 resv0[3]; + u32 reserved_0x014[3]; u32 pll7_ctrl; - u32 resv1[3]; + u32 reserved_0x024[3]; u32 pll2_ctrl; - u32 resv2[3]; + u32 reserved_0x034[3]; u32 pll2_ss; - u32 resv3[3]; + u32 reserved_0x044[3]; u32 pll2_num; - u32 resv4[3]; + u32 reserved_0x054[3]; u32 pll2_denom; - u32 resv5[3]; + u32 reserved_0x064[3]; u32 pll4_ctrl; - u32 resv6[3]; + u32 reserved_0x074[3]; u32 pll4_num; - u32 resv7[3]; + u32 reserved_0x084[3]; u32 pll4_denom; + u32 reserved_0x094[3]; u32 pll6_ctrl; - u32 resv8[3]; + u32 reserved_0x0A4[3]; u32 pll6_num; - u32 resv9[3]; + u32 reserved_0x0B4[3]; u32 pll6_denom; - u32 resv10[3]; + u32 reserved_0x0C4[7]; u32 pll5_ctrl; - u32 resv11[3]; + u32 reserved_0x0E4[3]; u32 pll3_pfd; - u32 resv12[3]; + u32 reserved_0x0F4[3]; u32 pll2_pfd; - u32 resv13[3]; + u32 reserved_0x104[3]; u32 reg_1p1; - u32 resv14[3]; + u32 reserved_0x114[3]; u32 reg_3p0; - u32 resv15[3]; + u32 reserved_0x124[3]; u32 reg_2p5; - u32 resv16[7]; + u32 reserved_0x134[7]; u32 ana_misc0; - u32 resv17[3]; + u32 reserved_0x154[3]; u32 ana_misc1; - u32 resv18[63]; + u32 reserved_0x164[63]; u32 anadig_digprog; - u32 resv19[3]; + u32 reserved_0x264[3]; u32 pll1_ctrl; - u32 resv20[3]; + u32 reserved_0x274[3]; u32 pll1_ss; - u32 resv21[3]; + u32 reserved_0x284[3]; u32 pll1_num; - u32 resv22[3]; + u32 reserved_0x294[3]; u32 pll1_denom; - u32 resv23[3]; + u32 reserved_0x2A4[3]; u32 pll1_pdf; - u32 resv24[3]; + u32 reserved_0x2B4[3]; u32 pll_lock; }; #endif