[U-Boot] [RFC] ARM: omap3: Add option to disable errata workarounds.
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear. So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism?
regards, Andreas
PS. Does anybody have the "ARM Core Cortex-A8 (AT400/AT401) errata" document to make sure my assumption above holds true?
--- arch/arm/cpu/armv7/omap3/board.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index b72fadc..84045d8 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -236,8 +236,10 @@ void s_init(void)
try_unlock_memory();
+#ifndef CONFIG_SYS_DISABLE_CORTEXA8_ERRATA_WORKAROUNDS /* Errata workarounds */ omap3_setup_aux_cr(); +#endif
#ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */
Hi Andreas,
On Tue, 09 Jul 2013 10:08:10 +0200, Andreas Naumann dev@andin.de wrote:
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear. So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism?
regards, Andreas
PS. Does anybody have the "ARM Core Cortex-A8 (AT400/AT401) errata" document to make sure my assumption above holds true?
arch/arm/cpu/armv7/omap3/board.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index b72fadc..84045d8 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -236,8 +236,10 @@ void s_init(void)
try_unlock_memory();
+#ifndef CONFIG_SYS_DISABLE_CORTEXA8_ERRATA_WORKAROUNDS /* Errata workarounds */ omap3_setup_aux_cr(); +#endif
#ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */
Two remarks:
1. I would prefer the option to be the other way around, i.e. forcing the inclusion of the workaround when defined rather than when not defined; e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATA
2. (if applicable) I would prefer erratum-specific options, e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATUM_430973 -- ok, "ERRATA" will be fine too; what I want is easing the search for errata by number.
Amicalement,
Hi Andreas,
On 07/09/2013 11:10 AM, Albert ARIBAUD wrote:
Hi Andreas,
On Tue, 09 Jul 2013 10:08:10 +0200, Andreas Naumann dev@andin.de wrote:
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that.
So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism?
regards, Andreas
PS. Does anybody have the "ARM Core Cortex-A8 (AT400/AT401) errata" document to make sure my assumption above holds true?
I have rev 20.0 from 13-Apr-10. The three mentioned errata should be fixed in r2p1.
<snip>
Two remarks:
- I would prefer the option to be the other way around, i.e. forcing
the inclusion of the workaround when defined rather than when not defined; e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATA
- (if applicable) I would prefer erratum-specific options, e.g.
CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATUM_430973 -- ok, "ERRATA" will be fine too; what I want is easing the search for errata by number.
I join Albert's suggestion. Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary.
Best regards
Andreas Bießmann
Hi Andreas,
On Tue, 09 Jul 2013 12:42:27 +0200, "Andreas Bießmann" andreas.devel@googlemail.com wrote:
Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary.
Seconded.
Best regards
Andreas Bießmann
Amicalement,
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that.
I dont know what bootloader the guy used, but he states that he needs to enable the errata fix in the kernel for the segfaults to disappear. I found exactly the same: Initially I had no errata fixes configured for the kernel, only when I added them the segfaults disappeared. However they also disappear if I remove the workarounds from kernel as well as u-boot, hence this patch.
So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism?
regards, Andreas
PS. Does anybody have the "ARM Core Cortex-A8 (AT400/AT401) errata" document to make sure my assumption above holds true?
I have rev 20.0 from 13-Apr-10. The three mentioned errata should be fixed in r2p1.
<snip>
Two remarks:
- I would prefer the option to be the other way around, i.e. forcing
the inclusion of the workaround when defined rather than when not defined; e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATA
If we do that, lots of board configs have to be adapted. People who have custom configs probably wont notice and loose their apropriate errata handling.
- (if applicable) I would prefer erratum-specific options, e.g.
CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATUM_430973 -- ok, "ERRATA" will be fine too; what I want is easing the search for errata by number.
I join Albert's suggestion. Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary.
So I'd rather do that, but can we map the ARM revision e.g. r2p1 to the TI die versions ES1.0, 1.1 and so on? Or can the ARM revision be read directly?
cheers, Andreas
Hi Andreas,
On 07/09/2013 05:01 PM, Andreas Naumann wrote:
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that.
I dont know what bootloader the guy used, but he states that he needs to enable the errata fix in the kernel for the segfaults to disappear. I found exactly the same: Initially I had no errata fixes configured for the kernel, only when I added them the segfaults disappeared. However they also disappear if I remove the workarounds from kernel as well as u-boot, hence this patch.
Ok, understand.
<snip>
I join Albert's suggestion. Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary.
So I'd rather do that, but can we map the ARM revision e.g. r2p1 to the TI die versions ES1.0, 1.1 and so on? Or can the ARM revision be read directly?
You should use the ARM revisions. They are available, but dunno how:
---8<--- ~ cat /proc/cpuinfo Processor : ARMv7 Processor rev 2 (v7l) BogoMIPS : 512.57 Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x3 CPU part : 0xc08 CPU revision : 2 --->8---
AFAIK is CPU variant 'r3' and CPU revision 'p2' for this cpuinfo.
Regards
Andreas Bießmann
Hello,
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that.
#430973 is still needed on latest Cortex-A8 silicon of DM3730 according to my testing; this is in contradiction to what TI and ARM claim
I dont know what bootloader the guy used, but he states that he needs to enable the errata fix in the kernel for the segfaults to disappear. I
the guy used u-boot 2012.10 and linux 3.7 :)
found exactly the same: Initially I had no errata fixes configured for the kernel, only when I added them the segfaults disappeared. However they also disappear if I remove the workarounds from kernel as well as u-boot, hence this patch.
interesting; I did not consider this dependency between u-boot and kernel here; will try it
regards, p.
participants (4)
-
Albert ARIBAUD -
Andreas Bießmann -
Andreas Naumann -
Peter Meerwald