On 11/13/2017 10:47 AM, Eugeniy Paltsev wrote:

Implement dw_spi_get_clk function to override its weak implementation in designware_spi.c driver.

We need this change to get rid of cm_get_spi_controller_clk_hz function and clock_manager.h include in designware_spi.c driver.

Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com

Reviewed-by: Marek Vasut marex@denx.de

---

arch/arm/mach-socfpga/clock_manager_arria10.c | 9 +++++++++ arch/arm/mach-socfpga/clock_manager_gen5.c | 9 +++++++++ 2 files changed, 18 insertions(+)

diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 482b854..623a266 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -7,6 +7,7 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> +#include <dm.h> #include <asm/arch/clock_manager.h>

DECLARE_GLOBAL_DATA_PTR; @@ -1076,6 +1077,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void) return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); }

+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */ +int dw_spi_get_clk(struct udevice *bus, ulong *rate) +{

• *rate = cm_get_spi_controller_clk_hz();
• return 0;

+}

void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 31fd510..a371d83 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -6,6 +6,7 @@

#include <common.h> #include <asm/io.h> +#include <dm.h> #include <asm/arch/clock_manager.h> #include <wait_bit.h>

@@ -509,6 +510,14 @@ unsigned int cm_get_spi_controller_clk_hz(void) return clock; }

+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */ +int dw_spi_get_clk(struct udevice *bus, ulong *rate) +{

• *rate = cm_get_spi_controller_clk_hz();
• return 0;

+}

void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);

On 11/13/2017 10:47 AM, Eugeniy Paltsev wrote:

Add option to set spi controller clock frequency via device tree using standard clock bindings.

Define dw_spi_get_clk function as 'weak' as some targets (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API

^ don't ... detail

and implement dw_spi_get_clk their own way in their clock manager.

Get rid of clock_manager.h include as we don't use cm_get_spi_controller_clk_hz function anymore. (we use redefined dw_spi_get_clk in SOCFPGA clock managers instead)

Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com

drivers/spi/designware_spi.c | 46 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 6cc4f51..5460ad7 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -12,6 +12,7 @@

#include <asm-generic/gpio.h> #include <common.h> +#include <clk.h> #include <dm.h> #include <errno.h> #include <malloc.h> @@ -19,7 +20,6 @@ #include <fdtdec.h> #include <linux/compat.h> #include <asm/io.h> -#include <asm/arch/clock_manager.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -95,6 +95,7 @@ struct dw_spi_priv { void __iomem *regs; unsigned int freq; /* Default frequency */ unsigned int mode;

• unsigned long bus_clk_rate;

  struct gpio_desc cs_gpio; /* External chip-select gpio */

@@ -195,14 +196,55 @@ static void spi_hw_init(struct dw_spi_priv *priv) debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); }

+/*

• • We define dw_spi_get_clk function as 'weak' as some targets
• • (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
• • and implement dw_spi_get_clk their own way in their clock manager.
• */

+__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate) +{ +#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)

You can drop this ifdef IMO, this code will be overridden on SoCFPGA and all the other systems should use DT and clock framework.

• struct clk clk;
• int ret;
• ret = clk_get_by_index(bus, 0, &clk);
• if (ret)

• return -EINVAL;
  

• ret = clk_enable(&clk);
• if (ret && ret != -ENOSYS)

• return ret;
  

• *rate = clk_get_rate(&clk);
• if (!*rate) {

• clk_disable(&clk);
  

• return -EINVAL;
  

• }
• debug("%s: get spi controller clk via device tree: %lu Hz\n",

•      __func__, *rate);
  

• clk_free(&clk);
• return 0;

+#else

• return -ENOSYS;

+#endif +}

static int dw_spi_probe(struct udevice *bus) { struct dw_spi_platdata *plat = dev_get_platdata(bus); struct dw_spi_priv *priv = dev_get_priv(bus);

• int ret;

  priv->regs = plat->regs; priv->freq = plat->frequency;

• ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);

• if (ret)

• return ret;
  

• /* Currently only bits_per_word == 8 supported */ priv->bits_per_word = 8;

@@ -411,7 +453,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed) spi_enable_chip(priv, 0);

/* clk_div doesn't support odd number */

• clk_div = cm_get_spi_controller_clk_hz() / speed;

• clk_div = priv->bus_clk_rate / speed; clk_div = (clk_div + 1) & 0xfffe; dw_write(priv, DW_SPI_BAUDR, clk_div);