[PATCH v3 0/7] add ArmSoM Sige7 Rk3588 board
Devicetree of ArmSoM Sige7 is merged to kernel v6.10-rc1 with USBDP and GPU nodes. So I use update-dts-subtree.sh to pick related commits of rk3588s.dtsi, and then pick the commit of ArmSoM Sige7's devicetree. I also did run command: ./dts/update-dts-subtree.sh pull v6.10-rc1-dts based on my work but there is a merge conflict of file: dts/upstream/Bindings/Makefile I think this should not be related to my work.
Changes in v3: - Use update-dts-subtree.sh to pick upstream dts
Changes in v2: - Fix alphabetical order of MAINTAINERS - Use arch/arm/dts/rk3588-armsom-sige7* in board MAINTAINERS - Remove spi flash related config - Move kernel dts to dts/upstream/src/arm64/rockchip/
Boris Brezillon (1): arm64: dts: rockchip: Add rk3588 GPU node
Diederik de Haas (1): arm64: dts: rockchip: Fix ordering of nodes on rk3588s
Jianfeng Liu (2): arm64: dts: rockchip: Add ArmSom Sige7 board board: rockchip: add ArmSoM Sige7 Rk3588 board
Sebastian Reichel (3): arm64: dts: rockchip: fix usb2phy nodename for rk3588 arm64: dts: rockchip: add USBDP phys on rk3588 arm64: dts: rockchip: add USB3 DRD controllers on rk3588
MAINTAINERS | 1 + arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi | 28 + arch/arm/mach-rockchip/rk3588/Kconfig | 26 + board/armsom/sige7-rk3588/Kconfig | 12 + board/armsom/sige7-rk3588/MAINTAINERS | 7 + configs/sige7-rk3588_defconfig | 93 +++ doc/board/rockchip/rockchip.rst | 1 + .../arm64/rockchip/rk3588-armsom-sige7.dts | 721 ++++++++++++++++++ dts/upstream/src/arm64/rockchip/rk3588.dtsi | 72 ++ dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 337 +++++--- include/configs/sige7-rk3588.h | 15 + 11 files changed, 1215 insertions(+), 98 deletions(-) create mode 100644 arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi create mode 100644 board/armsom/sige7-rk3588/Kconfig create mode 100644 board/armsom/sige7-rk3588/MAINTAINERS create mode 100644 configs/sige7-rk3588_defconfig create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts create mode 100644 include/configs/sige7-rk3588.h
From: Boris Brezillon boris.brezillon@collabora.com
Add Mali GPU Node to the RK3588 SoC DT including GPU clock operating points
Signed-off-by: Boris Brezillon boris.brezillon@collabora.com Signed-off-by: Sebastian Reichel sebastian.reichel@collabora.com Link: https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reichel@collabora... Signed-off-by: Heiko Stuebner heiko@sntech.de
[ upstream commit: 6fca4edb93d335f29f81e484936f38a5eed6a9b1 ]
(cherry picked from commit 3cd15354ea0c8668812bc0b3a4136606c10803e9) Signed-off-by: Jianfeng Liu liujianfeng1994@gmail.com ---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 87b83c87bd5..89d40cff635 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -501,6 +501,62 @@ status = "disabled"; };
+ gpu: gpu@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells = <2>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names = "core", "coregroup", "stacks"; + dynamic-power-coefficient = <2982>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; + }; + pmu1grf: syscon@fd58a000 { compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfd58a000 0x0 0x10000>;
From: Diederik de Haas didi.debian@cknow.org
Fix the ordering of the main nodes by sorting them alphabetically and then the ones with a memory address sequentially by that address.
Signed-off-by: Diederik de Haas didi.debian@cknow.org Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner heiko@sntech.de
[ upstream commit: cbb97fe18e299ece1c0074924c630de6a19b320f ]
(cherry picked from commit bbf7c16f2f1208b96349f6f6648b69cfaa1a482b) Signed-off-by: Jianfeng Liu liujianfeng1994@gmail.com ---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 304 +++++++++---------- 1 file changed, 152 insertions(+), 152 deletions(-)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 89d40cff635..ac5bd630f15 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -347,6 +347,11 @@ }; };
+ display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + firmware { optee: optee { compatible = "linaro,optee-tz"; @@ -394,11 +399,6 @@ #clock-cells = <0>; };
- display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, @@ -436,6 +436,62 @@ }; };
+ gpu: gpu@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells = <2>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names = "core", "coregroup", "stacks"; + dynamic-power-coefficient = <2982>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; + }; + usb_host0_ehci: usb@fc800000 { compatible = "rockchip,rk3588-ehci", "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>; @@ -501,62 +557,6 @@ status = "disabled"; };
- gpu: gpu@fb000000 { - compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; - reg = <0x0 0xfb000000 0x0 0x200000>; - #cooling-cells = <2>; - assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; - assigned-clock-rates = <200000000>; - clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - clock-names = "core", "coregroup", "stacks"; - dynamic-power-coefficient = <2982>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "job", "mmu", "gpu"; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3588_PD_GPU>; - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <700000 700000 850000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <750000 750000 850000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <800000 800000 850000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <850000 850000 850000>; - }; - }; - }; - pmu1grf: syscon@fd58a000 { compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfd58a000 0x0 0x10000>; @@ -702,74 +702,6 @@ status = "disabled"; };
- vop: vop@fdd90000 { - compatible = "rockchip,rk3588-vop"; - reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_VOP>, - <&cru HCLK_VOP>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; - clock-names = "aclk", - "hclk", - "dclk_vp0", - "dclk_vp1", - "dclk_vp2", - "dclk_vp3", - "pclk_vop"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; - rockchip,grf = <&sys_grf>; - rockchip,vop-grf = <&vop_grf>; - rockchip,vo1-grf = <&vo1_grf>; - rockchip,pmu = <&pmu>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - vp1: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - vp2: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - vp3: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - vop_mmu: iommu@fdd97e00 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; - interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3588_PD_VOP>; - status = "disabled"; - }; - uart0: serial@fd890000 { compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; reg = <0x0 0xfd890000 0x0 0x100>; @@ -1140,6 +1072,87 @@ }; };
+ av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "vdpu"; + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + assigned-clock-rates = <400000000>, <400000000>; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3588_PD_AV1>; + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; + }; + + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VOP>; + status = "disabled"; + }; + i2s4_8ch: i2s@fddc0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc0000 0x0 0x1000>; @@ -1431,6 +1444,16 @@ reg = <0x0 0xfdf82200 0x0 0x20>; };
+ dfi: dfi@fe060000 { + reg = <0x00 0xfe060000 0x00 0x10000>; + compatible = "rockchip,rk3588-dfi"; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; + rockchip,pmu = <&pmu1grf>; + }; + pcie2x1l1: pcie@fe180000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; bus-range = <0x30 0x3f>; @@ -1533,16 +1556,6 @@ }; };
- dfi: dfi@fe060000 { - reg = <0x00 0xfe060000 0x00 0x10000>; - compatible = "rockchip,rk3588-dfi"; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; - rockchip,pmu = <&pmu1grf>; - }; - gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>; @@ -2543,19 +2556,6 @@ #interrupt-cells = <2>; }; }; - - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "vdpu"; - assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - assigned-clock-rates = <400000000>, <400000000>; - clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3588_PD_AV1>; - resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; - }; };
#include "rk3588s-pinctrl.dtsi"
From: Sebastian Reichel sebastian.reichel@collabora.com
usb2-phy should be named usb2phy according to the DT binding, so let's fix it up accordingly.
Signed-off-by: Sebastian Reichel sebastian.reichel@collabora.com Link: https://lore.kernel.org/r/20240408225109.128953-5-sebastian.reichel@collabor... Signed-off-by: Heiko Stuebner heiko@sntech.de
[ upstream commit: 4e07a95f7402de092cd71b2cb96c69f85c98f251 ]
(cherry picked from commit 5a3e4638492497ae81b9bd4a8627f4727e312ccc) Signed-off-by: Jianfeng Liu liujianfeng1994@gmail.com ---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index ac5bd630f15..87df0902273 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -599,7 +599,7 @@ #address-cells = <1>; #size-cells = <1>;
- u2phy2: usb2-phy@8000 { + u2phy2: usb2phy@8000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0x8000 0x10>; interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; @@ -624,7 +624,7 @@ #address-cells = <1>; #size-cells = <1>;
- u2phy3: usb2-phy@c000 { + u2phy3: usb2phy@c000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0xc000 0x10>; interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
From: Sebastian Reichel sebastian.reichel@collabora.com
Add both USB3-DisplayPort PHYs to RK3588 SoC DT.
Signed-off-by: Sebastian Reichel sebastian.reichel@collabora.com Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabor... Signed-off-by: Heiko Stuebner heiko@sntech.de
[ upstream commit: e18e5e8188f2671abf63abe7db5f21555705130f ]
(cherry picked from commit 5110caca9865718616cf7093ed4a9a1bc54780db) Signed-off-by: Jianfeng Liu liujianfeng1994@gmail.com ---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588.dtsi | 52 ++++++++++++++++ dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 63 ++++++++++++++++++++ 2 files changed, 115 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588.dtsi index 5519c1430cb..4fdd047c9eb 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi @@ -17,6 +17,36 @@ reg = <0x0 0xfd5c0000 0x0 0x100>; };
+ usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -310,6 +340,28 @@ }; };
+ usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + combphy1_ps: phy@fee10000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee10000 0x0 0x100>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 87df0902273..8314a4ace31 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -572,12 +572,23 @@ reg = <0x0 0xfd5a4000 0x0 0x2000>; };
+ vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&cru PCLK_VO0GRF>; + }; + vo1_grf: syscon@fd5a8000 { compatible = "rockchip,rk3588-vo-grf", "syscon"; reg = <0x0 0xfd5a8000 0x0 0x100>; clocks = <&cru PCLK_VO1GRF>; };
+ usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + php_grf: syscon@fd5b0000 { compatible = "rockchip,rk3588-php-grf", "syscon"; reg = <0x0 0xfd5b0000 0x0 0x1000>; @@ -593,6 +604,36 @@ reg = <0x0 0xfd5c4000 0x0 0x100>; };
+ usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg = <0x0 0xfd5d8000 0x0 0x4000>; @@ -2449,6 +2490,28 @@ status = "disabled"; };
+ usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>;
From: Sebastian Reichel sebastian.reichel@collabora.com
Add both USB3 dual-role controllers to the RK3588 devicetree.
Signed-off-by: Sebastian Reichel sebastian.reichel@collabora.com Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabor... Signed-off-by: Heiko Stuebner heiko@sntech.de
[ upstream commit: 33f393a2a990e16f56931ca708295f31d2b44415 ]
(cherry picked from commit c7ed588e14f7dd04a92fb55f12680f94c7b14edf) Signed-off-by: Jianfeng Liu liujianfeng1994@gmail.com ---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588.dtsi | 20 ++++++++++++++++++ dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++ 2 files changed, 42 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588.dtsi index 4fdd047c9eb..5984016b5f9 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi @@ -7,6 +7,26 @@ #include "rk3588-pinctrl.dtsi"
/ { + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + pcie30_phy_grf: syscon@fd5b8000 { compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; reg = <0x0 0xfd5b8000 0x0 0x10000>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 8314a4ace31..94157cdfd5c 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -492,6 +492,28 @@ }; };
+ usb_host0_xhci: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + usb_host0_ehci: usb@fc800000 { compatible = "rockchip,rk3588-ehci", "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>;
Specification: Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16/32GB Memory LPDDR4/LPDDR4x Mali G610MP4 GPU 2× MIPI-CSI Connector 1× MIPI-DSI Connector 1x M.2 Key M (PCIe 3.0 4-lanes) 2x RTL8125 2.5G Ethernet Onboard AP6275P for WIFI6/BT5 32GB/64GB/128GB eMMC MicroSD card slot 1x USB2.0, 1x USB3.0 Type-A, 1x US3.0 Type-C 1x HDMI Output, 1x type-C DP Output
Functions work normally: USB2.0 Host USB3.0 Type-A Host M.2 Key M (PCIe 3.0 4-lanes) 2x RTL8125 2.5G Ethernet eMMC MicroSD card
More information can be obtained from the following website https://docs.armsom.org/armsom-sige7
Signed-off-by: Jianfeng Liu liujianfeng1994@gmail.com Reviewed-by: Weizhao Ouyang weizhao.ouyang@arm.com Link: https://lore.kernel.org/r/20240420034300.176920-4-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner heiko@sntech.de
[ upstream commit: 81c828a67c78bb03ea75819c417c93c7f3d637b5 ]
(cherry picked from commit d427a11542bcf5364a5260280e077f0a2e030dcb) ---
(no changes since v1)
.../arm64/rockchip/rk3588-armsom-sige7.dts | 721 ++++++++++++++++++ 1 file changed, 721 insertions(+) create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts new file mode 100644 index 00000000000..98c622b2764 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts @@ -0,0 +1,721 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include "rk3588.dtsi" + +/ { + model = "ArmSoM Sige7"; + compatible = "armsom,sige7", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s0_8ch_p0>; + label = "rk3588-es8316"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_g>; + + led_green: led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led_red: led-1 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +/* phy1 - right ethernet port */ +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* phy2 - WiFi */ +&pcie2x1l1 { + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* phy0 - left ethernet port */ +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_rgb_g: led-rgb-g { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_rgb_r: led-rgb-r { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs200-1_8v; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +};
ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by ArmSoM.
There are two variants depending on the DRAM size : 8G and 16G.
Specification:
Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16GB memory LPDDR4x Mali G610MC4 GPU 2x MIPI CSI 2 multiple lanes connector 64GB/128GB on board eMMC uSD slot 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C 1x HDMI 2.1 output 2x 2.5 Gbps Ethernet port 40-pin IO header including UART, SPI and I2C USB PD over USB Type-C Size: 92mm x 62mm
Kernel commit: 81c828a67c78 (arm64: dts: rockchip: Add ArmSom Sige7 board)
Signed-off-by: Jianfeng Liu liujianfeng1994@gmail.com ---
Changes in v3: - Use update-dts-subtree.sh to pick upstream dts
Changes in v2: - Fix alphabetical order of MAINTAINERS - Use arch/arm/dts/rk3588-armsom-sige7* in board MAINTAINERS - Remove spi flash related config - Move kernel dts to dts/upstream/src/arm64/rockchip/
MAINTAINERS | 1 + arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi | 28 ++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 26 ++++++ board/armsom/sige7-rk3588/Kconfig | 12 +++ board/armsom/sige7-rk3588/MAINTAINERS | 7 ++ configs/sige7-rk3588_defconfig | 93 ++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/sige7-rk3588.h | 15 ++++ 8 files changed, 183 insertions(+) create mode 100644 arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi create mode 100644 board/armsom/sige7-rk3588/Kconfig create mode 100644 board/armsom/sige7-rk3588/MAINTAINERS create mode 100644 configs/sige7-rk3588_defconfig create mode 100644 include/configs/sige7-rk3588.h
diff --git a/MAINTAINERS b/MAINTAINERS index 6c861b529df..fffcf898bf1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -534,6 +534,7 @@ F: arch/arm/include/asm/arch-rockchip/ F: arch/arm/mach-rockchip/ F: board/amarula/vyasa-rk3288/ F: board/anbernic/rgxx3_rk3566/ +F: board/armsom/sige7-rk3588/ F: board/chipspark/popmetal_rk3288 F: board/engicam/px30_core/ F: board/firefly/ diff --git a/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi new file mode 100644 index 00000000000..2c984d01471 --- /dev/null +++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 ArmSoM Technology Co., Ltd. + */ + +#include "rk3588-u-boot.dtsi" + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 39049ab35a9..4c14b0be1eb 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -152,6 +152,31 @@ config TARGET_ROCK5B_RK3588 USB PD over USB Type-C Size: 100mm x 72mm (Pico-ITX form factor)
+config TARGET_SIGE7_RK3588 + bool "ArmSoM Sige7 RK3588 board" + select BOARD_LATE_INIT + help + ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) + by ArmSoM. + + There are two variants depending on the DRAM size : 8G and 16G. + + Specification: + + Rockchip Rk3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB memory LPDDR4x + Mali G610MC4 GPU + 2x MIPI CSI 2 multiple lanes connector + 64GB/128GB on board eMMC + uSD slot + 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C + 1x HDMI 2.1 output + 2x 2.5 Gbps Ethernet port + 40-pin IO header including UART, SPI and I2C + USB PD over USB Type-C + Size: 92mm x 62mm + config TARGET_QUARTZPRO64_RK3588 bool "Pine64 QuartzPro64 RK3588 board" select BOARD_LATE_INIT @@ -221,6 +246,7 @@ config ROCKCHIP_COMMON_STACK_ADDR config TEXT_BASE default 0x00a00000
+source "board/armsom/sige7-rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/pine64/quartzpro64-rk3588/Kconfig" diff --git a/board/armsom/sige7-rk3588/Kconfig b/board/armsom/sige7-rk3588/Kconfig new file mode 100644 index 00000000000..793985f531b --- /dev/null +++ b/board/armsom/sige7-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SIGE7_RK3588 + +config SYS_BOARD + default "sige7-rk3588" + +config SYS_VENDOR + default "armsom" + +config SYS_CONFIG_NAME + default "sige7-rk3588" + +endif diff --git a/board/armsom/sige7-rk3588/MAINTAINERS b/board/armsom/sige7-rk3588/MAINTAINERS new file mode 100644 index 00000000000..0fba39b76c2 --- /dev/null +++ b/board/armsom/sige7-rk3588/MAINTAINERS @@ -0,0 +1,7 @@ +SIGE7-RK3588 +M: Jianfeng Liu liujianfeng1994@gmail.com +S: Maintained +F: board/armsom/sige7-rk3588 +F: include/configs/sige7-rk3588.h +F: configs/sige7-rk3588_defconfig +F: arch/arm/dts/rk3588-armsom-sige7* diff --git a/configs/sige7-rk3588_defconfig b/configs/sige7-rk3588_defconfig new file mode 100644 index 00000000000..d15fc09fc8d --- /dev/null +++ b/configs/sige7-rk3588_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-armsom-sige7" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_SIGE7_RK3588=y +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-armsom-sige7.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9a726e9cde6..6b826b3288f 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -118,6 +118,7 @@ List of mainline supported Rockchip boards: - Radxa ROCK 3 Model A (rock-3a-rk3568)
* rk3588 + - ArmSoM Sige7 (sige7-rk3588) - Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) diff --git a/include/configs/sige7-rk3588.h b/include/configs/sige7-rk3588.h new file mode 100644 index 00000000000..fd08da568b1 --- /dev/null +++ b/include/configs/sige7-rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 ArmSoM Technology Co., Ltd. + */ + +#ifndef __SIGE7_RK3588_H +#define __SIGE7_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __SIGE7_RK3588_H */
Hi Jianfeng,
On 2024-05-27 19:02, Jianfeng Liu wrote:
ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by ArmSoM.
There are two variants depending on the DRAM size : 8G and 16G.
Specification:
Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16GB memory LPDDR4x Mali G610MC4 GPU 2x MIPI CSI 2 multiple lanes connector 64GB/128GB on board eMMC uSD slot 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C 1x HDMI 2.1 output 2x 2.5 Gbps Ethernet port 40-pin IO header including UART, SPI and I2C USB PD over USB Type-C Size: 92mm x 62mmKernel commit: 81c828a67c78 (arm64: dts: rockchip: Add ArmSom Sige7 board)
Signed-off-by: Jianfeng Liu liujianfeng1994@gmail.com
Changes in v3:
- Use update-dts-subtree.sh to pick upstream dts
Changes in v2:
- Fix alphabetical order of MAINTAINERS
- Use arch/arm/dts/rk3588-armsom-sige7* in board MAINTAINERS
- Remove spi flash related config
- Move kernel dts to dts/upstream/src/arm64/rockchip/
MAINTAINERS | 1 + arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi | 28 ++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 26 ++++++ board/armsom/sige7-rk3588/Kconfig | 12 +++ board/armsom/sige7-rk3588/MAINTAINERS | 7 ++ configs/sige7-rk3588_defconfig | 93 ++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/sige7-rk3588.h | 15 ++++ 8 files changed, 183 insertions(+) create mode 100644 arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi create mode 100644 board/armsom/sige7-rk3588/Kconfig create mode 100644 board/armsom/sige7-rk3588/MAINTAINERS create mode 100644 configs/sige7-rk3588_defconfig create mode 100644 include/configs/sige7-rk3588.h
diff --git a/MAINTAINERS b/MAINTAINERS index 6c861b529df..fffcf898bf1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -534,6 +534,7 @@ F: arch/arm/include/asm/arch-rockchip/ F: arch/arm/mach-rockchip/ F: board/amarula/vyasa-rk3288/ F: board/anbernic/rgxx3_rk3566/ +F: board/armsom/sige7-rk3588/ F: board/chipspark/popmetal_rk3288 F: board/engicam/px30_core/ F: board/firefly/ diff --git a/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi new file mode 100644 index 00000000000..2c984d01471 --- /dev/null +++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- Copyright (c) 2024 ArmSoM Technology Co., Ltd.
- */
+#include "rk3588-u-boot.dtsi"
+&sdhci {
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
+};
The sdhci node should not be needed, mmc-hs200-1_8v is already defined in the upstream DT and cap-mmc-highspeed modes only work if HS200 can first be initialized.
+&u2phy1 {
- status = "okay";
+};
+&u2phy1_otg {
- status = "okay";
+};
+&usbdp_phy1 {
- status = "okay";
+};
+&usb_host1_xhci {
- dr_mode = "host";
- status = "okay";
+};
These usb related nodes is already defined in main DT, please remove.
Regards, Jonas
[snip]
Hi Jianfeng,
On 2024-05-27 19:02, Jianfeng Liu wrote:
Devicetree of ArmSoM Sige7 is merged to kernel v6.10-rc1 with USBDP and GPU nodes. So I use update-dts-subtree.sh to pick related commits of rk3588s.dtsi, and then pick the commit of ArmSoM Sige7's devicetree. I also did run command: ./dts/update-dts-subtree.sh pull v6.10-rc1-dts based on my work but there is a merge conflict of file: dts/upstream/Bindings/Makefile I think this should not be related to my work.
I have only received the cover letter and patch 7/7 but have two quick notes:
This seem to be missing 2 patches from v6.10-rc1-dts for rk3588s.dtsi: - f6835a60a8a2 ("arm64: dts: rockchip: reorder usb2phy properties for rk3588") - ea9a34aa0d78 ("arm64: dts: rockchip: add rk3588 pcie and php IOMMUs")
Probably better to fully sync the rk3588/rk3588s.dtsi-files to the v6.10-rc1-dts state.
Also please add a commit that removes the usbdpphy-grf, usb2phy-grf, usbdp-phy, vo-grf and usb-grf related nodes from rk3588-u-boot.dtsi and rk3588s-u-boot.dtsi. The usb nodes in rk3588 -u-boot.dtsi-files should be obsolete after this series.
Regards, Jonas
Changes in v3:
- Use update-dts-subtree.sh to pick upstream dts
Changes in v2:
- Fix alphabetical order of MAINTAINERS
- Use arch/arm/dts/rk3588-armsom-sige7* in board MAINTAINERS
- Remove spi flash related config
- Move kernel dts to dts/upstream/src/arm64/rockchip/
Boris Brezillon (1): arm64: dts: rockchip: Add rk3588 GPU node
Diederik de Haas (1): arm64: dts: rockchip: Fix ordering of nodes on rk3588s
Jianfeng Liu (2): arm64: dts: rockchip: Add ArmSom Sige7 board board: rockchip: add ArmSoM Sige7 Rk3588 board
Sebastian Reichel (3): arm64: dts: rockchip: fix usb2phy nodename for rk3588 arm64: dts: rockchip: add USBDP phys on rk3588 arm64: dts: rockchip: add USB3 DRD controllers on rk3588
MAINTAINERS | 1 + arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi | 28 + arch/arm/mach-rockchip/rk3588/Kconfig | 26 + board/armsom/sige7-rk3588/Kconfig | 12 + board/armsom/sige7-rk3588/MAINTAINERS | 7 + configs/sige7-rk3588_defconfig | 93 +++ doc/board/rockchip/rockchip.rst | 1 + .../arm64/rockchip/rk3588-armsom-sige7.dts | 721 ++++++++++++++++++ dts/upstream/src/arm64/rockchip/rk3588.dtsi | 72 ++ dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 337 +++++--- include/configs/sige7-rk3588.h | 15 + 11 files changed, 1215 insertions(+), 98 deletions(-) create mode 100644 arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi create mode 100644 board/armsom/sige7-rk3588/Kconfig create mode 100644 board/armsom/sige7-rk3588/MAINTAINERS create mode 100644 configs/sige7-rk3588_defconfig create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts create mode 100644 include/configs/sige7-rk3588.h
On Tue, May 28, 2024 at 01:02:07AM +0800, Jianfeng Liu wrote:
Devicetree of ArmSoM Sige7 is merged to kernel v6.10-rc1 with USBDP and GPU nodes. So I use update-dts-subtree.sh to pick related commits of rk3588s.dtsi, and then pick the commit of ArmSoM Sige7's devicetree. I also did run command: ./dts/update-dts-subtree.sh pull v6.10-rc1-dts based on my work but there is a merge conflict of file: dts/upstream/Bindings/Makefile I think this should not be related to my work.
Yes, I took a quick look at the conflict is unrelated to your series here and also with a quick local apply then resync to v6.10-rc1 everything else works as expected from my point of view.
participants (3)
-
Jianfeng Liu -
Jonas Karlman -
Tom Rini