On Mon, 17 Oct 2005 12:29:45 +0200 alebas@televes.com wrote:

Alex,

Again at work. I have some comment over those changes

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For the record here is the change I needed to make to u-boot-1.1.3.

Index: board/mpc8260ads/config.mk

== RCS file: /newcvs/pq2-linux/u-boot/board/mpc8260ads/config.mk,v retrieving revision 1.1.1.1 diff -u -r1.1.1.1 config.mk --- board/mpc8260ads/config.mk 24 Aug 2005 12:16:55 -0000 1.1.1.1 +++ board/mpc8260ads/config.mk 14 Oct 2005 08:36:46 -0000 @@ -29,4 +29,4 @@ # MPC8260ADS, MPC8266ADS, and PQ2FADS-ZU/VR boards #

-TEXT_BASE = 0xfff00000 +TEXT_BASE = 0xff800000

Are you sure you are using u-boot-1.1.3? Patch from Jerry Van Baren already made some changes to this file to allow the use of a different TEXT__BASE for lowboot in MPC8272ADS selecting it from Makefile config target. I have this changes already applied in 1.1.3.

I am using u-boot-1.1.3 from Denx ELDK 3.1.1. There is lowboot support in the top level Makefile - but not for any of the 82xx ADS platforms.

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Index: include/configs/MPC8260ADS.h

== RCS file: /newcvs/pq2-linux/u-boot/include/configs/MPC8260ADS.h,v retrieving revision 1.1.1.1 diff -u -r1.1.1.1 MPC8260ADS.h --- include/configs/MPC8260ADS.h 24 Aug 2005 12:17:01 -0000 1.1.1.1+++ include/configs/MPC8260ADS.h 14 Oct 2005 08:36:46 -0000 @@ -294,13 +294,8 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET

+#define CFG_HRCW_MASTER 0x0e72b605 /* like BCSR version, but with CIP=1, BMS=1 */

In order lowboot patch from Jerry to work (which has been applied to u-boot source, so I recommned you to use) in MPC8272ADS, ISB must also be ISB=100, not ISB=010 as in BCSR.

I think either are fine, as they result in an internal register space that doesn't conflict with the boot code (which is initially mapped by the CPU to 0x0...0x01ffffff). The startup assembly code remaps it anyway.

Also, from MPC8272RM, bits 20-21 are reserved and should be cleared. So, LBPC=00, although 01 works.

I used 01 because this is what the MPC8272ADS User Manual says the BCSR delivers in this field. But you are right - this does seem to contradict MPC8272RM. I've changed this now to 00.

And finally a question. You use MODCK_H = 0101 whereas I use in my patch MODCK_H=1010, while trying to set MODCK to 1010_100. Am I mis-understanding something?

You are right. I was overclocking my MPC8272. It has max ratings of 400/200/100 and I had it going at 450/200/100. My new HRCW is:

0x0e72b20a

Best regards,

Alex Bastos

Thanks,

Alex Zeffertt