[U-Boot] [PATCH] fsl-ddr: Fix two bugs in the ddr infrastructure
1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case.
Reported-by: Joakim Tjernlund Joakim.Tjernlund@transmode.se Signed-off-by: Dave Liu daveliu@freescale.com --- cpu/mpc8xxx/ddr/ctrl_regs.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 292980d..4c1498c 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -302,12 +302,15 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, */ wr_lat = 0; #elif defined(CONFIG_FSL_DDR2) - wr_lat = cas_latency + additive_latency - 1; + wr_lat = cas_latency - 1; #else #error "Fix WR_LAT for DDR3" #endif
rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps); +#if defined(CONFIG_FSL_DDR2) + rd_to_pre += additive_latency; +#endif wr_data_delay = popts->write_data_delay; cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps); four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
Kim,
If not any objection for the patch, Could you pick it up to 83xx tree to go main tree.
Thanks, Dave
-----Original Message----- From: Liu Dave-R63238 Sent: 2009?2?24? 7:10 PM To: Phillips Kim-R1AAHA; Fleming Andy-AFLEMING Cc: u-boot@lists.denx.de; Joakim.Tjernlund@transmode.se; Liu Dave-R63238 Subject: [PATCH] fsl-ddr: Fix two bugs in the ddr infrastructure
- wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1;
- rd_to_pre we missed to add the ADD_LAT for DDR2 case.
Reported-by: Joakim Tjernlund Joakim.Tjernlund@transmode.se Signed-off-by: Dave Liu daveliu@freescale.com
cpu/mpc8xxx/ddr/ctrl_regs.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 292980d..4c1498c 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -302,12 +302,15 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, */ wr_lat = 0; #elif defined(CONFIG_FSL_DDR2)
- wr_lat = cas_latency + additive_latency - 1;
- wr_lat = cas_latency - 1;
#else #error "Fix WR_LAT for DDR3" #endif
rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps); +#if defined(CONFIG_FSL_DDR2)
- rd_to_pre += additive_latency;
+#endif wr_data_delay = popts->write_data_delay; cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps); four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps); -- 1.5.4
On Tue, 24 Feb 2009 04:24:29 -0700 "Liu Dave-R63238" DaveLiu@freescale.com wrote:
Kim,
If not any objection for the patch, Could you pick it up to 83xx tree to go main tree.
no, this must go through either Andy or jdl, since it affects code mpc8 [56]xx use, and not mpc83xx.
rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps); +#if defined(CONFIG_FSL_DDR2)
- rd_to_pre += additive_latency;
+#endif
btw Jocke fixed this up differently, and addressed the issue in a different thread. Want to work on getting his ack before attempting to apply this?
Kim
participants (3)
-
Dave Liu -
Kim Phillips -
Liu Dave-R63238