[U-Boot] [PATCH] davinci: omapl138_lcdk: increase PLL0 frequency
The LCDC controller on the lcdk board has high memory throughput requirements. Even with the kernel-side tweaks to master peripheral and peripheral bus burst priorities, the default PLL0 frquency of 300 MHz is not enough to service the LCD controller and causes DMA FIFO underflows.
Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of 456 MHz - the same value that downstream reference u-boot from Texas Instruments uses.
Signed-off-by: Bartosz Golaszewski bgolaszewski@baylibre.com --- include/configs/omapl138_lcdk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index f751fe7..18abac0 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -75,7 +75,7 @@ #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLM 24 +#define CONFIG_SYS_DA850_PLL0_PLLM 37 #define CONFIG_SYS_DA850_PLL1_PLLM 21
/*
On Thu, Dec 01, 2016 at 12:07:43PM +0100, Bartosz Golaszewski wrote:
The LCDC controller on the lcdk board has high memory throughput requirements. Even with the kernel-side tweaks to master peripheral and peripheral bus burst priorities, the default PLL0 frquency of 300 MHz is not enough to service the LCD controller and causes DMA FIFO underflows.
Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of 456 MHz - the same value that downstream reference u-boot from Texas Instruments uses.
Signed-off-by: Bartosz Golaszewski bgolaszewski@baylibre.com
Reviewed-by: Tom Rini trini@konsulko.com
participants (2)
-
Bartosz Golaszewski -
Tom Rini