[U-Boot] [PATCH 0/4] MIPS: unify start.S
Currently we have mips32-specific & mips64-specific versions of start.S, which are very similar. This short series adapts the mips32 start.S to also be suitable for mips64 systems & then shares that single copy between mips32 & mips64 builds.
Paul Burton (4): MIPS: use asm.h macros in mips32 start.S MIPS: handle mips64 relocs in mips32 start.S MIPS: handle mips64 ST0_KX bit in mips32 start.S MIPS: share start.S between mips32 & mips64
arch/mips/Makefile | 3 +- arch/mips/cpu/mips32/Makefile | 1 - arch/mips/cpu/mips64/Makefile | 1 - arch/mips/cpu/mips64/start.S | 291 ---------------------------------- arch/mips/lib/Makefile | 2 + arch/mips/{cpu/mips32 => lib}/start.S | 137 +++++++++------- 6 files changed, 83 insertions(+), 352 deletions(-) delete mode 100644 arch/mips/cpu/mips64/start.S rename arch/mips/{cpu/mips32 => lib}/start.S (61%)
Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64.
The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such.
Signed-off-by: Paul Burton paul.burton@imgtec.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- arch/mips/cpu/mips32/start.S | 116 +++++++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 55 deletions(-)
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 36b92cc..227af6d 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -8,6 +8,7 @@
#include <asm-offsets.h> #include <config.h> +#include <asm/asm.h> #include <asm/regdef.h> #include <asm/mipsregs.h>
@@ -98,8 +99,8 @@ _start: reset:
/* Clear watch registers */ - mtc0 zero, CP0_WATCHLO - mtc0 zero, CP0_WATCHHI + MTC0 zero, CP0_WATCHLO + MTC0 zero, CP0_WATCHHI
/* WP(Watch Pending), SW0/1 should be cleared */ mtc0 zero, CP0_CAUSE @@ -116,21 +117,26 @@ reset: mtc0 t0, CP0_CONFIG #endif
- /* Initialize $gp */ + /* + * Initialize $gp, force pointer sized alignment of bal instruction to + * forbid the compiler to put nop's between bal and _gp. This is + * required to keep _gp and ra aligned to 8 byte. + */ + .align PTRLOG bal 1f nop - .word _gp + PTR _gp 1: - lw gp, 0(ra) + PTR_L gp, 0(ra)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* Initialize any external memory */ - la t9, lowlevel_init + PTR_LA t9, lowlevel_init jalr t9 nop
/* Initialize caches... */ - la t9, mips_cache_reset + PTR_LA t9, mips_cache_reset jalr t9 nop
@@ -140,15 +146,15 @@ reset: #endif
/* Set up temporary stack */ - li t0, -16 - li t1, CONFIG_SYS_INIT_SP_ADDR + PTR_LI t0, -16 + PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR and sp, t1, t0 # force 16 byte alignment - sub sp, sp, GD_SIZE # reserve space for gd + PTR_SUB sp, sp, GD_SIZE # reserve space for gd and sp, sp, t0 # force 16 byte alignment move k0, sp # save gd pointer #ifdef CONFIG_SYS_MALLOC_F_LEN - li t2, CONFIG_SYS_MALLOC_F_LEN - sub sp, sp, t2 # reserve space for early malloc + PTR_LI t2, CONFIG_SYS_MALLOC_F_LEN + PTR_SUB sp, sp, t2 # reserve space for early malloc and sp, sp, t0 # force 16 byte alignment #endif move fp, sp @@ -158,14 +164,14 @@ reset: 1: sw zero, 0(t0) blt t0, t1, 1b - addi t0, 4 + PTR_ADDI t0, 4
#ifdef CONFIG_SYS_MALLOC_F_LEN - addu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset + PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset sw sp, 0(t0) #endif
- la t9, board_init_f + PTR_LA t9, board_init_f jr t9 move ra, zero
@@ -188,14 +194,14 @@ relocate_code: move s0, a1 # save gd in s0 move s2, a2 # save destination address in s2
- li t0, CONFIG_SYS_MONITOR_BASE - sub s1, s2, t0 # s1 <-- relocation offset + PTR_LI t0, CONFIG_SYS_MONITOR_BASE + PTR_SUB s1, s2, t0 # s1 <-- relocation offset
- la t3, in_ram - lw t2, -12(t3) # t2 <-- __image_copy_end + PTR_LA t3, in_ram + PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end move t1, a2
- add gp, s1 # adjust gp + PTR_ADD gp, s1 # adjust gp
/* * t0 = source address @@ -205,26 +211,26 @@ relocate_code: 1: lw t3, 0(t0) sw t3, 0(t1) - addu t0, 4 + PTR_ADDU t0, 4 blt t0, t2, 1b - addu t1, 4 + PTR_ADDU t1, 4
/* If caches were enabled, we would have to flush them here. */ - sub a1, t1, s2 # a1 <-- size - la t9, flush_cache + PTR_SUB a1, t1, s2 # a1 <-- size + PTR_LA t9, flush_cache jalr t9 move a0, s2 # a0 <-- destination address
/* Jump to where we've relocated ourselves */ - addi t0, s2, in_ram - _start + PTR_ADDI t0, s2, in_ram - _start jr t0 nop
- .word __rel_dyn_end - .word __rel_dyn_start - .word __image_copy_end - .word _GLOBAL_OFFSET_TABLE_ - .word num_got_entries + PTR __rel_dyn_end + PTR __rel_dyn_start + PTR __image_copy_end + PTR _GLOBAL_OFFSET_TABLE_ + PTR num_got_entries
in_ram: /* @@ -233,46 +239,46 @@ in_ram: * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object * generated by GNU ld. Skip these reserved entries from relocation. */ - lw t3, -4(t0) # t3 <-- num_got_entries - lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ - add t8, s1 # t8 now holds relocated _G_O_T_ - addi t8, t8, 8 # skipping first two entries - li t2, 2 + PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries + PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_ + PTR_ADDI t8, t8, 2 * PTRSIZE # skipping first two entries + PTR_LI t2, 2 1: - lw t1, 0(t8) + PTR_L t1, 0(t8) beqz t1, 2f - add t1, s1 - sw t1, 0(t8) + PTR_ADD t1, s1 + PTR_S t1, 0(t8) 2: - addi t2, 1 + PTR_ADDI t2, 1 blt t2, t3, 1b - addi t8, 4 + PTR_ADDI t8, PTRSIZE
/* Update dynamic relocations */ - lw t1, -16(t0) # t1 <-- __rel_dyn_start - lw t2, -20(t0) # t2 <-- __rel_dyn_end + PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start + PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
b 2f # skip first reserved entry - addi t1, 8 + PTR_ADDI t1, 2 * PTRSIZE
1: lw t8, -4(t1) # t8 <-- relocation info
- li t3, 3 + PTR_LI t3, 3 bne t8, t3, 2f # skip non R_MIPS_REL32 entries nop
- lw t3, -8(t1) # t3 <-- location to fix up in FLASH + PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
- lw t8, 0(t3) # t8 <-- original pointer - add t8, s1 # t8 <-- adjusted pointer + PTR_L t8, 0(t3) # t8 <-- original pointer + PTR_ADD t8, s1 # t8 <-- adjusted pointer
- add t3, s1 # t3 <-- location to fix up in RAM - sw t8, 0(t3) + PTR_ADD t3, s1 # t3 <-- location to fix up in RAM + PTR_S t8, 0(t3)
2: blt t1, t2, 1b - addi t1, 8 # each rel.dyn entry is 8 bytes + PTR_ADDI t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
/* * Clear BSS @@ -280,17 +286,17 @@ in_ram: * GOT is now relocated. Thus __bss_start and __bss_end can be * accessed directly via $gp. */ - la t1, __bss_start # t1 <-- __bss_start - la t2, __bss_end # t2 <-- __bss_end + PTR_LA t1, __bss_start # t1 <-- __bss_start + PTR_LA t2, __bss_end # t2 <-- __bss_end
1: - sw zero, 0(t1) + PTR_S zero, 0(t1) blt t1, t2, 1b - addi t1, 4 + PTR_ADDI t1, PTRSIZE
move a0, s0 # a0 <-- gd move a1, s2 - la t9, board_init_r + PTR_LA t9, board_init_r jr t9 move ra, zero
In preparation for sharing a single copy of start.S between mips32 & mips64, handle mips64 relocations in the mips32 start.S when built for mips64.
Signed-off-by: Paul Burton paul.burton@imgtec.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- arch/mips/cpu/mips32/start.S | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 227af6d..699c59a 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -21,6 +21,21 @@ CONFIG_SYS_INIT_SP_OFFSET) #endif
+#ifdef CONFIG_32BIT +# define MIPS_RELOC 3 +#endif + +#ifdef CONFIG_64BIT +# ifdef CONFIG_SYS_LITTLE_ENDIAN +# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ + (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) +# else +# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ + ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) +# endif +# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) +#endif + /* * For the moment disable interrupts, mark the kernel mode and * set ST0_KX so that the CPU does not spit fire when using @@ -264,8 +279,8 @@ in_ram: 1: lw t8, -4(t1) # t8 <-- relocation info
- PTR_LI t3, 3 - bne t8, t3, 2f # skip non R_MIPS_REL32 entries + PTR_LI t3, MIPS_RELOC + bne t8, t3, 2f # skip non-MIPS_RELOC entries nop
PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
In preparation for sharing a single copy of start.S between mips32 & mips64, handle setting the KX bit of the cop0 Status register when the mips32 start.S is built for mips64.
Signed-off-by: Paul Burton paul.burton@imgtec.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- arch/mips/cpu/mips32/start.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 699c59a..3b5b622 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -23,6 +23,7 @@
#ifdef CONFIG_32BIT # define MIPS_RELOC 3 +# define STATUS_SET 0 #endif
#ifdef CONFIG_64BIT @@ -34,6 +35,7 @@ ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) # endif # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) +# define STATUS_SET ST0_KX #endif
/* @@ -120,7 +122,7 @@ reset: /* WP(Watch Pending), SW0/1 should be cleared */ mtc0 zero, CP0_CAUSE
- setup_c0_status 0 0 + setup_c0_status STATUS_SET 0
/* Init Timer */ mtc0 zero, CP0_COUNT
The mips32 copy of start.S now has everything required to also handle mips64 builds. Move it to arch/mips/lib, use it for all builds & remove the redundant mips64-specific version.
Signed-off-by: Paul Burton paul.burton@imgtec.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- arch/mips/Makefile | 3 +- arch/mips/cpu/mips32/Makefile | 1 - arch/mips/cpu/mips64/Makefile | 1 - arch/mips/cpu/mips64/start.S | 291 ---------------------------------- arch/mips/lib/Makefile | 2 + arch/mips/{cpu/mips32 => lib}/start.S | 0 6 files changed, 3 insertions(+), 295 deletions(-) delete mode 100644 arch/mips/cpu/mips64/start.S rename arch/mips/{cpu/mips32 => lib}/start.S (100%)
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0a9e7e6..5a66979 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -2,8 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ #
-head-$(CONFIG_CPU_MIPS32) := arch/mips/cpu/mips32/start.o -head-$(CONFIG_CPU_MIPS64) := arch/mips/cpu/mips64/start.o +head-y := arch/mips/lib/start.o
libs-$(CONFIG_CPU_MIPS32) += arch/mips/cpu/mips32/ libs-$(CONFIG_CPU_MIPS64) += arch/mips/cpu/mips64/ diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile index 19d316a..9973cd3 100644 --- a/arch/mips/cpu/mips32/Makefile +++ b/arch/mips/cpu/mips32/Makefile @@ -5,7 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ #
-extra-y = start.o obj-y = cpu.o interrupts.o time.o
obj-$(CONFIG_SOC_AU1X00) += au1x00/ diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile index cb4db9c..33fda36 100644 --- a/arch/mips/cpu/mips64/Makefile +++ b/arch/mips/cpu/mips64/Makefile @@ -5,5 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ #
-extra-y = start.o obj-y = cpu.o interrupts.o time.o diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S deleted file mode 100644 index 471bc1e..0000000 --- a/arch/mips/cpu/mips64/start.S +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Startup Code for MIPS64 CPU-core - * - * Copyright (c) 2003 Wolfgang Denk wd@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <asm/regdef.h> -#include <asm/mipsregs.h> - -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - -#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_SP_OFFSET) -#endif - -#ifdef CONFIG_SYS_LITTLE_ENDIAN -#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ - (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) -#else -#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ - ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) -#endif - - /* - * For the moment disable interrupts, mark the kernel mode and - * set ST0_KX so that the CPU does not spit fire when using - * 64-bit addresses. - */ - .macro setup_c0_status set clr - .set push - mfc0 t0, CP0_STATUS - or t0, ST0_CU0 | \set | 0x1f | \clr - xor t0, 0x1f | \clr - mtc0 t0, CP0_STATUS - .set noreorder - sll zero, 3 # ehb - .set pop - .endm - - .set noreorder - - .globl _start - .text -_start: - /* U-boot entry point */ - b reset - nop - - .org 0x200 - /* TLB refill, 32 bit task */ -1: b 1b - nop - - .org 0x280 - /* XTLB refill, 64 bit task */ -1: b 1b - nop - - .org 0x300 - /* Cache error exception */ -1: b 1b - nop - - .org 0x380 - /* General exception */ -1: b 1b - nop - - .org 0x400 - /* Catch interrupt exceptions */ -1: b 1b - nop - - .org 0x480 - /* EJTAG debug exception */ -1: b 1b - nop - - .align 4 -reset: - - /* Clear watch registers */ - dmtc0 zero, CP0_WATCHLO - dmtc0 zero, CP0_WATCHHI - - /* WP(Watch Pending), SW0/1 should be cleared */ - mtc0 zero, CP0_CAUSE - - setup_c0_status ST0_KX 0 - - /* Init Timer */ - mtc0 zero, CP0_COUNT - mtc0 zero, CP0_COMPARE - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* CONFIG0 register */ - dli t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG -#endif - - /* - * Initialize $gp, force 8 byte alignment of bal instruction to forbid - * the compiler to put nop's between bal and _gp. This is required to - * keep _gp and ra aligned to 8 byte. - */ - .align 3 - bal 1f - nop - .dword _gp -1: - ld gp, 0(ra) - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* Initialize any external memory */ - dla t9, lowlevel_init - jalr t9 - nop - - /* Initialize caches... */ - dla t9, mips_cache_reset - jalr t9 - nop - - /* ... and enable them */ - dli t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG -#endif - - /* Set up temporary stack */ - dli t0, -16 - dli t1, CONFIG_SYS_INIT_SP_ADDR - and sp, t1, t0 # force 16 byte alignment - dsub sp, sp, GD_SIZE # reserve space for gd - and sp, sp, t0 # force 16 byte alignment - move k0, sp # save gd pointer -#ifdef CONFIG_SYS_MALLOC_F_LEN - dli t2, CONFIG_SYS_MALLOC_F_LEN - dsub sp, sp, t2 # reserve space for early malloc - and sp, sp, t0 # force 16 byte alignment -#endif - move fp, sp - - /* Clear gd */ - move t0, k0 -1: - sw zero, 0(t0) - blt t0, t1, 1b - daddi t0, 4 - -#ifdef CONFIG_SYS_MALLOC_F_LEN - daddu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset - sw sp, 0(t0) -#endif - - dla t9, board_init_f - jr t9 - move ra, zero - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * a0 = addr_sp - * a1 = gd - * a2 = destination address - */ - .globl relocate_code - .ent relocate_code -relocate_code: - move sp, a0 # set new stack pointer - move fp, sp - - move s0, a1 # save gd in s0 - move s2, a2 # save destination address in s2 - - dli t0, CONFIG_SYS_MONITOR_BASE - dsub s1, s2, t0 # s1 <-- relocation offset - - dla t3, in_ram - ld t2, -24(t3) # t2 <-- __image_copy_end - move t1, a2 - - dadd gp, s1 # adjust gp - - /* - * t0 = source address - * t1 = target address - * t2 = source end address - */ -1: - lw t3, 0(t0) - sw t3, 0(t1) - daddu t0, 4 - blt t0, t2, 1b - daddu t1, 4 - - /* If caches were enabled, we would have to flush them here. */ - dsub a1, t1, s2 # a1 <-- size - dla t9, flush_cache - jalr t9 - move a0, s2 # a0 <-- destination address - - /* Jump to where we've relocated ourselves */ - daddi t0, s2, in_ram - _start - jr t0 - nop - - .dword __rel_dyn_end - .dword __rel_dyn_start - .dword __image_copy_end - .dword _GLOBAL_OFFSET_TABLE_ - .dword num_got_entries - -in_ram: - /* - * Now we want to update GOT. - * - * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object - * generated by GNU ld. Skip these reserved entries from relocation. - */ - ld t3, -8(t0) # t3 <-- num_got_entries - ld t8, -16(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ - dadd t8, s1 # t8 now holds relocated _G_O_T_ - daddi t8, t8, 16 # skipping first two entries - dli t2, 2 -1: - ld t1, 0(t8) - beqz t1, 2f - dadd t1, s1 - sd t1, 0(t8) -2: - daddi t2, 1 - blt t2, t3, 1b - daddi t8, 8 - - /* Update dynamic relocations */ - ld t1, -32(t0) # t1 <-- __rel_dyn_start - ld t2, -40(t0) # t2 <-- __rel_dyn_end - - b 2f # skip first reserved entry - daddi t1, 16 - -1: - lw t8, -4(t1) # t8 <-- relocation info - - dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) - bne t8, t3, 2f # skip non R_MIPS_REL32 entries - nop - - ld t3, -16(t1) # t3 <-- location to fix up in FLASH - - ld t8, 0(t3) # t8 <-- original pointer - dadd t8, s1 # t8 <-- adjusted pointer - - dadd t3, s1 # t3 <-- location to fix up in RAM - sd t8, 0(t3) - -2: - blt t1, t2, 1b - daddi t1, 16 # each rel.dyn entry is 16 bytes - - /* - * Clear BSS - * - * GOT is now relocated. Thus __bss_start and __bss_end can be - * accessed directly via $gp. - */ - dla t1, __bss_start # t1 <-- __bss_start - dla t2, __bss_end # t2 <-- __bss_end - -1: - sd zero, 0(t1) - blt t1, t2, 1b - daddi t1, 8 - - move a0, s0 # a0 <-- gd - move a1, s2 - dla t9, board_init_r - jr t9 - move ra, zero - - .end relocate_code diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index ac536da..8caa93f 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -5,6 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ #
+extra-y = start.o + obj-y += cache.o obj-y += cache_init.o obj-y += io.o diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/lib/start.S similarity index 100% rename from arch/mips/cpu/mips32/start.S rename to arch/mips/lib/start.S
Hi Paul,
2015-01-29 11:04 GMT+01:00 Paul Burton paul.burton@imgtec.com:
Currently we have mips32-specific & mips64-specific versions of start.S, which are very similar. This short series adapts the mips32 start.S to also be suitable for mips64 systems & then shares that single copy between mips32 & mips64 builds.
Paul Burton (4): MIPS: use asm.h macros in mips32 start.S MIPS: handle mips64 relocs in mips32 start.S MIPS: handle mips64 ST0_KX bit in mips32 start.S MIPS: share start.S between mips32 & mips64
very appreciated, thanks. But I'd like to replace patch 4/4 with
http://patchwork.ozlabs.org/patch/434556/ http://patchwork.ozlabs.org/patch/434555/
what do you think?
On Thu, Jan 29, 2015 at 02:48:59PM +0100, Daniel Schwierzeck wrote:
Hi Paul,
2015-01-29 11:04 GMT+01:00 Paul Burton paul.burton@imgtec.com:
Currently we have mips32-specific & mips64-specific versions of start.S, which are very similar. This short series adapts the mips32 start.S to also be suitable for mips64 systems & then shares that single copy between mips32 & mips64 builds.
Paul Burton (4): MIPS: use asm.h macros in mips32 start.S MIPS: handle mips64 relocs in mips32 start.S MIPS: handle mips64 ST0_KX bit in mips32 start.S MIPS: share start.S between mips32 & mips64
very appreciated, thanks. But I'd like to replace patch 4/4 with
http://patchwork.ozlabs.org/patch/434556/ http://patchwork.ozlabs.org/patch/434555/
what do you think?
--
- Daniel
Hi Daniel,
Seems good to me :)
Paul
participants (2)
-
Daniel Schwierzeck -
Paul Burton