[PATCH] ARM: zynq: Add missing twd timer for mini configurations
The commit b7e0750d8872 ("zynq: Convert arm twd timer to DM driver") switched timer to DM but missing to add nodes to all mini configurations. Based on it missing timer end up in non functional system where any delay doesn't work.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynq-cse-nand.dts | 7 +++++++ arch/arm/dts/zynq-cse-nor.dts | 7 +++++++ arch/arm/dts/zynq-cse-qspi.dtsi | 7 +++++++ 3 files changed, 21 insertions(+)
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts index 32cb3bffcb94..27adfb921622 100644 --- a/arch/arm/dts/zynq-cse-nand.dts +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -86,6 +86,13 @@ reg = <0x100 0x100>; }; }; + + scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clock-frequency = <333333333>; + }; }; };
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index 197fbd717aae..f22a149f7924 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -85,6 +85,13 @@ #address-cells = <1>; #size-cells = <1>; }; + + scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clock-frequency = <333333333>; + }; }; };
diff --git a/arch/arm/dts/zynq-cse-qspi.dtsi b/arch/arm/dts/zynq-cse-qspi.dtsi index 38410eeca886..f7ac92b8026d 100644 --- a/arch/arm/dts/zynq-cse-qspi.dtsi +++ b/arch/arm/dts/zynq-cse-qspi.dtsi @@ -116,6 +116,13 @@ reg = <0x100 0x100>; }; }; + + scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clock-frequency = <333333333>; + }; };
};
On 11/29/22 13:23, Michal Simek wrote:
The commit b7e0750d8872 ("zynq: Convert arm twd timer to DM driver") switched timer to DM but missing to add nodes to all mini configurations. Based on it missing timer end up in non functional system where any delay doesn't work.
Signed-off-by: Michal Simek michal.simek@amd.com
arch/arm/dts/zynq-cse-nand.dts | 7 +++++++ arch/arm/dts/zynq-cse-nor.dts | 7 +++++++ arch/arm/dts/zynq-cse-qspi.dtsi | 7 +++++++ 3 files changed, 21 insertions(+)
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts index 32cb3bffcb94..27adfb921622 100644 --- a/arch/arm/dts/zynq-cse-nand.dts +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -86,6 +86,13 @@ reg = <0x100 0x100>; }; };
scutimer: timer@f8f00600 {u-boot,dm-pre-reloc;compatible = "arm,cortex-a9-twd-timer";reg = <0xf8f00600 0x20>;clock-frequency = <333333333>;};diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index 197fbd717aae..f22a149f7924 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -85,6 +85,13 @@ #address-cells = <1>; #size-cells = <1>; };
scutimer: timer@f8f00600 {u-boot,dm-pre-reloc;compatible = "arm,cortex-a9-twd-timer";reg = <0xf8f00600 0x20>;clock-frequency = <333333333>;};diff --git a/arch/arm/dts/zynq-cse-qspi.dtsi b/arch/arm/dts/zynq-cse-qspi.dtsi index 38410eeca886..f7ac92b8026d 100644 --- a/arch/arm/dts/zynq-cse-qspi.dtsi +++ b/arch/arm/dts/zynq-cse-qspi.dtsi @@ -116,6 +116,13 @@ reg = <0x100 0x100>; }; };
scutimer: timer@f8f00600 {u-boot,dm-pre-reloc;compatible = "arm,cortex-a9-twd-timer";reg = <0xf8f00600 0x20>;clock-frequency = <333333333>;};};
};
Applied. M
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Michal Simek