Hi Jagan,

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-----Original Message----- From: Jagan Teki [mailto:jagannadh.teki@gmail.com] Sent: Friday, August 11, 2017 4:44 PM To: Suresh Gupta suresh.gupta@nxp.com Cc: u-boot@lists.denx.de; Jagan Teki jagan@openedev.com; yorksun@freescale.com; Anupam Kumar anupam.kumar_1@nxp.com Subject: Re: [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

On Mon, Jun 5, 2017 at 2:37 PM, Suresh Gupta suresh.gupta@nxp.com

wrote:

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In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta suresh.gupta@nxp.com Signed-off-by: Anupam Kumar anupam.kumar_1@nxp.com

Can some one Tested and verified the result?

Please pick this patch, we have the same patch in our SDK from last 2 months and do not face any issue.

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thanks!

Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.