[U-Boot] [PATCH 1/7] mx35: Move clock enums to clock.h
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/arm1136/mx35/generic.c | 4 +-- .../arch/arm/include/asm/arch-mx35/clock.h | 28 +++++++++++++++++++- .../arch/arm/include/asm/arch-mx35/imx-regs.h | 26 ------------------ 3 files changed, 29 insertions(+), 29 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index 986b1f9..dba4903 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -205,7 +205,7 @@ u32 imx_get_uartclk(void) return freq; }
-unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) +unsigned int mxc_get_main_clock(enum mxc_main_clock clk) { u32 nfc_pdf, hsp_podf; u32 pll, ret_val = 0, usb_prdf, usb_podf; @@ -270,7 +270,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
return ret_val; } -unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) +unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) { u32 ret_val = 0, pdf, pre_pdf, clk_sel; struct ccm_regs *ccm = diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/clock.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/clock.h index 4c0ddfd..5dc53ba 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/clock.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/clock.h @@ -25,7 +25,7 @@ #define __ASM_ARCH_CLOCK_H
enum mxc_clock { - MXC_ARM_CLK = 0, + MXC_ARM_CLK, MXC_AHB_CLK, MXC_IPG_CLK, MXC_IPG_PERCLK, @@ -36,6 +36,32 @@ enum mxc_clock { MXC_FEC_CLK, };
+enum mxc_main_clock { + CPU_CLK, + AHB_CLK, + IPG_CLK, + IPG_PER_CLK, + NFC_CLK, + USB_CLK, + HSP_CLK, +}; + +enum mxc_peri_clock { + UART1_BAUD, + UART2_BAUD, + UART3_BAUD, + SSI1_BAUD, + SSI2_BAUD, + CSI_BAUD, + MSHC_CLK, + ESDHC1_CLK, + ESDHC2_CLK, + ESDHC3_CLK, + SPDIF_CLK, + SPI1_CLK, + SPI2_CLK, +}; + unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
u32 imx_get_uartclk(void); diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h index 3146006..fba29b2 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -216,32 +216,6 @@ #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h>
-enum mxc_main_clocks { - CPU_CLK, - AHB_CLK, - IPG_CLK, - IPG_PER_CLK, - NFC_CLK, - USB_CLK, - HSP_CLK, -}; - -enum mxc_peri_clocks { - UART1_BAUD, - UART2_BAUD, - UART3_BAUD, - SSI1_BAUD, - SSI2_BAUD, - CSI_BAUD, - MSHC_CLK, - ESDHC1_CLK, - ESDHC2_CLK, - ESDHC3_CLK, - SPDIF_CLK, - SPI1_CLK, - SPI2_CLK, -}; - /* Clock Control Module (CCM) registers */ struct ccm_regs { u32 ccmr; /* Control */
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/include/asm/arch-mx35/clock.h | 2 -- 1 file changed, 2 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/clock.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/clock.h index 5dc53ba..e94f124 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/clock.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/clock.h @@ -62,8 +62,6 @@ enum mxc_peri_clock { SPI2_CLK, };
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); - u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk);
On 14/08/2012 22:32, Benoît Thébaudeau wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Hi Benoît,
.../arch/arm/include/asm/arch-mx35/clock.h | 2 -- 1 file changed, 2 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/clock.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/clock.h index 5dc53ba..e94f124 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/clock.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/clock.h @@ -62,8 +62,6 @@ enum mxc_peri_clock { SPI2_CLK, };
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk);
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
The MFN bit-field of the PLL registers represents a signed value. See the reference manual.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/arm1136/mx35/generic.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index dba4903..e369c86 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -24,6 +24,7 @@ */
#include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> @@ -126,15 +127,17 @@ static int get_ahb_div(u32 pdr0) static u32 decode_pll(u32 reg, u32 infreq) { u32 mfi = (reg >> 10) & 0xf; - u32 mfn = reg & 0x3f; - u32 mfd = (reg >> 16) & 0x3f; + s32 mfn = reg & 0x3ff; + u32 mfd = (reg >> 16) & 0x3ff; u32 pd = (reg >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1;
- return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); }
static u32 get_mcu_main_clk(void)
On 14/08/2012 22:32, Benoît Thébaudeau wrote:
The MFN bit-field of the PLL registers represents a signed value. See the reference manual.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Hi Benoît,
.../arch/arm/cpu/arm1136/mx35/generic.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index dba4903..e369c86 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -24,6 +24,7 @@ */
#include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> @@ -126,15 +127,17 @@ static int get_ahb_div(u32 pdr0) static u32 decode_pll(u32 reg, u32 infreq) { u32 mfi = (reg >> 10) & 0xf;
- u32 mfn = reg & 0x3f;
- u32 mfd = (reg >> 16) & 0x3f;
- s32 mfn = reg & 0x3ff;
- u32 mfd = (reg >> 16) & 0x3ff;
The MFN is a signed value. But you are masking now 11 bits. According to the manual, bit 9-0 are MFN. You are taking in the mask the first bit of MFI, and this is wrong, isn't it ?
Best regards, Stefano Babic
Am 01/09/2012 10:15, schrieb Stefano Babic:
On 14/08/2012 22:32, Benoît Thébaudeau wrote:
The MFN bit-field of the PLL registers represents a signed value. See the reference manual.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Hi Benoît,
.../arch/arm/cpu/arm1136/mx35/generic.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index dba4903..e369c86 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -24,6 +24,7 @@ */
#include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> @@ -126,15 +127,17 @@ static int get_ahb_div(u32 pdr0) static u32 decode_pll(u32 reg, u32 infreq) { u32 mfi = (reg >> 10) & 0xf;
- u32 mfn = reg & 0x3f;
- u32 mfd = (reg >> 16) & 0x3f;
- s32 mfn = reg & 0x3ff;
- u32 mfd = (reg >> 16) & 0x3ff;
The MFN is a signed value. But you are masking now 11 bits. According to the manual, bit 9-0 are MFN. You are taking in the mask the first bit of MFI, and this is wrong, isn't it ?
Sorry, mask is correct
Regards, Stefano
On 14/08/2012 22:32, Benoît Thébaudeau wrote:
The MFN bit-field of the PLL registers represents a signed value. See the reference manual.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/include/asm/arch-mx35/crm_regs.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/crm_regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/crm_regs.h index e903cf1..66bc1ba 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/crm_regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -144,6 +144,12 @@ #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0)
/* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR_CG_MASK 0x3 +#define MXC_CCM_CGR_CG_OFF 0x0 +#define MXC_CCM_CGR_CG_RUN_ON 0x1 +#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 +#define MXC_CCM_CGR_CG_ON 0x3 + #define MXC_CCM_CGR0_ASRC_OFFSET 0 #define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) #define MXC_CCM_CGR0_ATA_OFFSET 2
On 14/08/2012 22:33, Benoît Thébaudeau wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/arm1136/mx35/generic.c | 48 ++++++++------------ .../arch/arm/include/asm/arch-mx35/crm_regs.h | 42 ++++++----------- 2 files changed, 31 insertions(+), 59 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index e369c86..4af052c 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -171,17 +171,14 @@ static u32 get_ipg_per_clk(void) u32 pdr4 = readl(&ccm->pdr4); u32 div; if (pdr0 & MXC_CCM_PDR0_PER_SEL) { - div = (CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_PER0_PRDF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + div = CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_PER0_PODF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; } else { div = CCM_GET_DIVIDER(pdr0, MXC_CCM_PDR0_PER_PODF_MASK, MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; - freq /= get_ahb_div(pdr0); + div *= get_ahb_div(pdr0); } return freq / div; } @@ -199,19 +196,16 @@ u32 imx_get_uartclk(void) freq = decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ); } - freq /= ((CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_UART_PRDF_MASK, - MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + freq /= CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_UART_PODF_MASK, - MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; return freq; }
unsigned int mxc_get_main_clock(enum mxc_main_clock clk) { u32 nfc_pdf, hsp_podf; - u32 pll, ret_val = 0, usb_prdf, usb_podf; + u32 pll, ret_val = 0, usb_podf; struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
@@ -255,8 +249,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) ret_val = pll / (nfc_pdf + 1); break; case USB_CLK: - usb_prdf = (reg4 >> 25) & 0x7; - usb_podf = (reg4 >> 22) & 0x7; + usb_podf = (reg4 >> 22) & 0x3F; if (reg4 & 0x200) { pll = get_mcu_main_clk(); } else { @@ -264,7 +257,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) CONFIG_MX35_HCLK_FREQ); }
- ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); + ret_val = pll / (usb_podf + 1); break; default: printf("Unknown clock: %d\n", clk); @@ -287,11 +280,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) case UART2_BAUD: case UART3_BAUD: clk_sel = mpdr3 & (1 << 14); - pre_pdf = (mpdr4 >> 13) & 0x7; - pdf = (mpdr4 >> 10) & 0x7; + pdf = (mpdr4 >> 10) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case SSI1_BAUD: pre_pdf = (mpdr2 >> 24) & 0x7; @@ -311,11 +303,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) break; case CSI_BAUD: clk_sel = mpdr2 & (1 << 7); - pre_pdf = (mpdr2 >> 16) & 0x7; - pdf = (mpdr2 >> 19) & 0x7; + pdf = (mpdr2 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case MSHC_CLK: pre_pdf = readl(&ccm->pdr1); @@ -328,27 +319,24 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) break; case ESDHC1_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = mpdr3 & 0x7; - pdf = (mpdr3>>3) & 0x7; + pdf = mpdr3 & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case ESDHC2_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 8) & 0x7; - pdf = (mpdr3 >> 11) & 0x7; + pdf = (mpdr3 >> 8) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case ESDHC3_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 16) & 0x7; - pdf = (mpdr3 >> 19) & 0x7; + pdf = (mpdr3 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case SPDIF_CLK: clk_sel = mpdr3 & 0x400000; diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/crm_regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/crm_regs.h index 66bc1ba..f6b381b 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/crm_regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -32,8 +32,8 @@ #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) #define MXC_CCM_CCMR_ROMW_OFFSET 18 #define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) -#define MXC_CCM_CCMR_RAMW_OFFSET 21 -#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) +#define MXC_CCM_CCMR_RAMW_OFFSET 16 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) #define MXC_CCM_CCMR_LPM_OFFSET 14 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) #define MXC_CCM_CCMR_UPE (1 << 9) @@ -47,7 +47,7 @@ #define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) #define MXC_CCM_PDR0_CKIL_SEL (1 << 15) #define MXC_CCM_PDR0_PER_PODF_OFFSET 12 -#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) +#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) #define MXC_CCM_PDR0_AUTO_CON 0x1 @@ -62,10 +62,8 @@ #define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 #define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) -#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 -#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) #define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 -#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 #define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) #define MXC_CCM_PDR2_CSI_M_U (1 << 7) @@ -78,35 +76,23 @@ #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 #define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) #define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) -#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 -#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 -#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) -#define MXC_CCM_PDR3_UART_M_U (1 << 15) -#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 -#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 14) #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 -#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) #define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) -#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 -#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 -#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F)
#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 #define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) -#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 -#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) #define MXC_CCM_PDR4_USB_PODF_OFFSET 22 -#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) -#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 -#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) #define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 -#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) -#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 -#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR4_UART_PODF_OFFSET 10 -#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) +#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) #define MXC_CCM_PDR4_USB_M_U (1 << 9)
/* Bit definitions for RCSR */ @@ -257,10 +243,8 @@ #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 #define MXC_CCM_COSR_CLKOEN (1 << 5) #define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) -#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) -#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 -#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) -#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 +#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) +#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)
On 14/08/2012 22:33, Benoît Thébaudeau wrote:
The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
.../arch/arm/cpu/arm1136/mx35/generic.c | 48 ++++++++------------ .../arch/arm/include/asm/arch-mx35/crm_regs.h | 42 ++++++----------- 2 files changed, 31 insertions(+), 59 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index e369c86..4af052c 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -171,17 +171,14 @@ static u32 get_ipg_per_clk(void) u32 pdr4 = readl(&ccm->pdr4); u32 div; if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
div = (CCM_GET_DIVIDER(pdr4,MXC_CCM_PDR4_PER0_PRDF_MASK,MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *(CCM_GET_DIVIDER(pdr4,
It seems also to me that the current code is wrong if MXC_CCM_PDR0_PER_SEL is set. Maybe it was never set. As I see in figure 5-4, the ipg_per_clk depends only on pdr[21:16]. No idea where the second multiplier comes.
div = CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_PER0_PODF_MASK,
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
The name remains quite confusing. In the manual is PER0_DIV, which is the meaning of PODF here ?
Anyway, the masks you set are correct, I agree.
} else { div = CCM_GET_DIVIDER(pdr0, MXC_CCM_PDR0_PER_PODF_MASK, MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
freq /= get_ahb_div(pdr0);
div *= get_ahb_div(pdr0);
This does not change the behavior.
} return freq / div; } @@ -199,19 +196,16 @@ u32 imx_get_uartclk(void) freq = decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ); }
- freq /= ((CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_UART_PRDF_MASK,MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *(CCM_GET_DIVIDER(pdr4,
- freq /= CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_UART_PODF_MASK,
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
This is also right. I am only asking myself why it works correctly now.
return freq; }
unsigned int mxc_get_main_clock(enum mxc_main_clock clk) { u32 nfc_pdf, hsp_podf;
- u32 pll, ret_val = 0, usb_prdf, usb_podf;
- u32 pll, ret_val = 0, usb_podf; struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
@@ -255,8 +249,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) ret_val = pll / (nfc_pdf + 1); break; case USB_CLK:
usb_prdf = (reg4 >> 25) & 0x7;usb_podf = (reg4 >> 22) & 0x7;
usb_podf = (reg4 >> 22) & 0x3F;
Agree again. The code seems generated from another manual. Maybe the USB_DIV field was split into two fields. With this in mind, there is no apparent error in current code, but it cannot be derived from the manual.
break;default: printf("Unknown clock: %d\n", clk); @@ -287,11 +280,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) case UART2_BAUD: case UART3_BAUD: clk_sel = mpdr3 & (1 << 14);
pre_pdf = (mpdr4 >> 13) & 0x7;pdf = (mpdr4 >> 10) & 0x7;
pdf = (mpdr4 >> 10) & 0x3F;
Right !
The main issue about this patch is that it does not fix one problem, but a lot of. Really it should be split into several patches. Anyway, I will make some tests on the mx35 boards I have - if I will not get problems, I will push it, hoping that someone else can make some further tests.
Best regards, Stefano
Hi Stefano,
On Saturday, September 1, 2012 11:15:35 AM, Stefano Babic wrote:
On 14/08/2012 22:33, Benoît Thébaudeau wrote:
The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
.../arch/arm/cpu/arm1136/mx35/generic.c | 48 ++++++++------------ .../arch/arm/include/asm/arch-mx35/crm_regs.h | 42 ++++++----------- 2 files changed, 31 insertions(+), 59 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index e369c86..4af052c 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -171,17 +171,14 @@ static u32 get_ipg_per_clk(void) u32 pdr4 = readl(&ccm->pdr4); u32 div; if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
div = (CCM_GET_DIVIDER(pdr4,MXC_CCM_PDR4_PER0_PRDF_MASK,MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *(CCM_GET_DIVIDER(pdr4,It seems also to me that the current code is wrong if MXC_CCM_PDR0_PER_SEL is set. Maybe it was never set. As I see in figure 5-4, the ipg_per_clk depends only on pdr[21:16]. No idea where the second multiplier comes.
It looks like the current code is based on a pre(PRDF)-/post(PODF)-divider scheme. Perhaps the first silicon revision was different and incompatible, or it was just a bug in the older revisions of the reference manual. The history of the reference manual says that this figure and some CCM register descriptions have been updated at some point. Anyway, Linux does like my patch.
div = CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_PER0_PODF_MASK,
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;The name remains quite confusing. In the manual is PER0_DIV, which is the meaning of PODF here ?
It the abbreviation FSL uses for post-dividers. If the pre-divider is merged with the post-divider to form a single divider, the naming from the RM makes more sense. Do you want a new version changing this naming?
Anyway, the masks you set are correct, I agree.
} else { div = CCM_GET_DIVIDER(pdr0, MXC_CCM_PDR0_PER_PODF_MASK, MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
freq /= get_ahb_div(pdr0);
div *= get_ahb_div(pdr0);This does not change the behavior.
It does: Dividing twice in a row affects rounding.
} return freq / div; } @@ -199,19 +196,16 @@ u32 imx_get_uartclk(void) freq = decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ); }
- freq /= ((CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_UART_PRDF_MASK,MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *(CCM_GET_DIVIDER(pdr4,
- freq /= CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_UART_PODF_MASK,
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;This is also right. I am only asking myself why it works correctly now.
It currently works... or not depending on the divider settings selected by board inits. As long as the bits in the current PRDF bit-fields are kept cleared (luck...), it works.
return freq; }
unsigned int mxc_get_main_clock(enum mxc_main_clock clk) { u32 nfc_pdf, hsp_podf;
- u32 pll, ret_val = 0, usb_prdf, usb_podf;
- u32 pll, ret_val = 0, usb_podf; struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
@@ -255,8 +249,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) ret_val = pll / (nfc_pdf + 1); break; case USB_CLK:
usb_prdf = (reg4 >> 25) & 0x7;usb_podf = (reg4 >> 22) & 0x7;
usb_podf = (reg4 >> 22) & 0x3F;Agree again. The code seems generated from another manual. Maybe the USB_DIV field was split into two fields. With this in mind, there is no apparent error in current code, but it cannot be derived from the manual.
The resulting frequency is different here too if some PRDF bits are set.
break;default: printf("Unknown clock: %d\n", clk); @@ -287,11 +280,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) case UART2_BAUD: case UART3_BAUD: clk_sel = mpdr3 & (1 << 14);
pre_pdf = (mpdr4 >> 13) & 0x7;pdf = (mpdr4 >> 10) & 0x7;
pdf = (mpdr4 >> 10) & 0x3F;Right !
The main issue about this patch is that it does not fix one problem, but a lot of. Really it should be split into several patches.
Indeed, but these problems have a common root cause: wrong RM in some way.
Anyway, I will make some tests on the mx35 boards I have - if I will not get problems, I will push it, hoping that someone else can make some further tests.
OK. I have also tested it on a board that I have here.
The best test would be to set some PRDF bits and to scope the resulting frequency (e.g. with PER0_DIV and I²C SCL). I'm not sure I have already performed this specific test. I'll do that when possible.
There is also stuff like AUTO_CON and AUTO_MUX_DIV that are now marked as reserved in the RM. I've kept this code since it can not be harmful contrary to the wrong decoding of the divider fields.
Best regards, Benoît
On 03/09/2012 17:31, Benoît Thébaudeau wrote:
Hi Stefano,
Hi Benoît,
It seems also to me that the current code is wrong if MXC_CCM_PDR0_PER_SEL is set. Maybe it was never set. As I see in figure 5-4, the ipg_per_clk depends only on pdr[21:16]. No idea where the second multiplier comes.
It looks like the current code is based on a pre(PRDF)-/post(PODF)-divider scheme.
I thought the same.
Perhaps the first silicon revision was different and incompatible, or it was just a bug in the older revisions of the reference manual. The history of the reference manual says that this figure and some CCM register descriptions have been updated at some point. Anyway, Linux does like my patch.
div = CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_PER0_PODF_MASK,
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;The name remains quite confusing. In the manual is PER0_DIV, which is the meaning of PODF here ?
It the abbreviation FSL uses for post-dividers. If the pre-divider is merged with the post-divider to form a single divider, the naming from the RM makes more sense. Do you want a new version changing this naming?
Yes, make this small change - then from my point of view I am ready to merge it.
Regards, Stefano
On 03/09/2012 17:55, Stefano Babic wrote:
Yes, make this small change - then from my point of view I am ready to merge it.
Nevermind - this is really a detail. I prefer to fix soon the bugs. Thanks for having discovered and fixed. I merge the series now.
Regards, Stefano
On 14/08/2012 22:33, Benoît Thébaudeau wrote:
The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
Each eSDHC instance has a dedicated clock.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/arm1136/mx35/generic.c | 14 ++++++++++++-- .../arch/arm/include/asm/arch-mx35/clock.h | 4 +++- 2 files changed, 15 insertions(+), 3 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index 4af052c..15a0098 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -368,8 +368,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_ipg_per_clk(); case MXC_UART_CLK: return imx_get_uartclk(); - case MXC_ESDHC_CLK: + case MXC_ESDHC1_CLK: return mxc_get_peri_clock(ESDHC1_CLK); + case MXC_ESDHC2_CLK: + return mxc_get_peri_clock(ESDHC2_CLK); + case MXC_ESDHC3_CLK: + return mxc_get_peri_clock(ESDHC3_CLK); case MXC_USB_CLK: return mxc_get_main_clock(USB_CLK); case MXC_FEC_CLK: @@ -469,7 +473,13 @@ int cpu_eth_init(bd_t *bis) int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC - gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC1_BASE_ADDR + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); +#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); +#endif #endif return 0; } diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/clock.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/clock.h index e94f124..0575dad 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/clock.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/clock.h @@ -30,7 +30,9 @@ enum mxc_clock { MXC_IPG_CLK, MXC_IPG_PERCLK, MXC_UART_CLK, - MXC_ESDHC_CLK, + MXC_ESDHC1_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, MXC_USB_CLK, MXC_CSPI_CLK, MXC_FEC_CLK,
On 14/08/2012 22:33, Benoît Thébaudeau wrote:
Each eSDHC instance has a dedicated clock.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Hi Benoît,
.../arch/arm/cpu/arm1136/mx35/generic.c | 14 ++++++++++++-- .../arch/arm/include/asm/arch-mx35/clock.h | 4 +++- 2 files changed, 15 insertions(+), 3 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index 4af052c..15a0098 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -368,8 +368,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_ipg_per_clk(); case MXC_UART_CLK: return imx_get_uartclk();
- case MXC_ESDHC_CLK:
- case MXC_ESDHC1_CLK: return mxc_get_peri_clock(ESDHC1_CLK);
- case MXC_ESDHC2_CLK:
return mxc_get_peri_clock(ESDHC2_CLK);- case MXC_ESDHC3_CLK:
return mxc_get_peri_clock(ESDHC3_CLK);
Your change let understand that we can have different clocks among the ESDHC controllers. One thing is not clear to me is that the MX35 have two ESDHC controllers, and you define here a thitd one. Where is it ?
Even if the two controllers can have different clocks, this is not supported by the driver. In fact, in drivers/mmc/fsl_esdhc.c:
int sdhc_clk = gd->sdhc_clk;
The driver uses always the same clock, stored in the global structure. Before extending the code as in this patch, the driver should be modified to handle separate clocks. Currently the driver supports multiple controller, but they share the same clock or at least the same frequency.
Best regards, Stefano
Hi Stefano,
On 14/08/2012 22:33, Benoît Thébaudeau wrote:
Each eSDHC instance has a dedicated clock.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Hi Benoît,
.../arch/arm/cpu/arm1136/mx35/generic.c | 14 ++++++++++++-- .../arch/arm/include/asm/arch-mx35/clock.h | 4 +++- 2 files changed, 15 insertions(+), 3 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index 4af052c..15a0098 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -368,8 +368,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_ipg_per_clk(); case MXC_UART_CLK: return imx_get_uartclk();
- case MXC_ESDHC_CLK:
- case MXC_ESDHC1_CLK: return mxc_get_peri_clock(ESDHC1_CLK);
- case MXC_ESDHC2_CLK:
return mxc_get_peri_clock(ESDHC2_CLK);- case MXC_ESDHC3_CLK:
return mxc_get_peri_clock(ESDHC3_CLK);Your change let understand that we can have different clocks among the ESDHC controllers.
Indeed.
One thing is not clear to me is that the MX35 have two ESDHC controllers, and you define here a thitd one. Where is it ?
No, there are 3. See the reference manual. It's referenced in the memory map, in the interrupts, in the pin multiplexing and in the clocks.
Even if the two controllers can have different clocks, this is not supported by the driver. In fact, in drivers/mmc/fsl_esdhc.c:
int sdhc_clk = gd->sdhc_clk;
The driver uses always the same clock, stored in the global structure. Before extending the code as in this patch, the driver should be modified to handle separate clocks. Currently the driver supports multiple controller, but they share the same clock or at least the same frequency.
Indeed, I had seen that. I didn't know what to decide as to the driver clocks, so I made this change to select the correct clock if a single clock or frequency is used.
If several clock frequencies are to be supported at once, what kind of API would you like? gd->sdhc_clk could be changed to an array, then the corresponding index could be passed to the init function through the fsl_esdhc_cfg struct.
Best regards, Benoît
Hi Stefano,
Even if the two controllers can have different clocks, this is not supported by the driver. In fact, in drivers/mmc/fsl_esdhc.c:
int sdhc_clk = gd->sdhc_clk;
The driver uses always the same clock, stored in the global structure. Before extending the code as in this patch, the driver should be modified to handle separate clocks. Currently the driver supports multiple controller, but they share the same clock or at least the same frequency.
Indeed, I had seen that. I didn't know what to decide as to the driver clocks, so I made this change to select the correct clock if a single clock or frequency is used.
If several clock frequencies are to be supported at once, what kind of API would you like? gd->sdhc_clk could be changed to an array, then the corresponding index could be passed to the init function through the fsl_esdhc_cfg struct.
But there is also the issue of fsl_esdhc_mmc_init() that would need a new config just to pass this index. I don't like that. Any suggestion?
Best regards, Benoît
On 20/08/2012 14:34, Benoît Thébaudeau wrote:
Hi Stefano,
Hi Benoît,
Even if the two controllers can have different clocks, this is not supported by the driver. In fact, in drivers/mmc/fsl_esdhc.c:
int sdhc_clk = gd->sdhc_clk;
The driver uses always the same clock, stored in the global structure. Before extending the code as in this patch, the driver should be modified to handle separate clocks. Currently the driver supports multiple controller, but they share the same clock or at least the same frequency.
Indeed, I had seen that. I didn't know what to decide as to the driver clocks, so I made this change to select the correct clock if a single clock or frequency is used.
If several clock frequencies are to be supported at once, what kind of API would you like? gd->sdhc_clk could be changed to an array, then the corresponding index could be passed to the init function through the fsl_esdhc_cfg struct.
But there is also the issue of fsl_esdhc_mmc_init() that would need a new config just to pass this index. I don't like that. Any suggestion?
There is another issue. The driver is used by both ARM (i.MX) and PowerPCs (PowerQuickIII, ...).
fsl_esdhc_mmc_init() is already the interface when one parameter is enough. If we need more than one controller, we should already call fsl_esdhc_initialize() with the cfg structure.
Then adding a field to the struct fsl_esdhc_cfg is maybe not too bad. Instead of an index, we can add directly the frequency - reading the driver this is all that the driver needs.
Best regards, Stefano
Hi Stefano,
Even if the two controllers can have different clocks, this is not supported by the driver. In fact, in drivers/mmc/fsl_esdhc.c:
int sdhc_clk = gd->sdhc_clk;
The driver uses always the same clock, stored in the global structure. Before extending the code as in this patch, the driver should be modified to handle separate clocks. Currently the driver supports multiple controller, but they share the same clock or at least the same frequency.
Indeed, I had seen that. I didn't know what to decide as to the driver clocks, so I made this change to select the correct clock if a single clock or frequency is used.
If several clock frequencies are to be supported at once, what kind of API would you like? gd->sdhc_clk could be changed to an array, then the corresponding index could be passed to the init function through the fsl_esdhc_cfg struct.
But there is also the issue of fsl_esdhc_mmc_init() that would need a new config just to pass this index. I don't like that. Any suggestion?
There is another issue. The driver is used by both ARM (i.MX) and PowerPCs (PowerQuickIII, ...).
fsl_esdhc_mmc_init() is already the interface when one parameter is enough. If we need more than one controller, we should already call fsl_esdhc_initialize() with the cfg structure.
Then adding a field to the struct fsl_esdhc_cfg is maybe not too bad. Instead of an index, we can add directly the frequency - reading the driver this is all that the driver needs.
OK, then this patch does the job for the single eSDHC instance use case, which will still use gd->sdhc_clk. I will make another patch before or after this one for the multi-instance use case. I will do the same in the v2 of my mx5 clock series (for gd->sdhc_clk). I think I also have the same stuff for mx25.
Best regards, Benoît
On 20/08/2012 14:55, Benoît Thébaudeau wrote:
OK, then this patch does the job for the single eSDHC instance use case, which will still use gd->sdhc_clk.
Yes, but then we do not need ESDHC1, ESDHC2 and ESDHC3, because the driver does not support different clocks.
I will make another patch before or after this one for the multi-instance use case.
Fine.
I will do the same in the v2 of my mx5 clock series (for gd->sdhc_clk). I think I also have the same stuff for mx25.
Ok - I read the series for MX5, but I need to check it with the manuals to understand the changes. I need some more time...
Best regards, Stefano
Hi Stefano,
OK, then this patch does the job for the single eSDHC instance use case, which will still use gd->sdhc_clk.
Yes, but then we do not need ESDHC1, ESDHC2 and ESDHC3, because the driver does not support different clocks.
We need them: Yes, the driver supports a single eSDHC instance and a single clock with gd->sdhc_clk and fsl_esdhc_mmc_init(), but there is a choice to determine at compile time depending on CONFIG_SYS_FSL_ESDHC_ADDR. You don't want to use the clock of eSDHC1 if CONFIG_SYS_FSL_ESDHC_ADDR selects eSDHC2. This is use case exists on i.MX with cpu_mmc_init() if a single eSDHC instance is needed.
I will make another patch before or after this one for the multi-instance use case.
Fine.
OK.
I will do the same in the v2 of my mx5 clock series (for gd->sdhc_clk). I think I also have the same stuff for mx25.
Ok - I read the series for MX5, but I need to check it with the manuals to understand the changes. I need some more time...
No problem.
Best regards, Benoît
Each eSDHC instance has a dedicated clock.
gd->sdhc_clk must also be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()).
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de Cc: Eric Bénard eric@eukrea.com Cc: Otavio Salvador otavio@ossystems.com.br --- This patch supersedes http://patchwork.ozlabs.org/patch/177438/ . Changes for v2: - Improve detailed description. - Make eSDHC1 the default for gd->sdhc_clk.
.../arch/arm/cpu/arm1136/mx35/generic.c | 14 ++++++++++++-- .../arch/arm/include/asm/arch-mx35/clock.h | 4 +++- 2 files changed, 15 insertions(+), 3 deletions(-)
diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-imx-e1eb75b/arch/arm/cpu/arm1136/mx35/generic.c index ef65176..75c25d4 100644 --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-imx-e1eb75b/arch/arm/cpu/arm1136/mx35/generic.c @@ -360,8 +360,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_ipg_per_clk(); case MXC_UART_CLK: return imx_get_uartclk(); - case MXC_ESDHC_CLK: + case MXC_ESDHC1_CLK: return mxc_get_peri_clock(ESDHC1_CLK); + case MXC_ESDHC2_CLK: + return mxc_get_peri_clock(ESDHC2_CLK); + case MXC_ESDHC3_CLK: + return mxc_get_peri_clock(ESDHC3_CLK); case MXC_USB_CLK: return mxc_get_main_clock(USB_CLK); case MXC_FEC_CLK: @@ -471,7 +475,13 @@ int cpu_mmc_init(bd_t *bis) int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC - gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); +#else + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); +#endif #endif return 0; } diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx35/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx35/clock.h index eb7458a..60285df 100644 --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx35/clock.h +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx35/clock.h @@ -44,7 +44,9 @@ enum mxc_clock { MXC_IPG_CLK, MXC_IPG_PERCLK, MXC_UART_CLK, - MXC_ESDHC_CLK, + MXC_ESDHC1_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, MXC_USB_CLK, MXC_CSPI_CLK, MXC_FEC_CLK,
On 27/09/2012 22:26, Benoît Thébaudeau wrote:
Each eSDHC instance has a dedicated clock.
gd->sdhc_clk must also be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()).
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de Cc: Eric Bénard eric@eukrea.com Cc: Otavio Salvador otavio@ossystems.com.br
Applied to u-boot-imx, next branch, thanks.
Best regards, Stefano Babic
Add cpu_mmc_init() function to make it easy to init a single eSDHC instance.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/arm1136/mx35/generic.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index 15a0098..7b643b7 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -31,6 +31,9 @@ #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_FSL_ESDHC +#include <fsl_esdhc.h> +#endif #include <netdev.h>
#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) @@ -458,7 +461,6 @@ int print_cpuinfo(void) * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() */ - int cpu_eth_init(bd_t *bis) { int rc = -ENODEV; @@ -470,6 +472,21 @@ int cpu_eth_init(bd_t *bis) return rc; }
+/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t * bis) +{ + int rc = -ENODEV; + +#ifdef CONFIG_FSL_ESDHC + rc = fsl_esdhc_mmc_init(bis); +#endif + + return rc; +} + int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC
Add cpu_mmc_init() function to make it easy to init a single eSDHC instance.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- Changes for v2: - Do not define cpu_mmc_init() if CONFIG_FSL_ESDHC is not defined.
.../arch/arm/cpu/arm1136/mx35/generic.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index 15a0098..8f61069 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -31,6 +31,9 @@ #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_FSL_ESDHC +#include <fsl_esdhc.h> +#endif #include <netdev.h>
#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) @@ -458,7 +461,6 @@ int print_cpuinfo(void) * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() */ - int cpu_eth_init(bd_t *bis) { int rc = -ENODEV; @@ -470,6 +472,17 @@ int cpu_eth_init(bd_t *bis) return rc; }
+#ifdef CONFIG_FSL_ESDHC +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ + return fsl_esdhc_mmc_init(bis); +} +#endif + int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC
On 17/08/2012 22:43, Benoît Thébaudeau wrote:
Add cpu_mmc_init() function to make it easy to init a single eSDHC instance.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Changes for v2:
- Do not define cpu_mmc_init() if CONFIG_FSL_ESDHC is not defined.
.../arch/arm/cpu/arm1136/mx35/generic.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index 15a0098..8f61069 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -31,6 +31,9 @@ #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_FSL_ESDHC +#include <fsl_esdhc.h> +#endif #include <netdev.h>
#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) @@ -458,7 +461,6 @@ int print_cpuinfo(void)
- Initializes on-chip ethernet controllers.
- to override, implement board_eth_init()
*/
int cpu_eth_init(bd_t *bis) { int rc = -ENODEV; @@ -470,6 +472,17 @@ int cpu_eth_init(bd_t *bis) return rc; }
+#ifdef CONFIG_FSL_ESDHC +/*
- Initializes on-chip MMC controllers.
- to override, implement board_mmc_init()
- */
+int cpu_mmc_init(bd_t *bis) +{
- return fsl_esdhc_mmc_init(bis);
+} +#endif
int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 17/08/2012 22:43, Benoît Thébaudeau wrote:
Add cpu_mmc_init() function to make it easy to init a single eSDHC instance.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Changes for v2:
- Do not define cpu_mmc_init() if CONFIG_FSL_ESDHC is not defined.
.../arch/arm/cpu/arm1136/mx35/generic.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index 15a0098..8f61069 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -31,6 +31,9 @@ #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_FSL_ESDHC +#include <fsl_esdhc.h> +#endif #include <netdev.h>
#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) @@ -458,7 +461,6 @@ int print_cpuinfo(void)
- Initializes on-chip ethernet controllers.
- to override, implement board_eth_init()
*/
int cpu_eth_init(bd_t *bis) { int rc = -ENODEV; @@ -470,6 +472,17 @@ int cpu_eth_init(bd_t *bis) return rc; }
+#ifdef CONFIG_FSL_ESDHC +/*
- Initializes on-chip MMC controllers.
- to override, implement board_mmc_init()
- */
+int cpu_mmc_init(bd_t *bis) +{
- return fsl_esdhc_mmc_init(bis);
+} +#endif
int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
On 14/08/2012 22:32, Benoît Thébaudeau wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
.../arch/arm/cpu/arm1136/mx35/generic.c | 4 +-- .../arch/arm/include/asm/arch-mx35/clock.h | 28 +++++++++++++++++++- .../arch/arm/include/asm/arch-mx35/imx-regs.h | 26 ------------------ 3 files changed, 29 insertions(+), 29 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index 986b1f9..dba4903 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -205,7 +205,7 @@ u32 imx_get_uartclk(void) return freq; }
-unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) +unsigned int mxc_get_main_clock(enum mxc_main_clock clk) { u32 nfc_pdf, hsp_podf; u32 pll, ret_val = 0, usb_prdf, usb_podf; @@ -270,7 +270,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
return ret_val; } -unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) +unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) { u32 ret_val = 0, pdf, pre_pdf, clk_sel; struct ccm_regs *ccm = diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/clock.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/clock.h index 4c0ddfd..5dc53ba 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/clock.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/clock.h @@ -25,7 +25,7 @@ #define __ASM_ARCH_CLOCK_H
enum mxc_clock {
- MXC_ARM_CLK = 0,
- MXC_ARM_CLK, MXC_AHB_CLK, MXC_IPG_CLK, MXC_IPG_PERCLK,
@@ -36,6 +36,32 @@ enum mxc_clock { MXC_FEC_CLK, };
+enum mxc_main_clock {
- CPU_CLK,
- AHB_CLK,
- IPG_CLK,
- IPG_PER_CLK,
- NFC_CLK,
- USB_CLK,
- HSP_CLK,
+};
+enum mxc_peri_clock {
- UART1_BAUD,
- UART2_BAUD,
- UART3_BAUD,
- SSI1_BAUD,
- SSI2_BAUD,
- CSI_BAUD,
- MSHC_CLK,
- ESDHC1_CLK,
- ESDHC2_CLK,
- ESDHC3_CLK,
- SPDIF_CLK,
- SPI1_CLK,
- SPI2_CLK,
+};
unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
u32 imx_get_uartclk(void); diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h index 3146006..fba29b2 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -216,32 +216,6 @@ #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h>
-enum mxc_main_clocks {
- CPU_CLK,
- AHB_CLK,
- IPG_CLK,
- IPG_PER_CLK,
- NFC_CLK,
- USB_CLK,
- HSP_CLK,
-};
-enum mxc_peri_clocks {
- UART1_BAUD,
- UART2_BAUD,
- UART3_BAUD,
- SSI1_BAUD,
- SSI2_BAUD,
- CSI_BAUD,
- MSHC_CLK,
- ESDHC1_CLK,
- ESDHC2_CLK,
- ESDHC3_CLK,
- SPDIF_CLK,
- SPI1_CLK,
- SPI2_CLK,
-};
/* Clock Control Module (CCM) registers */ struct ccm_regs { u32 ccmr; /* Control */
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 14/08/2012 22:32, Benoît Thébaudeau wrote:
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
participants (3)
-
Benoît Thébaudeau -
Stefano Babic -
stefano babic