[U-Boot] [PATCH 0/2] add STM32F7 MMC support
From: Patrice Chotard patrice.chotard@st.com
STM32F7 SoCs uses arm_pl180_mmci MMC IP. Enable MMC support by updating DT and enabling MMC related flags into defconfig.
Patrice Chotard (2): ARM: DTS: stm32: add MMC nodes for stm32f746-disco and stm32f769-disco configs: stm32f746-disco: enable MMC related flags
arch/arm/dts/stm32f746-disco.dts | 12 ++++ arch/arm/dts/stm32f746.dtsi | 85 +++++++++++++++++++++++++ arch/arm/dts/stm32f769-disco.dts | 12 ++++ configs/stm32f746-disco_defconfig | 15 ++++- include/dt-bindings/pinctrl/stm32f746-pinfunc.h | 19 +++++- 5 files changed, 141 insertions(+), 2 deletions(-)
From: Patrice Chotard patrice.chotard@st.com
Add DT nodes to enable ARM_PL180_MMCI IP support for STM32F746 and STM32F769 discovery boards
There is a hardware issue on these boards, it misses a pullup on the GPIO line used as card detect to allow correct SD card detection. As workaround, cd-gpios property is not present in DT. So SD card is always considered present in the slot.
Signed-off-by: Christophe Priouzeau christophe.priouzeau@st.com Signed-off-by: Patrice Chotard patrice.chotard@st.com --- arch/arm/dts/stm32f746-disco.dts | 12 ++++ arch/arm/dts/stm32f746.dtsi | 85 +++++++++++++++++++++++++ arch/arm/dts/stm32f769-disco.dts | 12 ++++ include/dt-bindings/pinctrl/stm32f746-pinfunc.h | 19 +++++- 4 files changed, 127 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index c92c2e2..9e8d2a0 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -65,6 +65,7 @@ aliases { serial0 = &usart1; spi0 = &qspi; + mmc0 = &sdio; /* Aliases for gpios so as to use sequence */ gpio0 = &gpioa; gpio1 = &gpiob; @@ -238,3 +239,14 @@ reg = <0>; }; }; + +&sdio { + status = "okay"; + cd-gpios = <&gpioc 13 0>; + cd-inverted; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + bus-width = <4>; + max-frequency = <25000000>; +}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index f62360f..929bf82 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -234,6 +234,91 @@ u-boot,dm-pre-reloc; };
+ sdio_pins: sdio_pins@0 { + pins { + pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>, + <STM32F746_PC9_FUNC_SDMMC1_D1>, + <STM32F746_PC10_FUNC_SDMMC1_D2>, + <STM32F746_PC11_FUNC_SDMMC1_D3>, + <STM32F746_PC12_FUNC_SDMMC1_CK>, + <STM32F746_PD2_FUNC_SDMMC1_CMD>; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od: sdio_pins_od@0 { + pins1 { + pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>, + <STM32F746_PC9_FUNC_SDMMC1_D1>, + <STM32F746_PC10_FUNC_SDMMC1_D2>, + <STM32F746_PC11_FUNC_SDMMC1_D3>, + <STM32F746_PC12_FUNC_SDMMC1_CK>; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>; + drive-open-drain; + slew-rate = <2>; + }; + }; + + sdio_pins_b: sdio_pins_b@0 { + pins { + pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>, + <STM32F769_PG10_FUNC_SDMMC2_D1>, + <STM32F769_PB3_FUNC_SDMMC2_D2>, + <STM32F769_PB4_FUNC_SDMMC2_D3>, + <STM32F769_PD6_FUNC_SDMMC2_CLK>, + <STM32F769_PD7_FUNC_SDMMC2_CMD>; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od_b: sdio_pins_od_b@0 { + pins1 { + pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>, + <STM32F769_PG10_FUNC_SDMMC2_D1>, + <STM32F769_PB3_FUNC_SDMMC2_D2>, + <STM32F769_PB4_FUNC_SDMMC2_D3>, + <STM32F769_PD6_FUNC_SDMMC2_CLK>; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>; + drive-open-drain; + slew-rate = <2>; + }; + }; + + }; + sdio: sdio@40012c00 { + compatible = "st,stm32f4xx-sdio"; + reg = <0x40012c00 0x400>; + clocks = <&rcc 0 171>; + interrupts = <49>; + status = "disabled"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + pinctrl-names = "default", "opendrain"; + max-frequency = <48000000>; + }; + + sdio2: sdio2@40011c00 { + compatible = "st,stm32f4xx-sdio"; + reg = <0x40011c00 0x400>; + clocks = <&rcc 0 167>; + interrupts = <103>; + status = "disabled"; + pinctrl-0 = <&sdio_pins_b>; + pinctrl-1 = <&sdio_pins_od_b>; + pinctrl-names = "default", "opendrain"; + max-frequency = <48000000>; }; }; }; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index f34ffcc..59c9d31 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -60,6 +60,7 @@ aliases { serial0 = &usart1; spi0 = &qspi; + mmc0 = &sdio2; /* Aliases for gpios so as to use sequence */ gpio0 = &gpioa; gpio1 = &gpiob; @@ -252,3 +253,14 @@ reg = <0>; }; }; + +&sdio2 { + status = "okay"; + cd-gpios = <&gpioi 15 0>; + cd-inverted; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins_b>; + pinctrl-1 = <&sdio_pins_od_b>; + bus-width = <4>; + max-frequency = <25000000>; +}; diff --git a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h index 6348c6a..549323f 100644 --- a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h @@ -154,7 +154,6 @@ #define STM32F746_PA15_FUNC_EVENTOUT 0xf10 #define STM32F746_PA15_FUNC_ANALOG 0xf11
- #define STM32F746_PB0_FUNC_GPIO 0x1000 #define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002 #define STM32F746_PB0_FUNC_TIM3_CH3 0x1003 @@ -188,6 +187,9 @@ #define STM32F746_PB3_FUNC_TIM2_CH2 0x1302 #define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306 #define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 + +#define STM32F769_PB3_FUNC_SDMMC2_D2 0x130b + #define STM32F746_PB3_FUNC_EVENTOUT 0x1310 #define STM32F746_PB3_FUNC_ANALOG 0x1311
@@ -197,6 +199,9 @@ #define STM32F746_PB4_FUNC_SPI1_MISO 0x1406 #define STM32F746_PB4_FUNC_SPI3_MISO 0x1407 #define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408 + +#define STM32F769_PB4_FUNC_SDMMC2_D3 0x140b + #define STM32F746_PB4_FUNC_EVENTOUT 0x1410 #define STM32F746_PB4_FUNC_ANALOG 0x1411
@@ -505,6 +510,9 @@ #define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 #define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607 #define STM32F746_PD6_FUNC_USART2_RX 0x3608 + +#define STM32F769_PD6_FUNC_SDMMC2_CLK 0x360c + #define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d #define STM32F746_PD6_FUNC_DCMI_D10 0x360e #define STM32F746_PD6_FUNC_LCD_B2 0x360f @@ -514,6 +522,9 @@ #define STM32F746_PD7_FUNC_GPIO 0x3700 #define STM32F746_PD7_FUNC_USART2_CK 0x3708 #define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709 + +#define STM32F769_PD7_FUNC_SDMMC2_CMD 0x370c + #define STM32F746_PD7_FUNC_FMC_NE1 0x370d #define STM32F746_PD7_FUNC_EVENTOUT 0x3710 #define STM32F746_PD7_FUNC_ANALOG 0x3711 @@ -893,6 +904,9 @@ #define STM32F746_PG9_FUNC_USART6_RX 0x6909 #define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a #define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b + +#define STM32F769_PG9_FUNC_SDMMC2_D0 0x690c + #define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d #define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e #define STM32F746_PG9_FUNC_EVENTOUT 0x6910 @@ -901,6 +915,9 @@ #define STM32F746_PG10_FUNC_GPIO 0x6a00 #define STM32F746_PG10_FUNC_LCD_G3 0x6a0a #define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b + +#define STM32F769_PG10_FUNC_SDMMC2_D1 0x6a0c + #define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d #define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e #define STM32F746_PG10_FUNC_LCD_B2 0x6a0f
From: Patrice Chotard patrice.chotard@st.com
STM32F469-disco embeds an arm_pl180 mmc IP, so enable CMD_MMC, DM_MMC and ARM_PL180_MMCI flags.
Also enables all filesystem command related flags : _ CMD_EXT2 _ CMD_EXT4 _ CMD_FAT _ CMD_FS_GENERIC _ CMD_GPT _ CMD_BOOTZ
Signed-off-by: Patrice Chotard patrice.chotard@st.com --- configs/stm32f746-disco_defconfig | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index b661761..321321f 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -15,7 +15,11 @@ CONFIG_SYS_PROMPT="U-Boot > " CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_MMC=y CONFIG_CMD_SF=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -25,14 +29,23 @@ CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y +# CONFIG_BLK is not set CONFIG_CLK=y CONFIG_DM_GPIO=y CONFIG_MISC=y CONFIG_STM32_RCC=y -# CONFIG_MMC is not set +CONFIG_DM_MMC=y +# CONFIG_SPL_DM_MMC is not set +CONFIG_ARM_PL180_MMCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_DM_SPI_FLASH=y
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