[U-Boot] [PATCH 1/4] arm: mvebu: solidrun-microsom: update SPI flash compatible
Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the SolidRun SOM.
Signed-off-by: Baruch Siach baruch@tkos.co.il --- arch/arm/dts/armada-38x-solidrun-microsom.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi index a2627223ce3b..74f58de85c43 100644 --- a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi @@ -86,7 +86,7 @@ w25q32: spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "w25q32", "jedec,spi-nor"; + compatible = "w25q32", "jedec,spi-nor", "spi-flash"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <3000000>; status = "disabled";
Use hardware description from the recently introduced microsom .dtsi file to reduce duplication.
Signed-off-by: Baruch Siach baruch@tkos.co.il --- arch/arm/dts/armada-388-clearfog.dts | 63 +++------------------------- 1 file changed, 6 insertions(+), 57 deletions(-)
diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts index a0b566a5ae0e..1403600e5b02 100644 --- a/arch/arm/dts/armada-388-clearfog.dts +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -50,6 +50,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> #include "armada-388.dtsi" +#include "armada-38x-solidrun-microsom.dtsi"
/ { model = "SolidRun Clearfog A1"; @@ -70,11 +71,6 @@ stdout-path = "serial0:115200n8"; };
- memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; @@ -84,11 +80,6 @@ };
soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 - MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 - MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 - MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; - internal-regs { ethernet@30000 { mac-address = [00 50 43 02 02 02]; @@ -108,15 +99,6 @@ status = "okay"; };
- ethernet@70000 { - mac-address = [00 50 43 02 02 01]; - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy_dedicated>; - phy-mode = "rgmii-id"; - status = "okay"; - }; - i2c@11000 { /* Is there anything on this? */ clock-frequency = <100000>; @@ -226,22 +208,6 @@ status = "okay"; };
- mdio@72004 { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy_dedicated: ethernet-phy@0 { - /* - * Annoyingly, the marvell phy driver - * configures the LED register, rather - * than preserving reset-loaded setting. - * We undo that rubbish here. - */ - marvell,reg-init = <3 16 0 0x101e>; - reg = <0>; - }; - }; - pinctrl@18000 { clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { marvell,pins = "mpp46"; @@ -260,12 +226,6 @@ marvell,pins = "mpp20"; marvell,function = "gpio"; }; - clearfog_sdhci_pins: clearfog-sdhci-pins { - marvell,pins = "mpp21", "mpp28", - "mpp37", "mpp38", - "mpp39", "mpp40"; - marvell,function = "sd0"; - }; clearfog_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp55"; marvell,function = "spi1"; @@ -311,7 +271,7 @@ bus-width = <4>; cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; no-1-8-v; - pinctrl-0 = <&clearfog_sdhci_pins + pinctrl-0 = <µsom_sdhci_pins &clearfog_sdhci_cd_pins>; pinctrl-names = "default"; status = "okay"; @@ -319,13 +279,6 @@ wp-inverted; };
- serial@12000 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; - u-boot,dm-pre-reloc; - }; - serial@12100 { /* mikrobus uart */ pinctrl-0 = <&mikro_uart_pins>; @@ -342,14 +295,6 @@ pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; pinctrl-names = "default"; status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "w25q32", "jedec,spi-nor", "spi-flash"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <3000000>; - }; };
usb3@f8000 { @@ -457,6 +402,10 @@ }; };
+&w25q32 { + status = "okay"; +}; + /* +#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 MPP18: gpio ? (pca9655 int?)
Reviewed-by: Dennis Gilmore dennis@ausil.us Tested-by: Dennis Gilmore dennis@ausil.us
On Thu, 2018-06-14 at 18:17 +0300, Baruch Siach wrote:
Use hardware description from the recently introduced microsom .dtsi file to reduce duplication.
Signed-off-by: Baruch Siach baruch@tkos.co.il
arch/arm/dts/armada-388-clearfog.dts | 63 +++-----------------------
1 file changed, 6 insertions(+), 57 deletions(-)
diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts index a0b566a5ae0e..1403600e5b02 100644 --- a/arch/arm/dts/armada-388-clearfog.dts +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -50,6 +50,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> #include "armada-388.dtsi" +#include "armada-38x-solidrun-microsom.dtsi"
/ { model = "SolidRun Clearfog A1"; @@ -70,11 +71,6 @@ stdout-path = "serial0:115200n8"; };
- memory {
device_type = "memory";reg = <0x00000000 0x10000000>; /* 256 MB */- };
- reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V";
@@ -84,11 +80,6 @@ };
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;- internal-regs { ethernet@30000 { mac-address = [00 50 43 02 02 02];
@@ -108,15 +99,6 @@ status = "okay"; };
ethernet@70000 {mac-address = [00 50 43 02 02 01];pinctrl-0 = <&ge0_rgmii_pins>;pinctrl-names = "default";phy = <&phy_dedicated>;phy-mode = "rgmii-id";status = "okay";};i2c@11000 { /* Is there anything on this? */ clock-frequency = <100000>;@@ -226,22 +208,6 @@ status = "okay"; };
mdio@72004 {pinctrl-0 = <&mdio_pins>;pinctrl-names = "default";phy_dedicated: ethernet-phy@0 {/** Annoyingly, the marvellphy driver
* configures the LEDregister, rather
* than preserving reset-loaded setting.
* We undo that rubbishhere.
*/marvell,reg-init = <3 16 00x101e>;
reg = <0>;};};pinctrl@18000 { clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { marvell,pins = "mpp46"; @@ -260,12 +226,6 @@ marvell,pins = "mpp20"; marvell,function = "gpio"; };
clearfog_sdhci_pins: clearfog-sdhci-pins {
marvell,pins = "mpp21","mpp28",
"mpp37","mpp38",
"mpp39","mpp40";
marvell,function = "sd0";}; clearfog_spi1_cs_pins: spi1-cs-pins{ marvell,pins = "mpp55"; marvell,function = "spi1"; @@ -311,7 +271,7 @@ bus-width = <4>; cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; no-1-8-v;
pinctrl-0 = <&clearfog_sdhci_pins
pinctrl-0 = <µsom_sdhci_pins &clearfog_sdhci_cd_pins;
pinctrl-names = "default"; status = "okay";@@ -319,13 +279,6 @@ wp-inverted; };
serial@12000 {pinctrl-0 = <&uart0_pins>;pinctrl-names = "default";status = "okay";u-boot,dm-pre-reloc;};serial@12100 { /* mikrobus uart */ pinctrl-0 = <&mikro_uart_pins>;@@ -342,14 +295,6 @@ pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; pinctrl-names = "default"; status = "okay";
spi-flash@0 {#address-cells = <1>;#size-cells = <0>;compatible = "w25q32","jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0*/
spi-max-frequency =<3000000>;
}; }; usb3@f8000 {@@ -457,6 +402,10 @@ }; };
+&w25q32 {
- status = "okay";
+};
/* +#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 MPP18: gpio ? (pca9655 int?)
From: Jon Nettleton jon@solid-run.com
This makes changes so the u-boot dts file is structured more similar to the mainline linux dtsi file. It provides a minimal common dts that can work for most boards based on the ClearFog platform. Ethernet support is only supported for eth0 however all devices are left enabled so u-boot can generate and provide mac addresses for all of the network interfaces.
Signed-off-by: Jon Nettleton jon@solid-run.com [baruch: rebase on recent changes] Signed-off-by: Baruch Siach baruch@tkos.co.il --- arch/arm/dts/armada-388-clearfog.dts | 386 +++++++++++---------------- 1 file changed, 151 insertions(+), 235 deletions(-)
diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts index 1403600e5b02..16a47d59e667 100644 --- a/arch/arm/dts/armada-388-clearfog.dts +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -81,174 +81,6 @@
soc { internal-regs { - ethernet@30000 { - mac-address = [00 50 43 02 02 02]; - phy-mode = "sgmii"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - ethernet@34000 { - mac-address = [00 50 43 02 02 03]; - managed = "in-band-status"; - phy-mode = "sgmii"; - status = "okay"; - }; - - i2c@11000 { - /* Is there anything on this? */ - clock-frequency = <100000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* - * PCA9655 GPIO expander, up to 1MHz clock. - * 0-CON3 CLKREQ# - * 1-CON3 PERST# - * 2-CON2 PERST# - * 3-CON3 W_DISABLE - * 4-CON2 CLKREQ# - * 5-USB3 overcurrent - * 6-USB3 power - * 7-CON2 W_DISABLE - * 8-JP4 P1 - * 9-JP4 P4 - * 10-JP4 P5 - * 11-m.2 DEVSLP - * 12-SFP_LOS - * 13-SFP_TX_FAULT - * 14-SFP_TX_DISABLE - * 15-SFP_MOD_DEF0 - */ - expander0: gpio-expander@20 { - /* - * This is how it should be: - * compatible = "onnn,pca9655", - * "nxp,pca9555"; - * but you can't do this because of - * the way I2C works. - */ - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - - pcie1_0_clkreq { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - input; - line-name = "pcie1.0-clkreq"; - }; - pcie1_0_w_disable { - gpio-hog; - gpios = <3 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pcie1.0-w-disable"; - }; - pcie2_0_clkreq { - gpio-hog; - gpios = <4 GPIO_ACTIVE_LOW>; - input; - line-name = "pcie2.0-clkreq"; - }; - pcie2_0_w_disable { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pcie2.0-w-disable"; - }; - usb3_ilimit { - gpio-hog; - gpios = <5 GPIO_ACTIVE_LOW>; - input; - line-name = "usb3-current-limit"; - }; - usb3_power { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb3-power"; - }; - m2_devslp { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "m.2 devslp"; - }; - }; - - /* The MCP3021 is 100kHz clock only */ - mikrobus_adc: mcp3021@4c { - compatible = "microchip,mcp3021"; - reg = <0x4c>; - }; - - /* Also something at 0x64 */ - }; - - i2c@11100 { - /* - * Routed to SFP, mikrobus, and PCIe. - * SFP limits this to 100kHz, and requires - * an AT24C01A/02/04 with address pins tied - * low, which takes addresses 0x50 and 0x51. - * Mikrobus doesn't specify beyond an I2C - * bus being present. - * PCIe uses ARP to assign addresses, or - * 0x63-0x64. - */ - clock-frequency = <100000>; - pinctrl-0 = <&clearfog_i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - pinctrl@18000 { - clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { - marvell,pins = "mpp46"; - marvell,function = "ref"; - }; - clearfog_dsa0_pins: clearfog-dsa0-pins { - marvell,pins = "mpp23", "mpp41"; - marvell,function = "gpio"; - }; - clearfog_i2c1_pins: i2c1-pins { - /* SFP, PCIe, mSATA, mikrobus */ - marvell,pins = "mpp26", "mpp27"; - marvell,function = "i2c1"; - }; - clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - clearfog_spi1_cs_pins: spi1-cs-pins { - marvell,pins = "mpp55"; - marvell,function = "spi1"; - }; - mikro_pins: mikro-pins { - /* int: mpp22 rst: mpp29 */ - marvell,pins = "mpp22", "mpp29"; - marvell,function = "gpio"; - }; - mikro_spi_pins: mikro-spi-pins { - marvell,pins = "mpp43"; - marvell,function = "spi1"; - }; - mikro_uart_pins: mikro-uart-pins { - marvell,pins = "mpp24", "mpp25"; - marvell,function = "ua1"; - }; - rear_button_pins: rear-button-pins { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - }; - rtc@a3800 { /* * If the rtc doesn't work, run "date reset" @@ -297,7 +129,8 @@ status = "okay"; };
- usb3@f8000 { + usb0: usb3@f8000 { + /* CON7, USB-A port on back of device */ status = "okay"; }; }; @@ -321,72 +154,6 @@ }; };
- sfp: sfp { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; - moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; - sfp,ethernet = <ð2>; - tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; - }; - - dsa@0 { - compatible = "marvell,dsa"; - dsa,ethernet = <ð1>; - dsa,mii-bus = <&mdio>; - pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; - pinctrl-names = "default"; - #address-cells = <2>; - #size-cells = <0>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4 0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "lan5"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - - port@6 { - /* 88E1512 external phy */ - reg = <6>; - label = "lan6"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&rear_button_pins>; @@ -406,6 +173,155 @@ status = "okay"; };
+ð1 { + managed = "in-band-status"; + phy-mode = "sgmii"; + status = "okay"; +}; + +ð2 { + phy-mode = "sgmii"; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * PCA9655 GPIO expander, up to 1MHz clock. + * 0-CON3 CLKREQ# + * 1-CON3 PERST# + * 2-CON2 PERST# + * 3-CON3 W_DISABLE + * 4-CON2 CLKREQ# + * 5-USB3 overcurrent + * 6-USB3 power + * 7-CON2 W_DISABLE + * 8-JP4 P1 + * 9-JP4 P4 + * 10-JP4 P5 + * 11-m.2 DEVSLP + * 12-SFP_LOS + * 13-SFP_TX_FAULT + * 14-SFP_TX_DISABLE + * 15-SFP_MOD_DEF0 + */ + expander0: gpio-expander@20 { + /* + * This is how it should be: + * compatible = "onnn,pca9655", + * "nxp,pca9555"; + * but you can't do this because of + * the way I2C works. + */ + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + + pcie1_0_clkreq { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie1.0-clkreq"; + }; + pcie1_0_w_disable { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie1.0-w-disable"; + }; + pcie2_0_clkreq { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie2.0-clkreq"; + }; + pcie2_0_w_disable { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie2.0-w-disable"; + }; + usb3_ilimit { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + input; + line-name = "usb3-current-limit"; + }; + usb3_power { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb3-power"; + }; + m2_devslp { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "m.2 devslp"; + }; + }; + + mikrobus_adc: mcp3021@4c { + compatible = "microchip,mcp3021"; + reg = <0x4c>; + }; +}; + +&i2c1 { + /* + * Routed to SFP, mikrobus, and PCIe. + * SFP limits this to 100kHz, and requires + * an AT24C01A/02/04 with address pins tied + * low, which takes addresses 0x50 and 0x51. + * Mikrobus doesn't specify beyond an I2C + * bus being present. + * PCIe uses ARP to assign addresses, or + * 0x63-0x64. + */ + clock-frequency = <100000>; + pinctrl-0 = <&clearfog_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + clearfog_i2c1_pins: i2c1-pins { + /* SFP, PCIe, mSATA, mikrobus */ + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + clearfog_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp55"; + marvell,function = "spi1"; + }; + mikro_pins: mikro-pins { + /* int: mpp22 rst: mpp29 */ + marvell,pins = "mpp22", "mpp29"; + marvell,function = "gpio"; + }; + mikro_spi_pins: mikro-spi-pins { + marvell,pins = "mpp43"; + marvell,function = "spi1"; + }; + mikro_uart_pins: mikro-uart-pins { + marvell,pins = "mpp24", "mpp25"; + marvell,function = "ua1"; + }; + rear_button_pins: rear-button-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; +}; + /* +#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 MPP18: gpio ? (pca9655 int?)
Reviewed-by: Dennis Gilmore dennis@ausil.us Tested-by: Dennis Gilmore dennis@ausil.us
On Thu, 2018-06-14 at 18:17 +0300, Baruch Siach wrote:
From: Jon Nettleton jon@solid-run.com
This makes changes so the u-boot dts file is structured more similar to the mainline linux dtsi file. It provides a minimal common dts that can work for most boards based on the ClearFog platform. Ethernet support is only supported for eth0 however all devices are left enabled so u-boot can generate and provide mac addresses for all of the network interfaces.
Signed-off-by: Jon Nettleton jon@solid-run.com [baruch: rebase on recent changes] Signed-off-by: Baruch Siach baruch@tkos.co.il
arch/arm/dts/armada-388-clearfog.dts | 386 +++++++++++------------
1 file changed, 151 insertions(+), 235 deletions(-)
diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts index 1403600e5b02..16a47d59e667 100644 --- a/arch/arm/dts/armada-388-clearfog.dts +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -81,174 +81,6 @@
soc { internal-regs {
ethernet@30000 {mac-address = [00 50 43 02 02 02];phy-mode = "sgmii";status = "okay";fixed-link {speed = <1000>;full-duplex;};};ethernet@34000 {mac-address = [00 50 43 02 02 03];managed = "in-band-status";phy-mode = "sgmii";status = "okay";};i2c@11000 {/* Is there anything on this? */clock-frequency = <100000>;pinctrl-0 = <&i2c0_pins>;pinctrl-names = "default";status = "okay";/** PCA9655 GPIO expander, up to 1MHzclock.
* 0-CON3 CLKREQ#* 1-CON3 PERST#* 2-CON2 PERST#* 3-CON3 W_DISABLE* 4-CON2 CLKREQ#* 5-USB3 overcurrent* 6-USB3 power* 7-CON2 W_DISABLE* 8-JP4 P1* 9-JP4 P4* 10-JP4 P5* 11-m.2 DEVSLP* 12-SFP_LOS* 13-SFP_TX_FAULT* 14-SFP_TX_DISABLE* 15-SFP_MOD_DEF0*/expander0: gpio-expander@20 {/** This is how it should be:* compatible ="onnn,pca9655",
* "nxp,pca9555";* but you can't do thisbecause of
* the way I2C works.*/compatible = "nxp,pca9555";gpio-controller;#gpio-cells = <2>;reg = <0x20>;pcie1_0_clkreq {gpio-hog;gpios = <0GPIO_ACTIVE_LOW>;
input;line-name ="pcie1.0-clkreq";
};pcie1_0_w_disable {gpio-hog;gpios = <3GPIO_ACTIVE_LOW>;
output-low;line-name ="pcie1.0-w-disable";
};pcie2_0_clkreq {gpio-hog;gpios = <4GPIO_ACTIVE_LOW>;
input;line-name ="pcie2.0-clkreq";
};pcie2_0_w_disable {gpio-hog;gpios = <7GPIO_ACTIVE_LOW>;
output-low;line-name ="pcie2.0-w-disable";
};usb3_ilimit {gpio-hog;gpios = <5GPIO_ACTIVE_LOW>;
input;line-name = "usb3-current-limit";
};usb3_power {gpio-hog;gpios = <6GPIO_ACTIVE_HIGH>;
output-high;line-name = "usb3-power";
};m2_devslp {gpio-hog;gpios = <11GPIO_ACTIVE_HIGH>;
output-low;line-name = "m.2devslp";
};};/* The MCP3021 is 100kHz clock only*/
mikrobus_adc: mcp3021@4c {compatible ="microchip,mcp3021";
reg = <0x4c>;};/* Also something at 0x64 */};i2c@11100 {/** Routed to SFP, mikrobus, andPCIe.
* SFP limits this to 100kHz, andrequires
* an AT24C01A/02/04 with addresspins tied
* low, which takes addresses 0x50and 0x51.
* Mikrobus doesn't specify beyondan I2C
* bus being present.* PCIe uses ARP to assignaddresses, or
* 0x63-0x64.*/clock-frequency = <100000>;pinctrl-0 = <&clearfog_i2c1_pins>;pinctrl-names = "default";status = "okay";};pinctrl@18000 {clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
marvell,pins = "mpp46";marvell,function = "ref";};clearfog_dsa0_pins: clearfog-dsa0-pins {
marvell,pins = "mpp23","mpp41";
marvell,function = "gpio";};clearfog_i2c1_pins: i2c1-pins {/* SFP, PCIe, mSATA,mikrobus */
marvell,pins = "mpp26","mpp27";
marvell,function = "i2c1";};clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
marvell,pins = "mpp20";marvell,function = "gpio";};clearfog_spi1_cs_pins: spi1-cs-pins{
marvell,pins = "mpp55";marvell,function = "spi1";};mikro_pins: mikro-pins {/* int: mpp22 rst: mpp29 */marvell,pins = "mpp22","mpp29";
marvell,function = "gpio";};mikro_spi_pins: mikro-spi-pins {marvell,pins = "mpp43";marvell,function = "spi1";};mikro_uart_pins: mikro-uart-pins {marvell,pins = "mpp24","mpp25";
marvell,function = "ua1";};rear_button_pins: rear-button-pins {marvell,pins = "mpp34";marvell,function = "gpio";};};rtc@a3800 { /* * If the rtc doesn't work, run"date reset" @@ -297,7 +129,8 @@ status = "okay"; };
usb3@f8000 {
usb0: usb3@f8000 {/* CON7, USB-A port on back ofdevice */ status = "okay"; }; }; @@ -321,72 +154,6 @@ }; };
- sfp: sfp {
compatible = "sff,sfp";i2c-bus = <&i2c1>;los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;sfp,ethernet = <ð2>;tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;- };
- dsa@0 {
compatible = "marvell,dsa";dsa,ethernet = <ð1>;dsa,mii-bus = <&mdio>;pinctrl-0 = <&clearfog_dsa0_clk_pins&clearfog_dsa0_pins>;
pinctrl-names = "default";#address-cells = <2>;#size-cells = <0>;switch@0 {#address-cells = <1>;#size-cells = <0>;reg = <4 0>;port@0 {reg = <0>;label = "lan1";};port@1 {reg = <1>;label = "lan2";};port@2 {reg = <2>;label = "lan3";};port@3 {reg = <3>;label = "lan4";};port@4 {reg = <4>;label = "lan5";};port@5 {reg = <5>;label = "cpu";};port@6 {/* 88E1512 external phy */reg = <6>;label = "lan6";fixed-link {speed = <1000>;full-duplex;};};};- };
- gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&rear_button_pins>;
@@ -406,6 +173,155 @@ status = "okay"; };
+ð1 {
- managed = "in-band-status";
- phy-mode = "sgmii";
- status = "okay";
+};
+ð2 {
- phy-mode = "sgmii";
- status = "okay";
+};
+&i2c0 {
- clock-frequency = <400000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
- /*
* PCA9655 GPIO expander, up to 1MHz clock.* 0-CON3 CLKREQ#* 1-CON3 PERST#* 2-CON2 PERST#* 3-CON3 W_DISABLE* 4-CON2 CLKREQ#* 5-USB3 overcurrent* 6-USB3 power* 7-CON2 W_DISABLE* 8-JP4 P1* 9-JP4 P4* 10-JP4 P5* 11-m.2 DEVSLP* 12-SFP_LOS* 13-SFP_TX_FAULT* 14-SFP_TX_DISABLE* 15-SFP_MOD_DEF0*/- expander0: gpio-expander@20 {
/** This is how it should be:* compatible = "onnn,pca9655",* "nxp,pca9555";* but you can't do this because of* the way I2C works.*/compatible = "nxp,pca9555";gpio-controller;#gpio-cells = <2>;reg = <0x20>;pcie1_0_clkreq {gpio-hog;gpios = <0 GPIO_ACTIVE_LOW>;input;line-name = "pcie1.0-clkreq";};pcie1_0_w_disable {gpio-hog;gpios = <3 GPIO_ACTIVE_LOW>;output-low;line-name = "pcie1.0-w-disable";};pcie2_0_clkreq {gpio-hog;gpios = <4 GPIO_ACTIVE_LOW>;input;line-name = "pcie2.0-clkreq";};pcie2_0_w_disable {gpio-hog;gpios = <7 GPIO_ACTIVE_LOW>;output-low;line-name = "pcie2.0-w-disable";};usb3_ilimit {gpio-hog;gpios = <5 GPIO_ACTIVE_LOW>;input;line-name = "usb3-current-limit";};usb3_power {gpio-hog;gpios = <6 GPIO_ACTIVE_HIGH>;output-high;line-name = "usb3-power";};m2_devslp {gpio-hog;gpios = <11 GPIO_ACTIVE_HIGH>;output-low;line-name = "m.2 devslp";};- };
- mikrobus_adc: mcp3021@4c {
compatible = "microchip,mcp3021";reg = <0x4c>;- };
+};
+&i2c1 {
- /*
* Routed to SFP, mikrobus, and PCIe.* SFP limits this to 100kHz, and requires* an AT24C01A/02/04 with address pins tied* low, which takes addresses 0x50 and 0x51.* Mikrobus doesn't specify beyond an I2C* bus being present.* PCIe uses ARP to assign addresses, or* 0x63-0x64.*/- clock-frequency = <100000>;
- pinctrl-0 = <&clearfog_i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
+};
+&pinctrl {
- clearfog_i2c1_pins: i2c1-pins {
/* SFP, PCIe, mSATA, mikrobus */marvell,pins = "mpp26", "mpp27";marvell,function = "i2c1";- };
- clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
marvell,pins = "mpp20";marvell,function = "gpio";- };
- clearfog_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp55";marvell,function = "spi1";- };
- mikro_pins: mikro-pins {
/* int: mpp22 rst: mpp29 */marvell,pins = "mpp22", "mpp29";marvell,function = "gpio";- };
- mikro_spi_pins: mikro-spi-pins {
marvell,pins = "mpp43";marvell,function = "spi1";- };
- mikro_uart_pins: mikro-uart-pins {
marvell,pins = "mpp24", "mpp25";marvell,function = "ua1";- };
- rear_button_pins: rear-button-pins {
marvell,pins = "mpp34";marvell,function = "gpio";- };
+};
/* +#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 MPP18: gpio ? (pca9655 int?)
The same pinctrl node appears in the solidrun-microsom dtsi. Use that instead.
Cc: Dennis Gilmore dennis@ausil.us Signed-off-by: Baruch Siach baruch@tkos.co.il --- arch/arm/dts/armada-388-helios4.dts | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/arch/arm/dts/armada-388-helios4.dts b/arch/arm/dts/armada-388-helios4.dts index 049d32296475..a154e0f4f477 100644 --- a/arch/arm/dts/armada-388-helios4.dts +++ b/arch/arm/dts/armada-388-helios4.dts @@ -248,7 +248,7 @@ bus-width = <4>; cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; no-1-8-v; - pinctrl-0 = <&helios_sdhci_pins + pinctrl-0 = <µsom_sdhci_pins &helios_sdhci_cd_pins>; pinctrl-names = "default"; status = "okay"; @@ -286,12 +286,6 @@ marvell,pins = "mpp20"; marvell,function = "gpio"; }; - helios_sdhci_pins: helios-sdhci-pins { - marvell,pins = "mpp21", "mpp28", - "mpp37", "mpp38", - "mpp39", "mpp40"; - marvell,function = "sd0"; - }; helios_led_pins: helios-led-pins { marvell,pins = "mpp24", "mpp25", "mpp49", "mpp50",
Reviewed-by: Dennis Gilmore dennis@ausil.us Tested-by: Dennis Gilmore dennis@ausil.us
On Thu, 2018-06-14 at 18:17 +0300, Baruch Siach wrote:
The same pinctrl node appears in the solidrun-microsom dtsi. Use that instead.
Cc: Dennis Gilmore dennis@ausil.us Signed-off-by: Baruch Siach baruch@tkos.co.il
arch/arm/dts/armada-388-helios4.dts | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/arch/arm/dts/armada-388-helios4.dts b/arch/arm/dts/armada-388-helios4.dts index 049d32296475..a154e0f4f477 100644 --- a/arch/arm/dts/armada-388-helios4.dts +++ b/arch/arm/dts/armada-388-helios4.dts @@ -248,7 +248,7 @@ bus-width = <4>; cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; no-1-8-v;
pinctrl-0 = <&helios_sdhci_pins
pinctrl-0 = <µsom_sdhci_pins &helios_sdhci_cd_pins>; pinctrl-names = "default"; status = "okay";@@ -286,12 +286,6 @@ marvell,pins = "mpp20"; marvell,function = "gpio"; };
helios_sdhci_pins: helios-sdhci-pins{
marvell,pins = "mpp21","mpp28",
"mpp37","mpp38",
"mpp39","mpp40";
marvell,function = "sd0";}; helios_led_pins: helios-led-pins { marvell,pins = "mpp24","mpp25", "mpp49", "mpp50",
running sf probe on one of my clearfogs with this set of patches applied I got
SF: unrecognized JEDEC id bytes: ff, ff, ff Failed to initialize SPI flash at 1:0 (error -2)
Dennis
On Thu, 2018-06-14 at 18:17 +0300, Baruch Siach wrote:
Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the SolidRun SOM.
Signed-off-by: Baruch Siach baruch@tkos.co.il
arch/arm/dts/armada-38x-solidrun-microsom.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi index a2627223ce3b..74f58de85c43 100644 --- a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi @@ -86,7 +86,7 @@ w25q32: spi-flash@0 { #address-cells = <1>; #size-cells = <1>;
compatible = "w25q32", "jedec,spi-nor";
compatible = "w25q32", "jedec,spi-nor", "spi-flash";
Hi Dennis,
On Thu, Jun 14, 2018 at 02:10:31PM -0500, Dennis Gilmore wrote:
running sf probe on one of my clearfogs with this set of patches applied I got
SF: unrecognized JEDEC id bytes: ff, ff, ff Failed to initialize SPI flash at 1:0 (error -2)
Do you use the clearfog_defconfig?
Does current U-Boot master work for you?
For the record, on my Clearfog Base 'sf probe' shows:
SF: Detected w25q32bv with page size 256 Bytes, erase size 4 KiB, total 4 MiB
This works with or without these patches.
baruch
Dennis
On Thu, 2018-06-14 at 18:17 +0300, Baruch Siach wrote:
Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the SolidRun SOM.
Signed-off-by: Baruch Siach baruch@tkos.co.il
arch/arm/dts/armada-38x-solidrun-microsom.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi index a2627223ce3b..74f58de85c43 100644 --- a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi @@ -86,7 +86,7 @@ w25q32: spi-flash@0 { #address-cells = <1>; #size-cells = <1>;
compatible = "w25q32", "jedec,spi-nor";
compatible = "w25q32", "jedec,spi-nor", "spi-flash";
On Thu, 2018-06-14 at 22:23 +0300, Baruch Siach wrote:
Hi Dennis,
On Thu, Jun 14, 2018 at 02:10:31PM -0500, Dennis Gilmore wrote:
running sf probe on one of my clearfogs with this set of patches applied I got
SF: unrecognized JEDEC id bytes: ff, ff, ff Failed to initialize SPI flash at 1:0 (error -2)
Do you use the clearfog_defconfig?
yes I did, I am testing on a clearfog pro
Does current U-Boot master work for you?
2018.03 fails the same. I have another clearfog pro and a clearfog base I can test with, though I have the internal mmc on my base and now wish I had not done so.
For the record, on my Clearfog Base 'sf probe' shows:
SF: Detected w25q32bv with page size 256 Bytes, erase size 4 KiB, total 4 MiB
This works with or without these patches.
mine does not work either way, so it is no worse off. I would like to put u-boot in SPI on them all
Dennis
baruch
Dennis
On Thu, 2018-06-14 at 18:17 +0300, Baruch Siach wrote:
Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the SolidRun SOM.
Signed-off-by: Baruch Siach baruch@tkos.co.il
arch/arm/dts/armada-38x-solidrun-microsom.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi index a2627223ce3b..74f58de85c43 100644 --- a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi @@ -86,7 +86,7 @@ w25q32: spi-flash@0 { #address-cells = <1>; #size-cells = <1>;
compatible = "w25q32", "jedec,spi-nor";
compatible = "w25q32", "jedec,spi-nor", "spi-flash"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <3000000>; status = "disabled";
Hi Dennis,
On Fri, Jun 15, 2018 at 10:40:20AM -0500, Dennis Gilmore wrote:
On Thu, 2018-06-14 at 22:23 +0300, Baruch Siach wrote:
On Thu, Jun 14, 2018 at 02:10:31PM -0500, Dennis Gilmore wrote:
running sf probe on one of my clearfogs with this set of patches applied I got
SF: unrecognized JEDEC id bytes: ff, ff, ff Failed to initialize SPI flash at 1:0 (error -2)
Do you use the clearfog_defconfig?
yes I did, I am testing on a clearfog pro
Does current U-Boot master work for you?
2018.03 fails the same. I have another clearfog pro and a clearfog base I can test with, though I have the internal mmc on my base and now wish I had not done so.
For the record, on my Clearfog Base 'sf probe' shows:
SF: Detected w25q32bv with page size 256 Bytes, erase size 4 KiB, total 4 MiB
This works with or without these patches.
mine does not work either way, so it is no worse off. I would like to put u-boot in SPI on them all
Can you read/write the SPI flash from Linux?
baruch
On Thu, 2018-06-14 at 18:17 +0300, Baruch Siach wrote:
Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the SolidRun SOM.
Signed-off-by: Baruch Siach baruch@tkos.co.il
arch/arm/dts/armada-38x-solidrun-microsom.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi index a2627223ce3b..74f58de85c43 100644 --- a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi @@ -86,7 +86,7 @@ w25q32: spi-flash@0 { #address-cells = <1>; #size-cells = <1>;
compatible = "w25q32", "jedec,spi-nor";
compatible = "w25q32", "jedec,spi-nor", "spi-flash"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <3000000>; status = "disabled";
El vie, 15-06-2018 a las 19:01 +0300, Baruch Siach escribió:
Hi Dennis,
On Fri, Jun 15, 2018 at 10:40:20AM -0500, Dennis Gilmore wrote:
On Thu, 2018-06-14 at 22:23 +0300, Baruch Siach wrote:
On Thu, Jun 14, 2018 at 02:10:31PM -0500, Dennis Gilmore wrote:
running sf probe on one of my clearfogs with this set of patches applied I got
SF: unrecognized JEDEC id bytes: ff, ff, ff Failed to initialize SPI flash at 1:0 (error -2)
Do you use the clearfog_defconfig?
yes I did, I am testing on a clearfog pro
Does current U-Boot master work for you?
2018.03 fails the same. I have another clearfog pro and a clearfog base I can test with, though I have the internal mmc on my base and now wish I had not done so.
For the record, on my Clearfog Base 'sf probe' shows:
SF: Detected w25q32bv with page size 256 Bytes, erase size 4 KiB, total 4 MiB
This works with or without these patches.
mine does not work either way, so it is no worse off. I would like to put u-boot in SPI on them all
Can you read/write the SPI flash from Linux?
Sorry, I have been travelling, I can not access the SPI flash from Linux, I currently do not have physical access to my solid-run based boards. Nothing in my testing is any worse off.
Dennis
baruch
On Thu, 2018-06-14 at 18:17 +0300, Baruch Siach wrote:
Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the SolidRun SOM.
Signed-off-by: Baruch Siach baruch@tkos.co.il
arch/arm/dts/armada-38x-solidrun-microsom.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi index a2627223ce3b..74f58de85c43 100644 --- a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi @@ -86,7 +86,7 @@ w25q32: spi-flash@0 { #address-cells = <1>; #size-cells = <1>;
compatible = "w25q32", "jedec,spi-nor";
compatible = "w25q32", "jedec,spi-nor","spi- flash"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <3000000>; status = "disabled";
participants (2)
-
Baruch Siach -
Dennis Gilmore