IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support.

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org

---

Changes in v3: None Changes in v2: - Drop patches which were already applied - Rebase on top of u-boot-x86/master - Change fsp files license from Intel to GPL-2.0+

arch/x86/cpu/ivybridge/Kconfig | 8 ++++ arch/x86/cpu/ivybridge/Makefile | 4 ++ arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++++++++++++++++ arch/x86/cpu/ivybridge/ivybridge.c | 22 +++++++++++ .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++++++ 6 files changed, 131 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h

diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 1768a26..b9f290a 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -71,4 +71,12 @@ config ENABLE_VMX will be unable to support virtualisation, or it will run very slowly.

+config FSP_ADDR + hex + default 0xfff80000 + +config FSP_USE_UPD + bool + default n + endif diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 45ef141..d7332ff 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -4,6 +4,9 @@ # SPDX-License-Identifier: GPL-2.0+ #

+ifdef CONFIG_HAVE_FSP +obj-y += fsp_configs.o ivybridge.o +else obj-y += bd82x6x.o obj-y += car.o obj-y += cpu.o @@ -17,3 +20,4 @@ obj-y += northbridge.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o +endif diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c new file mode 100644 index 0000000..c7f475b --- /dev/null +++ b/arch/x86/cpu/ivybridge/fsp_configs.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/fsp/fsp_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) +{ + struct platform_config *plat_config = &config->plat_config; + struct memory_config *mem_config = &config->mem_config; + const void *blob = gd->fdt_blob; + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IVYBRIDGE_FSP); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + plat_config->enable_ht = + fdtdec_get_bool(blob, node, "fsp,enable-ht"); + plat_config->enable_turbo = + fdtdec_get_bool(blob, node, "fsp,enable-turbo"); + plat_config->enable_memory_down = + fdtdec_get_bool(blob, node, "fsp,enable-memory-down"); + plat_config->enable_fast_boot = + fdtdec_get_bool(blob, node, "fsp,enable-fast-boot"); + + /* Initialize runtime buffer for fsp_init() */ + rt_buf->stack_top = config->common.stack_top - 32; + rt_buf->boot_mode = config->common.boot_mode; + rt_buf->plat_config = plat_config; + + if (plat_config->enable_memory_down) + rt_buf->mem_config = mem_config; + else + rt_buf->mem_config = NULL; +} diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c new file mode 100644 index 0000000..c770b53 --- /dev/null +++ b/arch/x86/cpu/ivybridge/ivybridge.c @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/post.h> +#include <asm/processor.h> + +int arch_cpu_init(void) +{ + int ret; + + post_code(POST_CPU_INIT); + + ret = x86_cpu_init_f(); + if (ret) + return ret; + + return 0; +} diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h new file mode 100644 index 0000000..9b0613d --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +struct platform_config { + u8 enable_ht; + u8 enable_turbo; + u8 enable_memory_down; + u8 enable_fast_boot; +}; + +/* + * Dummy structure for now as currently only SPD is verified in U-Boot. + * + * We can add the missing parameters when adding support on a board with + * memory down configuration. + */ +struct memory_config { + u8 dummy; +}; + +struct fsp_config_data { + struct fsp_cfg_common common; + struct platform_config plat_config; + struct memory_config mem_config; +}; + +struct fspinit_rtbuf { + u32 stack_top; + u32 boot_mode; + struct platform_config *plat_config; + struct memory_config *mem_config; +}; + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h new file mode 100644 index 0000000..3b255cc --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSP_VPD_H__ +#define __FSP_VPD_H__ + +/* IvyBridge FSP does not support VPD/UPD */ + +#endif

The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management.

This adds a simple driver to enable serial port and handle GPIO.

Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++ include/smsc_sio1007.h | 115 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/smsc_sio1007.h

diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index e1e3c6b..f2b08ab 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -32,6 +32,7 @@ ifdef CONFIG_DM_I2C obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_SANDBOX) += swap_case.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c new file mode 100644 index 0000000..ec53533 --- /dev/null +++ b/drivers/misc/smsc_sio1007.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <smsc_sio1007.h> + +static inline u8 sio1007_read(int port, int reg) +{ + outb(reg, port); + + return inb(port + 1); +} + +static inline void sio1007_write(int port, int reg, int val) +{ + outb(reg, port); + outb(val, port + 1); +} + +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) +{ + sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set); +} + +void sio1007_enable_serial(int port, int num, int iobase, int irq) +{ + if (num < 0 || num > SIO1007_UART_NUM) + return; + + /* enter configuration state */ + outb(0x55, port); + + /* power on serial port and set up its i/o base & irq */ + if (!num) { + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON); + sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2); + sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4); + } else { + sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON); + sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2); + sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq); + } + + /* exit configuration state */ + outb(0xaa, port); +} + +void sio1007_enable_runtime(int port, int iobase) +{ + /* enter configuration state */ + outb(0x55, port); + + /* set i/o base for the runtime register block */ + sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4); + sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12); + /* turn on address decoding for this block */ + sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN); + + /* exit configuration state */ + outb(0xaa, port); +} + +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type) +{ + int reg = GPIO0_DIR; + + if (gpio < 0 || gpio > SIO1007_GPIO_NUM) + return; + if (gpio >= GPIO_NUM_PER_GROUP) { + reg = GPIO1_DIR; + gpio -= GPIO_NUM_PER_GROUP; + } + + /* enter configuration state */ + outb(0x55, port); + + /* set gpio pin direction, polority and type */ + sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio); + sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio); + sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio); + + /* exit configuration state */ + outb(0xaa, port); +} + +int sio1007_gpio_get_value(int port, int gpio) +{ + int reg = GPIO0_DATA; + int val; + + if (gpio < 0 || gpio > SIO1007_GPIO_NUM) + return -EINVAL; + if (gpio >= GPIO_NUM_PER_GROUP) { + reg = GPIO1_DATA; + gpio -= GPIO_NUM_PER_GROUP; + } + + val = inb(port + reg); + if (val & (1 << gpio)) + return 1; + else + return 0; +} + +void sio1007_gpio_set_value(int port, int gpio, int val) +{ + int reg = GPIO0_DATA; + u8 data; + + if (gpio < 0 || gpio > SIO1007_GPIO_NUM) + return; + if (gpio >= GPIO_NUM_PER_GROUP) { + reg = GPIO1_DATA; + gpio -= GPIO_NUM_PER_GROUP; + } + + data = inb(port + reg); + data &= ~(1 << gpio); + data |= (val << gpio); + outb(data, port + reg); +} diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h new file mode 100644 index 0000000..805fa0e --- /dev/null +++ b/include/smsc_sio1007.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SMSC_SIO1007_H_ +#define _SMSC_SIO1007_H_ + +/* + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0 + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of + * SYSOPT0 and SYSOPT1 determines one of the following addresses. + */ +#define SIO1007_IOPORT0 0x002e +#define SIO1007_IOPORT1 0x004e +#define SIO1007_IOPORT2 0x162e +#define SIO1007_IOPORT3 0x164e + +/* SIO1007 registers */ + +#define DEV_POWER_CTRL 0x02 +#define UART1_POWER_ON (1 << 3) +#define UART2_POWER_ON (1 << 7) + +#define UART1_IOBASE 0x24 +#define UART2_IOBASE 0x25 +#define UART_IRQ 0x28 + +#define RTR_IOBASE_HIGH 0x21 +#define RTR_IOBASE_LOW 0x30 + +#define GPIO0_DIR 0x31 +#define GPIO1_DIR 0x35 +#define GPIO_DIR_INPUT 0 +#define GPIO_DIR_OUTPUT 1 + +#define GPIO0_POL 0x32 +#define GPIO1_POL 0x36 +#define GPIO_POL_NO_INVERT 0 +#define GPIO_POL_INVERT 1 + +#define GPIO0_TYPE 0x33 +#define GPIO1_TYPE 0x37 +#define GPIO_TYPE_PUSH_PULL 0 +#define GPIO_TYPE_OPEN_DRAIN 1 + +#define DEV_ACTIVATE 0x3a +#define RTR_EN (1 << 1) + +/* Runtime register offset */ + +#define GPIO0_DATA 0xc +#define GPIO1_DATA 0xe + +/* Number of serial ports supported */ +#define SIO1007_UART_NUM 2 + +/* Number of gpio pins supported */ +#define GPIO_NUM_PER_GROUP 8 +#define GPIO_GROUP_NUM 2 +#define SIO1007_GPIO_NUM (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM) + +/** + * Configure the I/O port address of the specified serial device and + * enable the serial device. + * + * @port: SIO1007 I/O port address + * @num: serial device number (0 or 1) + * @iobase: processor I/O port address to assign to this serial device + * @irq: processor IRQ number to assign to this serial device + */ +void sio1007_enable_serial(int port, int num, int iobase, int irq); + +/** + * Configure the I/O port address of the runtime register block and + * enable the address decoding. + * + * @port: SIO1007 I/O port address + * @iobase: processor I/O port address to assign to the runtime registers + */ +void sio1007_enable_runtime(int port, int iobase); + +/** + * Configure the direction/polority/type of a specified GPIO pin + * + * @port: SIO1007 I/O port address + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) + * @dir: GPIO_DIR_INPUT or GPIO_DIR_OUTPUT + * @pol: GPIO_POL_NO_INVERT or GPIO_POL_INVERT + * @type: GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN + */ +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type); + +/** + * Get a GPIO pin value. + * This will work whether the GPIO is an input or an output. + * + * @port: runtime register block I/O port address + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) + * @return: 0 if low, 1 if high, -EINVAL if gpio number is invalid + */ +int sio1007_gpio_get_value(int port, int gpio); + +/** + * Set a GPIO pin value. + * This will only work when the GPIO is configured as an output. + * + * @port: runtime register block I/O port address + * @gpio: GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37) + * @val: 0 if low, 1 if high + */ +void sio1007_gpio_set_value(int port, int gpio, int val); + +#endif /* _SMSC_SIO1007_H_ */

Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail.

To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address.

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org Tested on link (ivybridge non-FSP) Tested-by: Simon Glass sjg@chromium.org

---

Changes in v3: None Changes in v2: - Introduce a Kconfig option to wrap these codes

arch/x86/Kconfig | 10 ++++++++++ arch/x86/lib/fsp/fsp_support.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 49e173c..a0bd344 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -248,6 +248,16 @@ config FSP_USE_UPD are still some FSPs that might not even have UPD. For such FSPs, override this to n in their platform Kconfig files.

+config FSP_BROKEN_HOB + bool + depends on HAVE_FSP + help + Indicate some buggy FSPs that does not report memory used by FSP + itself as reserved in the resource descriptor HOB. Select this to + tell U-Boot to do some additional work to ensure U-Boot relocation + do not overwrite the important boot service data which is used by + FSP, otherwise the subsequent call to fsp_notify() will fail. + config ENABLE_MRC_CACHE bool "Enable MRC cache" depends on !EFI && !SYS_COREBOOT diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 29fa060..b05dced 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -225,6 +225,10 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list) struct hob_res_desc *res_desc; phys_addr_t phys_start; u32 top; +#ifdef CONFIG_FSP_BROKEN_HOB + struct hob_mem_alloc *res_mem; + phys_addr_t mem_base = 0; +#endif

/* Get the HOB list for processing */ hdr = hob_list; @@ -242,9 +246,38 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list) top += (u32)(res_desc->len); } } + +#ifdef CONFIG_FSP_BROKEN_HOB + /* + * Find out the lowest memory base address allocated by FSP + * for the boot service data + */ + if (hdr->type == HOB_TYPE_MEM_ALLOC) { + res_mem = (struct hob_mem_alloc *)hdr; + if (!mem_base) + mem_base = res_mem->mem_base; + if (res_mem->mem_base < mem_base) + mem_base = res_mem->mem_base; + } +#endif + hdr = get_next_hob(hdr); }

+#ifdef CONFIG_FSP_BROKEN_HOB + /* + * Check whether the memory top address is below the FSP HOB list. + * If not, use the lowest memory base address allocated by FSP as + * the memory top address. This is to prevent U-Boot relocation + * overwrites the important boot service data which is used by FSP, + * otherwise the subsequent call to fsp_notify() will fail. + */ + if (top > (u32)hob_list) { + debug("Adjust memory top address due to a buggy FSP\n"); + top = (u32)mem_base; + } +#endif + return top; }

Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif, and enable the build for both FSP and non-FSP configurations.

Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

arch/x86/cpu/ivybridge/Makefile | 2 +- arch/x86/cpu/ivybridge/bd82x6x.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index d7332ff..9203219 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,7 +7,6 @@ ifdef CONFIG_HAVE_FSP obj-y += fsp_configs.o ivybridge.o else -obj-y += bd82x6x.o obj-y += car.o obj-y += cpu.o obj-y += early_me.o @@ -21,3 +20,4 @@ obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o endif +obj-y += bd82x6x.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 996707b..9972b0a 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -22,6 +22,7 @@ #define GPIO_BASE 0x48 #define BIOS_CTRL 0xdc

+#ifndef CONFIG_HAVE_FSP static int pch_revision_id = -1; static int pch_type = -1;

@@ -170,6 +171,7 @@ static int bd82x6x_probe(struct udevice *dev)

return 0; } +#endif /* CONFIG_HAVE_FSP */

static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep) { @@ -247,6 +249,8 @@ U_BOOT_DRIVER(bd82x6x_drv) = { .name = "bd82x6x", .id = UCLASS_PCH, .of_match = bd82x6x_ids, +#ifndef CONFIG_HAVE_FSP .probe = bd82x6x_probe, +#endif .ops = &bd82x6x_pch_ops, };

This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset.

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org

---

Changes in v3: - Update README.x86 to include intructions for this board

Changes in v2: - Change include order - <asm/...> go after the normal includes - Use PCH uclass driver and change to use dm pci config APIs

arch/x86/cpu/ivybridge/Kconfig | 4 ++ arch/x86/dts/Makefile | 1 + arch/x86/dts/cougarcanyon2.dts | 104 ++++++++++++++++++++++++++++++ board/intel/Kconfig | 9 +++ board/intel/cougarcanyon2/Kconfig | 25 +++++++ board/intel/cougarcanyon2/MAINTAINERS | 6 ++ board/intel/cougarcanyon2/Makefile | 7 ++ board/intel/cougarcanyon2/cougarcanyon2.c | 58 +++++++++++++++++ board/intel/cougarcanyon2/start.S | 9 +++ configs/cougarcanyon2_defconfig | 20 ++++++ doc/README.x86 | 21 ++++++ include/configs/cougarcanyon2.h | 34 ++++++++++ 12 files changed, 298 insertions(+) create mode 100644 arch/x86/dts/cougarcanyon2.dts create mode 100644 board/intel/cougarcanyon2/Kconfig create mode 100644 board/intel/cougarcanyon2/MAINTAINERS create mode 100644 board/intel/cougarcanyon2/Makefile create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c create mode 100644 board/intel/cougarcanyon2/start.S create mode 100644 configs/cougarcanyon2_defconfig create mode 100644 include/configs/cougarcanyon2.h

diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index b9f290a..0819347 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -79,4 +79,8 @@ config FSP_USE_UPD bool default n

+config FSP_BROKEN_HOB + bool + default y + endif diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 64e5694..84feb19 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -5,6 +5,7 @@ dtb-y += bayleybay.dtb \ chromebook_link.dtb \ chromebox_panther.dtb \ + cougarcanyon2.dtb \ crownbay.dtb \ efi.dtb \ galileo.dtb \ diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts new file mode 100644 index 0000000..d415566 --- /dev/null +++ b/arch/x86/dts/cougarcanyon2.dts @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "keyboard.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "Intel Cougar Canyon 2"; + compatible = "intel,cougarcanyon2", "intel,chiefriver"; + + aliases { + spi0 = &spi0; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + microcode { + update@0 { +#include "microcode/m12306a2_00000008.dtsi" + }; + update@1 { +#include "microcode/m12306a4_00000007.dtsi" + }; + update@2 { +#include "microcode/m12306a5_00000007.dtsi" + }; + update@3 { +#include "microcode/m12306a8_00000010.dtsi" + }; + update@4 { +#include "microcode/m12306a9_0000001b.dtsi" + }; + }; + + fsp { + compatible = "intel,ivybridge-fsp"; + fsp,enable-ht; + }; + + pci { + #address-cells = <3>; + #size-cells = <2>; + compatible = "pci-x86"; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,bd82x6x"; + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + + spi0: spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9-spi"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q64bv", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; + }; + }; + +}; diff --git a/board/intel/Kconfig b/board/intel/Kconfig index f7d71c3..4d341aa 100644 --- a/board/intel/Kconfig +++ b/board/intel/Kconfig @@ -18,6 +18,14 @@ config TARGET_BAYLEYBAY 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC, PCIe and some other sensor interfaces.

+config TARGET_COUGARCANYON2 + bool "Cougar Canyon 2" + help + This is the Intel Cougar Canyon 2 Customer Reference Board. It + is built on the Chief River platform with Intel Ivybridge Processor + and Panther Point chipset. The board has 4GB RAM, with some other + peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI. + config TARGET_CROWNBAY bool "Crown Bay" help @@ -54,6 +62,7 @@ config TARGET_MINNOWMAX endchoice

source "board/intel/bayleybay/Kconfig" +source "board/intel/cougarcanyon2/Kconfig" source "board/intel/crownbay/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig" diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig new file mode 100644 index 0000000..95a617b --- /dev/null +++ b/board/intel/cougarcanyon2/Kconfig @@ -0,0 +1,25 @@ +if TARGET_COUGARCANYON2 + +config SYS_BOARD + default "cougarcanyon2" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "cougarcanyon2" + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_FSP + select BOARD_ROMSIZE_KB_2048 + +endif diff --git a/board/intel/cougarcanyon2/MAINTAINERS b/board/intel/cougarcanyon2/MAINTAINERS new file mode 100644 index 0000000..a486739 --- /dev/null +++ b/board/intel/cougarcanyon2/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL COUGAR CANYON 2 BOARD +M: Bin Meng bmeng.cn@gmail.com +S: Maintained +F: board/intel/cougarcanyon2/ +F: include/configs/cougarcanyon2.h +F: configs/cougarcanyon2_defconfig diff --git a/board/intel/cougarcanyon2/Makefile b/board/intel/cougarcanyon2/Makefile new file mode 100644 index 0000000..abd924c --- /dev/null +++ b/board/intel/cougarcanyon2/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cougarcanyon2.o start.o diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c new file mode 100644 index 0000000..31a480a --- /dev/null +++ b/board/intel/cougarcanyon2/cougarcanyon2.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <pci.h> +#include <smsc_sio1007.h> +#include <asm/ibmpc.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> + +#define SIO1007_RUNTIME_IOPORT 0x180 + +int board_early_init_f(void) +{ + struct udevice *pch; + int ret; + + ret = uclass_first_device(UCLASS_PCH, &pch); + if (ret) + return ret; + if (!pch) + return -ENODEV; + + /* Initialize LPC interface to turn on superio chipset decode range */ + dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE); + dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN); + dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B | + (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN); + dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B | + SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN); + + /* Enable legacy serial port at 0x3f8 */ + sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ); + + /* Enable SIO1007 runtime I/O port at 0x180 */ + sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT); + + /* + * On Cougar Canyon 2 board, the RS232 transiver connected to serial + * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007. + * Set the pin value to 1 to enable the RS232 transiver. + */ + sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT, + GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL); + sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1); + + return 0; +} + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} diff --git a/board/intel/cougarcanyon2/start.S b/board/intel/cougarcanyon2/start.S new file mode 100644 index 0000000..d8f227c --- /dev/null +++ b/board/intel/cougarcanyon2/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig new file mode 100644 index 0000000..09306bb --- /dev/null +++ b/configs/cougarcanyon2_defconfig @@ -0,0 +1,20 @@ +CONFIG_X86=y +CONFIG_VENDOR_INTEL=y +CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2" +CONFIG_TARGET_COUGARCANYON2=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_OF_CONTROL=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/doc/README.x86 b/doc/README.x86 index 6d9cb10..948deca 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -133,6 +133,27 @@ $ make all

---

+Intel Cougar Canyon 2 specific instructions for bare mode: + +This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors +with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP +website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the +time of writing) in the board directory and rename it to fsp.bin. + +Now build U-Boot and obtain u-boot.rom + +$ make cougarcanyon2_defconfig +$ make all + +The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in +the board manual. The SPI-0 flash should have flash descriptor plus ME firmware +and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0 +flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program +this image to the SPI-0 flash according to the board manual just once and we are +all set. For programming U-Boot we just need to program SPI-1 flash. + +--- + Intel Minnowboard Max instructions for bare mode:

This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h new file mode 100644 index 0000000..88845dc --- /dev/null +++ b/include/configs/cougarcanyon2.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (2 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SMSC_SIO1007 + +#define CONFIG_PCI_PNP + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} + +/* Environment configuration */ +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x5ff000 + +/* Video is not supported for now */ +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE + +#endif /* __CONFIG_H */