Add the base address map for Statix10 SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 38 ++++++++++++++++++++ 1 files changed, 38 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file mode 100644 index 0000000..e18d2bf --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ +#define _SOCFPGA_S10_BASE_HARDWARE_H_ + +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 +#define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_SMMU_ADDRESS 0xfa000000 +#define SOCFPGA_MAILBOX_ADDRESS 0xffA30000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc02100 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300 +#define SOCFPGA_L4WD2_ADDRESS 0xffd00400 +#define SOCFPGA_L4WD3_ADDRESS 0xffd00500 +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 +#define SOCFPGA_FIREWALL_L4_PER 0xffd21000 +#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 +#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 +#define SOCFPGA_FIREWALL_TCU 0xffd21400 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 +#define SOCFPGA_OCRAM_ADDRESS 0xffe00000 +#define GICD_BASE 0xfffc1000 +#define GICC_BASE 0xfffc2000 + +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

Add Clock Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/clock_manager.c | 4 +- arch/arm/mach-socfpga/clock_manager_s10.c | 380 ++++++++++++++++++++ arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 + .../mach-socfpga/include/mach/clock_manager_s10.h | 210 +++++++++++ arch/arm/mach-socfpga/include/mach/handoff_s10.h | 32 ++ arch/arm/mach-socfpga/wrap_pll_config_s10.c | 59 +++ 7 files changed, 689 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 286bfef..e5f9dd7 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -30,6 +30,10 @@ obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o endif

+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +obj-y += clock_manager_s10.o +obj-y += wrap_pll_config_s10.o +endif ifdef CONFIG_SPL_BUILD obj-y += spl.o ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 43e72a8..924b3c7 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask) do { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) inter_val = readl(&clock_manager_base->inter) & mask; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else inter_val = readl(&clock_manager_base->stat) & mask; #endif /* Wait for stable lock */ @@ -52,7 +52,7 @@ int set_cpu_clk_info(void)

#if defined(CONFIG_TARGET_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else gd->bd->bi_ddr_freq = 0; #endif

diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c new file mode 100644 index 0000000..3ba2a00 --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/handoff_s10.h> +#include <asm/arch/system_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_clock_manager *clock_manager_base = + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; +static const struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static void cm_write_bypass_mainpll(u32 val) +{ + writel(val, &clock_manager_base->main_pll.bypass); + cm_wait_for_fsm(); +} + +static void cm_write_bypass_perpll(u32 val) +{ + writel(val, &clock_manager_base->per_pll.bypass); + cm_wait_for_fsm(); +} + +/* function to write the ctrl register which requires a poll of the busy bit */ +static void cm_write_ctrl(u32 val) +{ + writel(val, &clock_manager_base->ctrl); + cm_wait_for_fsm(); +} + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + */ +void cm_basic_init(const struct cm_config * const cfg) +{ + u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib; + + if (cfg == 0) + return; + + /* Put all plls in bypass */ + cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL); + cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL); + + /* setup main PLL dividers where calculate the vcocalib value */ + mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & + CLKMGR_FDBCK_MDIV_MASK; + refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; + hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - + CLKMGR_HSCNT_CONST; + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) << + CLKMGR_VCOCALIB_MSCNT_OFFSET); + + writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & + ~CLKMGR_PLLGLOB_RST_MASK), + &clock_manager_base->main_pll.pllglob); + writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck); + writel(vcocalib, &clock_manager_base->main_pll.vcocalib); + writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0); + writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1); + writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv); + + /* setup peripheral PLL dividers */ + /* calculate the vcocalib value */ + mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & + CLKMGR_FDBCK_MDIV_MASK; + refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; + hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - + CLKMGR_HSCNT_CONST; + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) << + CLKMGR_VCOCALIB_MSCNT_OFFSET); + + writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & + ~CLKMGR_PLLGLOB_RST_MASK), + &clock_manager_base->per_pll.pllglob); + writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck); + writel(vcocalib, &clock_manager_base->per_pll.vcocalib); + writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0); + writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1); + writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl); + writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv); + + /* Take both PLL out of reset and power up */ + setbits_le32(&clock_manager_base->main_pll.pllglob, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + setbits_le32(&clock_manager_base->per_pll.pllglob, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + +#define LOCKED_MASK \ + (CLKMGR_STAT_MAINPLL_LOCKED | \ + CLKMGR_STAT_PERPLL_LOCKED) + + cm_wait_for_lock(LOCKED_MASK); + + /* + * Dividers for C2 to C9 only init after PLLs are lock. As dividers + * only take effect upon value change, we shall set a maximum value as + * default value. + */ + writel(0xff, &clock_manager_base->main_pll.mpuclk); + writel(0xff, &clock_manager_base->main_pll.nocclk); + writel(0xff, &clock_manager_base->main_pll.cntr2clk); + writel(0xff, &clock_manager_base->main_pll.cntr3clk); + writel(0xff, &clock_manager_base->main_pll.cntr4clk); + writel(0xff, &clock_manager_base->main_pll.cntr5clk); + writel(0xff, &clock_manager_base->main_pll.cntr6clk); + writel(0xff, &clock_manager_base->main_pll.cntr7clk); + writel(0xff, &clock_manager_base->main_pll.cntr8clk); + writel(0xff, &clock_manager_base->main_pll.cntr9clk); + writel(0xff, &clock_manager_base->per_pll.cntr2clk); + writel(0xff, &clock_manager_base->per_pll.cntr3clk); + writel(0xff, &clock_manager_base->per_pll.cntr4clk); + writel(0xff, &clock_manager_base->per_pll.cntr5clk); + writel(0xff, &clock_manager_base->per_pll.cntr6clk); + writel(0xff, &clock_manager_base->per_pll.cntr7clk); + writel(0xff, &clock_manager_base->per_pll.cntr8clk); + writel(0xff, &clock_manager_base->per_pll.cntr9clk); + + writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk); + writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk); + writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk); + writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk); + writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk); + writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk); + writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk); + writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk); + writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk); + writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk); + writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk); + writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk); + writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk); + writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk); + writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk); + writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk); + writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk); + writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk); + + /* Take all PLLs out of bypass */ + cm_write_bypass_mainpll(0); + cm_write_bypass_perpll(0); + + /* clear safe mode / out of boot mode */ + cm_write_ctrl(readl(&clock_manager_base->ctrl) + & ~(CLKMGR_CTRL_SAFEMODE)); + + /* Now ungate non-hw-managed clocks */ + writel(~0, &clock_manager_base->main_pll.en); + writel(~0, &clock_manager_base->per_pll.en); + + /* Clear the loss of lock bits (write 1 to clear) */ + writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK, + &clock_manager_base->intrclr); +} + +static unsigned long cm_get_main_vco_clk_hz(void) +{ + unsigned long fref, refdiv, mdiv, reg, vco; + + reg = readl(&clock_manager_base->main_pll.pllglob); + + fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & + CLKMGR_PLLGLOB_VCO_PSRC_MASK; + switch (fref) { + case CLKMGR_VCO_PSRC_EOSC1: + fref = cm_get_osc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_INTOSC: + fref = cm_get_intosc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_F2S: + fref = cm_get_fpga_clk_hz(); + break; + } + + refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + + reg = readl(&clock_manager_base->main_pll.fdbck); + mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; + + vco = fref / refdiv; + vco = vco * (CLKMGR_MDIV_CONST + mdiv); + return vco; +} + +static unsigned long cm_get_per_vco_clk_hz(void) +{ + unsigned long fref, refdiv, mdiv, reg, vco; + + reg = readl(&clock_manager_base->per_pll.pllglob); + + fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & + CLKMGR_PLLGLOB_VCO_PSRC_MASK; + switch (fref) { + case CLKMGR_VCO_PSRC_EOSC1: + fref = cm_get_osc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_INTOSC: + fref = cm_get_intosc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_F2S: + fref = cm_get_fpga_clk_hz(); + break; + } + + refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + + reg = readl(&clock_manager_base->per_pll.fdbck); + mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; + + vco = fref / refdiv; + vco = vco * (CLKMGR_MDIV_CONST + mdiv); + return vco; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk); + + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = cm_get_main_vco_clk_hz(); + clock /= (readl(&clock_manager_base->main_pll.pllc0) & + CLKMGR_PLLC0_DIV_MASK); + break; + + case CLKMGR_CLKSRC_PER: + clock = cm_get_per_vco_clk_hz(); + clock /= (readl(&clock_manager_base->per_pll.pllc0) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + + clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) & + CLKMGR_CLKCNT_MSK); + return clock; +} + +unsigned int cm_get_l3_main_clk_hz(void) +{ + u32 clock = readl(&clock_manager_base->main_pll.nocclk); + + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = cm_get_main_vco_clk_hz(); + clock /= (readl(&clock_manager_base->main_pll.pllc1) & + CLKMGR_PLLC0_DIV_MASK); + break; + + case CLKMGR_CLKSRC_PER: + clock = cm_get_per_vco_clk_hz(); + clock /= (readl(&clock_manager_base->per_pll.pllc1) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + + clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) & + CLKMGR_CLKCNT_MSK); + return clock; +} + +unsigned int cm_get_mmc_controller_clk_hz(void) +{ + u32 clock = readl(&clock_manager_base->per_pll.cntr6clk); + + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = cm_get_l3_main_clk_hz(); + clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_PER: + clock = cm_get_l3_main_clk_hz(); + clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + return clock / 4; +} + +unsigned int cm_get_l4_sp_clk_hz(void) +{ + u32 clock = cm_get_l3_main_clk_hz(); + + clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK)); + return clock; +} + +unsigned int cm_get_qspi_controller_clk_hz(void) +{ + return readl(&sysmgr_regs->boot_scratch_cold0); +} + +unsigned int cm_get_spi_controller_clk_hz(void) +{ + u32 clock = cm_get_l3_main_clk_hz(); + + clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >> + CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK)); + return clock; +} + +unsigned int cm_get_l4_sys_free_clk_hz(void) +{ + return cm_get_l3_main_clk_hz() / 4; +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000)); + printf("L3 main %d kHz\n", cm_get_l3_main_clk_hz() / 1000); + printf("Main VCO %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000)); + printf("Per VCO %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000)); + printf("EOSC1 %d kHz\n", cm_get_osc_clk_hz() / 1000); + printf("HPS MMC %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); + printf("UART %d kHz\n", cm_get_l4_sp_clk_hz() / 1000); +} diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 4c6b1f8..ddf814f 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -17,6 +17,8 @@ void cm_print_clock_quick_summary(void); #include <asm/arch/clock_manager_gen5.h> #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include <asm/arch/clock_manager_arria10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include <asm/arch/clock_manager_s10.h> #endif

#endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h new file mode 100644 index 0000000..24b20de --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#ifndef _CLOCK_MANAGER_S10_ +#define _CLOCK_MANAGER_S10_ + +/* Clock speed accessors */ +unsigned long cm_get_mpu_clk_hz(void); +unsigned long cm_get_sdram_clk_hz(void); +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); +const unsigned int cm_get_osc_clk_hz(void); +const unsigned int cm_get_f2s_per_ref_clk_hz(void); +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); +const unsigned int cm_get_intosc_clk_hz(void); +const unsigned int cm_get_fpga_clk_hz(void); + +#define CLKMGR_EOSC1_HZ 25000000 +#define CLKMGR_INTOSC_HZ 460000000 +#define CLKMGR_FPGA_CLK_HZ 50000000 + +/* Clock configuration accessors */ +const struct cm_config * const cm_get_default_config(void); + +struct cm_config { + /* main group */ + u32 main_pll_mpuclk; + u32 main_pll_nocclk; + u32 main_pll_cntr2clk; + u32 main_pll_cntr3clk; + u32 main_pll_cntr4clk; + u32 main_pll_cntr5clk; + u32 main_pll_cntr6clk; + u32 main_pll_cntr7clk; + u32 main_pll_cntr8clk; + u32 main_pll_cntr9clk; + u32 main_pll_nocdiv; + u32 main_pll_pllglob; + u32 main_pll_fdbck; + u32 main_pll_pllc0; + u32 main_pll_pllc1; + u32 spare; + + /* peripheral group */ + u32 per_pll_cntr2clk; + u32 per_pll_cntr3clk; + u32 per_pll_cntr4clk; + u32 per_pll_cntr5clk; + u32 per_pll_cntr6clk; + u32 per_pll_cntr7clk; + u32 per_pll_cntr8clk; + u32 per_pll_cntr9clk; + u32 per_pll_emacctl; + u32 per_pll_gpiodiv; + u32 per_pll_pllglob; + u32 per_pll_fdbck; + u32 per_pll_pllc0; + u32 per_pll_pllc1; + + /* incoming clock */ + u32 hps_osc_clk_hz; + u32 fpga_clk_hz; +}; + +void cm_basic_init(const struct cm_config * const cfg); + +struct socfpga_clock_manager_main_pll { + u32 en; + u32 ens; + u32 enr; + u32 bypass; + u32 bypasss; + u32 bypassr; + u32 mpuclk; + u32 nocclk; + u32 cntr2clk; + u32 cntr3clk; + u32 cntr4clk; + u32 cntr5clk; + u32 cntr6clk; + u32 cntr7clk; + u32 cntr8clk; + u32 cntr9clk; + u32 nocdiv; + u32 pllglob; + u32 fdbck; + u32 mem; + u32 memstat; + u32 pllc0; + u32 pllc1; + u32 vcocalib; + u32 _pad_0x90_0xA0[5]; +}; + +struct socfpga_clock_manager_per_pll { + u32 en; + u32 ens; + u32 enr; + u32 bypass; + u32 bypasss; + u32 bypassr; + u32 cntr2clk; + u32 cntr3clk; + u32 cntr4clk; + u32 cntr5clk; + u32 cntr6clk; + u32 cntr7clk; + u32 cntr8clk; + u32 cntr9clk; + u32 emacctl; + u32 gpiodiv; + u32 pllglob; + u32 fdbck; + u32 mem; + u32 memstat; + u32 pllc0; + u32 pllc1; + u32 vcocalib; + u32 _pad_0x100_0x124[10]; +}; + +struct socfpga_clock_manager { + u32 ctrl; + u32 stat; + u32 testioctrl; + u32 intrgen; + u32 intrmsk; + u32 intrclr; + u32 intrsts; + u32 intrstk; + u32 intrraw; + u32 _pad_0x24_0x2c[3]; + struct socfpga_clock_manager_main_pll main_pll; + struct socfpga_clock_manager_per_pll per_pll; +}; + +#define CLKMGR_CTRL_SAFEMODE BIT(0) +#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007 +#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f + +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008 +#define CLKMGR_STAT_BUSY BIT(0) +#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8) +#define CLKMGR_STAT_PERPLL_LOCKED BIT(9) + +#define CLKMGR_PLLGLOB_PD_MASK 0x00000001 +#define CLKMGR_PLLGLOB_RST_MASK 0x00000002 +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3 +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 +#define CLKMGR_VCO_PSRC_EOSC1 0 +#define CLKMGR_VCO_PSRC_INTOSC 1 +#define CLKMGR_VCO_PSRC_F2S 2 +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f +#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 + +#define CLKMGR_CLKSRC_MASK 0x7 +#define CLKMGR_CLKSRC_OFFSET 16 +#define CLKMGR_CLKSRC_MAIN 0 +#define CLKMGR_CLKSRC_PER 1 +#define CLKMGR_CLKSRC_OSC1 2 +#define CLKMGR_CLKSRC_INTOSC 3 +#define CLKMGR_CLKSRC_FPGA 4 +#define CLKMGR_CLKCNT_MSK 0x7ff + +#define CLKMGR_FDBCK_MDIV_MASK 0xff +#define CLKMGR_FDBCK_MDIV_OFFSET 24 + +#define CLKMGR_PLLC0_DIV_MASK 0xff +#define CLKMGR_PLLC1_DIV_MASK 0xff +#define CLKMGR_PLLC0_EN_OFFSET 27 +#define CLKMGR_PLLC1_EN_OFFSET 24 + +#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0 +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8 +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16 +#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24 +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 + +#define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3 +#define CLKMGR_NOCDIV_DIV1 0 +#define CLKMGR_NOCDIV_DIV2 1 +#define CLKMGR_NOCDIV_DIV4 2 +#define CLKMGR_NOCDIV_DIV8 3 +#define CLKMGR_CSPDBGCLK_DIV1 0 +#define CLKMGR_CSPDBGCLK_DIV4 1 + +#define CLKMGR_MSCNT_CONST 200 +#define CLKMGR_MDIV_CONST 6 +#define CLKMGR_HSCNT_CONST 9 + +#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff +#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9 +#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff + +#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26 +#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27 +#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28 + +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020 + +#endif /* _CLOCK_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h new file mode 100644 index 0000000..c32b431 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#ifndef _HANDOFF_S10_H_ +#define _HANDOFF_S10_H_ + +/* + * Offset for HW handoff from Quartus tools + */ +#define CONFIG_HANDOFF_BASE 0xFFE3F000 +#define CONFIG_HANDOFF_MUX (CONFIG_HANDOFF_BASE + 0x10) +#define CONFIG_HANDOFF_IOCTL (CONFIG_HANDOFF_BASE + 0x1A0) +#define CONFIG_HANDOFF_FPGA (CONFIG_HANDOFF_BASE + 0x330) +#define CONFIG_HANODFF_DELAY (CONFIG_HANDOFF_BASE + 0x3F0) +#define CONFIG_HANDOFF_CLOCK (CONFIG_HANDOFF_BASE + 0x580) +#define CONFIG_HANDOFF_MISC (CONFIG_HANDOFF_BASE + 0x610) +#define CONFIG_HANDOFF_MAGIC_MUX 0x504D5558 +#define CONFIG_HANDOFF_MAGIC_IOCTL 0x494F4354 +#define CONFIG_HANDOFF_MAGIC_FPGA 0x46504741 +#define CONFIG_HANDOFF_MAGIC_DELAY 0x444C4159 +#define CONFIG_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#define CONFIG_HANDOFF_MAGIC_MISC 0x4D495343 +#define CONFIG_HANDOFF_OFFSET_LENGTH 0x4 +#define CONFIG_HANDOFF_OFFSET_DATA 0x10 + +#define CONFIG_HANDOFF_CLOCK_OSC (CONFIG_HANDOFF_BASE + 0x608) +#define CONFIG_HANDOFF_CLOCK_FPGA (CONFIG_HANDOFF_BASE + 0x60C) + +#endif /* _HANDOFF_S10_H_ */ diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c new file mode 100644 index 0000000..c68b239 --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/arch/clock_manager.h> +#include <asm/io.h> +#include <asm/arch/handoff_s10.h> +#include <asm/arch/system_manager.h> + +static const struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +const struct cm_config * const cm_get_default_config(void) +{ + struct cm_config *cm_handoff_cfg = (struct cm_config *) + (CONFIG_HANDOFF_CLOCK + CONFIG_HANDOFF_OFFSET_DATA); + u32 *conversion = (u32 *)cm_handoff_cfg; + u32 i; + u32 handoff_clk = readl(CONFIG_HANDOFF_CLOCK); + + if (swab32(handoff_clk) == CONFIG_HANDOFF_MAGIC_CLOCK) { + writel(swab32(handoff_clk), CONFIG_HANDOFF_CLOCK); + for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++) + conversion[i] = swab32(conversion[i]); + return cm_handoff_cfg; + } else if (handoff_clk == CONFIG_HANDOFF_MAGIC_CLOCK) { + return cm_handoff_cfg; + } + + return NULL; +} + +const unsigned int cm_get_osc_clk_hz(void) +{ +#ifdef CONFIG_SPL_BUILD + u32 clock = readl(CONFIG_HANDOFF_CLOCK_OSC); + + writel(clock, &sysmgr_regs->boot_scratch_cold1); +#endif + return readl(&sysmgr_regs->boot_scratch_cold1); +} + +const unsigned int cm_get_intosc_clk_hz(void) +{ + return CLKMGR_INTOSC_HZ; +} + +const unsigned int cm_get_fpga_clk_hz(void) +{ +#ifdef CONFIG_SPL_BUILD + u32 clock = readl(CONFIG_HANDOFF_CLOCK_FPGA); + + writel(clock, &sysmgr_regs->boot_scratch_cold2); +#endif + return readl(&sysmgr_regs->boot_scratch_cold2); +}

Add pinmux driver support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 2 + .../arm/mach-socfpga/include/mach/system_manager.h | 5 +- .../mach-socfpga/include/mach/system_manager_s10.h | 176 ++++++++++++++++++++ arch/arm/mach-socfpga/system_manager_s10.c | 91 ++++++++++ arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 ++++++ 5 files changed, 329 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index f10b05c..910eb6f 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -33,6 +33,8 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o obj-y += reset_manager_s10.o +obj-y += system_manager_s10.o +obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_s10.o endif ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index e6d4280..80c7d0b 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -7,6 +7,9 @@ #ifndef _SYSTEM_MANAGER_H_ #define _SYSTEM_MANAGER_H_

+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include <asm/arch/system_manager_s10.h> +#else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) #define SYSMGR_ECC_OCRAM_EN BIT(0) @@ -89,5 +92,5 @@

#define SYSMGR_GET_BOOTINFO_BSEL(bsel) \ (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7) - +#endif #endif /* _SYSTEM_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h new file mode 100644 index 0000000..813dff2 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#ifndef _SYSTEM_MANAGER_S10_ +#define _SYSTEM_MANAGER_S10_ + +void sysmgr_pinmux_init(void); +void populate_sysmgr_fpgaintf_module(void); +void populate_sysmgr_pinmux(void); +void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); + +struct socfpga_system_manager { + /* System Manager Module */ + u32 siliconid1; /* 0x00 */ + u32 siliconid2; + u32 wddbg; + u32 _pad_0xc; + u32 mpu_status; /* 0x10 */ + u32 mpu_ace; + u32 _pad_0x18_0x1c[2]; + u32 dma; /* 0x20 */ + u32 dma_periph; + /* SDMMC Controller Group */ + u32 sdmmcgrp_ctrl; + u32 sdmmcgrp_l3master; + /* NAND Flash Controller Register Group */ + u32 nandgrp_bootstrap; /* 0x30 */ + u32 nandgrp_l3master; + /* USB Controller Group */ + u32 usb0_l3master; + u32 usb1_l3master; + /* EMAC Group */ + u32 emac_gbl; /* 0x40 */ + u32 emac0; + u32 emac1; + u32 emac2; + u32 emac0_ace; /* 0x50 */ + u32 emac1_ace; + u32 emac2_ace; + u32 nand_axuser; + u32 _pad_0x60_0x64[2]; /* 0x60 */ + /* FPGA interface Group */ + u32 fpgaintf_en_1; + u32 fpgaintf_en_2; + u32 fpgaintf_en_3; /* 0x70 */ + u32 dma_l3master; + u32 etr_l3master; + u32 _pad_0x7c; + u32 sec_ctrl_slt; /* 0x80 */ + u32 osc_trim; + u32 _pad_0x88_0x8c[2]; + /* ECC Group */ + u32 ecc_intmask_value; /* 0x90 */ + u32 ecc_intmask_set; + u32 ecc_intmask_clr; + u32 ecc_intstatus_serr; + u32 ecc_intstatus_derr; /* 0xa0 */ + u32 _pad_0xa4_0xac[3]; + u32 noc_addr_remap; /* 0xb0 */ + u32 hmc_clk; + u32 io_pa_ctrl; + u32 _pad_0xbc; + /* NOC Group */ + u32 noc_timeout; /* 0xc0 */ + u32 noc_idlereq_set; + u32 noc_idlereq_clr; + u32 noc_idlereq_value; + u32 noc_idleack; /* 0xd0 */ + u32 noc_idlestatus; + u32 fpga2soc_ctrl; + u32 fpga_config; + u32 iocsrclk_gate; /* 0xe0 */ + u32 gpo; + u32 gpi; + u32 _pad_0xec; + u32 mpu; /* 0xf0 */ + u32 sdm_hps_spare; + u32 hps_sdm_spare; + u32 _pad_0xfc_0x1fc[65]; + /* Boot scratch register group */ + u32 boot_scratch_cold0; /* 0x200 */ + u32 boot_scratch_cold1; + u32 boot_scratch_cold2; + u32 boot_scratch_cold3; + u32 boot_scratch_cold4; /* 0x210 */ + u32 boot_scratch_cold5; + u32 boot_scratch_cold6; + u32 boot_scratch_cold7; + u32 boot_scratch_cold8; /* 0x220 */ + u32 boot_scratch_cold9; + u32 _pad_0x228_0xffc[886]; + /* Pin select and pin control group */ + u32 pinsel0[40]; /* 0x1000 */ + u32 _pad_0x10a0_0x10fc[24]; + u32 pinsel40[8]; + u32 _pad_0x1120_0x112c[4]; + u32 ioctrl0[28]; + u32 _pad_0x11a0_0x11fc[24]; + u32 ioctrl28[20]; + u32 _pad_0x1250_0x12fc[44]; + /* Use FPGA mux */ + u32 rgmii0usefpga; /* 0x1300 */ + u32 rgmii1usefpga; + u32 rgmii2usefpga; + u32 i2c0usefpga; + u32 i2c1usefpga; + u32 i2c_emac0_usefpga; + u32 i2c_emac1_usefpga; + u32 i2c_emac2_usefpga; + u32 nandusefpga; + u32 _pad_0x1324; + u32 spim0usefpga; + u32 spim1usefpga; + u32 spis0usefpga; + u32 spis1usefpga; + u32 uart0usefpga; + u32 uart1usefpga; + u32 mdio0usefpga; + u32 mdio1usefpga; + u32 mdio2usefpga; + u32 _pad_0x134c; + u32 jtagusefpga; + u32 sdmmcusefpga; + u32 hps_osc_clk; + u32 _pad_0x135c_0x13fc[41]; + u32 iodelay0[40]; + u32 _pad_0x14a0_0x14fc[24]; + u32 iodelay40[8]; + +}; + +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) +#define SYSMGR_ECC_OCRAM_EN BIT(0) +#define SYSMGR_ECC_OCRAM_SERR BIT(3) +#define SYSMGR_ECC_OCRAM_DERR BIT(4) +#define SYSMGR_FPGAINTF_USEFPGA 0x1 + +#define SYSMGR_FPGAINTF_NAND BIT(4) +#define SYSMGR_FPGAINTF_SDMMC BIT(8) +#define SYSMGR_FPGAINTF_SPIM0 BIT(16) +#define SYSMGR_FPGAINTF_SPIM1 BIT(24) +#define SYSMGR_FPGAINTF_EMAC0 (0x11 << 0) +#define SYSMGR_FPGAINTF_EMAC1 (0x11 << 8) +#define SYSMGR_FPGAINTF_EMAC2 (0x11 << 16) + +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#define SYSMGR_SDMMC_DRVSEL_SHIFT 0 + +/* EMAC Group Bit definitions */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 + +#define SYSMGR_NOC_H2F_MSK 0x00000001 +#define SYSMGR_NOC_LWH2F_MSK 0x00000010 +#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001 + +#define SYSMGR_DMA_IRQ_NS 0xFF000000 +#define SYSMGR_DMA_MGR_NS 0x00010000 + +#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF + +#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F + +#endif /* _SYSTEM_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c new file mode 100644 index 0000000..122828c --- /dev/null +++ b/arch/arm/mach-socfpga/system_manager_s10.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/system_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * Configure all the pin muxes + */ +void sysmgr_pinmux_init(void) +{ + populate_sysmgr_pinmux(); + populate_sysmgr_fpgaintf_module(); +} + +/* + * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. + * The value is not wrote to SYSMGR.FPGAINTF.MODULE but + * CONFIG_SYSMGR_ISWGRP_HANDOFF. + */ +void populate_sysmgr_fpgaintf_module(void) +{ + u32 handoff_val = 0; + + /* Enable the signal for those HPS peripherals that use FPGA. */ + if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_NAND; + if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SDMMC; + if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM0; + if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM1; + writel(handoff_val, &sysmgr_regs->fpgaintf_en_2); + + handoff_val = 0; + if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC0; + if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC1; + if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC2; + writel(handoff_val, &sysmgr_regs->fpgaintf_en_3); +} + +/* + * Configure all the pin muxes + */ +void populate_sysmgr_pinmux(void) +{ + const u32 *sys_mgr_table_u32; + unsigned int len, i; + + /* setup the pin sel */ + sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len); + for (i = 0; i < len; i = i + 2) { + writel(sys_mgr_table_u32[i + 1], + sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]); + } + + /* setup the pin ctrl */ + sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len); + for (i = 0; i < len; i = i + 2) { + writel(sys_mgr_table_u32[i + 1], + sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]); + } + + /* setup the fpga use */ + sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len); + for (i = 0; i < len; i = i + 2) { + writel(sys_mgr_table_u32[i + 1], + sys_mgr_table_u32[i] + + (u8 *)&sysmgr_regs->rgmii0usefpga); + } + + /* setup the IO delay */ + sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len); + for (i = 0; i < len; i = i + 2) { + writel(sys_mgr_table_u32[i + 1], + sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]); + } +} diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c new file mode 100644 index 0000000..89c3153 --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/handoff_s10.h> + +static void sysmgr_pinmux_handoff_read(void *handoff_address, + const u32 **table, + unsigned int *table_len) +{ + unsigned int handoff_entry = (swab32(readl(handoff_address + + CONFIG_HANDOFF_OFFSET_LENGTH)) - + CONFIG_HANDOFF_OFFSET_DATA) / + sizeof(unsigned int); + unsigned int handoff_chunk[handoff_entry], temp, i; + + if (swab32(readl(CONFIG_HANDOFF_MUX)) == CONFIG_HANDOFF_MAGIC_MUX) { + /* using handoff from Quartus tools if exists */ + for (i = 0; i < handoff_entry; i++) { + temp = readl(handoff_address + + CONFIG_HANDOFF_OFFSET_DATA + (i * 4)); + handoff_chunk[i] = swab32(temp); + } + *table = handoff_chunk; + *table_len = ARRAY_SIZE(handoff_chunk); + } +} + +void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len) +{ + sysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_MUX, table, + table_len); +} + +void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len) +{ + sysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_IOCTL, table, + table_len); +} + +void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len) +{ + sysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_FPGA, table, + table_len); +} + +void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len) +{ + sysmgr_pinmux_handoff_read((void *)CONFIG_HANODFF_DELAY, table, + table_len); +}

Move eth reset to common misc driver so can used by other device families.

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc.c | 69 +++++++++++++++++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 74 +---------------------------- 3 files changed, 72 insertions(+), 72 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 0b65783..8466023 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -8,6 +8,7 @@ #define _MISC_H_

void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode); +int socfpga_eth_reset(void);

struct bsel { const char *mode; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 01f824c..d15cbc7 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -140,3 +140,72 @@ int arch_cpu_init(void)

return 0; } + +#ifdef CONFIG_ETH_DESIGNWARE +static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) +{ + if (!phymode) + return -EINVAL; + + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + return 0; + } + + if (!strcmp(phymode, "rgmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + return 0; + } + + if (!strcmp(phymode, "rmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + return 0; + } + + return -EINVAL; +} + +int socfpga_eth_reset(void) +{ + const void *fdt = gd->fdt_blob; + struct fdtdec_phandle_args args; + const char *phy_mode; + u32 phy_modereg; + int nodes[3]; /* Max. 3 GMACs */ + int ret, count; + int i, node; + + count = fdtdec_find_aliases_for_id(fdt, "ethernet", + COMPAT_ALTERA_SOCFPGA_DWMAC, + nodes, ARRAY_SIZE(nodes)); + for (i = 0; i < count; i++) { + node = nodes[i]; + if (node <= 0) + continue; + + ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", + "#reset-cells", 1, 0, + &args); + if (ret || args.args_count != 1) { + debug("GMAC%i: Failed to parse DT 'resets'!\n", i); + continue; + } + + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); + ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); + if (ret) { + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); + continue; + } + + dwmac_deassert_reset(args.args[0], phy_modereg); + } + + return 0; +} +#else +int socfpga_eth_reset(void) +{ + return 0; +}; +#endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 177b35f..f642524 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -63,84 +63,13 @@ void dwmac_deassert_reset(const unsigned int of_reset_id, /* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); } - -static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) -{ - if (!phymode) - return -EINVAL; - - if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - return 0; - } - - if (!strcmp(phymode, "rgmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - return 0; - } - - if (!strcmp(phymode, "rmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - return 0; - } - - return -EINVAL; -} - -static int socfpga_eth_reset(void) -{ - const void *fdt = gd->fdt_blob; - struct fdtdec_phandle_args args; - const char *phy_mode; - u32 phy_modereg; - int nodes[2]; /* Max. two GMACs */ - int ret, count; - int i, node; - - /* Put both GMACs into RESET state. */ - socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); - socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); - - count = fdtdec_find_aliases_for_id(fdt, "ethernet", - COMPAT_ALTERA_SOCFPGA_DWMAC, - nodes, ARRAY_SIZE(nodes)); - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", - "#reset-cells", 1, 0, - &args); - if (ret || (args.args_count != 1)) { - debug("GMAC%i: Failed to parse DT 'resets'!\n", i); - continue; - } - - phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); - ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); - if (ret) { - debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); - continue; - } - - dwmac_deassert_reset(args.args[0], phy_modereg); - } - - return 0; -} -#else -static int socfpga_eth_reset(void) -{ - return 0; -}; #endif

static const struct { const u16 pn; const char *name; const char *var; -} socfpga_fpga_model[] = { +} const socfpga_fpga_model[] = { /* Cyclone V E */ { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, @@ -218,6 +147,7 @@ int arch_misc_init(void) env_set("bootmode", bsel_str[bsel].mode); if (fpga_id >= 0) env_set("fpgatype", socfpga_fpga_model[fpga_id].var); + return socfpga_eth_reset(); } #endif

Restructure the SPL so each devices such as CV, A10 and S10 will have their own dedicated SPL file. SPL file determine the HW initialization flow which is device specific

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 5 +- arch/arm/mach-socfpga/spl_a10.c | 105 +++++++++++++++++++++++++++ arch/arm/mach-socfpga/{spl.c => spl_gen5.c} | 57 +++------------ 3 files changed, 120 insertions(+), 47 deletions(-) create mode 100644 arch/arm/mach-socfpga/spl_a10.c rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (82%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 098e5e9..b669d43 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -41,13 +41,16 @@ obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_s10.o endif ifdef CONFIG_SPL_BUILD -obj-y += spl.o ifdef CONFIG_TARGET_SOCFPGA_GEN5 +obj-y += spl_gen5.o obj-y += freeze_controller.o obj-y += wrap_iocsr_config.o obj-y += wrap_pinmux_config.o obj-y += wrap_sdram_config.o endif +ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +obj-y += spl_a10.o +endif endif

ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c new file mode 100644 index 0000000..e6fc766 --- /dev/null +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/pl310.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <image.h> +#include <asm/arch/reset_manager.h> +#include <spl.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/scan_manager.h> +#include <asm/arch/sdram.h> +#include <asm/arch/scu.h> +#include <asm/arch/nic301.h> +#include <asm/sections.h> +#include <fdtdec.h> +#include <watchdog.h> +#include <asm/arch/pinmux.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +u32 spl_boot_device(void) +{ + const u32 bsel = readl(&sysmgr_regs->bootinfo); + + switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { + case 0x1: /* FPGA (HPS2FPGA Bridge) */ + return BOOT_DEVICE_RAM; + case 0x2: /* NAND Flash (1.8V) */ + case 0x3: /* NAND Flash (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); + return BOOT_DEVICE_NAND; + case 0x4: /* SD/MMC External Transceiver (1.8V) */ + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); + socfpga_per_reset(SOCFPGA_RESET(DMA), 0); + return BOOT_DEVICE_MMC1; + case 0x6: /* QSPI Flash (1.8V) */ + case 0x7: /* QSPI Flash (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); + return BOOT_DEVICE_SPI; + default: + printf("Invalid boot device (bsel=%08x)!\n", bsel); + hang(); + } +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(const u32 boot_device) +{ +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif +} +#endif + +void spl_board_init(void) +{ + /* configuring the clock based on handoff */ + cm_basic_init(gd->fdt_blob); + WATCHDOG_RESET(); + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); + + /* Release UART from reset */ + socfpga_reset_uart(0); + + /* enable console uart printing */ + preloader_console_init(); +} + +void board_init_f(ulong dummy) +{ + /* + * Configure Clock Manager to use intosc clock instead external osc to + * ensure success watchdog operation. We do it as early as possible. + */ + cm_use_intosc(); + + socfpga_watchdog_disable(); + + arch_early_init_r(); + +#ifdef CONFIG_HW_WATCHDOG + /* release osc1 watchdog timer 0 from reset */ + socfpga_reset_deassert_osc1wd0(); + + /* reconfigure and enable the watchdog */ + hw_watchdog_init(); + WATCHDOG_RESET(); +#endif /* CONFIG_HW_WATCHDOG */ +} diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl_gen5.c similarity index 82% rename from arch/arm/mach-socfpga/spl.c rename to arch/arm/mach-socfpga/spl_gen5.c index 9bf3b9a..9864082 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -22,21 +22,15 @@ #include <asm/sections.h> #include <fdtdec.h> #include <watchdog.h> -#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#include <asm/arch/pinmux.h> -#endif

DECLARE_GLOBAL_DATA_PTR;

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -#endif - static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

@@ -66,7 +60,17 @@ u32 spl_boot_device(void) } }

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(const u32 boot_device) +{ +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif +} +#endif + static void socfpga_nic301_slave_ns(void) { writel(0x1, &nic301_regs->lwhps2fpgaregs); @@ -182,42 +186,3 @@ void board_init_f(ulong dummy) /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); } -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -void spl_board_init(void) -{ - /* configuring the clock based on handoff */ - cm_basic_init(gd->fdt_blob); - WATCHDOG_RESET(); - - config_dedicated_pins(gd->fdt_blob); - WATCHDOG_RESET(); - - /* Release UART from reset */ - socfpga_reset_uart(0); - - /* enable console uart printing */ - preloader_console_init(); -} - -void board_init_f(ulong dummy) -{ - /* - * Configure Clock Manager to use intosc clock instead external osc to - * ensure success watchdog operation. We do it as early as possible. - */ - cm_use_intosc(); - - socfpga_watchdog_disable(); - - arch_early_init_r(); - -#ifdef CONFIG_HW_WATCHDOG - /* release osc1 watchdog timer 0 from reset */ - socfpga_reset_deassert_osc1wd0(); - - /* reconfigure and enable the watchdog */ - hw_watchdog_init(); - WATCHDOG_RESET(); -#endif /* CONFIG_HW_WATCHDOG */ -} -#endif

Add DDR support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/include/mach/sdram_s10.h | 340 ++++++++++++++++++++ drivers/ddr/altera/Makefile | 1 + drivers/ddr/altera/sdram_s10.c | 392 ++++++++++++++++++++++++ 3 files changed, 733 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h create mode 100644 drivers/ddr/altera/sdram_s10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h new file mode 100644 index 0000000..6ce5180 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h @@ -0,0 +1,340 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * + */ + +#ifndef _SDRAM_S10_H_ +#define _SDRAM_S10_H_ + +unsigned long sdram_calculate_size(void); +int sdram_mmr_init_full(unsigned int sdr_phy_reg); +int sdram_calibration_full(void); + +#define DDR_TWR 15 +#define DDR_READ_LATENCY_DELAY 40 +#define DDR_ACTIVATE_FAWBANK 0x1 + +struct socfpga_ecc_hmc { + u32 ip_rev_id; + u32 _pad_0x4_0x7; + u32 ddrioctrl; + u32 ddrcalstat; + u32 mpr_0beat1; + u32 mpr_1beat1; + u32 mpr_2beat1; + u32 mpr_3beat1; + u32 mpr_4beat1; + u32 mpr_5beat1; + u32 mpr_6beat1; + u32 mpr_7beat1; + u32 mpr_8beat1; + u32 mpr_0beat2; + u32 mpr_1beat2; + u32 mpr_2beat2; + u32 mpr_3beat2; + u32 mpr_4beat2; + u32 mpr_5beat2; + u32 mpr_6beat2; + u32 mpr_7beat2; + u32 mpr_8beat2; + u32 _pad_0x58_0x5f[2]; + u32 auto_precharge; + u32 _pad_0x64_0xdf[31]; + u32 dramaddrwidth; + u32 _pad_0xe4_0xff[7]; + u32 eccctrl; + u32 eccctrl2; + u32 _pad_0x108_0x10f[2]; + u32 errinten; + u32 errintens; + u32 errintenr; + u32 intmode; + u32 intstat; + u32 diaginttest; + u32 modstat; + u32 derraddra; + u32 serraddra; + u32 _pad_0x134_0x137; + u32 autowb_corraddr; + u32 serrcntreg; + u32 autowb_drop_cntreg; + u32 ecc_reg2wreccdatabus; + u32 ecc_rdeccdata2regbus; + u32 ecc_reg2rdeccdatabus; + u32 ecc_diagon; + u32 ecc_decstat; + u32 _pad_0x158_0x15f[2]; + u32 ecc_errgenaddr_0; + u32 ecc_errgenaddr_1; + u32 ecc_errgenaddr_2; + u32 ecc_errgenaddr_3; + u32 ecc_ref2rddatabus_beat0; + u32 ecc_ref2rddatabus_beat1; + u32 ecc_ref2rddatabus_beat2; + u32 ecc_ref2rddatabus_beat3; + u32 ecc_errgenhaddr_0; + u32 ecc_errgenhaddr_1; + u32 ecc_errgenhaddr_2; + u32 ecc_errgenhaddr_3; + u32 ecc_rdeccdata2regbus_beat0; + u32 ecc_rdeccdata2regbus_beat1; + u32 ecc_rdeccdata2regbus_beat2; + u32 ecc_rdeccdata2regbus_beat3; + u32 _pad_0x1a0_0x1af[4]; + u32 derrhaddr; + u32 serrhaddr; + u32 _pad_0x1b8_0x1bb; + u32 autowb_corrhaddr; + u32 _pad_0x1c0_0x20f[20]; + u32 hpsintfcsel; + u32 rsthandshakectrl; + u32 rsthandshakestat; +}; + +struct socfpga_noc_ddr_scheduler { + u32 main_scheduler_id_coreid; + u32 main_scheduler_id_revisionid; + u32 main_scheduler_ddrconf; + u32 main_scheduler_ddrtiming; + u32 main_scheduler_ddrmode; + u32 main_scheduler_readlatency; + u32 _pad_0x18_0x37[8]; + u32 main_scheduler_activate; + u32 main_scheduler_devtodev; + u32 main_scheduler_ddr4timing; +}; + +struct socfpga_io48_mmr { + u32 dbgcfg0; + u32 dbgcfg1; + u32 dbgcfg2; + u32 dbgcfg3; + u32 dbgcfg4; + u32 dbgcfg5; + u32 dbgcfg6; + u32 reserve0; + u32 reserve1; + u32 reserve2; + u32 ctrlcfg0; + u32 ctrlcfg1; + u32 ctrlcfg2; + u32 ctrlcfg3; + u32 ctrlcfg4; + u32 ctrlcfg5; + u32 ctrlcfg6; + u32 ctrlcfg7; + u32 ctrlcfg8; + u32 ctrlcfg9; + u32 dramtiming0; + u32 dramodt0; + u32 dramodt1; + u32 sbcfg0; + u32 sbcfg1; + u32 sbcfg2; + u32 sbcfg3; + u32 sbcfg4; + u32 sbcfg5; + u32 sbcfg6; + u32 sbcfg7; + u32 caltiming0; + u32 caltiming1; + u32 caltiming2; + u32 caltiming3; + u32 caltiming4; + u32 caltiming5; + u32 caltiming6; + u32 caltiming7; + u32 caltiming8; + u32 caltiming9; + u32 caltiming10; + u32 dramaddrw; + u32 sideband0; + u32 sideband1; + u32 sideband2; + u32 sideband3; + u32 sideband4; + u32 sideband5; + u32 sideband6; + u32 sideband7; + u32 sideband8; + u32 sideband9; + u32 sideband10; + u32 sideband11; + u32 sideband12; + u32 sideband13; + u32 sideband14; + u32 sideband15; + u32 dramsts; + u32 dbgdone; + u32 dbgsignals; + u32 dbgreset; + u32 dbgmatch; + u32 counter0mask; + u32 counter1mask; + u32 counter0match; + u32 counter1match; + u32 niosreserve0; + u32 niosreserve1; + u32 niosreserve2; +}; + +union dramaddrw_reg { + struct { + u32 cfg_col_addr_width:5; + u32 cfg_row_addr_width:5; + u32 cfg_bank_addr_width:4; + u32 cfg_bank_group_addr_width:2; + u32 cfg_cs_addr_width:3; + u32 reserved:13; + }; + u32 word; +}; + +union ctrlcfg0_reg { + struct { + u32 cfg_mem_type:4; + u32 cfg_dimm_type:3; + u32 cfg_ac_pos:2; + u32 cfg_ctrl_burst_len:5; + u32 reserved:18; /* Other fields unused */ + }; + u32 word; +}; + +union ctrlcfg1_reg { + struct { + u32 cfg_dbc3_burst_len:5; + u32 cfg_addr_order:2; + u32 cfg_ctrl_enable_ecc:1; + u32 reserved:24; /* Other fields unused */ + }; + u32 word; +}; + +union dramtiming0_reg { + struct { + u32 cfg_tcl:6; + u32 reserved:8; /* Other fields unused */ + }; + u32 word; +}; + +union caltiming0_reg { + struct { + u32 cfg_act_to_rdwr:6; + u32 cfg_act_to_pch:6; + u32 cfg_act_to_act:6; + u32 cfg_act_to_act_db:6; + u32 reserved:8; /* Other fields unused */ + }; + u32 word; +}; + +union caltiming1_reg { + struct { + u32 cfg_rd_to_rd:6; + u32 cfg_rd_to_rd_dc:6; + u32 cfg_rd_to_rd_db:6; + u32 cfg_rd_to_wr:6; + u32 cfg_rd_to_wr_dc:6; + u32 reserved:2; + }; + u32 word; +}; + +union caltiming2_reg { + struct { + u32 cfg_rd_to_wr_db:6; + u32 cfg_rd_to_pch:6; + u32 cfg_rd_ap_to_valid:6; + u32 cfg_wr_to_wr:6; + u32 cfg_wr_to_wr_dc:6; + u32 reserved:2; + }; + u32 word; +}; + +union caltiming3_reg { + struct { + u32 cfg_wr_to_wr_db:6; + u32 cfg_wr_to_rd:6; + u32 cfg_wr_to_rd_dc:6; + u32 cfg_wr_to_rd_db:6; + u32 cfg_wr_to_pch:6; + u32 reserved:2; + }; + u32 word; +}; + +union caltiming4_reg { + struct { + u32 cfg_wr_ap_to_valid:6; + u32 cfg_pch_to_valid:6; + u32 cfg_pch_all_to_valid:6; + u32 cfg_arf_to_valid:8; + u32 cfg_pdn_to_valid:6; + }; + u32 word; +}; + +union caltiming9_reg { + struct { + u32 cfg_4_act_to_act:8; + u32 reserved:24; + }; + u32 word; +}; + +#define DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET 0 +#define DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET 6 +#define DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET 12 +#define DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET 18 +#define DDR_SCHED_DDRTIMING_RDTOWR_OFFSET 21 +#define DDR_SCHED_DDRTIMING_WRTORD_OFFSET 26 +#define DDR_SCHED_DDRTIMING_BWRATIO_OFFSET 31 +#define DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET 1 +#define DDR_SCHED_ACTIVATE_RRD_OFFSET 0 +#define DDR_SCHED_ACTIVATE_FAW_OFFSET 4 +#define DDR_SCHED_ACTIVATE_FAWBANK_OFFSET 10 +#define DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET 0 +#define DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET 2 +#define DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET 4 +#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 +#define DDR_HMC_DDRCALSTAT_CAL_MSK 0x00000001 +#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK 0x00010000 +#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK 0x00000100 +#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK 0x00000001 +#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK 0x00000100 +#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK 0x00000001 +#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK 0x00010000 +#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK 0x00000001 +#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK 0x00000001 +#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK 0x00000002 +#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK 0x00000001 +#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK 0x00000002 +#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK 0x00010000 +#define DDR_HMC_INTMODE_INTMODE_SET_MSK 0x00000001 +#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff +#define DDR_HMC_CORE2SEQ_INT_REQ 0xF +#define DDR_HMC_SEQ2CORE_INT_RESP_MASK 0x8 +#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f + +#define CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR 0xf7004400 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR 0xf70045c0 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR 0xf70045e0 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR 0xf7004600 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR 0xf7004620 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR 0xf7004640 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR 0xf7004660 + +#define CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR 0xf7018560 +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR 0xf7018580 +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR 0xf70185a0 +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR 0xf70185c0 +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR 0xf70185e0 +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR 0xf7018600 + +#define CCU_ADBASE_DI_MASK 0x00000010 + +#endif /* _SDRAM_S10_H_ */ diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index bdd2872..943b6cd 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -10,4 +10,5 @@

ifdef CONFIG_ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o endif diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c new file mode 100644 index 0000000..4c9cd34 --- /dev/null +++ b/drivers/ddr/altera/sdram_s10.c @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <errno.h> +#include <div64.h> +#include <asm/io.h> +#include <watchdog.h> +#include <asm/arch/sdram_s10.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = + (void *)SOCFPGA_SDR_ADDRESS; +static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base = + (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS; +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base = + (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS; +static const struct socfpga_system_manager *sysmgr_regs = + (void *)SOCFPGA_SYSMGR_ADDRESS; + +#define DDR_CONFIG(A, B, C, R) ((A << 24) | (B << 16) | (C << 8) | R) + +/* The followring are the supported configurations */ +u32 ddr_config[] = { + /* DDR_CONFIG(Address order,Bank,Column,Row) */ + /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */ + DDR_CONFIG(0, 3, 10, 12), + DDR_CONFIG(0, 3, 9, 13), + DDR_CONFIG(0, 3, 10, 13), + DDR_CONFIG(0, 3, 9, 14), + DDR_CONFIG(0, 3, 10, 14), + DDR_CONFIG(0, 3, 10, 15), + DDR_CONFIG(0, 3, 11, 14), + DDR_CONFIG(0, 3, 11, 15), + DDR_CONFIG(0, 3, 10, 16), + DDR_CONFIG(0, 3, 11, 16), + DDR_CONFIG(0, 3, 12, 15), /* 0xa */ + /* List for DDR4 only (pinout order > chip, bank, row, column) */ + DDR_CONFIG(1, 3, 10, 14), + DDR_CONFIG(1, 4, 10, 14), + DDR_CONFIG(1, 3, 10, 15), + DDR_CONFIG(1, 4, 10, 15), + DDR_CONFIG(1, 3, 10, 16), + DDR_CONFIG(1, 4, 10, 16), + DDR_CONFIG(1, 3, 10, 17), + DDR_CONFIG(1, 4, 10, 17), +}; + +#define DDR_CONFIG_ELEMENTS (sizeof(ddr_config) / sizeof(u32)) + +int match_ddr_conf(u32 ddr_conf) +{ + int i; + + for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) { + if (ddr_conf == ddr_config[i]) + return i; + } + return 0; +} + +static int emif_clear(void) +{ + u32 s2c, i; + + writel(0, &socfpga_ecc_hmc_base->rsthandshakectrl); + s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) & + DDR_HMC_RSTHANDSHAKE_MASK; + + for (i = 1000; (i > 0) && s2c; i--) { + WATCHDOG_RESET(); + mdelay(1); + s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) & + DDR_HMC_RSTHANDSHAKE_MASK; + } + return !s2c; +} + +static int emif_reset(void) +{ + u32 c2s, s2c, i; + + c2s = readl(&socfpga_ecc_hmc_base->rsthandshakectrl) & + DDR_HMC_RSTHANDSHAKE_MASK; + s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) & + DDR_HMC_RSTHANDSHAKE_MASK; + + debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", + c2s, s2c, readl(&socfpga_io48_mmr_base->niosreserve0), + readl(&socfpga_io48_mmr_base->niosreserve1), + readl(&socfpga_io48_mmr_base->niosreserve2), + readl(&socfpga_io48_mmr_base->dramsts)); + + if (s2c && emif_clear()) { + printf("DDR: emif_clear() failed\n"); + return -1; + } + + puts("DDR: Triggerring emif reset\n"); + writel(DDR_HMC_CORE2SEQ_INT_REQ, + &socfpga_ecc_hmc_base->rsthandshakectrl); + + for (i = 1000; i > 0; i--) { + /* if seq2core[3] = 0, we are good */ + if (!(readl(&socfpga_ecc_hmc_base->rsthandshakestat) & + DDR_HMC_SEQ2CORE_INT_RESP_MASK)) + break; + WATCHDOG_RESET(); + mdelay(1); + } + + if (!i) { + printf("DDR: failed to get ack from EMIF\n"); + return -2; + } + + if (emif_clear()) { + printf("DDR: emif_clear() failed\n"); + return -3; + } + + printf("DDR: %s triggered successly\n", __func__); + return 0; +} + +static int poll_hmc_clock_status(void) +{ + u32 status, i; + + for (i = 1000; i > 0; i--) { + status = readl(&sysmgr_regs->hmc_clk) & + SYSMGR_HMC_CLK_STATUS_MSK; + udelay(1); + if (status) + break; + WATCHDOG_RESET(); + } + return status; +} + +/** + * sdram_mmr_init_full() - Function to initialize SDRAM MMR + * + * Initialize the SDRAM MMR. + */ +int sdram_mmr_init_full(unsigned int unused) +{ + u32 update_value, io48_value, ddrioctl; + u32 i, j, cal_success; + + /* Enable access to DDR from CPU master */ + clrbits_le32(CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK); + + /* Enable access to DDR from IO master */ + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK); + + /* this enables nonsecure access to DDR */ + /* mpuregion0addr_limit */ + writel(0xFFFF0000, 0xF8020118); + writel(0x1F, 0xF802011c); + + /* nonmpuregion0addr_limit */ + writel(0xFFFF0000, 0xF8020198); + writel(0x1F, 0xF802019C); + + /* Enable mpuregion0enable and nonmpuregion0enable */ + writel(BIT(0) | BIT(8), 0xF8020100); + + /* Ensure HMC clock is running */ + if (!poll_hmc_clock_status()) { + puts("DDR: Error as HMC clock not running\n"); + return -1; + } + + /* release DDR scheduler from reset */ + socfpga_per_reset(SOCFPGA_RESET(SDR), 0); + + /* Try 3 times to do a calibration */ + for (i = 0; i < 3; i++) { + cal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat) & + DDR_HMC_DDRCALSTAT_CAL_MSK; + /* A delay to wait for calibration bit to set */ + for (j = 0; (j < 1000) && !cal_success; j++) { + WATCHDOG_RESET(); + mdelay(1); + cal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat) + & DDR_HMC_DDRCALSTAT_CAL_MSK; + } + + if (cal_success) + break; + + emif_reset(); + } + + if (!cal_success) { + puts("DDR: Error as SDRAM calibration failed\n"); + return -1; + } + puts("DDR: Calibration success\n"); + + union ctrlcfg0_reg ctrlcfg0 = (union ctrlcfg0_reg) + readl(&socfpga_io48_mmr_base->ctrlcfg0); + union ctrlcfg1_reg ctrlcfg1 = (union ctrlcfg1_reg) + readl(&socfpga_io48_mmr_base->ctrlcfg1); + union dramaddrw_reg dramaddrw = (union dramaddrw_reg) + readl(&socfpga_io48_mmr_base->dramaddrw); + union dramtiming0_reg dramtim0 = (union dramtiming0_reg) + readl(&socfpga_io48_mmr_base->dramtiming0); + union caltiming0_reg caltim0 = (union caltiming0_reg) + readl(&socfpga_io48_mmr_base->caltiming0); + union caltiming1_reg caltim1 = (union caltiming1_reg) + readl(&socfpga_io48_mmr_base->caltiming1); + union caltiming2_reg caltim2 = (union caltiming2_reg) + readl(&socfpga_io48_mmr_base->caltiming2); + union caltiming3_reg caltim3 = (union caltiming3_reg) + readl(&socfpga_io48_mmr_base->caltiming3); + union caltiming4_reg caltim4 = (union caltiming4_reg) + readl(&socfpga_io48_mmr_base->caltiming4); + union caltiming9_reg caltim9 = (union caltiming9_reg) + readl(&socfpga_io48_mmr_base->caltiming9); + + /* + * Configure the DDR IO size [0xFFCFB008] + * niosreserve0: Used to indicate DDR width & + * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit) + * bit[8] = 1 if user-mode OCT is present + * bit[9] = 1 if warm reset compiled into EMIF Cal Code + * bit[10] = 1 if warm reset is on during generation in EMIF Cal + * niosreserve1: IP ADCDS version encoded as 16 bit value + * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, + * 3=EAP, 4-6 are reserved) + * bit[5:3] = Service Pack # (e.g. 1) + * bit[9:6] = Minor Release # + * bit[14:10] = Major Release # + */ + update_value = readl(&socfpga_io48_mmr_base->niosreserve0); + writel(((update_value & 0xFF) >> 5), &socfpga_ecc_hmc_base->ddrioctrl); + ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl); + + /* enable HPS interface to HMC */ + writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, + &socfpga_ecc_hmc_base->hpsintfcsel); + + /* Set the DDR Configuration */ + io48_value = DDR_CONFIG(ctrlcfg1.cfg_addr_order, + (dramaddrw.cfg_bank_addr_width + + dramaddrw.cfg_bank_group_addr_width), + dramaddrw.cfg_col_addr_width, + dramaddrw.cfg_row_addr_width); + + update_value = match_ddr_conf(io48_value); + if (update_value) + writel(update_value, + &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrconf); + + /* Configure HMC dramaddrw */ + writel(readl(&socfpga_io48_mmr_base->dramaddrw), + &socfpga_ecc_hmc_base->dramaddrwidth); + + /* + * Configure DDR timing + * RDTOMISS = tRTP + tRP + tRCD - BL/2 + * WRTOMISS = WL + tWR + tRP + tRCD and + * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... + * First part of equation is in memory clock units so divide by 2 + * for HMC clock units. 1066MHz is close to 1ns so use 15 directly. + * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD + */ + update_value = caltim2.cfg_rd_to_pch + caltim4.cfg_pch_to_valid + + caltim0.cfg_act_to_rdwr - + (ctrlcfg0.cfg_ctrl_burst_len >> 2); + io48_value = (((dramtim0.cfg_tcl + 2 + DDR_TWR + + (ctrlcfg0.cfg_ctrl_burst_len >> 1)) >> 1) - + /* Up to here was in memory cycles so divide by 2 */ + caltim1.cfg_rd_to_wr + caltim0.cfg_act_to_rdwr + + caltim4.cfg_pch_to_valid); + + writel(((caltim0.cfg_act_to_act << + DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET) | + (update_value << DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET) | + (io48_value << DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET) | + ((ctrlcfg0.cfg_ctrl_burst_len >> 2) << + DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET) | + (caltim1.cfg_rd_to_wr << DDR_SCHED_DDRTIMING_RDTOWR_OFFSET) | + (caltim3.cfg_wr_to_rd << DDR_SCHED_DDRTIMING_WRTORD_OFFSET) | + (((ddrioctl == 1) ? 1 : 0) << + DDR_SCHED_DDRTIMING_BWRATIO_OFFSET)), + &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrtiming); + + /* Configure DDR mode [precharge = 0] */ + writel(((ddrioctl ? 0 : 1) << DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET), + &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrmode); + + /* Configure the read latency */ + writel((dramtim0.cfg_tcl >> 1) + DDR_READ_LATENCY_DELAY, + &socfpga_noc_ddr_scheduler_base->main_scheduler_readlatency); + + /* + * Configuring timing values concerning activate commands + * [FAWBANK alway 1 because always 4 bank DDR] + */ + writel(((caltim0.cfg_act_to_act_db << DDR_SCHED_ACTIVATE_RRD_OFFSET) | + (caltim9.cfg_4_act_to_act << DDR_SCHED_ACTIVATE_FAW_OFFSET) | + (DDR_ACTIVATE_FAWBANK << DDR_SCHED_ACTIVATE_FAWBANK_OFFSET)), + &socfpga_noc_ddr_scheduler_base->main_scheduler_activate); + + /* + * Configuring timing values concerning device to device data bus + * ownership change + */ + writel(((caltim1.cfg_rd_to_rd_dc << + DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET) | + (caltim1.cfg_rd_to_wr_dc << + DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET) | + (caltim3.cfg_wr_to_rd_dc << + DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET)), + &socfpga_noc_ddr_scheduler_base->main_scheduler_devtodev); + + /* assigning the SDRAM size */ + unsigned long long size = sdram_calculate_size(); + /* If the size is invalid, use default Config size */ + if (size <= 0) + gd->ram_size = PHYS_SDRAM_1_SIZE; + else + gd->ram_size = size; + + /* Enable or disable the SDRAM ECC */ + if (ctrlcfg1.cfg_ctrl_enable_ecc) { + setbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK)); + setbits_le32(&socfpga_ecc_hmc_base->eccctrl2, + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + } else { + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2, + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + } + + puts("DDR: HMC init success\n"); + return 0; +} + +/** + * sdram_calculate_size() - Calculate SDRAM size + * + * Calculate SDRAM device size based on SDRAM controller parameters. + * Size is specified in bytes. + */ +unsigned long sdram_calculate_size(void) +{ + union dramaddrw_reg dramaddrw = + (union dramaddrw_reg)readl(&socfpga_io48_mmr_base->dramaddrw); + + u32 size = (1 << (dramaddrw.cfg_cs_addr_width + + dramaddrw.cfg_bank_group_addr_width + + dramaddrw.cfg_bank_addr_width + + dramaddrw.cfg_row_addr_width + + dramaddrw.cfg_col_addr_width)); + + size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) & + DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); + + return size; +}