[U-Boot] [PATCH v2 0/2] Fix minor issues with Serval SoC.
This patch series fix different issues with Serval. - first patch fix resets when DDR training fails. - second patch fix the detection of the board.
This patch series is based on u-boot-mips/next.
v2-changes: - Update reset based on Daniel's comments
Horatiu Vultur (2): mips: mscc: serval: Fix reset board: mscc: serval: Fix board detect
arch/mips/mach-mscc/include/mach/ddr.h | 55 ++++++++++++++++++---------------- arch/mips/mach-mscc/reset.c | 2 +- board/mscc/serval/serval.c | 2 +- 3 files changed, 32 insertions(+), 27 deletions(-)
In case the ddr training was failing, it couldn't reset, it was just hanging. Therefore reimplement it, so when ddr training is failing it would call _machine_restart, which power downs the DDR and does a force reset.
Signed-off-by: Horatiu Vultur horatiu.vultur@microchip.com --- arch/mips/mach-mscc/include/mach/ddr.h | 55 ++++++++++++++++++---------------- arch/mips/mach-mscc/reset.c | 2 +- 2 files changed, 31 insertions(+), 26 deletions(-)
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index 84ecfbd..d1f4287 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -401,23 +401,7 @@ static inline void sleep_100ns(u32 val) ; }
-#if defined(CONFIG_SOC_OCELOT) -static inline void hal_vcoreiii_ddr_reset_assert(void) -{ - /* DDR has reset pin on GPIO 19 toggle Low-High to release */ - setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); - writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR); - sleep_100ns(10000); -} - -static inline void hal_vcoreiii_ddr_reset_release(void) -{ - /* DDR has reset pin on GPIO 19 toggle Low-High to release */ - setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); - writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); - sleep_100ns(10000); -} - +#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL) /* * DDR memory sanity checking failed, tally and do hard reset * @@ -427,9 +411,11 @@ static inline void hal_vcoreiii_ddr_failed(void) { register u32 reset;
+#if defined(CONFIG_SOC_OCELOT) writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6));
clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); +#endif
/* We have to execute the reset function from cache. Indeed, * the reboot workaround in _machine_restart() will change the @@ -452,6 +438,33 @@ static inline void hal_vcoreiii_ddr_failed(void)
panic("DDR init failed\n"); } +#else /* JR2 || ServalT */ +static inline void hal_vcoreiii_ddr_failed(void) +{ + writel(0, BASE_CFG + ICPU_RESET); + writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); + + panic("DDR init failed\n"); +} +#endif + +#if defined(CONFIG_SOC_OCELOT) +static inline void hal_vcoreiii_ddr_reset_assert(void) +{ + /* DDR has reset pin on GPIO 19 toggle Low-High to release */ + setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); + writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR); + sleep_100ns(10000); +} + +static inline void hal_vcoreiii_ddr_reset_release(void) +{ + /* DDR has reset pin on GPIO 19 toggle Low-High to release */ + setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); + writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); + sleep_100ns(10000); +} + #else /* JR2 || ServalT || Serval */ static inline void hal_vcoreiii_ddr_reset_assert(void) { @@ -463,14 +476,6 @@ static inline void hal_vcoreiii_ddr_reset_assert(void) writel(readl(BASE_CFG + ICPU_RESET) | ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET); } - -static inline void hal_vcoreiii_ddr_failed(void) -{ - writel(0, BASE_CFG + ICPU_RESET); - writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); - - panic("DDR init failed\n"); -} #endif /* JR2 || ServalT || Serval */
/* diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c index a555fc9..a121457 100644 --- a/arch/mips/mach-mscc/reset.c +++ b/arch/mips/mach-mscc/reset.c @@ -36,7 +36,7 @@ void _machine_restart(void) /* Do global reset */ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
- for (i = 0; i < 1000; i++) + for (i = 0; i < 2000; i++) ;
/* Power down DDR for clean DDR re-training */
When detecting the board, it was reading a register in the GPIO page of the phy and based on that value it was making a decision. The bug was that after the GPIO page for the first phy was set it was not reseted back.
Signed-off-by: Horatiu Vultur horatiu.vultur@microchip.com --- board/mscc/serval/serval.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c index 24ee5e5..ade041e 100644 --- a/board/mscc/serval/serval.c +++ b/board/mscc/serval/serval.c @@ -42,10 +42,10 @@ static void do_board_detect(void) gd->board_type = BOARD_TYPE_PCB106; else gd->board_type = BOARD_TYPE_PCB105; - mscc_phy_wr(1, 16, 15, 0); } else { gd->board_type = BOARD_TYPE_PCB105; } + mscc_phy_wr(1, 16, 31, 0x0); }
#if defined(CONFIG_MULTI_DTB_FIT)
Am 15.04.19 um 11:56 schrieb Horatiu Vultur:
This patch series fix different issues with Serval.
- first patch fix resets when DDR training fails.
- second patch fix the detection of the board.
This patch series is based on u-boot-mips/next.
v2-changes:
- Update reset based on Daniel's comments
Horatiu Vultur (2): mips: mscc: serval: Fix reset board: mscc: serval: Fix board detect
arch/mips/mach-mscc/include/mach/ddr.h | 55 ++++++++++++++++++---------------- arch/mips/mach-mscc/reset.c | 2 +- board/mscc/serval/serval.c | 2 +- 3 files changed, 32 insertions(+), 27 deletions(-)
series applied to u-boot-mips, thanks.
participants (2)
-
Daniel Schwierzeck -
Horatiu Vultur