From: Peng Fan peng.fan@nxp.com

Support NXP pca9451a

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/power/pmic/pca9450.c | 1 + include/power/pca9450.h | 1 + 2 files changed, 2 insertions(+)

diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index a186edc08da..3c4f5207e14 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -111,6 +111,7 @@ static const struct udevice_id pca9450_ids[] = { { .compatible = "nxp,pca9450a", .data = NXP_CHIP_TYPE_PCA9450A, }, { .compatible = "nxp,pca9450b", .data = NXP_CHIP_TYPE_PCA9450BC, }, { .compatible = "nxp,pca9450c", .data = NXP_CHIP_TYPE_PCA9450BC, }, + { .compatible = "nxp,pca9451a", .data = NXP_CHIP_TYPE_PCA9451A, }, { } };

diff --git a/include/power/pca9450.h b/include/power/pca9450.h index fa0405fcb87..f6d546f5711 100644 --- a/include/power/pca9450.h +++ b/include/power/pca9450.h @@ -59,6 +59,7 @@ int power_pca9450_init(unsigned char bus, unsigned char addr); enum { NXP_CHIP_TYPE_PCA9450A = 0, NXP_CHIP_TYPE_PCA9450BC, + NXP_CHIP_TYPE_PCA9451A, NXP_CHIP_TYPE_AMOUNT };

From: Peng Fan peng.fan@nxp.com

Without this config, there is boot error: Error binding ulp_wdt driver

Signed-off-by: Peng Fan peng.fan@nxp.com --- configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 64da123c372..53ab0f61610 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -112,5 +112,6 @@ CONFIG_RTC_EMULATION=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y CONFIG_LZO=y CONFIG_BZIP2=y

From: Peng Fan peng.fan@nxp.com

The M33 systick should be 24M per reference mannual, so correct it.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 04f3116fd1c..51aa259aa05 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -700,8 +700,8 @@ int clock_init(void) ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2); /* SWO TRACE to 133M */ ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); - /* M33 systetick to 133M */ - ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 systetick to 24M */ + ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); /* NIC to 400M */ ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2); /* NIC_APB to 133M */

From: Peng Fan peng.fan@nxp.com

The freq parameter was ignored, should use it when configuring ARM PLL

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 7d3a4c01333..f6021502b3d 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -674,7 +674,7 @@ void set_arm_clk(ulong freq) { /* Increase ARM clock to 1.7Ghz */ ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); - configure_intpll(ARM_PLL_CLK, 1700000000); + configure_intpll(ARM_PLL_CLK, freq); ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); }

From: Peng Fan peng.fan@nxp.com

Simplify the clk root settings with an array

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/clock.h | 6 ++++ arch/arm/mach-imx/imx9/clock.c | 38 +++++++++++++++----------- 2 files changed, 28 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h index 336d8613181..1169ffd74d3 100644 --- a/arch/arm/include/asm/arch-imx9/clock.h +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -205,6 +205,12 @@ struct clk_root_map { u32 mux_type; };

+struct imx_clk_setting { + u32 clk_root; + enum ccm_clk_src src; + u32 div; +}; + int clock_init(void); u32 get_clk_src_rate(enum ccm_clk_src source); u32 get_lpuart_clk(void); diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index a0efee96e51..a5f95fbcb8a 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -680,36 +680,42 @@ void set_arm_clk(ulong freq)

#endif

-int clock_init(void) -{ - int i; - +struct imx_clk_setting imx_clk_settings[] = { /* Set A55 periphal to 333M */ - ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3); + {ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3}, /* Set A55 mtr bus to 133M */ - ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); - + {ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* Sentinel to 200M */ - ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); + {SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2}, /* Bus_wakeup to 133M */ - ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + {BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* Bus_AON to 133M */ - ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + {BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* M33 to 200M */ - ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); + {M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2}, /* * WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for * generating MII clock at 2.5M */ - ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2); + {WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2}, /* SWO TRACE to 133M */ - ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + {SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}, /* M33 systetick to 24M */ - ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); + {M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1}, /* NIC to 400M */ - ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2); + {NIC_CLK_ROOT, SYS_PLL_PFD1, 2}, /* NIC_APB to 133M */ - ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + {NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3} +}; + +int clock_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx_clk_settings); i++) { + ccm_clk_root_cfg(imx_clk_settings[i].clk_root, + imx_clk_settings[i].src, imx_clk_settings[i].div); + }

/* allow for non-secure access */ for (i = 0; i < OSCPLL_END; i++)

From: Ye Li ye.li@nxp.com

The MAC addresses are hard coded for bring up. Change it to support reading from fuse.

Reviewed-by: Jacky Bai ping.bai@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/soc.c | 49 +++++++++++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index fd9280a3b1d..db24e547db5 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -30,6 +30,7 @@ #include <asm/arch-imx/cpu.h> #include <asm/mach-imx/s400_api.h> #include <linux/delay.h> +#include <fuse.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -337,12 +338,48 @@ phys_size_t get_effective_memsize(void)

void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { - mac[0] = 0x1; - mac[1] = 0x2; - mac[2] = 0x3; - mac[3] = 0x4; - mac[4] = 0x5; - mac[5] = 0x6; + u32 val[2] = {}; + int ret; + + if (dev_id == 0) { + ret = fuse_read(39, 3, &val[0]); + if (ret) + goto err; + + ret = fuse_read(39, 4, &val[1]); + if (ret) + goto err; + + mac[0] = val[1] >> 8; + mac[1] = val[1]; + mac[2] = val[0] >> 24; + mac[3] = val[0] >> 16; + mac[4] = val[0] >> 8; + mac[5] = val[0]; + + } else { + ret = fuse_read(39, 5, &val[0]); + if (ret) + goto err; + + ret = fuse_read(39, 4, &val[1]); + if (ret) + goto err; + + mac[0] = val[1] >> 24; + mac[1] = val[1] >> 16; + mac[2] = val[0] >> 24; + mac[3] = val[0] >> 16; + mac[4] = val[0] >> 8; + mac[5] = val[0]; + } + + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +err: + memset(mac, 0, 6); + printf("%s: fuse read err: %d\n", __func__, ret); }

int print_cpuinfo(void)

From: Peng Fan peng.fan@nxp.com

Add reset cause print to u-boot log on i.MX93. Since the SRC GENERAL registers are read only for non-secure mode. We have to clear SRSR in secure mode (SPL) and pass the value to non-secure mode via GPR1 register.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/soc.c | 54 ++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index ed75be6e195..60044155a63 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -461,10 +461,59 @@ err: printf("%s: fuse read err: %d\n", __func__, ret); }

+const char *reset_cause[] = { + "POR ", + "JTAG ", + "IPP USER ", + "WDOG1 ", + "WDOG2 ", + "WDOG3 ", + "WDOG4 ", + "WDOG5 ", + "TEMPSENSE ", + "CSU ", + "JTAG_SW ", + "M33_REQ ", + "M33_LOCKUP " + "UNK ", + "UNK ", + "UNK " +}; + +static void save_reset_cause(void) +{ + struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE; + u32 srsr = readl(&src->srsr); + + /* clear srsr in sec mode */ + writel(srsr, &src->srsr); + /* Save value to GPR1 to pass to nonsecure */ + writel(srsr, &src->gpr[0]); +} + +static const char *get_reset_cause(u32 *srsr_ret) +{ + struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE; + u32 srsr; + u32 i; + + srsr = readl(&src->gpr[0]); + if (srsr_ret) + *srsr_ret = srsr; + + for (i = ARRAY_SIZE(reset_cause); i > 0; i--) { + if (srsr & (BIT(i - 1))) + return reset_cause[i - 1]; + } + + return "unknown reset"; +} + int print_cpuinfo(void) { u32 cpurev, max_freq; int minc, maxc; + u32 ssrs_ret;

cpurev = get_cpu_rev();

@@ -495,6 +544,8 @@ int print_cpuinfo(void) } printf("(%dC to %dC)", minc, maxc);

+ printf("\nReset cause: %s (0x%x)\n", get_reset_cause(&ssrs_ret), ssrs_ret); + return 0; }

@@ -528,6 +579,9 @@ int arch_cpu_init(void) clock_init();

trdc_early_init(); + + /* Save SRC SRSR to GPR1 and clear it */ + save_reset_cause(); }

return 0;

From: Peng Fan peng.fan@nxp.com

According to datasheet, iMX93 has fused parts with CORE1 or NPU or both disabled. So update code to support it, the kernel device tree runtime update will be added in future patches.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx/cpu.h | 7 +++ arch/arm/include/asm/mach-imx/sys_proto.h | 12 ++++- arch/arm/mach-imx/imx9/soc.c | 53 ++++++++++++++++++++++- 3 files changed, 69 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index a666271fc11..cbd2717f97c 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -61,6 +61,13 @@ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_CPU_IMX93 0xC1 /* dummy ID */ +#define MXC_CPU_IMX9351 0xC2 /* dummy ID */ +#define MXC_CPU_IMX9332 0xC3 /* dummy ID */ +#define MXC_CPU_IMX9331 0xC4 /* dummy ID */ +#define MXC_CPU_IMX9322 0xC5 /* dummy ID */ +#define MXC_CPU_IMX9321 0xC6 /* dummy ID */ +#define MXC_CPU_IMX9312 0xC7 /* dummy ID */ +#define MXC_CPU_IMX9311 0xC8 /* dummy ID */

#define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index dd0d3f29333..de241c2450e 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -82,7 +82,17 @@ struct bd_info;

#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))

-#define is_imx93() (is_cpu_type(MXC_CPU_IMX93)) +#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \ + is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \ + is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \ + is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311)) +#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351)) +#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332)) +#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331)) +#define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322)) +#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321)) +#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312)) +#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))

#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 60044155a63..96e485e23cf 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -157,11 +157,34 @@ static void set_cpu_info(struct sentinel_get_info_data *info) memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32)); }

+static u32 get_cpu_variant_type(u32 type) +{ + /* word 19 */ + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2)); + bool npu_disable = !!(val & BIT(13)); + bool core1_disable = !!(val & BIT(15)); + u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24); + + if ((val2 & pack_9x9_fused) == pack_9x9_fused) + type = MXC_CPU_IMX9322; + + if (npu_disable && core1_disable) + return type + 3; + else if (npu_disable) + return type + 2; + else if (core1_disable) + return type + 1; + + return type; +} + u32 get_cpu_rev(void) { u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;

- return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev); + return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) | + (CHIP_REV_1_0 + rev); }

#define UNLOCK_WORD 0xD928C520 /* unlock word */ @@ -461,6 +484,30 @@ err: printf("%s: fuse read err: %d\n", __func__, ret); }

+const char *get_imx_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX93: + return "93(52)";/* iMX93 Dual core with NPU */ + case MXC_CPU_IMX9351: + return "93(51)";/* iMX93 Single core with NPU */ + case MXC_CPU_IMX9332: + return "93(32)";/* iMX93 Dual core without NPU */ + case MXC_CPU_IMX9331: + return "93(31)";/* iMX93 Single core without NPU */ + case MXC_CPU_IMX9322: + return "93(22)";/* iMX93 9x9 Dual core */ + case MXC_CPU_IMX9321: + return "93(21)";/* iMX93 9x9 Single core */ + case MXC_CPU_IMX9312: + return "93(12)";/* iMX93 9x9 Dual core without NPU */ + case MXC_CPU_IMX9311: + return "93(11)";/* iMX93 9x9 Single core without NPU */ + default: + return "??"; + } +} + const char *reset_cause[] = { "POR ", "JTAG ", @@ -517,7 +564,9 @@ int print_cpuinfo(void)

cpurev = get_cpu_rev();

- printf("CPU: i.MX93 rev%d.%d", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0); + printf("CPU: i.MX%s rev%d.%d", + get_imx_type((cpurev & 0x1FF000) >> 12), + (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);

max_freq = get_cpu_speed_grade_hz(); if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {

From: Peng Fan peng.fan@nxp.com

Add a static u-boot config for i.MX93 low drive mode support. When low drive mode is enabled, VDD_SOC is set to 0.75V. Bus clocks, A55 core clock (900Mhz), DDR clock (1866MTS), and some peripherals clocks (USDHC/FLEXSPI/PDM/DISP_PIX/CAM_PIX) must decrease to meet max frequencies in low drive mode.

Also set standby voltage for buck1

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- board/freescale/imx93_evk/MAINTAINERS | 1 + board/freescale/imx93_evk/Makefile | 4 + board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 +++++++++++++++++ board/freescale/imx93_evk/spl.c | 26 +- configs/imx93_11x11_evk_ld_defconfig | 118 ++ 5 files changed, 1639 insertions(+), 6 deletions(-) create mode 100644 board/freescale/imx93_evk/lpddr4x_timing_ld.c create mode 100644 configs/imx93_11x11_evk_ld_defconfig

diff --git a/board/freescale/imx93_evk/MAINTAINERS b/board/freescale/imx93_evk/MAINTAINERS index 389f17ae1e4..8ca4646f20f 100644 --- a/board/freescale/imx93_evk/MAINTAINERS +++ b/board/freescale/imx93_evk/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/imx93_evk/ F: include/configs/imx93_evk.h F: configs/imx93_11x11_evk_defconfig + configs/imx93_11x11_evk_ld_defconfig diff --git a/board/freescale/imx93_evk/Makefile b/board/freescale/imx93_evk/Makefile index 575f8e94604..17956d24bf7 100644 --- a/board/freescale/imx93_evk/Makefile +++ b/board/freescale/imx93_evk/Makefile @@ -8,5 +8,9 @@ obj-y += imx93_evk.o

ifdef CONFIG_SPL_BUILD obj-y += spl.o +ifdef CONFIG_IMX9_LOW_DRIVE_MODE +obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing_ld.o +else obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o endif +endif diff --git a/board/freescale/imx93_evk/lpddr4x_timing_ld.c b/board/freescale/imx93_evk/lpddr4x_timing_ld.c new file mode 100644 index 00000000000..f080322f112 --- /dev/null +++ b/board/freescale/imx93_evk/lpddr4x_timing_ld.c @@ -0,0 +1,1496 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Generated code from IMX_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44140001 }, + { 0x4e301000, 0x0 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000512 }, + { 0x4e300084, 0x0 }, + { 0x4e300114, 0x2 }, + { 0x4e300260, 0x0 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300104, 0xaa77000e }, + { 0x4e300108, 0x1816b1aa }, + { 0x4e30010c, 0x5101e6 }, + { 0x4e300100, 0x12552100 }, + { 0x4e300160, 0x9002 }, + { 0x4e30016c, 0x30900000 }, + { 0x4e300250, 0x14 }, + { 0x4e300254, 0xaa00aa }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x11281109 }, + { 0x4e300304, 0xaa110a }, + { 0x4e300308, 0x620071e }, + { 0x4e300170, 0x8a0a0508 }, + { 0x4e300124, 0xe3c0000 }, + { 0x4e300804, 0x1f1f1f1f }, + { 0x4e301240, 0x0 }, + { 0x4e301244, 0x0 }, + { 0x4e301248, 0x0 }, + { 0x4e30124c, 0x0 }, + { 0x4e301250, 0x0 }, + { 0x4e301254, 0x0 }, + { 0x4e301258, 0x0 }, + { 0x4e30125c, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, + { 0x1005f, 0x5ff }, + { 0x1015f, 0x5ff }, + { 0x1105f, 0x5ff }, + { 0x1115f, 0x5ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x200c5, 0xb }, + { 0x2002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x2007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x20056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x10049, 0xe00 }, + { 0x10149, 0xe00 }, + { 0x11049, 0xe00 }, + { 0x11149, 0xe00 }, + { 0x43, 0x60 }, + { 0x1043, 0x60 }, + { 0x2043, 0x60 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x2009b, 0x2 }, + { 0x20008, 0x1d3 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x10c }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x200fa, 0x2 }, + { 0x20019, 0x1 }, + { 0x200f0, 0x0 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x20021, 0x0 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x74a }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x1bb4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1f46 }, + { 0x5401c, 0x1708 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x1bb4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1f46 }, + { 0x54022, 0x1708 }, + { 0x54024, 0x6 }, + { 0x54032, 0xb400 }, + { 0x54033, 0x321b }, + { 0x54034, 0x4600 }, + { 0x54035, 0x81f }, + { 0x54036, 0x17 }, + { 0x54037, 0x600 }, + { 0x54038, 0xb400 }, + { 0x54039, 0x321b }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x81f }, + { 0x5403c, 0x17 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x74a }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x2080 }, + { 0x54012, 0x110 }, + { 0x54019, 0x1bb4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1f46 }, + { 0x5401c, 0x1708 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x1bb4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1f46 }, + { 0x54022, 0x1708 }, + { 0x54024, 0x6 }, + { 0x54032, 0xb400 }, + { 0x54033, 0x321b }, + { 0x54034, 0x4600 }, + { 0x54035, 0x81f }, + { 0x54036, 0x17 }, + { 0x54037, 0x600 }, + { 0x54038, 0xb400 }, + { 0x54039, 0x321b }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x81f }, + { 0x5403c, 0x17 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x30 }, + { 0x90051, 0x65a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x45a }, + { 0x90055, 0x9 }, + { 0x90056, 0x0 }, + { 0x90057, 0x448 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x179 }, + { 0x9005c, 0x1 }, + { 0x9005d, 0x618 }, + { 0x9005e, 0x109 }, + { 0x9005f, 0x40c0 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x8 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x4040 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x0 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x48 }, + { 0x9006b, 0x40 }, + { 0x9006c, 0x633 }, + { 0x9006d, 0x149 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x658 }, + { 0x90070, 0x109 }, + { 0x90071, 0x10 }, + { 0x90072, 0x4 }, + { 0x90073, 0x18 }, + { 0x90074, 0x0 }, + { 0x90075, 0x4 }, + { 0x90076, 0x78 }, + { 0x90077, 0x549 }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0xd49 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x159 }, + { 0x9007d, 0x94a }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x159 }, + { 0x90080, 0x441 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x42 }, + { 0x90084, 0x633 }, + { 0x90085, 0x149 }, + { 0x90086, 0x1 }, + { 0x90087, 0x633 }, + { 0x90088, 0x149 }, + { 0x90089, 0x0 }, + { 0x9008a, 0xe0 }, + { 0x9008b, 0x109 }, + { 0x9008c, 0xa }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x9 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x149 }, + { 0x90092, 0x9 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x159 }, + { 0x90095, 0x18 }, + { 0x90096, 0x10 }, + { 0x90097, 0x109 }, + { 0x90098, 0x0 }, + { 0x90099, 0x3c0 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x18 }, + { 0x9009c, 0x4 }, + { 0x9009d, 0x48 }, + { 0x9009e, 0x18 }, + { 0x9009f, 0x4 }, + { 0x900a0, 0x58 }, + { 0x900a1, 0xb }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x1 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x5 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x1ff8 }, + { 0x900db, 0x85a8 }, + { 0x900dc, 0x1e8 }, + { 0x900dd, 0x50 }, + { 0x900de, 0x798 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x60 }, + { 0x900e1, 0x7a0 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x8 }, + { 0x900e4, 0x8310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0x8 }, + { 0x900e7, 0xa310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0xa }, + { 0x900ea, 0x408 }, + { 0x900eb, 0x169 }, + { 0x900ec, 0x6e }, + { 0x900ed, 0x0 }, + { 0x900ee, 0x68 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x408 }, + { 0x900f1, 0x169 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x8310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0xa310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x1ff8 }, + { 0x900f9, 0x85a8 }, + { 0x900fa, 0x1e8 }, + { 0x900fb, 0x68 }, + { 0x900fc, 0x798 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x78 }, + { 0x900ff, 0x7a0 }, + { 0x90100, 0x16a }, + { 0x90101, 0x68 }, + { 0x90102, 0x790 }, + { 0x90103, 0x16a }, + { 0x90104, 0x8 }, + { 0x90105, 0x8b10 }, + { 0x90106, 0x168 }, + { 0x90107, 0x8 }, + { 0x90108, 0xab10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0xa }, + { 0x9010b, 0x408 }, + { 0x9010c, 0x169 }, + { 0x9010d, 0x58 }, + { 0x9010e, 0x0 }, + { 0x9010f, 0x68 }, + { 0x90110, 0x0 }, + { 0x90111, 0x408 }, + { 0x90112, 0x169 }, + { 0x90113, 0x0 }, + { 0x90114, 0x8b10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x1 }, + { 0x90117, 0xab10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0x1d8 }, + { 0x9011b, 0x169 }, + { 0x9011c, 0x80 }, + { 0x9011d, 0x790 }, + { 0x9011e, 0x16a }, + { 0x9011f, 0x18 }, + { 0x90120, 0x7aa }, + { 0x90121, 0x6a }, + { 0x90122, 0xa }, + { 0x90123, 0x0 }, + { 0x90124, 0x1e9 }, + { 0x90125, 0x8 }, + { 0x90126, 0x8080 }, + { 0x90127, 0x108 }, + { 0x90128, 0xf }, + { 0x90129, 0x408 }, + { 0x9012a, 0x169 }, + { 0x9012b, 0xc }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x68 }, + { 0x9012e, 0x9 }, + { 0x9012f, 0x0 }, + { 0x90130, 0x1a9 }, + { 0x90131, 0x0 }, + { 0x90132, 0x408 }, + { 0x90133, 0x169 }, + { 0x90134, 0x0 }, + { 0x90135, 0x8080 }, + { 0x90136, 0x108 }, + { 0x90137, 0x8 }, + { 0x90138, 0x7aa }, + { 0x90139, 0x6a }, + { 0x9013a, 0x0 }, + { 0x9013b, 0x8568 }, + { 0x9013c, 0x108 }, + { 0x9013d, 0xb7 }, + { 0x9013e, 0x790 }, + { 0x9013f, 0x16a }, + { 0x90140, 0x1f }, + { 0x90141, 0x0 }, + { 0x90142, 0x68 }, + { 0x90143, 0x8 }, + { 0x90144, 0x8558 }, + { 0x90145, 0x168 }, + { 0x90146, 0xf }, + { 0x90147, 0x408 }, + { 0x90148, 0x169 }, + { 0x90149, 0xd }, + { 0x9014a, 0x0 }, + { 0x9014b, 0x68 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x408 }, + { 0x9014e, 0x169 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x8558 }, + { 0x90151, 0x168 }, + { 0x90152, 0x8 }, + { 0x90153, 0x3c8 }, + { 0x90154, 0x1a9 }, + { 0x90155, 0x3 }, + { 0x90156, 0x370 }, + { 0x90157, 0x129 }, + { 0x90158, 0x20 }, + { 0x90159, 0x2aa }, + { 0x9015a, 0x9 }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x104 }, + { 0x90164, 0x8 }, + { 0x90165, 0x448 }, + { 0x90166, 0x109 }, + { 0x90167, 0xf }, + { 0x90168, 0x7c0 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x0 }, + { 0x9016b, 0xe8 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x47 }, + { 0x9016e, 0x630 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0x618 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0xe0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0x7c8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0x8140 }, + { 0x9017b, 0x10c }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x478 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x69 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x0 }, + { 0x2000b, 0x20c }, + { 0x2000c, 0x74 }, + { 0x2000d, 0x48e }, + { 0x2000e, 0x2c }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x400fd, 0xf }, + { 0x400f1, 0xe }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 1866mts 2D */ + .drate = 1866, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1866, }, +}; diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 38cfbac6ea6..34debb62d73 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -67,10 +67,23 @@ int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);

- /* 0.9v - */ - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) { + /* 0.75v for Low drive mode + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c); + } else { + /* 0.9v for Over drive mode + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + } + + /* set standby voltage to 0.65v */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);

/* I2C_LT_EN*/ pmic_reg_write(dev, 0xa, 0x3); @@ -106,10 +119,11 @@ void board_init_f(ulong dummy) printf("SOC: 0x%x\n", gd->arch.soc_rev); printf("LC: 0x%x\n", gd->arch.lifecycle); } + power_init_board();

- /* 1.7GHz */ - set_arm_clk(1700000000); + if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + set_arm_clk(get_cpu_speed_grade_hz());

/* Init power of mix */ soc_power_init(); diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig new file mode 100644 index 00000000000..945dc504726 --- /dev/null +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -0,0 +1,118 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_TARGET_IMX93_11X11_EVK=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_IMX9_LOW_DRIVE_MODE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2051e000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x2051ddd0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y +CONFIG_LZO=y +CONFIG_BZIP2=y

From: Peng Fan peng.fan@nxp.com

The ahab was missed to be compiled, so add it back.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8ulp/Kconfig | 5 +++++ arch/arm/mach-imx/imx8ulp/Makefile | 1 + 2 files changed, 6 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index bbdeaac07b3..5f7c0f988a8 100644 --- a/arch/arm/mach-imx/imx8ulp/Kconfig +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -1,5 +1,10 @@ if ARCH_IMX8ULP

+config AHAB_BOOT + bool "Support i.MX8ULP AHAB features" + help + This option enables the support for AHAB secure boot. + config IMX8ULP bool

diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index 2c9938fcdf0..f7692cf3a78 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -5,6 +5,7 @@

obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o +obj-$(CONFIG_AHAB_BOOT) += ahab.o

ifeq ($(CONFIG_SPL_BUILD),y) obj-y += upower/

From: Peng Fan peng.fan@nxp.com

The NXP Public API Name is ele, not AHAB, AHAB is for secure boot or ELE AHAB for ELE secure boot. So update code to reflect that.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/ele_api.h | 60 +++++++ arch/arm/include/asm/mach-imx/s400_api.h | 60 ------- arch/arm/mach-imx/imx8ulp/rdc.c | 10 +- arch/arm/mach-imx/imx8ulp/soc.c | 6 +- arch/arm/mach-imx/imx9/soc.c | 10 +- arch/arm/mach-imx/imx9/trdc.c | 10 +- board/freescale/imx8ulp_evk/spl.c | 10 +- board/freescale/imx93_evk/spl.c | 1 - drivers/misc/sentinel/Makefile | 2 +- .../misc/sentinel/{s400_api.c => ele_api.c} | 158 +++++++++--------- drivers/misc/sentinel/{s4mu.c => ele_mu.c} | 8 +- drivers/misc/sentinel/fuse.c | 8 +- 12 files changed, 171 insertions(+), 172 deletions(-) create mode 100644 arch/arm/include/asm/mach-imx/ele_api.h delete mode 100644 arch/arm/include/asm/mach-imx/s400_api.h rename drivers/misc/sentinel/{s400_api.c => ele_api.c} (69%) rename drivers/misc/sentinel/{s4mu.c => ele_mu.c} (95%)

diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h new file mode 100644 index 00000000000..158e21971ea --- /dev/null +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef __S400_API_H__ +#define __S400_API_H__ + +#define ELE_VERSION 0x6 +#define ELE_CMD_TAG 0x17 +#define ELE_RESP_TAG 0xe1 + +#define ELE_LOG_CID 0x21 +#define ELE_AUTH_OEM_CTNR_CID 0x87 +#define ELE_VERIFY_IMG_CID 0x88 +#define ELE_RELEASE_CTNR_CID 0x89 +#define ELE_WRITE_SECURE_FUSE_REQ_CID 0x91 +#define ELE_FWD_LIFECYCLE_UP_REQ_CID 0x95 +#define ELE_READ_FUSE_REQ_CID 0x97 +#define ELE_GET_FW_VERSION_CID 0x9D +#define ELE_RELEASE_RDC_REQ_CID 0xC4 +#define ELE_GET_FW_STATUS_CID 0xC5 +#define ELE_WRITE_FUSE_REQ_CID 0xD6 +#define ELE_CAAM_RELEASE_CID 0xD7 +#define ELE_GET_INFO_CID 0xDA + +#define S400_MAX_MSG 255U + +struct ele_msg { + u8 version; + u8 size; + u8 command; + u8 tag; + u32 data[(S400_MAX_MSG - 1U)]; +}; + +struct ele_get_info_data { + u32 hdr; + u32 soc; + u32 lc; + u32 uid[4]; + u32 sha256_rom_patch[8]; + u32 sha_fw[8]; +}; + +int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response); +int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response); +int ele_release_container(u32 *response); +int ele_verify_image(u32 img_id, u32 *response); +int ele_forward_lifecycle(u16 life_cycle, u32 *response); +int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); +int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); +int ele_release_caam(u32 core_did, u32 *response); +int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); +int ele_dump_buffer(u32 *buffer, u32 buffer_length); +int ele_get_info(struct ele_get_info_data *info, u32 *response); +int ele_get_fw_status(u32 *status, u32 *response); +int ele_release_m33_trout(void); + +#endif diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h deleted file mode 100644 index 89fa373d06f..00000000000 --- a/arch/arm/include/asm/mach-imx/s400_api.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2021 NXP - */ - -#ifndef __S400_API_H__ -#define __S400_API_H__ - -#define AHAB_VERSION 0x6 -#define AHAB_CMD_TAG 0x17 -#define AHAB_RESP_TAG 0xe1 - -#define AHAB_LOG_CID 0x21 -#define AHAB_AUTH_OEM_CTNR_CID 0x87 -#define AHAB_VERIFY_IMG_CID 0x88 -#define AHAB_RELEASE_CTNR_CID 0x89 -#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91 -#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95 -#define AHAB_READ_FUSE_REQ_CID 0x97 -#define AHAB_GET_FW_VERSION_CID 0x9D -#define AHAB_RELEASE_RDC_REQ_CID 0xC4 -#define AHAB_GET_FW_STATUS_CID 0xC5 -#define AHAB_WRITE_FUSE_REQ_CID 0xD6 -#define AHAB_CAAM_RELEASE_CID 0xD7 -#define AHAB_GET_INFO_CID 0xDA - -#define S400_MAX_MSG 255U - -struct sentinel_msg { - u8 version; - u8 size; - u8 command; - u8 tag; - u32 data[(S400_MAX_MSG - 1U)]; -}; - -struct sentinel_get_info_data { - u32 hdr; - u32 soc; - u32 lc; - u32 uid[4]; - u32 sha256_rom_patch[8]; - u32 sha_fw[8]; -}; - -int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response); -int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response); -int ahab_release_container(u32 *response); -int ahab_verify_image(u32 img_id, u32 *response); -int ahab_forward_lifecycle(u16 life_cycle, u32 *response); -int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); -int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); -int ahab_release_caam(u32 core_did, u32 *response); -int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); -int ahab_dump_buffer(u32 *buffer, u32 buffer_length); -int ahab_get_info(struct sentinel_get_info_data *info, u32 *response); -int ahab_get_fw_status(u32 *status, u32 *response); -int ahab_release_m33_trout(void); - -#endif diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index e24eeff8a20..954a2d08ec6 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/mu_hal.h> -#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/ele_api.h> #include <asm/arch/rdc.h> #include <div64.h>

@@ -184,14 +184,14 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm) int release_rdc(enum rdc_type type) { ulong s_mu_base = 0x27020000UL; - struct sentinel_msg msg; + struct ele_msg msg; int ret; u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; - msg.command = AHAB_RELEASE_RDC_REQ_CID; + msg.command = ELE_RELEASE_RDC_REQ_CID; msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */

mu_hal_init(s_mu_base); diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 5d95fb89a61..7d01bfcd8a8 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -14,7 +14,7 @@ #include <event.h> #include <spl.h> #include <asm/arch/rdc.h> -#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/ele_api.h> #include <asm/mach-imx/mu_hal.h> #include <cpu_func.h> #include <asm/setup.h> @@ -517,9 +517,9 @@ void get_board_serial(struct tag_serialnr *serialnr) u32 res; int ret;

- ret = ahab_read_common_fuse(1, uid, 4, &res); + ret = ele_read_common_fuse(1, uid, 4, &res); if (ret) - printf("ahab read fuse failed %d, 0x%x\n", ret, res); + printf("ele read fuse failed %d, 0x%x\n", ret, res); else printf("UID 0x%x,0x%x,0x%x,0x%x\n", uid[0], uid[1], uid[2], uid[3]);

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index e857a3dc663..30361ccecd1 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -32,7 +32,7 @@ #include <asm/setup.h> #include <asm/bootm.h> #include <asm/arch-imx/cpu.h> -#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/ele_api.h> #include <fuse.h>

DECLARE_GLOBAL_DATA_PTR; @@ -151,7 +151,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) return val; }

-static void set_cpu_info(struct sentinel_get_info_data *info) +static void set_cpu_info(struct ele_get_info_data *info) { gd->arch.soc_rev = info->soc; gd->arch.lifecycle = info->lc; @@ -642,7 +642,7 @@ int imx9_probe_mu(void *ctx, struct event *event) struct udevice *devp; int node, ret; u32 res; - struct sentinel_get_info_data info; + struct ele_get_info_data info;

node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");

@@ -653,7 +653,7 @@ int imx9_probe_mu(void *ctx, struct event *event) if (gd->flags & GD_FLG_RELOC) return 0;

- ret = ahab_get_info(&info, &res); + ret = ele_get_info(&info, &res); if (ret) return ret;

@@ -849,7 +849,7 @@ int m33_prepare(void) val = readl(&mix_regs->func_stat);

/* Release Sentinel TROUT */ - ahab_release_m33_trout(); + ele_release_m33_trout();

/* Mask WDOG1 IRQ from A55, we use it for M33 reset */ setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6)); diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c index 3f37ce712c0..938fe78eec6 100644 --- a/arch/arm/mach-imx/imx9/trdc.c +++ b/arch/arm/mach-imx/imx9/trdc.c @@ -10,7 +10,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> #include <div64.h> -#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/ele_api.h> #include <asm/mach-imx/mu_hal.h>

#define DID_NUM 16 @@ -315,7 +315,7 @@ bool trdc_mbc_enabled(ulong trdc_base) int release_rdc(u8 xrdc) { ulong s_mu_base = 0x47520000UL; - struct sentinel_msg msg; + struct ele_msg msg; int ret; u32 rdc_id;

@@ -336,10 +336,10 @@ int release_rdc(u8 xrdc) return -EINVAL; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; - msg.command = AHAB_RELEASE_RDC_REQ_CID; + msg.command = ELE_RELEASE_RDC_REQ_CID; msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */

mu_hal_init(s_mu_base); diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index e672f6ee6cb..12e530c1ee2 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -19,7 +19,7 @@ #include <asm/arch/ddr.h> #include <asm/arch/rdc.h> #include <asm/arch/upower.h> -#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/ele_api.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -63,9 +63,9 @@ void display_ele_fw_version(void) u32 fw_version, sha1, res; int ret;

- ret = ahab_get_fw_version(&fw_version, &sha1, &res); + ret = ele_get_fw_version(&fw_version, &sha1, &res); if (ret) { - printf("ahab get firmware version failed %d, 0x%x\n", ret, res); + printf("ele get firmware version failed %d, 0x%x\n", ret, res); } else { printf("ELE firmware version %u.%u.%u-%x", (fw_version & (0x00ff0000)) >> 16, @@ -122,9 +122,9 @@ void spl_board_init(void) set_lpav_qos();

/* Enable A35 access to the CAAM */ - ret = ahab_release_caam(0x7, &res); + ret = ele_release_caam(0x7, &res); if (ret) - printf("ahab release caam failed %d, 0x%x\n", ret, res); + printf("ele release caam failed %d, 0x%x\n", ret, res); }

void board_init_f(ulong dummy) diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 34debb62d73..c44dadcb5f0 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -20,7 +20,6 @@ #include <asm/mach-imx/mxc_i2c.h> #include <asm/arch-mx7ulp/gpio.h> #include <asm/mach-imx/syscounter.h> -#include <asm/mach-imx/s400_api.h> #include <dm/uclass.h> #include <dm/device.h> #include <dm/uclass-internal.h> diff --git a/drivers/misc/sentinel/Makefile b/drivers/misc/sentinel/Makefile index 446154cb201..f8d8c55f983 100644 --- a/drivers/misc/sentinel/Makefile +++ b/drivers/misc/sentinel/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+

-obj-y += s400_api.o s4mu.o +obj-y += ele_api.o ele_mu.o obj-$(CONFIG_CMD_FUSE) += fuse.o diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/ele_api.c similarity index 69% rename from drivers/misc/sentinel/s400_api.c rename to drivers/misc/sentinel/ele_api.c index 65032f77362..d9d37b7ea48 100644 --- a/drivers/misc/sentinel/s400_api.c +++ b/drivers/misc/sentinel/ele_api.c @@ -9,16 +9,16 @@ #include <malloc.h> #include <asm/io.h> #include <dm.h> -#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/ele_api.h> #include <misc.h>

DECLARE_GLOBAL_DATA_PTR;

-int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) +int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -26,10 +26,10 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; - msg.command = AHAB_RELEASE_RDC_REQ_CID; + msg.command = ELE_RELEASE_RDC_REQ_CID; switch (xrdc) { case 0: msg.data[0] = (0x74 << 8) | core_id; @@ -59,11 +59,11 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) return ret; }

-int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) +int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -71,10 +71,10 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 3; - msg.command = AHAB_AUTH_OEM_CTNR_CID; + msg.command = ELE_AUTH_OEM_CTNR_CID; msg.data[0] = upper_32_bits(ctnr_addr); msg.data[1] = lower_32_bits(ctnr_addr);

@@ -89,11 +89,11 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) return ret; }

-int ahab_release_container(u32 *response) +int ele_release_container(u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -101,10 +101,10 @@ int ahab_release_container(u32 *response) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; - msg.command = AHAB_RELEASE_CTNR_CID; + msg.command = ELE_RELEASE_CTNR_CID;

ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) @@ -117,11 +117,11 @@ int ahab_release_container(u32 *response) return ret; }

-int ahab_verify_image(u32 img_id, u32 *response) +int ele_verify_image(u32 img_id, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -129,10 +129,10 @@ int ahab_verify_image(u32 img_id, u32 *response) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; - msg.command = AHAB_VERIFY_IMG_CID; + msg.command = ELE_VERIFY_IMG_CID; msg.data[0] = 1 << img_id;

ret = misc_call(dev, false, &msg, size, &msg, size); @@ -146,11 +146,11 @@ int ahab_verify_image(u32 img_id, u32 *response) return ret; }

-int ahab_forward_lifecycle(u16 life_cycle, u32 *response) +int ele_forward_lifecycle(u16 life_cycle, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -158,10 +158,10 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; - msg.command = AHAB_FWD_LIFECYCLE_UP_REQ_CID; + msg.command = ELE_FWD_LIFECYCLE_UP_REQ_CID; msg.data[0] = life_cycle;

ret = misc_call(dev, false, &msg, size, &msg, size); @@ -175,11 +175,11 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response) return ret; }

-int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response) +int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -198,10 +198,10 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo return -EINVAL; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; - msg.command = AHAB_READ_FUSE_REQ_CID; + msg.command = ELE_READ_FUSE_REQ_CID; msg.data[0] = fuse_id;

ret = misc_call(dev, false, &msg, size, &msg, size); @@ -223,11 +223,11 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo return ret; }

-int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) +int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -235,10 +235,10 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 3; - msg.command = AHAB_WRITE_FUSE_REQ_CID; + msg.command = ELE_WRITE_FUSE_REQ_CID; msg.data[0] = (32 << 16) | (fuse_id << 5); if (lock) msg.data[0] |= (1 << 31); @@ -256,11 +256,11 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) return ret; }

-int ahab_release_caam(u32 core_did, u32 *response) +int ele_release_caam(u32 core_did, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -268,10 +268,10 @@ int ahab_release_caam(u32 core_did, u32 *response) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 2; - msg.command = AHAB_CAAM_RELEASE_CID; + msg.command = ELE_CAAM_RELEASE_CID; msg.data[0] = core_did;

ret = misc_call(dev, false, &msg, size, &msg, size); @@ -285,11 +285,11 @@ int ahab_release_caam(u32 core_did, u32 *response) return ret; }

-int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) +int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -307,10 +307,10 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) return -EINVAL; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; - msg.command = AHAB_GET_FW_VERSION_CID; + msg.command = ELE_GET_FW_VERSION_CID;

ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) @@ -326,11 +326,11 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) return ret; }

-int ahab_dump_buffer(u32 *buffer, u32 buffer_length) +int ele_dump_buffer(u32 *buffer, u32 buffer_length) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret, i = 0;

if (!dev) { @@ -338,10 +338,10 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; - msg.command = AHAB_LOG_CID; + msg.command = ELE_LOG_CID;

ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) { @@ -360,11 +360,11 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length) return i; }

-int ahab_get_info(struct sentinel_get_info_data *info, u32 *response) +int ele_get_info(struct ele_get_info_data *info, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -372,13 +372,13 @@ int ahab_get_info(struct sentinel_get_info_data *info, u32 *response) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 4; - msg.command = AHAB_GET_INFO_CID; + msg.command = ELE_GET_INFO_CID; msg.data[0] = upper_32_bits((ulong)info); msg.data[1] = lower_32_bits((ulong)info); - msg.data[2] = sizeof(struct sentinel_get_info_data); + msg.data[2] = sizeof(struct ele_get_info_data);

ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) @@ -391,11 +391,11 @@ int ahab_get_info(struct sentinel_get_info_data *info, u32 *response) return ret; }

-int ahab_get_fw_status(u32 *status, u32 *response) +int ele_get_fw_status(u32 *status, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -403,10 +403,10 @@ int ahab_get_fw_status(u32 *status, u32 *response) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; - msg.command = AHAB_GET_FW_STATUS_CID; + msg.command = ELE_GET_FW_STATUS_CID;

ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) @@ -421,11 +421,11 @@ int ahab_get_fw_status(u32 *status, u32 *response) return ret; }

-int ahab_release_m33_trout(void) +int ele_release_m33_trout(void) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct sentinel_msg); - struct sentinel_msg msg; + int size = sizeof(struct ele_msg); + struct ele_msg msg; int ret;

if (!dev) { @@ -433,8 +433,8 @@ int ahab_release_m33_trout(void) return -ENODEV; }

- msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; msg.size = 1; msg.command = 0xd3;

diff --git a/drivers/misc/sentinel/s4mu.c b/drivers/misc/sentinel/ele_mu.c similarity index 95% rename from drivers/misc/sentinel/s4mu.c rename to drivers/misc/sentinel/ele_mu.c index 794fc40c620..63373ea614f 100644 --- a/drivers/misc/sentinel/s4mu.c +++ b/drivers/misc/sentinel/ele_mu.c @@ -9,7 +9,7 @@ #include <dm/lists.h> #include <dm/root.h> #include <dm/device-internal.h> -#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/ele_api.h> #include <asm/arch/imx-regs.h> #include <linux/iopoll.h> #include <misc.h> @@ -85,7 +85,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)

static int imx8ulp_mu_read(struct mu_type *base, void *data) { - struct sentinel_msg *msg = (struct sentinel_msg *)data; + struct ele_msg *msg = (struct ele_msg *)data; int ret; u8 count = 0;

@@ -118,7 +118,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data)

static int imx8ulp_mu_write(struct mu_type *base, void *data) { - struct sentinel_msg *msg = (struct sentinel_msg *)data; + struct ele_msg *msg = (struct ele_msg *)data; int ret; u8 count = 0;

@@ -171,7 +171,7 @@ static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg, return ret; }

- result = ((struct sentinel_msg *)rx_msg)->data[0]; + result = ((struct ele_msg *)rx_msg)->data[0]; if ((result & 0xff) == 0xd6) return 0;

diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c index e2b68757664..4185a524a5f 100644 --- a/drivers/misc/sentinel/fuse.c +++ b/drivers/misc/sentinel/fuse.c @@ -10,7 +10,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/imx-regs.h> #include <env.h> -#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/ele_api.h> #include <asm/global_data.h>

DECLARE_GLOBAL_DATA_PTR; @@ -197,7 +197,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val) if (word_index != 1) size = 1;

- ret = ahab_read_common_fuse(word_index, data, size, &res); + ret = ele_read_common_fuse(word_index, data, size, &res); if (ret) { printf("ahab read fuse failed %d, 0x%x\n", ret, res); return ret; @@ -246,7 +246,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val) u32 res, size = 1; int ret;

- ret = ahab_read_common_fuse(word_index, &data, size, &res); + ret = ele_read_common_fuse(word_index, &data, size, &res); if (ret) { printf("ahab read fuse failed %d, 0x%x\n", ret, res); return ret; @@ -274,7 +274,7 @@ int fuse_prog(u32 bank, u32 word, u32 val) if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val) return -EINVAL;

- ret = ahab_write_fuse((bank * 8 + word), val, false, &res); + ret = ele_write_fuse((bank * 8 + word), val, false, &res); if (ret) { printf("ahab write fuse failed %d, 0x%x\n", ret, res); return ret;

From: Peng Fan peng.fan@nxp.com

Add get_events API to retrieve any singular events that has occurred since the FW has started from sentinel

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/ele_api.h | 2 ++ drivers/misc/sentinel/ele_api.c | 45 +++++++++++++++++++++++++ 2 files changed, 47 insertions(+)

diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 158e21971ea..5dc4a20c5fd 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -18,6 +18,7 @@ #define ELE_FWD_LIFECYCLE_UP_REQ_CID 0x95 #define ELE_READ_FUSE_REQ_CID 0x97 #define ELE_GET_FW_VERSION_CID 0x9D +#define ELE_GET_EVENTS_REQ_CID 0xA2 #define ELE_RELEASE_RDC_REQ_CID 0xC4 #define ELE_GET_FW_STATUS_CID 0xC5 #define ELE_WRITE_FUSE_REQ_CID 0xD6 @@ -56,5 +57,6 @@ int ele_dump_buffer(u32 *buffer, u32 buffer_length); int ele_get_info(struct ele_get_info_data *info, u32 *response); int ele_get_fw_status(u32 *status, u32 *response); int ele_release_m33_trout(void); +int ele_get_events(u32 *events, u32 *events_cnt, u32 *response);

#endif diff --git a/drivers/misc/sentinel/ele_api.c b/drivers/misc/sentinel/ele_api.c index d9d37b7ea48..1e0640d192b 100644 --- a/drivers/misc/sentinel/ele_api.c +++ b/drivers/misc/sentinel/ele_api.c @@ -445,3 +445,48 @@ int ele_release_m33_trout(void)

return ret; } + +int ele_get_events(u32 *events, u32 *events_cnt, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; + int ret, i = 0; + u32 actual_events; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + if (!events || !events_cnt || *events_cnt == 0) { + printf("Invalid parameters for %s\n", __func__); + return -EINVAL; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_GET_EVENTS_REQ_CID; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + if (!ret) { + actual_events = msg.data[1] & 0xffff; + if (*events_cnt < actual_events) + actual_events = *events_cnt; + + for (; i < actual_events; i++) + events[i] = msg.data[i + 2]; + + *events_cnt = actual_events; + } + + return ret; +}

From: Peng Fan peng.fan@nxp.com

Update pin header file for i.MX93

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/imx93-pinfunc.h | 194 ++++++++++---------- arch/arm/include/asm/arch-imx9/imx93_pins.h | 44 ++--- 2 files changed, 118 insertions(+), 120 deletions(-)

diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h index 7f0136c70b6..4298a145f8a 100644 --- a/arch/arm/dts/imx93-pinfunc.h +++ b/arch/arm/dts/imx93-pinfunc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright 2022 NXP */ @@ -10,57 +10,57 @@ * The pin function ID is a tuple of * <mux_reg conf_reg input_reg mux_mode input_val> */ -#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03E0 0x0 0x0 +#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 -#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x03CC 0x5 0x0 -#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0438 0x6 0x0 -#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03E4 0x0 0x0 +#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 -#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x03D0 0x5 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 -#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03DC 0x0 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0 #define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 #define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 -#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x0434 0x6 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 -#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x043C 0x6 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0 #define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03EC 0x1 0x0 +#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0 #define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x043C 0x5 0x1 -#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03F4 0x6 0x0 +#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1 +#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0 #define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 #define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E8 0x1 0x0 +#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0 #define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0438 0x5 0x1 -#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03F0 0x6 0x0 +#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1 +#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0 #define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 #define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0 #define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x0434 0x5 0x1 -#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03FC 0x6 0x0 +#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1 +#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0 #define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 #define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0 #define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F8 0x6 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0 #define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 #define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 @@ -68,23 +68,23 @@ #define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03FC 0x6 0x1 +#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1 #define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 #define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0440 0x2 0x0 +#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0 #define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F8 0x6 0x1 +#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1 #define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 #define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x0444 0x2 0x0 +#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0 #define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x0404 0x6 0x0 +#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0 #define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 #define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 @@ -92,7 +92,7 @@ #define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x0400 0x6 0x0 +#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0 #define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 #define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 @@ -100,7 +100,7 @@ #define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x0404 0x6 0x1 +#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1 #define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 #define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 @@ -108,7 +108,7 @@ #define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x0400 0x6 0x1 +#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1 #define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 #define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 @@ -116,7 +116,7 @@ #define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x040C 0x6 0x0 +#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0 #define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 #define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 @@ -124,47 +124,47 @@ #define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0408 0x6 0x0 +#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0 #define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 #define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0448 0x2 0x0 +#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0 #define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x040C 0x6 0x1 -#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0458 0x7 0x0 +#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1 +#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0 #define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x044C 0x2 0x0 +#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0 #define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0408 0x6 0x1 +#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1 #define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 #define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x0424 0x1 0x0 +#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0 #define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0430 0x6 0x0 +#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0 #define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 #define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0420 0x1 0x0 +#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0 #define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x042C 0x6 0x0 +#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0 #define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 #define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0448 0x2 0x1 +#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1 #define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x041C 0x4 0x0 +#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0 #define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0428 0x6 0x0 +#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0 #define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 #define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 @@ -175,7 +175,7 @@ #define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 #define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x0454 0x1 0x0 +#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0 #define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 @@ -183,8 +183,8 @@ #define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 #define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0458 0x1 0x1 -#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x044C 0x2 0x1 +#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1 +#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1 #define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 @@ -192,7 +192,7 @@ #define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 #define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0440 0x2 0x1 +#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1 #define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 @@ -205,58 +205,58 @@ #define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x0454 0x7 0x1 +#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1 #define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0460 0x1 0x0 -#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x045C 0x2 0x0 +#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0 +#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0 #define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03F4 0x6 0x1 +#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1 #define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 #define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x0464 0x1 0x0 +#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0 #define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03F0 0x6 0x1 +#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1 #define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 #define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0468 0x1 0x0 +#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0 #define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 #define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x046C 0x1 0x0 +#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0 #define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03DC 0x5 0x1 +#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1 #define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 #define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0470 0x1 0x0 -#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x0444 0x2 0x1 +#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0 +#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1 #define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03E0 0x5 0x1 +#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1 #define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 #define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x0474 0x1 0x0 +#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0 #define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 #define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03E4 0x5 0x1 +#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1 #define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 #define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03EC 0x1 0x1 +#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1 #define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 #define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E8 0x1 0x1 +#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1 #define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 #define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 #define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 @@ -266,20 +266,19 @@ #define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 #define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 #define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 -#define MX93_PAD_CCM_CLKO3__GPIO3_IO28 0x0090 0x0240 0x03CC 0x5 0x1 +#define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0 #define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 #define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 -#define MX93_PAD_CCM_CLKO4__GPIO3_IO29 0x0094 0x0244 0x03D0 0x5 0x1 +#define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0 #define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 #define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03D4 0x2 0x0 +#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0 #define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 #define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 #define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_MDC__LPUART5_RTS_B 0x0098 0x0248 0x0000 0x6 0x0 #define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 #define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D8 0x2 0x0 +#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0 #define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 #define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 @@ -302,7 +301,7 @@ #define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 #define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 #define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x0424 0x1 0x1 +#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1 #define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 #define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 @@ -323,21 +322,21 @@ #define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0420 0x1 0x1 +#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1 #define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x041C 0x1 0x1 -#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0410 0x3 0x0 +#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1 +#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0 #define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x0414 0x3 0x0 +#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0 #define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 #define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 -#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0418 0x3 0x0 +#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0 #define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 #define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 @@ -365,7 +364,7 @@ #define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 #define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 #define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0430 0x1 0x1 +#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1 #define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 #define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 #define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 @@ -390,24 +389,24 @@ #define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x042C 0x1 0x1 +#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1 #define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 #define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x045C 0x1 0x1 +#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1 #define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 #define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0428 0x1 0x1 +#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1 #define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 #define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 #define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 #define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x045C 0x2 0x2 +#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2 #define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 #define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 @@ -457,43 +456,42 @@ #define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 #define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 #define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 -#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0418 0x2 0x1 +#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1 #define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 #define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 #define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 -#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0460 0x0 0x1 +#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1 #define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 #define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 #define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 -#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x0464 0x0 0x1 +#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1 #define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 #define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 #define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0468 0x0 0x1 +#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1 #define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 #define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x046C 0x0 0x1 +#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1 #define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 #define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0470 0x0 0x1 +#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1 #define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 #define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x0474 0x0 0x1 +#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1 #define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 #define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 #define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 #define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 -#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03D4 0x2 0x1 +#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1 #define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 #define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 -#define MX93_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x0150 0x0300 0x0000 0x6 0x0 #define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 #define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 -#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D8 0x2 0x1 +#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1 #define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 #define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 #define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 @@ -523,34 +521,34 @@ #define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 #define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 #define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 -#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0410 0x1 0x1 +#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1 #define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 #define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 #define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 #define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 #define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 -#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x0414 0x1 0x1 +#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1 #define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 #define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 #define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 -#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x0 0x0 +#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0 #define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 #define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 #define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 #define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 -#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x0 0x0 +#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0 #define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 #define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 #define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 #define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 -#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x0 0x0 +#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0 #define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 #define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 #define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 #define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 #define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 #define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 -#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x0 0x0 +#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0 #define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 #define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 #define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 @@ -569,7 +567,7 @@ #define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 #define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 #define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 -#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0450 0x4 0x0 +#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0 #define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 #define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 #define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 @@ -581,14 +579,14 @@ #define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 #define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 #define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 -#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0440 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2 #define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 #define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 #define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 #define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 #define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 #define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 -#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x0444 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2 #define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 #define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 #define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 @@ -614,7 +612,7 @@ #define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 #define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 #define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 -#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0450 0x1 0x1 +#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1 #define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 #define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 #define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h b/arch/arm/include/asm/arch-imx9/imx93_pins.h index f13aef5619c..cce9f62b8df 100644 --- a/arch/arm/include/asm/arch-imx9/imx93_pins.h +++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h @@ -34,39 +34,39 @@ enum { MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX = IOMUX_PAD(0x1BC, 0x000C, 6, 0x434, 0, 0),

MX93_PAD_GPIO_IO00__GPIO2_IO00 = IOMUX_PAD(0x1C0, 0x0010, 0, 0x0000, 0, 0), - MX93_PAD_GPIO_IO00__LPI2C3_SDA = IOMUX_PAD(0x1C0, 0x0010, 1, 0x3E4, 0, 0), + MX93_PAD_GPIO_IO00__LPI2C3_SDA = IOMUX_PAD(0x1C0, 0x0010, 1 | IOMUX_CONFIG_SION, 0x3E4, 0, 0), MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK = IOMUX_PAD(0x1C0, 0x0010, 2, 0x0000, 0, 0), MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK = IOMUX_PAD(0x1C0, 0x0010, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO00__LPSPI6_PCS0 = IOMUX_PAD(0x1C0, 0x0010, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO00__LPUART5_TX = IOMUX_PAD(0x1C0, 0x0010, 5, 0x434, 1, 0), - MX93_PAD_GPIO_IO00__LPI2C5_SDA = IOMUX_PAD(0x1C0, 0x0010, 6, 0x3EC, 0, 0), + MX93_PAD_GPIO_IO00__LPI2C5_SDA = IOMUX_PAD(0x1C0, 0x0010, 6 | IOMUX_CONFIG_SION, 0x3EC, 0, 0), MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x1C0, 0x0010, 7, 0x36C, 0, 0),

MX93_PAD_GPIO_IO01__GPIO2_IO01 = IOMUX_PAD(0x1C4, 0x0014, 0, 0x0000, 0, 0), - MX93_PAD_GPIO_IO01__LPI2C3_SCL = IOMUX_PAD(0x1C4, 0x0014, 1, 0x3E0, 0, 0), + MX93_PAD_GPIO_IO01__LPI2C3_SCL = IOMUX_PAD(0x1C4, 0x0014, 1 | IOMUX_CONFIG_SION, 0x3E0, 0, 0), MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 = IOMUX_PAD(0x1C4, 0x0014, 2, 0x0000, 0, 0), MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE = IOMUX_PAD(0x1C4, 0x0014, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO01__LPSPI6_SIN = IOMUX_PAD(0x1C4, 0x0014, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO01__LPUART5_RX = IOMUX_PAD(0x1C4, 0x0014, 5, 0x430, 1, 0), - MX93_PAD_GPIO_IO01__LPI2C5_SCL = IOMUX_PAD(0x1C4, 0x0014, 6, 0x3E8, 0, 0), + MX93_PAD_GPIO_IO01__LPI2C5_SCL = IOMUX_PAD(0x1C4, 0x0014, 6 | IOMUX_CONFIG_SION, 0x3E8, 0, 0), MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x1C4, 0x0014, 7, 0x370, 0, 0),

MX93_PAD_GPIO_IO02__GPIO2_IO02 = IOMUX_PAD(0x1C8, 0x0018, 0, 0x0000, 0, 0), - MX93_PAD_GPIO_IO02__LPI2C4_SDA = IOMUX_PAD(0x1C8, 0x0018, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__LPI2C4_SDA = IOMUX_PAD(0x1C8, 0x0018, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC = IOMUX_PAD(0x1C8, 0x0018, 2, 0x0000, 0, 0), MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC = IOMUX_PAD(0x1C8, 0x0018, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO02__LPSPI6_SOUT = IOMUX_PAD(0x1C8, 0x0018, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO02__LPUART5_CTS_B = IOMUX_PAD(0x1C8, 0x0018, 5, 0x42C, 1, 0), - MX93_PAD_GPIO_IO02__LPI2C6_SDA = IOMUX_PAD(0x1C8, 0x0018, 6, 0x3F4, 0, 0), + MX93_PAD_GPIO_IO02__LPI2C6_SDA = IOMUX_PAD(0x1C8, 0x0018, 6 | IOMUX_CONFIG_SION, 0x3F4, 0, 0), MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x1C8, 0x0018, 7, 0x374, 0, 0),

MX93_PAD_GPIO_IO03__GPIO2_IO03 = IOMUX_PAD(0x1CC, 0x001C, 0, 0x0000, 0, 0), - MX93_PAD_GPIO_IO03__LPI2C4_SCL = IOMUX_PAD(0x1CC, 0x001C, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPI2C4_SCL = IOMUX_PAD(0x1CC, 0x001C, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC = IOMUX_PAD(0x1CC, 0x001C, 2, 0x0000, 0, 0), MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC = IOMUX_PAD(0x1CC, 0x001C, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO03__LPSPI6_SCK = IOMUX_PAD(0x1CC, 0x001C, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO03__LPUART5_RTS_B = IOMUX_PAD(0x1CC, 0x001C, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO03__LPI2C6_SCL = IOMUX_PAD(0x1CC, 0x001C, 6, 0x3F0, 0, 0), + MX93_PAD_GPIO_IO03__LPI2C6_SCL = IOMUX_PAD(0x1CC, 0x001C, 6 | IOMUX_CONFIG_SION, 0x3F0, 0, 0), MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x1CC, 0x001C, 7, 0x378, 0, 0),

MX93_PAD_GPIO_IO04__GPIO2_IO04 = IOMUX_PAD(0x1D0, 0x0020, 0, 0x0000, 0, 0), @@ -75,7 +75,7 @@ enum { MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 = IOMUX_PAD(0x1D0, 0x0020, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO04__LPSPI7_PCS0 = IOMUX_PAD(0x1D0, 0x0020, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO04__LPUART6_TX = IOMUX_PAD(0x1D0, 0x0020, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO04__LPI2C6_SDA = IOMUX_PAD(0x1D0, 0x0020, 6, 0x3F4, 1, 0), + MX93_PAD_GPIO_IO04__LPI2C6_SDA = IOMUX_PAD(0x1D0, 0x0020, 6 | IOMUX_CONFIG_SION, 0x3F4, 1, 0), MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x1D0, 0x0020, 7, 0x37C, 0, 0),

MX93_PAD_GPIO_IO05__GPIO2_IO05 = IOMUX_PAD(0x1D4, 0x0024, 0, 0x0000, 0, 0), @@ -84,7 +84,7 @@ enum { MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 = IOMUX_PAD(0x1D4, 0x0024, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO05__LPSPI7_SIN = IOMUX_PAD(0x1D4, 0x0024, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO05__LPUART6_RX = IOMUX_PAD(0x1D4, 0x0024, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO05__LPI2C6_SCL = IOMUX_PAD(0x1D4, 0x0024, 6, 0x3F0, 1, 0), + MX93_PAD_GPIO_IO05__LPI2C6_SCL = IOMUX_PAD(0x1D4, 0x0024, 6 | IOMUX_CONFIG_SION, 0x3F0, 1, 0), MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x1D4, 0x0024, 7, 0x380, 0, 0),

MX93_PAD_GPIO_IO06__GPIO2_IO06 = IOMUX_PAD(0x1D8, 0x0028, 0, 0x0000, 0, 0), @@ -93,7 +93,7 @@ enum { MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 = IOMUX_PAD(0x1D8, 0x0028, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO06__LPSPI7_SOUT = IOMUX_PAD(0x1D8, 0x0028, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO06__LPUART6_CTS_B = IOMUX_PAD(0x1D8, 0x0028, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO06__LPI2C7_SDA = IOMUX_PAD(0x1D8, 0x0028, 6, 0x3FC, 0, 0), + MX93_PAD_GPIO_IO06__LPI2C7_SDA = IOMUX_PAD(0x1D8, 0x0028, 6 | IOMUX_CONFIG_SION, 0x3FC, 0, 0), MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x1D8, 0x0028, 7, 0x384, 0, 0),

MX93_PAD_GPIO_IO07__GPIO2_IO07 = IOMUX_PAD(0x1DC, 0x002C, 0, 0x0000, 0, 0), @@ -102,7 +102,7 @@ enum { MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 = IOMUX_PAD(0x1DC, 0x002C, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO07__LPSPI7_SCK = IOMUX_PAD(0x1DC, 0x002C, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO07__LPUART6_RTS_B = IOMUX_PAD(0x1DC, 0x002C, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO07__LPI2C7_SCL = IOMUX_PAD(0x1DC, 0x002C, 6, 0x3F8, 0, 0), + MX93_PAD_GPIO_IO07__LPI2C7_SCL = IOMUX_PAD(0x1DC, 0x002C, 6 | IOMUX_CONFIG_SION, 0x3F8, 0, 0), MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x1DC, 0x002C, 7, 0x388, 0, 0),

MX93_PAD_GPIO_IO08__GPIO2_IO08 = IOMUX_PAD(0x1E0, 0x0030, 0, 0x0000, 0, 0), @@ -111,7 +111,7 @@ enum { MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 = IOMUX_PAD(0x1E0, 0x0030, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO08__TPM6_CH0 = IOMUX_PAD(0x1E0, 0x0030, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO08__LPUART7_TX = IOMUX_PAD(0x1E0, 0x0030, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO08__LPI2C7_SDA = IOMUX_PAD(0x1E0, 0x0030, 6, 0x3FC, 1, 0), + MX93_PAD_GPIO_IO08__LPI2C7_SDA = IOMUX_PAD(0x1E0, 0x0030, 6 | IOMUX_CONFIG_SION, 0x3FC, 1, 0), MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x1E0, 0x0030, 7, 0x38C, 0, 0),

MX93_PAD_GPIO_IO09__GPIO2_IO09 = IOMUX_PAD(0x1E4, 0x0034, 0, 0x0000, 0, 0), @@ -120,7 +120,7 @@ enum { MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 = IOMUX_PAD(0x1E4, 0x0034, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO09__TPM3_EXTCLK = IOMUX_PAD(0x1E4, 0x0034, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO09__LPUART7_RX = IOMUX_PAD(0x1E4, 0x0034, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO09__LPI2C7_SCL = IOMUX_PAD(0x1E4, 0x0034, 6, 0x3F8, 1, 0), + MX93_PAD_GPIO_IO09__LPI2C7_SCL = IOMUX_PAD(0x1E4, 0x0034, 6 | IOMUX_CONFIG_SION, 0x3F8, 1, 0), MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x1E4, 0x0034, 7, 0x390, 0, 0),

MX93_PAD_GPIO_IO10__GPIO2_IO10 = IOMUX_PAD(0x1E8, 0x0038, 0, 0x0000, 0, 0), @@ -129,7 +129,7 @@ enum { MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 = IOMUX_PAD(0x1E8, 0x0038, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO10__TPM4_EXTCLK = IOMUX_PAD(0x1E8, 0x0038, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO10__LPUART7_CTS_B = IOMUX_PAD(0x1E8, 0x0038, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO10__LPI2C8_SDA = IOMUX_PAD(0x1E8, 0x0038, 6, 0x404, 0, 0), + MX93_PAD_GPIO_IO10__LPI2C8_SDA = IOMUX_PAD(0x1E8, 0x0038, 6 | IOMUX_CONFIG_SION, 0x404, 0, 0), MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x1E8, 0x0038, 7, 0x394, 0, 0),

MX93_PAD_GPIO_IO11__GPIO2_IO11 = IOMUX_PAD(0x1EC, 0x003C, 0, 0x0000, 0, 0), @@ -138,7 +138,7 @@ enum { MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 = IOMUX_PAD(0x1EC, 0x003C, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO11__TPM5_EXTCLK = IOMUX_PAD(0x1EC, 0x003C, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO11__LPUART7_RTS_B = IOMUX_PAD(0x1EC, 0x003C, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO11__LPI2C8_SCL = IOMUX_PAD(0x1EC, 0x003C, 6, 0x400, 0, 0), + MX93_PAD_GPIO_IO11__LPI2C8_SCL = IOMUX_PAD(0x1EC, 0x003C, 6 | IOMUX_CONFIG_SION, 0x400, 0, 0), MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x1EC, 0x003C, 7, 0x398, 0, 0),

MX93_PAD_GPIO_IO12__GPIO2_IO12 = IOMUX_PAD(0x1F0, 0x0040, 0, 0x0000, 0, 0), @@ -147,7 +147,7 @@ enum { MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 = IOMUX_PAD(0x1F0, 0x0040, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO12__LPSPI8_PCS0 = IOMUX_PAD(0x1F0, 0x0040, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO12__LPUART8_TX = IOMUX_PAD(0x1F0, 0x0040, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO12__LPI2C8_SDA = IOMUX_PAD(0x1F0, 0x0040, 6, 0x404, 1, 0), + MX93_PAD_GPIO_IO12__LPI2C8_SDA = IOMUX_PAD(0x1F0, 0x0040, 6 | IOMUX_CONFIG_SION, 0x404, 1, 0), MX93_PAD_GPIO_IO12__SAI3_RX_SYNC = IOMUX_PAD(0x1F0, 0x0040, 7, 0x450, 0, 0),

MX93_PAD_GPIO_IO13__GPIO2_IO13 = IOMUX_PAD(0x1F4, 0x0044, 0, 0x0000, 0, 0), @@ -156,7 +156,7 @@ enum { MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 = IOMUX_PAD(0x1F4, 0x0044, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO13__LPSPI8_SIN = IOMUX_PAD(0x1F4, 0x0044, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO13__LPUART8_RX = IOMUX_PAD(0x1F4, 0x0044, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO13__LPI2C8_SCL = IOMUX_PAD(0x1F4, 0x0044, 6, 0x400, 1, 0), + MX93_PAD_GPIO_IO13__LPI2C8_SCL = IOMUX_PAD(0x1F4, 0x0044, 6 | IOMUX_CONFIG_SION, 0x400, 1, 0), MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x1F4, 0x0044, 7, 0x39C, 0, 0),

MX93_PAD_GPIO_IO14__GPIO2_IO14 = IOMUX_PAD(0x1F8, 0x0048, 0, 0x0000, 0, 0), @@ -237,7 +237,7 @@ enum { MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 = IOMUX_PAD(0x218, 0x0068, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO22__TPM5_CH1 = IOMUX_PAD(0x218, 0x0068, 4, 0x0000, 0, 0), MX93_PAD_GPIO_IO22__TPM6_EXTCLK = IOMUX_PAD(0x218, 0x0068, 5, 0x0000, 0, 0), - MX93_PAD_GPIO_IO22__LPI2C5_SDA = IOMUX_PAD(0x218, 0x0068, 6, 0x3EC, 1, 0), + MX93_PAD_GPIO_IO22__LPI2C5_SDA = IOMUX_PAD(0x218, 0x0068, 6 | IOMUX_CONFIG_SION, 0x3EC, 1, 0), MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x218, 0x0068, 7, 0x3B8, 0, 0),

MX93_PAD_GPIO_IO23__GPIO2_IO23 = IOMUX_PAD(0x21C, 0x006C, 0, 0x0000, 0, 0), @@ -245,7 +245,7 @@ enum { MX93_PAD_GPIO_IO23__SPDIF_OUT = IOMUX_PAD(0x21C, 0x006C, 2, 0x0000, 0, 0), MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 = IOMUX_PAD(0x21C, 0x006C, 3, 0x0000, 0, 0), MX93_PAD_GPIO_IO23__TPM6_CH1 = IOMUX_PAD(0x21C, 0x006C, 4, 0x0000, 0, 0), - MX93_PAD_GPIO_IO23__LPI2C5_SCL = IOMUX_PAD(0x21C, 0x006C, 6, 0x3E8, 1, 0), + MX93_PAD_GPIO_IO23__LPI2C5_SCL = IOMUX_PAD(0x21C, 0x006C, 6 | IOMUX_CONFIG_SION, 0x3E8, 1, 0), MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x21C, 0x006C, 7, 0x3BC, 0, 0),

MX93_PAD_GPIO_IO24__GPIO2_IO24 = IOMUX_PAD(0x220, 0x0070, 0, 0x0000, 0, 0), @@ -284,11 +284,11 @@ enum { MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x22C, 0x007C, 7, 0x3C8, 0, 0),

MX93_PAD_GPIO_IO28__GPIO2_IO28 = IOMUX_PAD(0x230, 0x0080, 0, 0x0000, 0, 0), - MX93_PAD_GPIO_IO28__LPI2C3_SDA = IOMUX_PAD(0x230, 0x0080, 1, 0x3E4, 1, 0), + MX93_PAD_GPIO_IO28__LPI2C3_SDA = IOMUX_PAD(0x230, 0x0080, 1 | IOMUX_CONFIG_SION, 0x3E4, 1, 0), MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 = IOMUX_PAD(0x230, 0x0080, 7, 0x0000, 0, 0),

MX93_PAD_GPIO_IO29__GPIO2_IO29 = IOMUX_PAD(0x234, 0x0084, 0, 0x0000, 0, 0), - MX93_PAD_GPIO_IO29__LPI2C3_SCL = IOMUX_PAD(0x234, 0x0084, 1, 0x3E0, 1, 0), + MX93_PAD_GPIO_IO29__LPI2C3_SCL = IOMUX_PAD(0x234, 0x0084, 1 | IOMUX_CONFIG_SION, 0x3E0, 1, 0), MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 = IOMUX_PAD(0x234, 0x0084, 7, 0x0000, 0, 0),

MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x238, 0x0088, 0, 0x0000, 0, 0),

From: Peng Fan peng.fan@nxp.com

Print ELE FW version in uboot log

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/soc.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 30361ccecd1..9ce4abf43e1 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -599,8 +599,36 @@ int print_cpuinfo(void) return 0; }

+void build_info(void) +{ + u32 fw_version, sha1, res, status; + int ret; + + printf("\nBuildInfo:\n"); + + ret = ele_get_fw_status(&status, &res); + if (ret) { + printf(" - ELE firmware status failed %d, 0x%x\n", ret, res); + } else if ((status & 0xff) == 1) { + ret = ele_get_fw_version(&fw_version, &sha1, &res); + if (ret) { + printf(" - ELE firmware version failed %d, 0x%x\n", ret, res); + } else { + printf(" - ELE firmware version %u.%u.%u-%x", + (fw_version & (0x00ff0000)) >> 16, + (fw_version & (0x0000ff00)) >> 8, + (fw_version & (0x000000ff)), sha1); + ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n"); + } + } else { + printf(" - ELE firmware not included\n"); + } + puts("\n"); +} + int arch_misc_init(void) { + build_info(); return 0; }

From: Ye Li ye.li@nxp.com

Improve the DDR bandwidth by changing to auto precharge, setting RD_TO_PRE to 0xe, REFREC_PB and REFTOREF_PB to 0x15b, set RD/WR_CNT, and improve RWT/WRT frequency

Also reduce debug message to Stage completion only.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- board/freescale/imx93_evk/lpddr4x_timing.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/board/freescale/imx93_evk/lpddr4x_timing.c b/board/freescale/imx93_evk/lpddr4x_timing.c index e34096fee1e..a355ca28c4f 100644 --- a/board/freescale/imx93_evk/lpddr4x_timing.c +++ b/board/freescale/imx93_evk/lpddr4x_timing.c @@ -21,21 +21,23 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x4e300114, 0x2 }, { 0x4e300260, 0x0 }, { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, { 0x4e300104, 0xaaee001b }, { 0x4e300108, 0x626ee273 }, - { 0x4e30010c, 0x5c18b }, + { 0x4e30010c, 0x5e18b }, { 0x4e300100, 0x25ab321b }, { 0x4e300160, 0x9002 }, { 0x4e30016c, 0x35f00000 }, { 0x4e300250, 0x2b }, - { 0x4e300254, 0x0 }, + { 0x4e300254, 0x015b015b }, { 0x4e30025c, 0x400 }, { 0x4e300300, 0x16291314 }, { 0x4e300304, 0x163110c }, { 0x4e300308, 0xa200e3c }, { 0x4e300170, 0x8b0b0608 }, - { 0x4e300124, 0x1c77071d }, - { 0x4e300f04, 0x80 }, + { 0x4e300124, 0x1c770000 }, + { 0x4e300800, 0x43930002 }, + { 0x4e300804, 0x1f1f1f1f }, };

/* PHY Initialize Configuration */ @@ -841,7 +843,7 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54004, 0x4 }, { 0x54006, 0x15 }, { 0x54008, 0x131f }, - { 0x54009, 0xff }, + { 0x54009, 0xc8 }, { 0x5400b, 0x4 }, { 0x5400c, 0x1 }, { 0x5400d, 0x100 }, @@ -879,7 +881,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54004, 0x4 }, { 0x54006, 0x15 }, { 0x54008, 0x61 }, - { 0x54009, 0xff }, + { 0x54009, 0xc8 }, { 0x5400b, 0x4 }, { 0x5400c, 0x1 }, { 0x5400d, 0x100 },

From: Peng Fan peng.fan@nxp.com

Get and print boot stage through ROM API in SPL

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/sys_proto.h | 7 +++++++ arch/arm/mach-imx/spl_imx_romapi.c | 22 +++++++++++++++++++++- 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index de241c2450e..8d8f580a5aa 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -180,6 +180,13 @@ enum boot_dev_type_e { BT_DEV_TYPE_INVALID = 0xFF };

+enum boot_stage_type { + BT_STAGE_PRIMARY = 0x6, + BT_STAGE_SECONDARY = 0x9, + BT_STAGE_RECOVERY = 0xa, + BT_STAGE_USB = 0x5, +}; + #define QUERY_ROM_VER 1 #define QUERY_BT_DEV 2 #define QUERY_PAGE_SZ 3 diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 4480d3c7115..3a26fcc91a8 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -378,15 +378,35 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { int ret; - u32 boot; + u32 boot, bstage;

ret = rom_api_query_boot_infor(QUERY_BT_DEV, &boot); + ret |= rom_api_query_boot_infor(QUERY_BT_STAGE, &bstage);

if (ret != ROM_API_OKAY) { puts("ROMAPI: failure at query_boot_info\n"); return -1; }

+ printf("Boot Stage: "); + + switch (bstage) { + case BT_STAGE_PRIMARY: + printf("Primary boot\n"); + break; + case BT_STAGE_SECONDARY: + printf("Secondary boot\n"); + break; + case BT_STAGE_RECOVERY: + printf("Recovery boot\n"); + break; + case BT_STAGE_USB: + printf("USB boot\n"); + break; + default: + printf("Unknown (0x%x)\n", bstage); + } + if (is_boot_from_stream_device(boot)) return spl_romapi_load_image_stream(spl_image, bootdev);

From: Jacky Bai ping.bai@nxp.com

Update the ddr init flow to support LPDDR3 and PLL bypass mode.

Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Jacky Bai ping.bai@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/ddr/imx/imx8ulp/ddr_init.c | 55 +++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 12 deletions(-)

diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c b/drivers/ddr/imx/imx8ulp/ddr_init.c index a5a9fd8d7c8..3f04f533825 100644 --- a/drivers/ddr/imx/imx8ulp/ddr_init.c +++ b/drivers/ddr/imx/imx8ulp/ddr_init.c @@ -31,6 +31,7 @@ #define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25)

#define DENALI_PHY_1624 (DDR_PHY_BASE_ADDR + 4 * 1624) +#define DENALI_PHY_1625 (DDR_PHY_BASE_ADDR + 4 * 1625) #define DENALI_PHY_1537 (DDR_PHY_BASE_ADDR + 4 * 1537) #define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8) #define PHY_FREQ_SEL_INDEX(X) ((X) << 16) @@ -82,25 +83,39 @@ int ddr_calibration(unsigned int fsp_table[3]) u32 int_status_init, phy_freq_req, phy_freq_type; u32 lock_0, lock_1, lock_2; u32 freq_chg_pt, freq_chg_cnt; + u32 is_lpddr4 = 0;

if (IS_ENABLED(CONFIG_IMX8ULP_DRAM_PHY_PLL_BYPASS)) { ddr_enable_pll_bypass(); freq_chg_cnt = 0; freq_chg_pt = 0; } else { - reg_val = readl(DENALI_CTL_250); - if (((reg_val >> 16) & 0x3) == 1) - freq_chg_cnt = 2; - else - freq_chg_cnt = 3; - - reg_val = readl(DENALI_PI_12); - if (reg_val == 0x3) { - freq_chg_pt = 1; - } else if (reg_val == 0x7) { - freq_chg_pt = 2; + reg_val = (readl(DENALI_CTL_00) >> 8) & 0xf; + if (reg_val == 0x7) { + /* LPDDR3 type */ + set_ddr_clk(fsp_table[1] >> 1); + freq_chg_cnt = 0; + freq_chg_pt = 0; + } else if (reg_val == 0xb) { + /* LPDDR4/4x type */ + is_lpddr4 = 1; + reg_val = readl(DENALI_CTL_250); + if (((reg_val >> 16) & 0x3) == 1) + freq_chg_cnt = 2; + else + freq_chg_cnt = 3; + + reg_val = readl(DENALI_PI_12); + if (reg_val == 0x3) { + freq_chg_pt = 1; + } else if (reg_val == 0x7) { + freq_chg_pt = 2; + } else { + printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val); + return -1; + } } else { - printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val); + printf("Incorrect DDR type configured!\r\n"); return -1; } } @@ -179,6 +194,22 @@ int ddr_calibration(unsigned int fsp_table[3]) }

debug("De-Skew PLL is locked and ready\n"); + + /* Change LPDDR4 FREQ1 to bypass mode if it is lower than 200MHz */ + if (is_lpddr4 && fsp_table[1] < 400) { + /* Set FREQ1 to bypass mode */ + reg_val = PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(0); + writel(reg_val, DENALI_PHY_1537); + + /* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */ + reg_val = readl(DENALI_PHY_1624) | 0x1; + writel(reg_val, DENALI_PHY_1624); + + /* DENALI_PHY_1625: bypass mode in PHY PLL */ + reg_val = readl(DENALI_PHY_1625) & ~0xf; + writel(reg_val, DENALI_PHY_1625); + } + return 0; }

From: Ye Li ye.li@nxp.com

Support DDR inline ECC feature for i.MX9 DDR driver. It uses top 1/8 DDR size for ECC data.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/ddr.h | 5 ++++ drivers/ddr/imx/imx9/Kconfig | 6 +++++ drivers/ddr/imx/imx9/ddr_init.c | 35 ++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index 10aaf486f29..45d1f69dac1 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -13,12 +13,17 @@ #define DDR_PHY_BASE 0x4E100000 #define DDRMIX_BLK_CTRL_BASE 0x4E010000

+#define REG_DDR_CS0_BNDS (DDR_CTL_BASE + 0x0) +#define REG_DDR_CS1_BNDS (DDR_CTL_BASE + 0x8) #define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104) #define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110) +#define REG_DDR_SDRAM_CFG2 (DDR_CTL_BASE + 0x114) #define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160) #define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24) #define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)

+#define REG_DDR_ERR_EN (DDR_CTL_BASE + 0x1000) + #define SRC_BASE_ADDR (0x44460000) #define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400) #define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20) diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index 123ad173cfc..95e15e5f800 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -17,6 +17,12 @@ config IMX9_DRAM_PM_COUNTER help Enable DDR controller performance monitor counter for reference events.

+config IMX9_DRAM_INLINE_ECC + bool "Enable DDR INLINE ECC feature" + default n + help + Select to enable DDR INLINE ECC feature + config SAVED_DRAM_TIMING_BASE hex "Define the base address for saved dram timing" help diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c index 651612611aa..ad298793929 100644 --- a/drivers/ddr/imx/imx9/ddr_init.c +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -196,6 +196,37 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) writel(tmp_t, REG_DDR_TIMING_CFG_4); }

+void update_inline_ecc_setting(void) +{ + u32 val, sa, ea; + + val = readl(REG_DDR_CS0_BNDS); + if (val != 0) { + sa = (val >> 16) & 0xff; + ea = val & 0xff; + + /* 1/8 size is used for inline ecc */ + ea = ea - ((ea + 1 - sa) >> 3); + writel((sa << 16) | ea, REG_DDR_CS0_BNDS); + } + + val = readl(REG_DDR_CS1_BNDS); + if (val != 0) { + sa = (val >> 16) & 0xff; + ea = val & 0xff; + + /* 1/8 size is used for inline ecc */ + ea = ea - ((ea + 1 - sa) >> 3); + writel((sa << 16) | ea, REG_DDR_CS1_BNDS); + } + + /* Enable Inline ECC */ + setbits_le32(REG_DDR_ERR_EN, BIT(31) | BIT(30)); + + /* Enable data initialization */ + setbits_le32(REG_DDR_SDRAM_CFG2, BIT(4)); +} + int ddr_init(struct dram_timing_info *dram_timing) { unsigned int initial_drate; @@ -232,6 +263,10 @@ int ddr_init(struct dram_timing_info *dram_timing)

update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1);

+#ifdef CONFIG_IMX9_DRAM_INLINE_ECC + update_inline_ecc_setting(); +#endif + #ifdef CONFIG_IMX9_DRAM_PM_COUNTER writel(0x200000, REG_DDR_DEBUG_19); #endif

From: Ye Li ye.li@nxp.com

The IS_ENABLED, which does not consider SPL build, should be replaced by CONFIG_IS_ENABLED. For the case that we only enable DM CLK for u-boot but not in SPL, the IS_ENABLED(CONFIG_CLK) still returns true, then cause clock failure.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/i2c/imx_lpi2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index 92c500327b4..ad9293c92e1 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -282,7 +282,7 @@ static int bus_i2c_set_bus_speed(struct udevice *bus, int speed) bool mode; int i;

- if (IS_ENABLED(CONFIG_CLK)) { + if (CONFIG_IS_ENABLED(CLK)) { clock_rate = clk_get_rate(&i2c_bus->per_clk); if (clock_rate <= 0) { dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate); @@ -462,7 +462,7 @@ static int imx_lpi2c_probe(struct udevice *bus) return ret; }

- if (IS_ENABLED(CONFIG_CLK)) { + if (CONFIG_IS_ENABLED(CLK)) { ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk); if (ret) { dev_err(bus, "Failed to get per clk\n");

From: Peng Fan peng.fan@nxp.com

Print tempeature for i.MX93

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/soc.c | 17 +++++++++++++++++ configs/imx93_11x11_evk_defconfig | 2 ++ configs/imx93_11x11_evk_ld_defconfig | 2 ++ 3 files changed, 21 insertions(+)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 9ce4abf43e1..e3e96e7bc9b 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -594,6 +594,23 @@ int print_cpuinfo(void) } printf("(%dC to %dC)", minc, maxc);

+#if defined(CONFIG_IMX_TMU) + struct udevice *udev; + int ret, temp; + + ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal", &udev); + if (!ret) { + ret = thermal_get_temp(udev, &temp); + + if (!ret) + printf(" at %dC", temp); + else + debug(" - invalid sensor data\n"); + } else { + debug(" - invalid sensor device\n"); + } +#endif + printf("\nReset cause: %s (0x%x)\n", get_reset_cause(&ssrs_ret), ssrs_ret);

return 0; diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 53ab0f61610..b5f43827400 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -111,6 +111,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y CONFIG_ULP_WATCHDOG=y CONFIG_WDT=y CONFIG_LZO=y diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig index 945dc504726..c785576fe92 100644 --- a/configs/imx93_11x11_evk_ld_defconfig +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -112,6 +112,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y CONFIG_ULP_WATCHDOG=y CONFIG_WDT=y CONFIG_LZO=y

From: Seb Fagard sebastien.fagard@nxp.com

parameter 'end address' must be inclusive of address range. And include cpu_func.h header file

Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Seb Fagard sebastien.fagard@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8/ahab.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 5a4d39cdaad..1ca7b7f2182 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -106,7 +106,7 @@ int authenticate_os_container(ulong addr) flush_dcache_range(s, e);

/* Find the memreg and set permission for seco pt */ - err = sc_rm_find_memreg(-1, &mr, s, e); + err = sc_rm_find_memreg(-1, &mr, s, e - 1); if (err) { printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err); ret = -ENOMEM;

From: Peng Fan peng.fan@nxp.com

The container may have image which conflicts with spl_get_load_buffer address, then there are processing failures. So use malloc instead of spl_get_load_buffer.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/parse-container.c | 37 +++++++++++++++++++---------- 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c index 5f87b6c202c..7d5c677814d 100644 --- a/arch/arm/mach-imx/parse-container.c +++ b/arch/arm/mach-imx/parse-container.c @@ -4,6 +4,7 @@ */

#include <common.h> +#include <stdlib.h> #include <errno.h> #include <log.h> #include <spl.h> @@ -68,25 +69,27 @@ static int read_auth_container(struct spl_image_info *spl_image, size = roundup(CONTAINER_HDR_ALIGNMENT, info->bl_len); sectors = size / info->bl_len;

- /* - * It will not override the ATF code, so safe to use it here, - * no need malloc - */ - container = (struct container_hdr *)spl_get_load_buffer(-size, size); + container = malloc(size); + if (!container) + return -ENOMEM;

debug("%s: container: %p sector: %lu sectors: %u\n", __func__, container, sector, sectors); - if (info->read(info, sector, sectors, container) != sectors) - return -EIO; + if (info->read(info, sector, sectors, container) != sectors) { + ret = -EIO; + goto end; + }

if (container->tag != 0x87 && container->version != 0x0) { printf("Wrong container header\n"); - return -ENOENT; + ret = -ENOENT; + goto end; }

if (!container->num_images) { printf("Wrong container, no image found\n"); - return -ENOENT; + ret = -ENOENT; + goto end; }

length = container->length_lsb + (container->length_msb << 8); @@ -96,13 +99,17 @@ static int read_auth_container(struct spl_image_info *spl_image, size = roundup(length, info->bl_len); sectors = size / info->bl_len;

- container = (struct container_hdr *)spl_get_load_buffer(-size, size); + free(container); + container = malloc(size); + if (!container) + return -ENOMEM;

debug("%s: container: %p sector: %lu sectors: %u\n", __func__, container, sector, sectors); - if (info->read(info, sector, sectors, container) != - sectors) - return -EIO; + if (info->read(info, sector, sectors, container) != sectors) { + ret = -EIO; + goto end; + } }

#ifdef CONFIG_AHAB_BOOT @@ -131,6 +138,10 @@ end_auth: #ifdef CONFIG_AHAB_BOOT ahab_auth_release(); #endif + +end: + free(container); + return ret; }