[U-Boot] [PATCH] arm: dts: amX/draX: fix DTC unit name warnings

15 Apr 2016

Fi all DTC warnings for TI  boards.
Signed-off-by: Heiko Schocher hs@denx.de
---
This warnings pop up with the DTC compiler:
$ /tmp/dtc/dtc -v
Version: DTC 1.4.1-gbeef80b8
This fixes the compile warnings for:
https://travis-ci.org/hsdenx/u-boot/jobs/123238798
see:
https://travis-ci.org/hsdenx/u-boot/jobs/123254198
arch/arm/dts/am335x-bone-common.dtsi |  12 +-
 arch/arm/dts/am335x-evm.dts          |  16 +-
 arch/arm/dts/am33xx-clocks.dtsi      |  90 ++++-----
 arch/arm/dts/am33xx.dtsi             |   4 +-
 arch/arm/dts/am4372.dtsi             |  10 +-
 arch/arm/dts/am437x-gp-evm.dts       |   4 +-
 arch/arm/dts/am437x-sk-evm.dts       |  12 +-
 arch/arm/dts/am43xx-clocks.dtsi      | 114 +++++------
 arch/arm/dts/am57xx-beagle-x15.dts   |  10 +-
 arch/arm/dts/dra7-evm.dts            |   2 +-
 arch/arm/dts/dra7.dtsi               |  16 +-
 arch/arm/dts/dra72-evm.dts           |   2 +-
 arch/arm/dts/dra74x.dtsi             |   2 +-
 arch/arm/dts/dra7xx-clocks.dtsi      | 370 +++++++++++++++++------------------
 arch/arm/dts/k2e-clocks.dtsi         |   8 +-
 arch/arm/dts/k2e-netcp.dtsi          |   6 +-
 arch/arm/dts/k2e.dtsi                |   2 +-
 arch/arm/dts/k2g-netcp.dtsi          |   6 +-
 arch/arm/dts/k2g.dtsi                |   4 +-
 arch/arm/dts/k2hk-clocks.dtsi        |  74 +++----
 arch/arm/dts/k2hk-netcp.dtsi         |   8 +-
 arch/arm/dts/k2hk.dtsi               |  16 +-
 arch/arm/dts/k2l-clocks.dtsi         |  44 ++---
 arch/arm/dts/k2l-netcp.dtsi          |   6 +-
 arch/arm/dts/k2l.dtsi                |   8 +-
 arch/arm/dts/keystone-clocks.dtsi    |  52 ++---
 arch/arm/dts/keystone.dtsi           |   6 +-
 27 files changed, 452 insertions(+), 452 deletions(-)

diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index fec7834..68d87ca 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -13,7 +13,7 @@
    	};
    };
-	memory {
+	memory@80000000 {
    	device_type = "memory";
    	reg = <0x80000000 0x10000000>; /* 256 MB */
    };
@@ -24,28 +24,28 @@
compatible = "gpio-leds";
-		led@2 {
+		led2 {
    		label = "beaglebone:green:heartbeat";
    		gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
    		linux,default-trigger = "heartbeat";
    		default-state = "off";
    	};
-		led@3 {
+		led3 {
    		label = "beaglebone:green:mmc0";
    		gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
    		linux,default-trigger = "mmc0";
    		default-state = "off";
    	};
-		led@4 {
+		led4 {
    		label = "beaglebone:green:usr2";
    		gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
    		linux,default-trigger = "cpu0";
    		default-state = "off";
    	};
-		led@5 {
+		led5 {
    		label = "beaglebone:green:usr3";
    		gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
    		linux,default-trigger = "mmc1";
@@ -53,7 +53,7 @@
    	};
    };
-	vmmcsd_fixed: fixedregulator@0 {
+	vmmcsd_fixed: fixedregulator {
    	compatible = "regulator-fixed";
    	regulator-name = "vmmcsd_fixed";
    	regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index c0bc2af..f9cdcdb 100644
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -25,12 +25,12 @@
    	};
    };
-	memory {
+	memory@80000000 {
    	device_type = "memory";
    	reg = <0x80000000 0x10000000>; /* 256 MB */
    };
-	vbat: fixedregulator@0 {
+	vbat: fixedregulator0 {
    	compatible = "regulator-fixed";
    	regulator-name = "vbat";
    	regulator-min-microvolt = <5000000>;
@@ -38,13 +38,13 @@
    	regulator-boot-on;
    };
-	lis3_reg: fixedregulator@1 {
+	lis3_reg: fixedregulator1 {
    	compatible = "regulator-fixed";
    	regulator-name = "lis3_reg";
    	regulator-boot-on;
    };
-	wlan_en_reg: fixedregulator@2 {
+	wlan_en_reg: fixedregulator2 {
    	compatible = "regulator-fixed";
    	regulator-name = "wlan-en-regulator";
    	regulator-min-microvolt = <1800000>;
@@ -58,7 +58,7 @@
    	enable-active-high;
    };
-	matrix_keypad: matrix_keypad@0 {
+	matrix_keypad: matrix_keypad {
    	compatible = "gpio-matrix-keypad";
    	debounce-delay-ms = <5>;
    	col-scan-delay-us = <2>;
@@ -78,20 +78,20 @@
    			0x0201006c>;	/* DOWN */
    };
-	gpio_keys: volume_keys@0 {
+	gpio_keys: volume_keys0 {
    	compatible = "gpio-keys";
    	#address-cells = <1>;
    	#size-cells = <0>;
    	autorepeat;
-		switch@9 {
+		switch9 {
    		label = "volume-up";
    		linux,code = <115>;
    		gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
    		gpio-key,wakeup;
    	};
-		switch@10 {
+		switch10 {
    		label = "volume-down";
    		linux,code = <114>;
    		gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi
index afb4b3a..7f65ba6 100644
--- a/arch/arm/dts/am33xx-clocks.dtsi
+++ b/arch/arm/dts/am33xx-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &scm_clocks {
-	sys_clkin_ck: sys_clkin_ck {
+	sys_clkin_ck: sys_clkin_ck@40{
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@@ -163,7 +163,7 @@
    	clock-frequency = <12000000>;
    };
-	dpll_core_ck: dpll_core_ck {
+	dpll_core_ck: dpll_core_ck@490 {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-core-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
@@ -176,7 +176,7 @@
    	clocks = <&dpll_core_ck>;
    };
-	dpll_core_m4_ck: dpll_core_m4_ck {
+	dpll_core_m4_ck: dpll_core_m4_ck@480 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -185,7 +185,7 @@
    	ti,index-starts-at-one;
    };
-	dpll_core_m5_ck: dpll_core_m5_ck {
+	dpll_core_m5_ck: dpll_core_m5_ck@484 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -194,7 +194,7 @@
    	ti,index-starts-at-one;
    };
-	dpll_core_m6_ck: dpll_core_m6_ck {
+	dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -203,14 +203,14 @@
    	ti,index-starts-at-one;
    };
-	dpll_mpu_ck: dpll_mpu_ck {
+	dpll_mpu_ck: dpll_mpu_ck@488 {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
    	reg = <0x0488>, <0x0420>, <0x042c>;
    };
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_mpu_ck>;
@@ -219,14 +219,14 @@
    	ti,index-starts-at-one;
    };
-	dpll_ddr_ck: dpll_ddr_ck {
+	dpll_ddr_ck: dpll_ddr_ck@494 {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-no-gate-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
    	reg = <0x0494>, <0x0434>, <0x0440>;
    };
-	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+	dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_ddr_ck>;
@@ -243,14 +243,14 @@
    	clock-div = <2>;
    };
-	dpll_disp_ck: dpll_disp_ck {
+	dpll_disp_ck: dpll_disp_ck@498 {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-no-gate-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
    	reg = <0x0498>, <0x0448>, <0x0454>;
    };
-	dpll_disp_m2_ck: dpll_disp_m2_ck {
+	dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_disp_ck>;
@@ -260,14 +260,14 @@
    	ti,set-rate-parent;
    };
-	dpll_per_ck: dpll_per_ck {
+	dpll_per_ck: dpll_per_ck@48c {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-no-gate-j-type-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
    	reg = <0x048c>, <0x0470>, <0x049c>;
    };
-	dpll_per_m2_ck: dpll_per_m2_ck {
+	dpll_per_m2_ck: dpll_per_m2_ck@4ac {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_per_ck>;
@@ -292,7 +292,7 @@
    	clock-div = <4>;
    };
-	cefuse_fck: cefuse_fck {
+	cefuse_fck: cefuse_fck@a20 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_clkin_ck>;
@@ -316,7 +316,7 @@
    	clock-div = <732>;
    };
-	clkdiv32k_ick: clkdiv32k_ick {
+	clkdiv32k_ick: clkdiv32k_ick@14c {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkdiv32k_ck>;
@@ -332,14 +332,14 @@
    	clock-div = <1>;
    };
-	pruss_ocp_gclk: pruss_ocp_gclk {
+	pruss_ocp_gclk: pruss_ocp_gclk@530 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
    	reg = <0x0530>;
    };
-	mmu_fck: mmu_fck {
+	mmu_fck: mmu_fck@914 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&dpll_core_m4_ck>;
@@ -347,56 +347,56 @@
    	reg = <0x0914>;
    };
-	timer1_fck: timer1_fck {
+	timer1_fck: timer1_fck@528 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
    	reg = <0x0528>;
    };
-	timer2_fck: timer2_fck {
+	timer2_fck: timer2_fck@508 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x0508>;
    };
-	timer3_fck: timer3_fck {
+	timer3_fck: timer3_fck@50c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x050c>;
    };
-	timer4_fck: timer4_fck {
+	timer4_fck: timer4_fck@510 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x0510>;
    };
-	timer5_fck: timer5_fck {
+	timer5_fck: timer5_fck@518 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x0518>;
    };
-	timer6_fck: timer6_fck {
+	timer6_fck: timer6_fck@51c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x051c>;
    };
-	timer7_fck: timer7_fck {
+	timer7_fck: timer7_fck@504 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x0504>;
    };
-	usbotg_fck: usbotg_fck {
+	usbotg_fck: usbotg_fck@47c {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&dpll_per_ck>;
@@ -412,7 +412,7 @@
    	clock-div = <2>;
    };
-	ieee5000_fck: ieee5000_fck {
+	ieee5000_fck: ieee5000_fck@e4 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&dpll_core_m4_div2_ck>;
@@ -420,7 +420,7 @@
    	reg = <0x00e4>;
    };
-	wdt1_fck: wdt1_fck {
+	wdt1_fck: wdt1_fck@538 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
@@ -483,21 +483,21 @@
    	clock-div = <2>;
    };
-	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
    	reg = <0x0520>;
    };
-	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@530 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
    	reg = <0x053c>;
    };
-	gpio0_dbclk: gpio0_dbclk {
+	gpio0_dbclk: gpio0_dbclk@408 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&gpio0_dbclk_mux_ck>;
@@ -505,7 +505,7 @@
    	reg = <0x0408>;
    };
-	gpio1_dbclk: gpio1_dbclk {
+	gpio1_dbclk: gpio1_dbclk@ac {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkdiv32k_ick>;
@@ -513,7 +513,7 @@
    	reg = <0x00ac>;
    };
-	gpio2_dbclk: gpio2_dbclk {
+	gpio2_dbclk: gpio2_dbclk@b0 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkdiv32k_ick>;
@@ -521,7 +521,7 @@
    	reg = <0x00b0>;
    };
-	gpio3_dbclk: gpio3_dbclk {
+	gpio3_dbclk: gpio3_dbclk@b4 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkdiv32k_ick>;
@@ -529,7 +529,7 @@
    	reg = <0x00b4>;
    };
-	lcd_gclk: lcd_gclk {
+	lcd_gclk: lcd_gclk@534 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
@@ -545,7 +545,7 @@
    	clock-div = <2>;
    };
-	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
@@ -553,7 +553,7 @@
    	reg = <0x052c>;
    };
-	gfx_fck_div_ck: gfx_fck_div_ck {
+	gfx_fck_div_ck: gfx_fck_div_ck@52c {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&gfx_fclk_clksel_ck>;
@@ -561,14 +561,14 @@
    	ti,max-div = <2>;
    };
-	sysclkout_pre_ck: sysclkout_pre_ck {
+	sysclkout_pre_ck: sysclkout_pre_ck@700 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
    	reg = <0x0700>;
    };
-	clkout2_div_ck: clkout2_div_ck {
+	clkout2_div_ck: clkout2_div_ck@700 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&sysclkout_pre_ck>;
@@ -577,7 +577,7 @@
    	reg = <0x0700>;
    };
-	dbg_sysclk_ck: dbg_sysclk_ck {
+	dbg_sysclk_ck: dbg_sysclk_ck@414 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_clkin_ck>;
@@ -585,7 +585,7 @@
    	reg = <0x0414>;
    };
-	dbg_clka_ck: dbg_clka_ck {
+	dbg_clka_ck: dbg_clka_ck@414 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&dpll_core_m4_ck>;
@@ -593,7 +593,7 @@
    	reg = <0x0414>;
    };
-	stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
+	stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
@@ -601,7 +601,7 @@
    	reg = <0x0414>;
    };
-	trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
+	trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
@@ -609,7 +609,7 @@
    	reg = <0x0414>;
    };
-	stm_clk_div_ck: stm_clk_div_ck {
+	stm_clk_div_ck: stm_clk_div_ck@414 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&stm_pmd_clock_mux_ck>;
@@ -619,7 +619,7 @@
    	ti,index-power-of-two;
    };
-	trace_clk_div_ck: trace_clk_div_ck {
+	trace_clk_div_ck: trace_clk_div_ck@414 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&trace_pmd_clk_mux_ck>;
@@ -629,7 +629,7 @@
    	ti,index-power-of-two;
    };
-	clkout2_ck: clkout2_ck {
+	clkout2_ck: clkout2_ck@700 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkout2_div_ck>;
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
index b26e21b..5b77389 100644
--- a/arch/arm/dts/am33xx.dtsi
+++ b/arch/arm/dts/am33xx.dtsi
@@ -746,12 +746,12 @@
    			status = "disabled";
    		};
-			cpsw_emac0: slave@4a100200 {
+			cpsw_emac0: slave_4a100200 {
    			/* Filled in by U-Boot */
    			mac-address = [ 00 00 00 00 00 00 ];
    		};
-			cpsw_emac1: slave@4a100300 {
+			cpsw_emac1: slave_4a100300 {
    			/* Filled in by U-Boot */
    			mac-address = [ 00 00 00 00 00 00 ];
    		};
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index c95d1d3..2611579 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -67,7 +67,7 @@
    	cache-level = <2>;
    };
-	ocp {
+	ocp@0 {
    	compatible = "ti,am4372-l3-noc", "simple-bus";
    	#address-cells = <1>;
    	#size-cells = <1>;
@@ -559,12 +559,12 @@
    			status = "disabled";
    		};
-			cpsw_emac0: slave@4a100200 {
+			cpsw_emac0: slave_4a100200 {
    			/* Filled in by U-Boot */
    			mac-address = [ 00 00 00 00 00 00 ];
    		};
-			cpsw_emac1: slave@4a100300 {
+			cpsw_emac1: slave_4a100300 {
    			/* Filled in by U-Boot */
    			mac-address = [ 00 00 00 00 00 00 ];
    		};
@@ -821,7 +821,7 @@
    		reg-names = "power";
    	};
-		ocp2scp0: ocp2scp@483a8000 {
+		ocp2scp0: ocp2scp_483a8000 {
    		compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
    		#address-cells = <1>;
    		#size-cells = <1>;
@@ -840,7 +840,7 @@
    		};
    	};
-		ocp2scp1: ocp2scp@483e8000 {
+		ocp2scp1: ocp2scp_483e8000 {
    		compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
    		#address-cells = <1>;
    		#size-cells = <1>;
diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts
index 8e23b96..3f74f22 100644
--- a/arch/arm/dts/am437x-gp-evm.dts
+++ b/arch/arm/dts/am437x-gp-evm.dts
@@ -64,7 +64,7 @@
    	default-brightness-level = <8>;
    };
-	matrix_keypad: matrix_keypad@0 {
+	matrix_keypad: matrix_keypad {
    	compatible = "gpio-matrix-keypad";
    	debounce-delay-ms = <5>;
    	col-scan-delay-us = <2>;
@@ -744,7 +744,7 @@
    pinctrl-0 = <&dss_pins>;
port {
-		dpi_out: endpoint@0 {
+		dpi_out: endpoint {
    		remote-endpoint = <&lcd_in>;
    		data-lines = <24>;
    	};
diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts
index 260edb9..2d92526 100644
--- a/arch/arm/dts/am437x-sk-evm.dts
+++ b/arch/arm/dts/am437x-sk-evm.dts
@@ -47,7 +47,7 @@
    		"Headphone Jack",       "HPROUT";
    };
-	matrix_keypad: matrix_keypad@0 {
+	matrix_keypad: matrix_keypad {
    	compatible = "gpio-matrix-keypad";
pinctrl-names = "default";
@@ -76,28 +76,28 @@
    	pinctrl-names = "default";
    	pinctrl-0 = <&leds_pins>;
-		led@0 {
+		led_0 {
    		label = "am437x-sk:red:heartbeat";
    		gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;	/* Bank 5, pin 0 */
    		linux,default-trigger = "heartbeat";
    		default-state = "off";
    	};
-		led@1 {
+		led_1 {
    		label = "am437x-sk:green:mmc1";
    		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;	/* Bank 5, pin 1 */
    		linux,default-trigger = "mmc0";
    		default-state = "off";
    	};
-		led@2 {
+		led_2 {
    		label = "am437x-sk:blue:cpu0";
    		gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;	/* Bank 5, pin 2 */
    		linux,default-trigger = "cpu0";
    		default-state = "off";
    	};
-		led@3 {
+		led_3 {
    		label = "am437x-sk:blue:usr3";
    		gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;	/* Bank 5, pin 3 */
    		default-state = "off";
@@ -667,7 +667,7 @@
    pinctrl-0 = <&dss_pins>;
port {
-		dpi_out: endpoint@0 {
+		dpi_out: endpoint {
    		remote-endpoint = <&lcd_in>;
    		data-lines = <24>;
    	};
diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi
index d0c0dfa..fdc8d2b 100644
--- a/arch/arm/dts/am43xx-clocks.dtsi
+++ b/arch/arm/dts/am43xx-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &scm_clocks {
-	sys_clkin_ck: sys_clkin_ck {
+	sys_clkin_ck: sys_clkin_ck@40 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
@@ -16,7 +16,7 @@
    	reg = <0x0040>;
    };
-	crystal_freq_sel_ck: crystal_freq_sel_ck {
+	crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@@ -104,7 +104,7 @@
    	clock-div = <1>;
    };
-	ehrpwm0_tbclk: ehrpwm0_tbclk {
+	ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&l4ls_gclk>;
@@ -112,7 +112,7 @@
    	reg = <0x0664>;
    };
-	ehrpwm1_tbclk: ehrpwm1_tbclk {
+	ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&l4ls_gclk>;
@@ -120,7 +120,7 @@
    	reg = <0x0664>;
    };
-	ehrpwm2_tbclk: ehrpwm2_tbclk {
+	ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&l4ls_gclk>;
@@ -128,7 +128,7 @@
    	reg = <0x0664>;
    };
-	ehrpwm3_tbclk: ehrpwm3_tbclk {
+	ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&l4ls_gclk>;
@@ -136,7 +136,7 @@
    	reg = <0x0664>;
    };
-	ehrpwm4_tbclk: ehrpwm4_tbclk {
+	ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&l4ls_gclk>;
@@ -144,7 +144,7 @@
    	reg = <0x0664>;
    };
-	ehrpwm5_tbclk: ehrpwm5_tbclk {
+	ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&l4ls_gclk>;
@@ -195,7 +195,7 @@
    	clock-frequency = <26000000>;
    };
-	dpll_core_ck: dpll_core_ck {
+	dpll_core_ck: dpll_core_ck@2d20 {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-core-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
@@ -208,7 +208,7 @@
    	clocks = <&dpll_core_ck>;
    };
-	dpll_core_m4_ck: dpll_core_m4_ck {
+	dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -219,7 +219,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_core_m5_ck: dpll_core_m5_ck {
+	dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -230,7 +230,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_core_m6_ck: dpll_core_m6_ck {
+	dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -241,14 +241,14 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_mpu_ck: dpll_mpu_ck {
+	dpll_mpu_ck: dpll_mpu_ck@2d60 {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
    	reg = <0x2d60>, <0x2d64>, <0x2d6c>;
    };
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_mpu_ck>;
@@ -259,14 +259,14 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_ddr_ck: dpll_ddr_ck {
+	dpll_ddr_ck: dpll_ddr_ck@2da0 {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
    	reg = <0x2da0>, <0x2da4>, <0x2dac>;
    };
-	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+	dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_ddr_ck>;
@@ -277,14 +277,14 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_disp_ck: dpll_disp_ck {
+	dpll_disp_ck: dpll_disp_ck@2e20 {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
    	reg = <0x2e20>, <0x2e24>, <0x2e2c>;
    };
-	dpll_disp_m2_ck: dpll_disp_m2_ck {
+	dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_disp_ck>;
@@ -296,14 +296,14 @@
    	ti,set-rate-parent;
    };
-	dpll_per_ck: dpll_per_ck {
+	dpll_per_ck: dpll_per_ck@2de0 {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-j-type-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
    	reg = <0x2de0>, <0x2de4>, <0x2dec>;
    };
-	dpll_per_m2_ck: dpll_per_m2_ck {
+	dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_per_ck>;
@@ -346,7 +346,7 @@
    	clock-div = <732>;
    };
-	clkdiv32k_ick: clkdiv32k_ick {
+	clkdiv32k_ick: clkdiv32k_ick@2a38 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkdiv32k_ck>;
@@ -362,7 +362,7 @@
    	clock-div = <1>;
    };
-	pruss_ocp_gclk: pruss_ocp_gclk {
+	pruss_ocp_gclk: pruss_ocp_gclk@4248 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
@@ -375,56 +375,56 @@
    	clock-frequency = <32768>;
    };
-	timer1_fck: timer1_fck {
+	timer1_fck: timer1_fck@4200 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
    	reg = <0x4200>;
    };
-	timer2_fck: timer2_fck {
+	timer2_fck: timer2_fck@4204 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x4204>;
    };
-	timer3_fck: timer3_fck {
+	timer3_fck: timer3_fck@4208 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x4208>;
    };
-	timer4_fck: timer4_fck {
+	timer4_fck: timer4_fck@420c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x420c>;
    };
-	timer5_fck: timer5_fck {
+	timer5_fck: timer5_fck@4210 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x4210>;
    };
-	timer6_fck: timer6_fck {
+	timer6_fck: timer6_fck@4214 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x4214>;
    };
-	timer7_fck: timer7_fck {
+	timer7_fck: timer7_fck@4218 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
    	reg = <0x4218>;
    };
-	wdt1_fck: wdt1_fck {
+	wdt1_fck: wdt1_fck@422c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
@@ -479,7 +479,7 @@
    	clock-div = <2>;
    };
-	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
@@ -492,14 +492,14 @@
    	clock-frequency = <32768>;
    };
-	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
    	reg = <0x4240>;
    };
-	gpio0_dbclk: gpio0_dbclk {
+	gpio0_dbclk: gpio0_dbclk@2b68 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&gpio0_dbclk_mux_ck>;
@@ -507,7 +507,7 @@
    	reg = <0x2b68>;
    };
-	gpio1_dbclk: gpio1_dbclk {
+	gpio1_dbclk: gpio1_dbclk@8c78 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkdiv32k_ick>;
@@ -515,7 +515,7 @@
    	reg = <0x8c78>;
    };
-	gpio2_dbclk: gpio2_dbclk {
+	gpio2_dbclk: gpio2_dbclk@8c80 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkdiv32k_ick>;
@@ -523,7 +523,7 @@
    	reg = <0x8c80>;
    };
-	gpio3_dbclk: gpio3_dbclk {
+	gpio3_dbclk: gpio3_dbclk@8c88 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkdiv32k_ick>;
@@ -531,7 +531,7 @@
    	reg = <0x8c88>;
    };
-	gpio4_dbclk: gpio4_dbclk {
+	gpio4_dbclk: gpio4_dbclk@8c90 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkdiv32k_ick>;
@@ -539,7 +539,7 @@
    	reg = <0x8c90>;
    };
-	gpio5_dbclk: gpio5_dbclk {
+	gpio5_dbclk: gpio5_dbclk@8c98 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkdiv32k_ick>;
@@ -555,7 +555,7 @@
    	clock-div = <2>;
    };
-	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
@@ -563,7 +563,7 @@
    	reg = <0x423c>;
    };
-	gfx_fck_div_ck: gfx_fck_div_ck {
+	gfx_fck_div_ck: gfx_fck_div_ck@423c {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&gfx_fclk_clksel_ck>;
@@ -571,7 +571,7 @@
    	ti,max-div = <2>;
    };
-	disp_clk: disp_clk {
+	disp_clk: disp_clk@4244 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
@@ -579,14 +579,14 @@
    	ti,set-rate-parent;
    };
-	dpll_extdev_ck: dpll_extdev_ck {
+	dpll_extdev_ck: dpll_extdev_ck@2e60 {
    	#clock-cells = <0>;
    	compatible = "ti,am3-dpll-clock";
    	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
    	reg = <0x2e60>, <0x2e64>, <0x2e6c>;
    };
-	dpll_extdev_m2_ck: dpll_extdev_m2_ck {
+	dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_extdev_ck>;
@@ -597,14 +597,14 @@
    	ti,invert-autoidle-bit;
    };
-	mux_synctimer32k_ck: mux_synctimer32k_ck {
+	mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
    	reg = <0x4230>;
    };
-	synctimer_32kclk: synctimer_32kclk {
+	synctimer_32kclk: synctimer_32kclk@2a30 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&mux_synctimer32k_ck>;
@@ -612,28 +612,28 @@
    	reg = <0x2a30>;
    };
-	timer8_fck: timer8_fck {
+	timer8_fck: timer8_fck@421c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
    	reg = <0x421c>;
    };
-	timer9_fck: timer9_fck {
+	timer9_fck: timer9_fck@4220 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
    	reg = <0x4220>;
    };
-	timer10_fck: timer10_fck {
+	timer10_fck: timer10_fck@4224 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
    	reg = <0x4224>;
    };
-	timer11_fck: timer11_fck {
+	timer11_fck: timer11_fck@4228 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
@@ -662,7 +662,7 @@
    	clocks = <&dpll_ddr_ck>;
    };
-	dpll_ddr_m4_ck: dpll_ddr_m4_ck {
+	dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_ddr_x2_ck>;
@@ -673,7 +673,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+	dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
    	#clock-cells = <0>;
    	compatible = "ti,fixed-factor-clock";
    	clocks = <&dpll_per_ck>;
@@ -684,7 +684,7 @@
    	ti,invert-autoidle-bit;
    };
-	dll_aging_clk_div: dll_aging_clk_div {
+	dll_aging_clk_div: dll_aging_clk_div@4250 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&sys_clkin_ck>;
@@ -716,14 +716,14 @@
    	clock-div = <2>;
    };
-	usbphy_32khz_clkmux: usbphy_32khz_clkmux {
+	usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
    	reg = <0x4260>;
    };
-	usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
+	usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&usbphy_32khz_clkmux>;
@@ -731,7 +731,7 @@
    	reg = <0x2a40>;
    };
-	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&usbphy_32khz_clkmux>;
@@ -739,7 +739,7 @@
    	reg = <0x2a48>;
    };
-	usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
+	usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&dpll_per_clkdcoldo>;
@@ -747,7 +747,7 @@
    	reg = <0x8a60>;
    };
-	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&dpll_per_clkdcoldo>;
diff --git a/arch/arm/dts/am57xx-beagle-x15.dts b/arch/arm/dts/am57xx-beagle-x15.dts
index e424562..981c8eb 100644
--- a/arch/arm/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/dts/am57xx-beagle-x15.dts
@@ -26,7 +26,7 @@
    	display0 = &hdmi0;
    };
-	memory {
+	memory@80000000 {
    	device_type = "memory";
    	reg = <0x80000000 0x80000000>;
    };
@@ -57,28 +57,28 @@
    	pinctrl-names = "default";
    	pinctrl-0 = <&leds_pins_default>;
-		led@0 {
+		led_0 {
    		label = "beagle-x15:usr0";
    		gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
    		linux,default-trigger = "heartbeat";
    		default-state = "off";
    	};
-		led@1 {
+		led_1 {
    		label = "beagle-x15:usr1";
    		gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
    		linux,default-trigger = "cpu0";
    		default-state = "off";
    	};
-		led@2 {
+		led_2 {
    		label = "beagle-x15:usr2";
    		gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
    		linux,default-trigger = "mmc0";
    		default-state = "off";
    	};
-		led@3 {
+		led_3 {
    		label = "beagle-x15:usr3";
    		gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
    		linux,default-trigger = "ide-disk";
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index 242fd53..bbf16b8 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -19,7 +19,7 @@
    	tick-timer = &timer2;
    };
-	memory {
+	memory@80000000 {
    	device_type = "memory";
    	reg = <0x80000000 0x60000000>; /* 1536 MB */
    };
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index e7fecf7..59e07d2 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -92,7 +92,7 @@
     * the moment, just use a fake OCP bus entry to represent the whole bus
     * hierarchy.
     */
-	ocp {
+	ocp@0 {
    	compatible = "ti,dra7-l3-noc", "simple-bus";
    	#address-cells = <1>;
    	#size-cells = <1>;
@@ -122,7 +122,7 @@
    				#address-cells = <1>;
    				#size-cells = <1>;
-					pbias_regulator: pbias_regulator {
+					pbias_regulator: pbias_regulator@e00 {
    					compatible = "ti,pbias-omap";
    					reg = <0xe00 0x4>;
    					syscon = <&scm_conf>;
@@ -917,7 +917,7 @@
    		status = "disabled";
    	};
-		abb_mpu: regulator-abb-mpu {
+		abb_mpu: regulator-abb-mpu@0 {
    		compatible = "ti,abb-v3";
    		regulator-name = "abb_mpu";
    		#address-cells = <0>;
@@ -950,7 +950,7 @@
    		>;
    	};
-		abb_ivahd: regulator-abb-ivahd {
+		abb_ivahd: regulator-abb-ivahd@0 {
    		compatible = "ti,abb-v3";
    		regulator-name = "abb_ivahd";
    		#address-cells = <0>;
@@ -983,7 +983,7 @@
    		>;
    	};
-		abb_dspeve: regulator-abb-dspeve {
+		abb_dspeve: regulator-abb-dspeve@0 {
    		compatible = "ti,abb-v3";
    		regulator-name = "abb_dspeve";
    		#address-cells = <0>;
@@ -1016,7 +1016,7 @@
    		>;
    	};
-		abb_gpu: regulator-abb-gpu {
+		abb_gpu: regulator-abb-gpu@0 {
    		compatible = "ti,abb-v3";
    		regulator-name = "abb_gpu";
    		#address-cells = <0>;
@@ -1452,12 +1452,12 @@
    			reg = <0x48485000 0x100>;
    		};
-			cpsw_emac0: slave@48480200 {
+			cpsw_emac0: slave_48480200 {
    			/* Filled in by U-Boot */
    			mac-address = [ 00 00 00 00 00 00 ];
    		};
-			cpsw_emac1: slave@48480300 {
+			cpsw_emac1: slave_48480300 {
    			/* Filled in by U-Boot */
    			mac-address = [ 00 00 00 00 00 00 ];
    		};
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index fc2d167..59276aa 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -19,7 +19,7 @@
    	tick-timer = &timer2;
    };
-	memory {
+	memory@80000000 {
    	device_type = "memory";
    	reg = <0x80000000 0x40000000>; /* 1024 MB */
    };
diff --git a/arch/arm/dts/dra74x.dtsi b/arch/arm/dts/dra74x.dtsi
index fa995d0..b5d91e5 100644
--- a/arch/arm/dts/dra74x.dtsi
+++ b/arch/arm/dts/dra74x.dtsi
@@ -51,7 +51,7 @@
    		     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
    };
-	ocp {
+	ocp@0 {
    	omap_dwc3_4: omap_dwc3_4@48940000 {
    		compatible = "ti,dwc3";
    		ti,hwmods = "usb_otg_ss4";
diff --git a/arch/arm/dts/dra7xx-clocks.dtsi b/arch/arm/dts/dra7xx-clocks.dtsi
index 357bede..49890d2 100644
--- a/arch/arm/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/dts/dra7xx-clocks.dtsi
@@ -188,7 +188,7 @@
    	clock-frequency = <0>;
    };
-	dpll_abe_ck: dpll_abe_ck {
+	dpll_abe_ck: dpll_abe_ck@1e0 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-m4xen-clock";
    	clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
@@ -201,7 +201,7 @@
    	clocks = <&dpll_abe_ck>;
    };
-	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_abe_x2_ck>;
@@ -212,7 +212,7 @@
    	ti,invert-autoidle-bit;
    };
-	abe_clk: abe_clk {
+	abe_clk: abe_clk@108 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_abe_m2x2_ck>;
@@ -221,7 +221,7 @@
    	ti,index-power-of-two;
    };
-	dpll_abe_m2_ck: dpll_abe_m2_ck {
+	dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_abe_ck>;
@@ -232,7 +232,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_abe_x2_ck>;
@@ -243,7 +243,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_core_byp_mux: dpll_core_byp_mux {
+	dpll_core_byp_mux: dpll_core_byp_mux@12c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -251,7 +251,7 @@
    	reg = <0x012c>;
    };
-	dpll_core_ck: dpll_core_ck {
+	dpll_core_ck: dpll_core_ck@120 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-core-clock";
    	clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
@@ -264,7 +264,7 @@
    	clocks = <&dpll_core_ck>;
    };
-	dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+	dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -283,14 +283,14 @@
    	clock-div = <1>;
    };
-	dpll_mpu_ck: dpll_mpu_ck {
+	dpll_mpu_ck: dpll_mpu_ck@160 {
    	#clock-cells = <0>;
    	compatible = "ti,omap5-mpu-dpll-clock";
    	clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
    	reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
    };
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_mpu_ck>;
@@ -317,7 +317,7 @@
    	clock-div = <1>;
    };
-	dpll_dsp_byp_mux: dpll_dsp_byp_mux {
+	dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
@@ -325,14 +325,14 @@
    	reg = <0x0240>;
    };
-	dpll_dsp_ck: dpll_dsp_ck {
+	dpll_dsp_ck: dpll_dsp_ck@234 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-clock";
    	clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
    	reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
    };
-	dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+	dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_dsp_ck>;
@@ -351,7 +351,7 @@
    	clock-div = <1>;
    };
-	dpll_iva_byp_mux: dpll_iva_byp_mux {
+	dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
@@ -359,14 +359,14 @@
    	reg = <0x01ac>;
    };
-	dpll_iva_ck: dpll_iva_ck {
+	dpll_iva_ck: dpll_iva_ck@1a0 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-clock";
    	clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
    	reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
    };
-	dpll_iva_m2_ck: dpll_iva_m2_ck {
+	dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_iva_ck>;
@@ -385,7 +385,7 @@
    	clock-div = <1>;
    };
-	dpll_gpu_byp_mux: dpll_gpu_byp_mux {
+	dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -393,14 +393,14 @@
    	reg = <0x02e4>;
    };
-	dpll_gpu_ck: dpll_gpu_ck {
+	dpll_gpu_ck: dpll_gpu_ck@2d8 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-clock";
    	clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
    	reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
    };
-	dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+	dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_gpu_ck>;
@@ -411,7 +411,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_core_m2_ck: dpll_core_m2_ck {
+	dpll_core_m2_ck: dpll_core_m2_ck@130 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_ck>;
@@ -430,7 +430,7 @@
    	clock-div = <1>;
    };
-	dpll_ddr_byp_mux: dpll_ddr_byp_mux {
+	dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -438,14 +438,14 @@
    	reg = <0x021c>;
    };
-	dpll_ddr_ck: dpll_ddr_ck {
+	dpll_ddr_ck: dpll_ddr_ck@210 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-clock";
    	clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
    	reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
    };
-	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+	dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_ddr_ck>;
@@ -456,7 +456,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_gmac_byp_mux: dpll_gmac_byp_mux {
+	dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -464,14 +464,14 @@
    	reg = <0x02b4>;
    };
-	dpll_gmac_ck: dpll_gmac_ck {
+	dpll_gmac_ck: dpll_gmac_ck@2a8 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-clock";
    	clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
    	reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
    };
-	dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+	dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_gmac_ck>;
@@ -530,7 +530,7 @@
    	clock-div = <1>;
    };
-	dpll_eve_byp_mux: dpll_eve_byp_mux {
+	dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
@@ -538,14 +538,14 @@
    	reg = <0x0290>;
    };
-	dpll_eve_ck: dpll_eve_ck {
+	dpll_eve_ck: dpll_eve_ck@284 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-clock";
    	clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
    	reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
    };
-	dpll_eve_m2_ck: dpll_eve_m2_ck {
+	dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_eve_ck>;
@@ -564,7 +564,7 @@
    	clock-div = <1>;
    };
-	dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+	dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -575,7 +575,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+	dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -586,7 +586,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+	dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -597,7 +597,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+	dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -608,7 +608,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+	dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_core_x2_ck>;
@@ -625,7 +625,7 @@
    	clocks = <&dpll_ddr_ck>;
    };
-	dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+	dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_ddr_x2_ck>;
@@ -642,7 +642,7 @@
    	clocks = <&dpll_dsp_ck>;
    };
-	dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+	dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_dsp_x2_ck>;
@@ -659,7 +659,7 @@
    	clocks = <&dpll_gmac_ck>;
    };
-	dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+	dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_gmac_x2_ck>;
@@ -670,7 +670,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+	dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_gmac_x2_ck>;
@@ -681,7 +681,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+	dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_gmac_x2_ck>;
@@ -692,7 +692,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+	dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_gmac_x2_ck>;
@@ -727,7 +727,7 @@
    	clock-div = <1>;
    };
-	l3_iclk_div: l3_iclk_div {
+	l3_iclk_div: l3_iclk_div@100 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	ti,max-div = <2>;
@@ -777,7 +777,7 @@
    	clock-div = <1>;
    };
-	ipu1_gfclk_mux: ipu1_gfclk_mux {
+	ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
@@ -785,7 +785,7 @@
    	reg = <0x0520>;
    };
-	mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+	mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -793,7 +793,7 @@
    	reg = <0x0550>;
    };
-	mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+	mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -801,7 +801,7 @@
    	reg = <0x0550>;
    };
-	mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+	mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -809,7 +809,7 @@
    	reg = <0x0550>;
    };
-	timer5_gfclk_mux: timer5_gfclk_mux {
+	timer5_gfclk_mux: timer5_gfclk_mux@558 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -817,7 +817,7 @@
    	reg = <0x0558>;
    };
-	timer6_gfclk_mux: timer6_gfclk_mux {
+	timer6_gfclk_mux: timer6_gfclk_mux@560 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -825,7 +825,7 @@
    	reg = <0x0560>;
    };
-	timer7_gfclk_mux: timer7_gfclk_mux {
+	timer7_gfclk_mux: timer7_gfclk_mux@568 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -833,7 +833,7 @@
    	reg = <0x0568>;
    };
-	timer8_gfclk_mux: timer8_gfclk_mux {
+	timer8_gfclk_mux: timer8_gfclk_mux@570 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -841,7 +841,7 @@
    	reg = <0x0570>;
    };
-	uart6_gfclk_mux: uart6_gfclk_mux {
+	uart6_gfclk_mux: uart6_gfclk_mux@580 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -856,7 +856,7 @@
    };
 };
 &prm_clocks {
-	sys_clkin1: sys_clkin1 {
+	sys_clkin1: sys_clkin1@110 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -864,28 +864,28 @@
    	ti,index-starts-at-one;
    };
-	abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+	abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&sys_clkin2>;
    	reg = <0x0118>;
    };
-	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
    	reg = <0x0114>;
    };
-	abe_dpll_clk_mux: abe_dpll_clk_mux {
+	abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
    	reg = <0x010c>;
    };
-	abe_24m_fclk: abe_24m_fclk {
+	abe_24m_fclk: abe_24m_fclk@11c {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_abe_m2x2_ck>;
@@ -893,7 +893,7 @@
    	ti,dividers = <8>, <16>;
    };
-	aess_fclk: aess_fclk {
+	aess_fclk: aess_fclk@178 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&abe_clk>;
@@ -901,7 +901,7 @@
    	ti,max-div = <2>;
    };
-	abe_giclk_div: abe_giclk_div {
+	abe_giclk_div: abe_giclk_div@174 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&aess_fclk>;
@@ -909,7 +909,7 @@
    	ti,max-div = <2>;
    };
-	abe_lp_clk_div: abe_lp_clk_div {
+	abe_lp_clk_div: abe_lp_clk_div@1d8 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_abe_m2x2_ck>;
@@ -917,7 +917,7 @@
    	ti,dividers = <16>, <32>;
    };
-	abe_sys_clk_div: abe_sys_clk_div {
+	abe_sys_clk_div: abe_sys_clk_div@120 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&sys_clkin1>;
@@ -925,14 +925,14 @@
    	ti,max-div = <2>;
    };
-	adc_gfclk_mux: adc_gfclk_mux {
+	adc_gfclk_mux: adc_gfclk_mux@1dc {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
    	reg = <0x01dc>;
    };
-	sys_clk1_dclk_div: sys_clk1_dclk_div {
+	sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&sys_clkin1>;
@@ -941,7 +941,7 @@
    	ti,index-power-of-two;
    };
-	sys_clk2_dclk_div: sys_clk2_dclk_div {
+	sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&sys_clkin2>;
@@ -950,7 +950,7 @@
    	ti,index-power-of-two;
    };
-	per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+	per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_abe_m2_ck>;
@@ -959,7 +959,7 @@
    	ti,index-power-of-two;
    };
-	dsp_gclk_div: dsp_gclk_div {
+	dsp_gclk_div: dsp_gclk_div@18c {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_dsp_m2_ck>;
@@ -968,7 +968,7 @@
    	ti,index-power-of-two;
    };
-	gpu_dclk: gpu_dclk {
+	gpu_dclk: gpu_dclk@1a0 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_gpu_m2_ck>;
@@ -977,7 +977,7 @@
    	ti,index-power-of-two;
    };
-	emif_phy_dclk_div: emif_phy_dclk_div {
+	emif_phy_dclk_div: emif_phy_dclk_div@190 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_ddr_m2_ck>;
@@ -986,7 +986,7 @@
    	ti,index-power-of-two;
    };
-	gmac_250m_dclk_div: gmac_250m_dclk_div {
+	gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_gmac_m2_ck>;
@@ -995,7 +995,7 @@
    	ti,index-power-of-two;
    };
-	l3init_480m_dclk_div: l3init_480m_dclk_div {
+	l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_usb_m2_ck>;
@@ -1004,7 +1004,7 @@
    	ti,index-power-of-two;
    };
-	usb_otg_dclk_div: usb_otg_dclk_div {
+	usb_otg_dclk_div: usb_otg_dclk_div@184 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&usb_otg_clkin_ck>;
@@ -1013,7 +1013,7 @@
    	ti,index-power-of-two;
    };
-	sata_dclk_div: sata_dclk_div {
+	sata_dclk_div: sata_dclk_div@1c0 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&sys_clkin1>;
@@ -1022,7 +1022,7 @@
    	ti,index-power-of-two;
    };
-	pcie2_dclk_div: pcie2_dclk_div {
+	pcie2_dclk_div: pcie2_dclk_div@1b8 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_pcie_ref_m2_ck>;
@@ -1031,7 +1031,7 @@
    	ti,index-power-of-two;
    };
-	pcie_dclk_div: pcie_dclk_div {
+	pcie_dclk_div: pcie_dclk_div@1b4 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&apll_pcie_m2_ck>;
@@ -1040,7 +1040,7 @@
    	ti,index-power-of-two;
    };
-	emu_dclk_div: emu_dclk_div {
+	emu_dclk_div: emu_dclk_div@194 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&sys_clkin1>;
@@ -1049,7 +1049,7 @@
    	ti,index-power-of-two;
    };
-	secure_32k_dclk_div: secure_32k_dclk_div {
+	secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&secure_32k_clk_src_ck>;
@@ -1058,21 +1058,21 @@
    	ti,index-power-of-two;
    };
-	clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+	clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
    	reg = <0x0158>;
    };
-	clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+	clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
    	reg = <0x015c>;
    };
-	clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+	clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
@@ -1087,21 +1087,21 @@
    	clock-div = <2>;
    };
-	eve_clk: eve_clk {
+	eve_clk: eve_clk@180 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
    	reg = <0x0180>;
    };
-	hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+	hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&sys_clkin2>;
    	reg = <0x0164>;
    };
-	mlb_clk: mlb_clk {
+	mlb_clk: mlb_clk@134 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&mlb_clkin_ck>;
@@ -1110,7 +1110,7 @@
    	ti,index-power-of-two;
    };
-	mlbp_clk: mlbp_clk {
+	mlbp_clk: mlbp_clk@130 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&mlbp_clkin_ck>;
@@ -1119,7 +1119,7 @@
    	ti,index-power-of-two;
    };
-	per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+	per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_abe_m2_ck>;
@@ -1128,7 +1128,7 @@
    	ti,index-power-of-two;
    };
-	timer_sys_clk_div: timer_sys_clk_div {
+	timer_sys_clk_div: timer_sys_clk_div@144 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&sys_clkin1>;
@@ -1136,28 +1136,28 @@
    	ti,max-div = <2>;
    };
-	video1_dpll_clk_mux: video1_dpll_clk_mux {
+	video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&sys_clkin2>;
    	reg = <0x0168>;
    };
-	video2_dpll_clk_mux: video2_dpll_clk_mux {
+	video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&sys_clkin2>;
    	reg = <0x016c>;
    };
-	wkupaon_iclk_mux: wkupaon_iclk_mux {
+	wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
    	reg = <0x0108>;
    };
-	gpio1_dbclk: gpio1_dbclk {
+	gpio1_dbclk: gpio1_dbclk@1838 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1165,7 +1165,7 @@
    	reg = <0x1838>;
    };
-	dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+	dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&sys_clkin2>;
@@ -1173,7 +1173,7 @@
    	reg = <0x1888>;
    };
-	timer1_gfclk_mux: timer1_gfclk_mux {
+	timer1_gfclk_mux: timer1_gfclk_mux@1840 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1181,7 +1181,7 @@
    	reg = <0x1840>;
    };
-	uart10_gfclk_mux: uart10_gfclk_mux {
+	uart10_gfclk_mux: uart10_gfclk_mux@1880 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1190,14 +1190,14 @@
    };
 };
 &cm_core_clocks {
-	dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+	dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-clock";
    	clocks = <&sys_clkin1>, <&sys_clkin1>;
    	reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
    };
-	dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+	dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_pcie_ref_ck>;
@@ -1216,7 +1216,7 @@
    	ti,bit-shift = <7>;
    };
-	apll_pcie_ck: apll_pcie_ck {
+	apll_pcie_ck: apll_pcie_ck@21c {
    	#clock-cells = <0>;
    	compatible = "ti,dra7-apll-clock";
    	clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
@@ -1305,7 +1305,7 @@
    	clock-div = <1>;
    };
-	dpll_per_byp_mux: dpll_per_byp_mux {
+	dpll_per_byp_mux: dpll_per_byp_mux@14c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
@@ -1313,14 +1313,14 @@
    	reg = <0x014c>;
    };
-	dpll_per_ck: dpll_per_ck {
+	dpll_per_ck: dpll_per_ck@140 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-clock";
    	clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
    	reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
    };
-	dpll_per_m2_ck: dpll_per_m2_ck {
+	dpll_per_m2_ck: dpll_per_m2_ck@150 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_per_ck>;
@@ -1339,7 +1339,7 @@
    	clock-div = <1>;
    };
-	dpll_usb_byp_mux: dpll_usb_byp_mux {
+	dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
@@ -1347,14 +1347,14 @@
    	reg = <0x018c>;
    };
-	dpll_usb_ck: dpll_usb_ck {
+	dpll_usb_ck: dpll_usb_ck@180 {
    	#clock-cells = <0>;
    	compatible = "ti,omap4-dpll-j-type-clock";
    	clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
    	reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
    };
-	dpll_usb_m2_ck: dpll_usb_m2_ck {
+	dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_usb_ck>;
@@ -1365,7 +1365,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+	dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_pcie_ref_ck>;
@@ -1382,7 +1382,7 @@
    	clocks = <&dpll_per_ck>;
    };
-	dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+	dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_per_x2_ck>;
@@ -1393,7 +1393,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+	dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_per_x2_ck>;
@@ -1404,7 +1404,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+	dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_per_x2_ck>;
@@ -1415,7 +1415,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+	dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_per_x2_ck>;
@@ -1426,7 +1426,7 @@
    	ti,invert-autoidle-bit;
    };
-	dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+	dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_per_x2_ck>;
@@ -1485,7 +1485,7 @@
    	clock-div = <2>;
    };
-	l3init_60m_fclk: l3init_60m_fclk {
+	l3init_60m_fclk: l3init_60m_fclkq104@104 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_usb_m2_ck>;
@@ -1493,7 +1493,7 @@
    	ti,dividers = <1>, <8>;
    };
-	clkout2_clk: clkout2_clk {
+	clkout2_clk: clkout2_clk@6b0 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&clkoutmux2_clk_mux>;
@@ -1501,7 +1501,7 @@
    	reg = <0x06b0>;
    };
-	l3init_960m_gfclk: l3init_960m_gfclk {
+	l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&dpll_usb_clkdcoldo>;
@@ -1509,7 +1509,7 @@
    	reg = <0x06c0>;
    };
-	dss_32khz_clk: dss_32khz_clk {
+	dss_32khz_clk: dss_32khz_clk@1120 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1517,7 +1517,7 @@
    	reg = <0x1120>;
    };
-	dss_48mhz_clk: dss_48mhz_clk {
+	dss_48mhz_clk: dss_48mhz_clk@1120 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&func_48m_fclk>;
@@ -1525,7 +1525,7 @@
    	reg = <0x1120>;
    };
-	dss_dss_clk: dss_dss_clk {
+	dss_dss_clk: dss_dss_clk@1120 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&dpll_per_h12x2_ck>;
@@ -1534,7 +1534,7 @@
    	ti,set-rate-parent;
    };
-	dss_hdmi_clk: dss_hdmi_clk {
+	dss_hdmi_clk: dss_hdmi_clk@1120 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&hdmi_dpll_clk_mux>;
@@ -1542,7 +1542,7 @@
    	reg = <0x1120>;
    };
-	dss_video1_clk: dss_video1_clk {
+	dss_video1_clk: dss_video1_clk@1120 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&video1_dpll_clk_mux>;
@@ -1550,7 +1550,7 @@
    	reg = <0x1120>;
    };
-	dss_video2_clk: dss_video2_clk {
+	dss_video2_clk: dss_video2_clk@1120 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&video2_dpll_clk_mux>;
@@ -1558,7 +1558,7 @@
    	reg = <0x1120>;
    };
-	gpio2_dbclk: gpio2_dbclk {
+	gpio2_dbclk: gpio2_dbclkq1760@1760 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1566,7 +1566,7 @@
    	reg = <0x1760>;
    };
-	gpio3_dbclk: gpio3_dbclk {
+	gpio3_dbclk: gpio3_dbclk@1768 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1574,7 +1574,7 @@
    	reg = <0x1768>;
    };
-	gpio4_dbclk: gpio4_dbclk {
+	gpio4_dbclk: gpio4_dbclk@1770 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1582,7 +1582,7 @@
    	reg = <0x1770>;
    };
-	gpio5_dbclk: gpio5_dbclk {
+	gpio5_dbclk: gpio5_dbclk@1778 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1590,7 +1590,7 @@
    	reg = <0x1778>;
    };
-	gpio6_dbclk: gpio6_dbclk {
+	gpio6_dbclk: gpio6_dbclk@1780 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1598,7 +1598,7 @@
    	reg = <0x1780>;
    };
-	gpio7_dbclk: gpio7_dbclk {
+	gpio7_dbclk: gpio7_dbclk@1810 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1606,7 +1606,7 @@
    	reg = <0x1810>;
    };
-	gpio8_dbclk: gpio8_dbclk {
+	gpio8_dbclk: gpio8_dbclk@1818 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1614,7 +1614,7 @@
    	reg = <0x1818>;
    };
-	mmc1_clk32k: mmc1_clk32k {
+	mmc1_clk32k: mmc1_clk32k@1328 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1622,7 +1622,7 @@
    	reg = <0x1328>;
    };
-	mmc2_clk32k: mmc2_clk32k {
+	mmc2_clk32k: mmc2_clk32k@1330 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1630,7 +1630,7 @@
    	reg = <0x1330>;
    };
-	mmc3_clk32k: mmc3_clk32k {
+	mmc3_clk32k: mmc3_clk32k@1820 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1638,7 +1638,7 @@
    	reg = <0x1820>;
    };
-	mmc4_clk32k: mmc4_clk32k {
+	mmc4_clk32k: mmc4_clk32k@1828 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1646,7 +1646,7 @@
    	reg = <0x1828>;
    };
-	sata_ref_clk: sata_ref_clk {
+	sata_ref_clk: sata_ref_clk@1388 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_clkin1>;
@@ -1654,7 +1654,7 @@
    	reg = <0x1388>;
    };
-	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&l3init_960m_gfclk>;
@@ -1662,7 +1662,7 @@
    	reg = <0x13f0>;
    };
-	usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+	usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&l3init_960m_gfclk>;
@@ -1670,7 +1670,7 @@
    	reg = <0x1340>;
    };
-	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1678,7 +1678,7 @@
    	reg = <0x0640>;
    };
-	usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+	usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1686,7 +1686,7 @@
    	reg = <0x0688>;
    };
-	usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+	usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&sys_32k_ck>;
@@ -1694,7 +1694,7 @@
    	reg = <0x0698>;
    };
-	atl_dpll_clk_mux: atl_dpll_clk_mux {
+	atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
@@ -1702,7 +1702,7 @@
    	reg = <0x0c00>;
    };
-	atl_gfclk_mux: atl_gfclk_mux {
+	atl_gfclk_mux: atl_gfclk_mux@c00 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
@@ -1710,7 +1710,7 @@
    	reg = <0x0c00>;
    };
-	gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+	gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@13d0 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&dpll_gmac_m2_ck>;
@@ -1719,7 +1719,7 @@
    	ti,dividers = <2>;
    };
-	gmac_rft_clk_mux: gmac_rft_clk_mux {
+	gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
@@ -1727,7 +1727,7 @@
    	reg = <0x13d0>;
    };
-	gpu_core_gclk_mux: gpu_core_gclk_mux {
+	gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1735,7 +1735,7 @@
    	reg = <0x1220>;
    };
-	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1743,7 +1743,7 @@
    	reg = <0x1220>;
    };
-	l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+	l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&wkupaon_iclk_mux>;
@@ -1752,7 +1752,7 @@
    	ti,dividers = <8>, <16>, <32>;
    };
-	mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+	mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1760,7 +1760,7 @@
    	reg = <0x1860>;
    };
-	mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+	mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1768,7 +1768,7 @@
    	reg = <0x1860>;
    };
-	mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+	mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1776,7 +1776,7 @@
    	reg = <0x1860>;
    };
-	mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+	mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1784,7 +1784,7 @@
    	reg = <0x1868>;
    };
-	mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+	mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1792,7 +1792,7 @@
    	reg = <0x1868>;
    };
-	mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+	mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1800,7 +1800,7 @@
    	reg = <0x1898>;
    };
-	mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+	mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1808,7 +1808,7 @@
    	reg = <0x1898>;
    };
-	mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+	mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1816,7 +1816,7 @@
    	reg = <0x1878>;
    };
-	mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+	mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1824,7 +1824,7 @@
    	reg = <0x1878>;
    };
-	mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+	mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1832,7 +1832,7 @@
    	reg = <0x1904>;
    };
-	mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+	mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1840,7 +1840,7 @@
    	reg = <0x1904>;
    };
-	mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+	mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1848,7 +1848,7 @@
    	reg = <0x1908>;
    };
-	mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+	mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1856,7 +1856,7 @@
    	reg = <0x1908>;
    };
-	mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+	mcasp8_ahclk_mux: mcasp8_ahclk_mux@1890 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1864,7 +1864,7 @@
    	reg = <0x1890>;
    };
-	mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+	mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1872,7 +1872,7 @@
    	reg = <0x1890>;
    };
-	mmc1_fclk_mux: mmc1_fclk_mux {
+	mmc1_fclk_mux: mmc1_fclk_mux@1328 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1880,7 +1880,7 @@
    	reg = <0x1328>;
    };
-	mmc1_fclk_div: mmc1_fclk_div {
+	mmc1_fclk_div: mmc1_fclk_div@1328 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&mmc1_fclk_mux>;
@@ -1890,7 +1890,7 @@
    	ti,index-power-of-two;
    };
-	mmc2_fclk_mux: mmc2_fclk_mux {
+	mmc2_fclk_mux: mmc2_fclk_mux@1330 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1898,7 +1898,7 @@
    	reg = <0x1330>;
    };
-	mmc2_fclk_div: mmc2_fclk_div {
+	mmc2_fclk_div: mmc2_fclk_div@1330 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&mmc2_fclk_mux>;
@@ -1908,7 +1908,7 @@
    	ti,index-power-of-two;
    };
-	mmc3_gfclk_mux: mmc3_gfclk_mux {
+	mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1916,7 +1916,7 @@
    	reg = <0x1820>;
    };
-	mmc3_gfclk_div: mmc3_gfclk_div {
+	mmc3_gfclk_div: mmc3_gfclk_div@1820 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&mmc3_gfclk_mux>;
@@ -1926,7 +1926,7 @@
    	ti,index-power-of-two;
    };
-	mmc4_gfclk_mux: mmc4_gfclk_mux {
+	mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1934,7 +1934,7 @@
    	reg = <0x1828>;
    };
-	mmc4_gfclk_div: mmc4_gfclk_div {
+	mmc4_gfclk_div: mmc4_gfclk_div@1828 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&mmc4_gfclk_mux>;
@@ -1944,7 +1944,7 @@
    	ti,index-power-of-two;
    };
-	qspi_gfclk_mux: qspi_gfclk_mux {
+	qspi_gfclk_mux: qspi_gfclk_mux@1838 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
@@ -1952,7 +1952,7 @@
    	reg = <0x1838>;
    };
-	qspi_gfclk_div: qspi_gfclk_div {
+	qspi_gfclk_div: qspi_gfclk_div@1838 {
    	#clock-cells = <0>;
    	compatible = "ti,divider-clock";
    	clocks = <&qspi_gfclk_mux>;
@@ -1962,7 +1962,7 @@
    	ti,index-power-of-two;
    };
-	timer10_gfclk_mux: timer10_gfclk_mux {
+	timer10_gfclk_mux: timer10_gfclk_mux@1728 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1970,7 +1970,7 @@
    	reg = <0x1728>;
    };
-	timer11_gfclk_mux: timer11_gfclk_mux {
+	timer11_gfclk_mux: timer11_gfclk_mux@1730 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1978,7 +1978,7 @@
    	reg = <0x1730>;
    };
-	timer13_gfclk_mux: timer13_gfclk_mux {
+	timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1986,7 +1986,7 @@
    	reg = <0x17c8>;
    };
-	timer14_gfclk_mux: timer14_gfclk_mux {
+	timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1994,7 +1994,7 @@
    	reg = <0x17d0>;
    };
-	timer15_gfclk_mux: timer15_gfclk_mux {
+	timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2002,7 +2002,7 @@
    	reg = <0x17d8>;
    };
-	timer16_gfclk_mux: timer16_gfclk_mux {
+	timer16_gfclk_mux: timer16_gfclk_mux@1830 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2010,7 +2010,7 @@
    	reg = <0x1830>;
    };
-	timer2_gfclk_mux: timer2_gfclk_mux {
+	timer2_gfclk_mux: timer2_gfclk_mux@1738 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2018,7 +2018,7 @@
    	reg = <0x1738>;
    };
-	timer3_gfclk_mux: timer3_gfclk_mux {
+	timer3_gfclk_mux: timer3_gfclk_mux@1740 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2026,7 +2026,7 @@
    	reg = <0x1740>;
    };
-	timer4_gfclk_mux: timer4_gfclk_mux {
+	timer4_gfclk_mux: timer4_gfclk_mux@1748 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2034,7 +2034,7 @@
    	reg = <0x1748>;
    };
-	timer9_gfclk_mux: timer9_gfclk_mux {
+	timer9_gfclk_mux: timer9_gfclk_mux@1750 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2042,7 +2042,7 @@
    	reg = <0x1750>;
    };
-	uart1_gfclk_mux: uart1_gfclk_mux {
+	uart1_gfclk_mux: uart1_gfclk_mux@1840 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2050,7 +2050,7 @@
    	reg = <0x1840>;
    };
-	uart2_gfclk_mux: uart2_gfclk_mux {
+	uart2_gfclk_mux: uart2_gfclk_mux@1848 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2058,7 +2058,7 @@
    	reg = <0x1848>;
    };
-	uart3_gfclk_mux: uart3_gfclk_mux {
+	uart3_gfclk_mux: uart3_gfclk_mux@1850 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2066,7 +2066,7 @@
    	reg = <0x1850>;
    };
-	uart4_gfclk_mux: uart4_gfclk_mux {
+	uart4_gfclk_mux: uart4_gfclk_mux@1858 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2074,7 +2074,7 @@
    	reg = <0x1858>;
    };
-	uart5_gfclk_mux: uart5_gfclk_mux {
+	uart5_gfclk_mux: uart5_gfclk_mux@1870 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2082,7 +2082,7 @@
    	reg = <0x1870>;
    };
-	uart7_gfclk_mux: uart7_gfclk_mux {
+	uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2090,7 +2090,7 @@
    	reg = <0x18d0>;
    };
-	uart8_gfclk_mux: uart8_gfclk_mux {
+	uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2098,7 +2098,7 @@
    	reg = <0x18e0>;
    };
-	uart9_gfclk_mux: uart9_gfclk_mux {
+	uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2106,7 +2106,7 @@
    	reg = <0x18e8>;
    };
-	vip1_gclk_mux: vip1_gclk_mux {
+	vip1_gclk_mux: vip1_gclk_mux@1020 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2114,7 +2114,7 @@
    	reg = <0x1020>;
    };
-	vip2_gclk_mux: vip2_gclk_mux {
+	vip2_gclk_mux: vip2_gclk_mux@1028 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2122,7 +2122,7 @@
    	reg = <0x1028>;
    };
-	vip3_gclk_mux: vip3_gclk_mux {
+	vip3_gclk_mux: vip3_gclk_mux@1030 {
    	#clock-cells = <0>;
    	compatible = "ti,mux-clock";
    	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2139,7 +2139,7 @@
 };
&scm_conf_clocks {
-	dss_deshdcp_clk: dss_deshdcp_clk {
+	dss_deshdcp_clk: dss_deshdcp_clk@558 {
    	#clock-cells = <0>;
    	compatible = "ti,gate-clock";
    	clocks = <&l3_iclk_div>;
diff --git a/arch/arm/dts/k2e-clocks.dtsi b/arch/arm/dts/k2e-clocks.dtsi
index d56d68f..4b79bde 100644
--- a/arch/arm/dts/k2e-clocks.dtsi
+++ b/arch/arm/dts/k2e-clocks.dtsi
@@ -35,7 +35,7 @@ clocks {
    	reg-names = "control";
    };
-	clkusb1: clkusb1 {
+	clkusb1: clkusb1@2350004 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk16>;
@@ -45,7 +45,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkhyperlink0: clkhyperlink0 {
+	clkhyperlink0: clkhyperlink0@2350030 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk12>;
@@ -55,7 +55,7 @@ clocks {
    	domain-id = <5>;
    };
-	clkpcie1: clkpcie1 {
+	clkpcie1: clkpcie1@235006c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk12>;
@@ -65,7 +65,7 @@ clocks {
    	domain-id = <18>;
    };
-	clkxge: clkxge {
+	clkxge: clkxge@23500c8 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
diff --git a/arch/arm/dts/k2e-netcp.dtsi b/arch/arm/dts/k2e-netcp.dtsi
index b13b3c9..01a44c5 100644
--- a/arch/arm/dts/k2e-netcp.dtsi
+++ b/arch/arm/dts/k2e-netcp.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
-qmss: qmss@2a40000 {
+qmss: qmss_2a40000 {
    compatible = "ti,keystone-navigator-qmss";
    dma-coherent;
    #address-cells = <1>;
@@ -23,7 +23,7 @@ qmss: qmss@2a40000 {
    	#address-cells = <1>;
    	#size-cells = <1>;
    	ranges;
-		qmgr0 {
+		qmgr0@0 {
    		managed-queues = <0 0x2000>;
    		reg = <0x2a40000 0x20000>,
    		      <0x2a06000 0x400>,
@@ -85,7 +85,7 @@ qmss: qmss@2a40000 {
    };
 }; /* qmss */
-knav_dmas: knav_dmas@0 {
+knav_dmas: knav_dmas0 {
    compatible = "ti,keystone-navigator-dma";
    clocks = <&papllclk>;
    #address-cells = <1>;
diff --git a/arch/arm/dts/k2e.dtsi b/arch/arm/dts/k2e.dtsi
index 675fb8e..f9be2ae 100644
--- a/arch/arm/dts/k2e.dtsi
+++ b/arch/arm/dts/k2e.dtsi
@@ -79,7 +79,7 @@
    		};
    	};
-		dspgpio0: keystone_dsp_gpio@02620240 {
+		dspgpio0: keystone_dsp_gpio_02620240 {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
diff --git a/arch/arm/dts/k2g-netcp.dtsi b/arch/arm/dts/k2g-netcp.dtsi
index 6f0ff86..879aa03 100644
--- a/arch/arm/dts/k2g-netcp.dtsi
+++ b/arch/arm/dts/k2g-netcp.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
-qmss: qmss@4020000 {
+qmss: qmss_4020000 {
    compatible = "ti,keystone-navigator-qmss-l";
    dma-coherent;
    #address-cells = <1>;
@@ -24,7 +24,7 @@ qmss: qmss@4020000 {
    	#address-cells = <1>;
    	#size-cells = <1>;
    	ranges;
-		qmgr0 {
+		qmgr0@0 {
    		managed-queues = <0 0x80>;
    		reg = <0x4100000 0x800>,
    		      <0x4040000 0x100>,
@@ -68,7 +68,7 @@ qmss: qmss@4020000 {
    };
 }; /* qmss */
-knav_dmas: knav_dmas@0 {
+knav_dmas: knav_dmas0 {
    compatible = "ti,keystone-navigator-dma";
    #address-cells = <1>;
    #size-cells = <1>;
diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi
index a3ed444..1eaab0a 100644
--- a/arch/arm/dts/k2g.dtsi
+++ b/arch/arm/dts/k2g.dtsi
@@ -21,7 +21,7 @@
    	serial0	= &uart0;
    };
-	memory {
+	memory@80000000 {
    	device_type = "memory";
    	reg = <0x80000000 0x80000000>;
    };
@@ -39,7 +39,7 @@
    	};
    };
-	gic: interrupt-controller {
+	gic: interrupt-controller@0 {
    	compatible = "arm,cortex-a15-gic";
    	#interrupt-cells = <3>;
    	interrupt-controller;
diff --git a/arch/arm/dts/k2hk-clocks.dtsi b/arch/arm/dts/k2hk-clocks.dtsi
index af9b719..63d3d2c 100644
--- a/arch/arm/dts/k2hk-clocks.dtsi
+++ b/arch/arm/dts/k2hk-clocks.dtsi
@@ -53,7 +53,7 @@ clocks {
    	reg-names = "control";
    };
-	clktsip: clktsip {
+	clktsip: clktsip@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk16>;
@@ -63,7 +63,7 @@ clocks {
    	domain-id = <0>;
    };
-	clksrio: clksrio {
+	clksrio: clksrio@235002c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1rstiso13>;
@@ -73,7 +73,7 @@ clocks {
    	domain-id = <4>;
    };
-	clkhyperlink0: clkhyperlink0 {
+	clkhyperlink0: clkhyperlink0@2350030 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk12>;
@@ -83,7 +83,7 @@ clocks {
    	domain-id = <5>;
    };
-	clkgem1: clkgem1 {
+	clkgem1: clkgem1@2350040 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -93,7 +93,7 @@ clocks {
    	domain-id = <9>;
    };
-	clkgem2: clkgem2 {
+	clkgem2: clkgem2@2350044 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -103,7 +103,7 @@ clocks {
    	domain-id = <10>;
    };
-	clkgem3: clkgem3 {
+	clkgem3: clkgem3@2350048 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -113,7 +113,7 @@ clocks {
    	domain-id = <11>;
    };
-	clkgem4: clkgem4 {
+	clkgem4: clkgem4@235004c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -123,7 +123,7 @@ clocks {
    	domain-id = <12>;
    };
-	clkgem5: clkgem5 {
+	clkgem5: clkgem5@2350050 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -133,7 +133,7 @@ clocks {
    	domain-id = <13>;
    };
-	clkgem6: clkgem6 {
+	clkgem6: clkgem6@2350054 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -143,7 +143,7 @@ clocks {
    	domain-id = <14>;
    };
-	clkgem7: clkgem7 {
+	clkgem7: clkgem7@2350058 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -153,7 +153,7 @@ clocks {
    	domain-id = <15>;
    };
-	clkddr31: clkddr31 {
+	clkddr31: clkddr31@2350060 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -163,7 +163,7 @@ clocks {
    	domain-id = <16>;
    };
-	clktac: clktac {
+	clktac: clktac@2350064 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -173,7 +173,7 @@ clocks {
    	domain-id = <17>;
    };
-	clkrac01: clkrac01 {
+	clkrac01: clkrac01@2350068 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -183,7 +183,7 @@ clocks {
    	domain-id = <17>;
    };
-	clkrac23: clkrac23 {
+	clkrac23: clkrac23@235006c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -193,7 +193,7 @@ clocks {
    	domain-id = <18>;
    };
-	clkfftc0: clkfftc0 {
+	clkfftc0: clkfftc0@2350070 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -203,7 +203,7 @@ clocks {
    	domain-id = <19>;
    };
-	clkfftc1: clkfftc1 {
+	clkfftc1: clkfftc1@2350074 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -213,7 +213,7 @@ clocks {
    	domain-id = <19>;
    };
-	clkfftc2: clkfftc2 {
+	clkfftc2: clkfftc2@2350078 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -223,7 +223,7 @@ clocks {
    	domain-id = <20>;
    };
-	clkfftc3: clkfftc3 {
+	clkfftc3: clkfftc3@235007c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -233,7 +233,7 @@ clocks {
    	domain-id = <20>;
    };
-	clkfftc4: clkfftc4 {
+	clkfftc4: clkfftc4@2350080 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -243,7 +243,7 @@ clocks {
    	domain-id = <20>;
    };
-	clkfftc5: clkfftc5 {
+	clkfftc5: clkfftc5@2350084 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -253,7 +253,7 @@ clocks {
    	domain-id = <20>;
    };
-	clkaif: clkaif {
+	clkaif: clkaif@2350088 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -263,7 +263,7 @@ clocks {
    	domain-id = <21>;
    };
-	clktcp3d0: clktcp3d0 {
+	clktcp3d0: clktcp3d0@235008c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -273,7 +273,7 @@ clocks {
    	domain-id = <22>;
    };
-	clktcp3d1: clktcp3d1 {
+	clktcp3d1: clktcp3d1@2350090 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -283,7 +283,7 @@ clocks {
    	domain-id = <22>;
    };
-	clktcp3d2: clktcp3d2 {
+	clktcp3d2: clktcp3d2@2350094 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -293,7 +293,7 @@ clocks {
    	domain-id = <23>;
    };
-	clktcp3d3: clktcp3d3 {
+	clktcp3d3: clktcp3d3@2350098 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -303,7 +303,7 @@ clocks {
    	domain-id = <23>;
    };
-	clkvcp0: clkvcp0 {
+	clkvcp0: clkvcp0@235009c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -313,7 +313,7 @@ clocks {
    	domain-id = <24>;
    };
-	clkvcp1: clkvcp1 {
+	clkvcp1: clkvcp1@23500a0 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -323,7 +323,7 @@ clocks {
    	domain-id = <24>;
    };
-	clkvcp2: clkvcp2 {
+	clkvcp2: clkvcp2@23500a4 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -333,7 +333,7 @@ clocks {
    	domain-id = <24>;
    };
-	clkvcp3: clkvcp3 {
+	clkvcp3: clkvcp3@23500a8 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -343,7 +343,7 @@ clocks {
    	domain-id = <24>;
    };
-	clkvcp4: clkvcp4 {
+	clkvcp4: clkvcp4@23500ac {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -353,7 +353,7 @@ clocks {
    	domain-id = <25>;
    };
-	clkvcp5: clkvcp5 {
+	clkvcp5: clkvcp5@23500b0 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -363,7 +363,7 @@ clocks {
    	domain-id = <25>;
    };
-	clkvcp6: clkvcp6 {
+	clkvcp6: clkvcp6@23500b4 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -373,7 +373,7 @@ clocks {
    	domain-id = <25>;
    };
-	clkvcp7: clkvcp7 {
+	clkvcp7: clkvcp7@23500b8 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -383,7 +383,7 @@ clocks {
    	domain-id = <25>;
    };
-	clkbcp: clkbcp {
+	clkbcp: clkbcp@23500bc {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -393,7 +393,7 @@ clocks {
    	domain-id = <26>;
    };
-	clkdxb: clkdxb {
+	clkdxb: clkdxb@23500c0 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -403,7 +403,7 @@ clocks {
    	domain-id = <27>;
    };
-	clkhyperlink1: clkhyperlink1 {
+	clkhyperlink1: clkhyperlink1@23500c4 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk12>;
@@ -413,7 +413,7 @@ clocks {
    	domain-id = <28>;
    };
-	clkxge: clkxge {
+	clkxge: clkxge@23500c8 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
diff --git a/arch/arm/dts/k2hk-netcp.dtsi b/arch/arm/dts/k2hk-netcp.dtsi
index 77a32c3..f974e1f 100644
--- a/arch/arm/dts/k2hk-netcp.dtsi
+++ b/arch/arm/dts/k2hk-netcp.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
-qmss: qmss@2a40000 {
+qmss: qmss_2a40000 {
    compatible = "ti,keystone-navigator-qmss";
    dma-coherent;
    #address-cells = <1>;
@@ -23,7 +23,7 @@ qmss: qmss@2a40000 {
    	#address-cells = <1>;
    	#size-cells = <1>;
    	ranges;
-		qmgr0 {
+		qmgr0@0 {
    		managed-queues = <0 0x2000>;
    		reg = <0x2a40000 0x20000>,
    		      <0x2a06000 0x400>,
@@ -35,7 +35,7 @@ qmss: qmss@2a40000 {
    			    "region", "push", "pop";
    	};
-		qmgr1 {
+		qmgr1@1 {
    		managed-queues = <0x2000 0x2000>;
    		reg = <0x2a60000 0x20000>,
    		      <0x2a06400 0x400>,
@@ -101,7 +101,7 @@ qmss: qmss@2a40000 {
    };
 }; /* qmss */
-knav_dmas: knav_dmas@0 {
+knav_dmas: knav_dmas0 {
    compatible = "ti,keystone-navigator-dma";
    clocks = <&papllclk>;
    #address-cells = <1>;
diff --git a/arch/arm/dts/k2hk.dtsi b/arch/arm/dts/k2hk.dtsi
index d0810a5..609c6cd 100644
--- a/arch/arm/dts/k2hk.dtsi
+++ b/arch/arm/dts/k2hk.dtsi
@@ -43,56 +43,56 @@
    soc {
    	/include/ "k2hk-clocks.dtsi"
-		dspgpio0: keystone_dsp_gpio@02620240 {
+		dspgpio0: keystone_dsp_gpio_02620240 {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
    		gpio,syscon-dev = <&devctrl 0x240>;
    	};
-		dspgpio1: keystone_dsp_gpio@2620244 {
+		dspgpio1: keystone_dsp_gpio_2620244 {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
    		gpio,syscon-dev = <&devctrl 0x244>;
    	};
-		dspgpio2: keystone_dsp_gpio@2620248 {
+		dspgpio2: keystone_dsp_gpio_2620248 {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
    		gpio,syscon-dev = <&devctrl 0x248>;
    	};
-		dspgpio3: keystone_dsp_gpio@262024c {
+		dspgpio3: keystone_dsp_gpio_262024c {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
    		gpio,syscon-dev = <&devctrl 0x24c>;
    	};
-		dspgpio4: keystone_dsp_gpio@2620250 {
+		dspgpio4: keystone_dsp_gpio_2620250 {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
    		gpio,syscon-dev = <&devctrl 0x250>;
    	};
-		dspgpio5: keystone_dsp_gpio@2620254 {
+		dspgpio5: keystone_dsp_gpio_2620254 {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
    		gpio,syscon-dev = <&devctrl 0x254>;
    	};
-		dspgpio6: keystone_dsp_gpio@2620258 {
+		dspgpio6: keystone_dsp_gpio_2620258 {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
    		gpio,syscon-dev = <&devctrl 0x258>;
    	};
-		dspgpio7: keystone_dsp_gpio@262025c {
+		dspgpio7: keystone_dsp_gpio_262025c {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
diff --git a/arch/arm/dts/k2l-clocks.dtsi b/arch/arm/dts/k2l-clocks.dtsi
index ef8464b..6d20d71 100644
--- a/arch/arm/dts/k2l-clocks.dtsi
+++ b/arch/arm/dts/k2l-clocks.dtsi
@@ -44,7 +44,7 @@ clocks {
    	reg-names = "control";
    };
-	clkdfeiqnsys: clkdfeiqnsys {
+	clkdfeiqnsys: clkdfeiqnsys@2350004 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk12>;
@@ -54,7 +54,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkpcie1: clkpcie1 {
+	clkpcie1: clkpcie1@235002c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk12>;
@@ -64,7 +64,7 @@ clocks {
    	domain-id = <4>;
    };
-	clkgem1: clkgem1 {
+	clkgem1: clkgem1@2350040 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -74,7 +74,7 @@ clocks {
    	domain-id = <9>;
    };
-	clkgem2: clkgem2 {
+	clkgem2: clkgem2@2350044 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -84,7 +84,7 @@ clocks {
    	domain-id = <10>;
    };
-	clkgem3: clkgem3 {
+	clkgem3: clkgem3@2350048 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -94,7 +94,7 @@ clocks {
    	domain-id = <11>;
    };
-	clktac: clktac {
+	clktac: clktac@2350068 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -104,7 +104,7 @@ clocks {
    	domain-id = <17>;
    };
-	clkrac: clkrac {
+	clkrac: clkrac@235006c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -114,7 +114,7 @@ clocks {
    	domain-id = <17>;
    };
-	clkdfepd0: clkdfepd0 {
+	clkdfepd0: clkdfepd0@235006c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -124,7 +124,7 @@ clocks {
    	domain-id = <18>;
    };
-	clkfftc0: clkfftc0 {
+	clkfftc0: clkfftc0@2350070 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -134,7 +134,7 @@ clocks {
    	domain-id = <19>;
    };
-	clkosr: clkosr {
+	clkosr: clkosr@2350088 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -144,7 +144,7 @@ clocks {
    	domain-id = <21>;
    };
-	clktcp3d0: clktcp3d0 {
+	clktcp3d0: clktcp3d0@235008c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -154,7 +154,7 @@ clocks {
    	domain-id = <22>;
    };
-	clktcp3d1: clktcp3d1 {
+	clktcp3d1: clktcp3d1@2350094 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -164,7 +164,7 @@ clocks {
    	domain-id = <23>;
    };
-	clkvcp0: clkvcp0 {
+	clkvcp0: clkvcp0@235009c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -174,7 +174,7 @@ clocks {
    	domain-id = <24>;
    };
-	clkvcp1: clkvcp1 {
+	clkvcp1: clkvcp1@23500a0 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -184,7 +184,7 @@ clocks {
    	domain-id = <24>;
    };
-	clkvcp2: clkvcp2 {
+	clkvcp2: clkvcp2@23500a4 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -194,7 +194,7 @@ clocks {
    	domain-id = <24>;
    };
-	clkvcp3: clkvcp3 {
+	clkvcp3: clkvcp3@23500a8 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -204,7 +204,7 @@ clocks {
    	domain-id = <24>;
    };
-	clkbcp: clkbcp {
+	clkbcp: clkbcp@23500bc {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -214,7 +214,7 @@ clocks {
    	domain-id = <26>;
    };
-	clkdfepd1: clkdfepd1 {
+	clkdfepd1: clkdfepd1@23500c0 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -224,7 +224,7 @@ clocks {
    	domain-id = <27>;
    };
-	clkfftc1: clkfftc1 {
+	clkfftc1: clkfftc1@23500c4 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -234,7 +234,7 @@ clocks {
    	domain-id = <28>;
    };
-	clkiqnail: clkiqnail {
+	clkiqnail: clkiqnail@23500c8 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -244,7 +244,7 @@ clocks {
    	domain-id = <29>;
    };
-	clkuart2: clkuart2 {
+	clkuart2: clkuart2@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -254,7 +254,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkuart3: clkuart3 {
+	clkuart3: clkuart3@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
diff --git a/arch/arm/dts/k2l-netcp.dtsi b/arch/arm/dts/k2l-netcp.dtsi
index 6b95284..f99945a 100644
--- a/arch/arm/dts/k2l-netcp.dtsi
+++ b/arch/arm/dts/k2l-netcp.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
-qmss: qmss@2a40000 {
+qmss: qmss_2a40000 {
    compatible = "ti,keystone-navigator-qmss";
    dma-coherent;
    #address-cells = <1>;
@@ -23,7 +23,7 @@ qmss: qmss@2a40000 {
    	#address-cells = <1>;
    	#size-cells = <1>;
    	ranges;
-		qmgr0 {
+		qmgr0@0 {
    		managed-queues = <0 0x2000>;
    		reg = <0x2a40000 0x20000>,
    		      <0x2a06000 0x400>,
@@ -85,7 +85,7 @@ qmss: qmss@2a40000 {
    };
 }; /* qmss */
-knav_dmas: knav_dmas@0 {
+knav_dmas: knav_dmas0 {
    compatible = "ti,keystone-navigator-dma";
    clocks = <&papllclk>;
    #address-cells = <1>;
diff --git a/arch/arm/dts/k2l.dtsi b/arch/arm/dts/k2l.dtsi
index 49fd414..a7e3a8a 100644
--- a/arch/arm/dts/k2l.dtsi
+++ b/arch/arm/dts/k2l.dtsi
@@ -51,28 +51,28 @@
    		interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
    	};
-		dspgpio0: keystone_dsp_gpio@02620240 {
+		dspgpio0: keystone_dsp_gpio_02620240 {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
    		gpio,syscon-dev = <&devctrl 0x240>;
    	};
-		dspgpio1: keystone_dsp_gpio@2620244 {
+		dspgpio1: keystone_dsp_gpio_2620244 {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
    		gpio,syscon-dev = <&devctrl 0x244>;
    	};
-		dspgpio2: keystone_dsp_gpio@2620248 {
+		dspgpio2: keystone_dsp_gpio_2620248 {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
    		gpio,syscon-dev = <&devctrl 0x248>;
    	};
-		dspgpio3: keystone_dsp_gpio@262024c {
+		dspgpio3: keystone_dsp_gpio_262024c {
    		compatible = "ti,keystone-dsp-gpio";
    		gpio-controller;
    		#gpio-cells = <2>;
diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi
index 0c334b2..becb331 100644
--- a/arch/arm/dts/keystone-clocks.dtsi
+++ b/arch/arm/dts/keystone-clocks.dtsi
@@ -51,7 +51,7 @@ clocks {
    	clock-output-names = "gemtraceclk";
    };
-	chipstmxptclk: chipstmxptclk {
+	chipstmxptclk: chipstmxptclk@2310164 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,pll-divider-clock";
    	clocks = <&mainmuxclk>;
@@ -160,7 +160,7 @@ clocks {
    	clock-output-names = "chipclk1rstiso112";
    };
-	clkmodrst0: clkmodrst0 {
+	clkmodrst0: clkmodrst0@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk16>;
@@ -171,7 +171,7 @@ clocks {
    };
-	clkusb: clkusb {
+	clkusb: clkusb@2350008 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk16>;
@@ -181,7 +181,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkaemifspi: clkaemifspi {
+	clkaemifspi: clkaemifspi@235000c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk16>;
@@ -192,7 +192,7 @@ clocks {
    };
-	clkdebugsstrc: clkdebugsstrc {
+	clkdebugsstrc: clkdebugsstrc@2350014 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -202,7 +202,7 @@ clocks {
    	domain-id = <1>;
    };
-	clktetbtrc: clktetbtrc {
+	clktetbtrc: clktetbtrc@2350018 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk13>;
@@ -212,7 +212,7 @@ clocks {
    	domain-id = <1>;
    };
-	clkpa: clkpa {
+	clkpa: clkpa@235001c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&paclk13>;
@@ -222,7 +222,7 @@ clocks {
    	domain-id = <2>;
    };
-	clkcpgmac: clkcpgmac {
+	clkcpgmac: clkcpgmac@2350020 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkpa>;
@@ -232,7 +232,7 @@ clocks {
    	domain-id = <2>;
    };
-	clksa: clksa {
+	clksa: clksa@2350024 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkpa>;
@@ -242,7 +242,7 @@ clocks {
    	domain-id = <2>;
    };
-	clkpcie: clkpcie {
+	clkpcie: clkpcie@2350028 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk12>;
@@ -252,7 +252,7 @@ clocks {
    	domain-id = <3>;
    };
-	clksr: clksr {
+	clksr: clksr@2350034 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1rstiso112>;
@@ -262,7 +262,7 @@ clocks {
    	domain-id = <6>;
    };
-	clkgem0: clkgem0 {
+	clkgem0: clkgem0@235003c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk1>;
@@ -272,7 +272,7 @@ clocks {
    	domain-id = <8>;
    };
-	clkddr30: clkddr30 {
+	clkddr30: clkddr30@235005c {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&chipclk12>;
@@ -282,7 +282,7 @@ clocks {
    	domain-id = <16>;
    };
-	clkwdtimer0: clkwdtimer0 {
+	clkwdtimer0: clkwdtimer0@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -292,7 +292,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkwdtimer1: clkwdtimer1 {
+	clkwdtimer1: clkwdtimer1@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -302,7 +302,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkwdtimer2: clkwdtimer2 {
+	clkwdtimer2: clkwdtimer2@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -312,7 +312,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkwdtimer3: clkwdtimer3 {
+	clkwdtimer3: clkwdtimer3@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -322,7 +322,7 @@ clocks {
    	domain-id = <0>;
    };
-	clktimer15: clktimer15 {
+	clktimer15: clktimer15@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -332,7 +332,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkuart0: clkuart0 {
+	clkuart0: clkuart0@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -342,7 +342,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkuart1: clkuart1 {
+	clkuart1: clkuart1@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -352,7 +352,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkaemif: clkaemif {
+	clkaemif: clkaemif@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkaemifspi>;
@@ -362,7 +362,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkusim: clkusim {
+	clkusim: clkusim@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -372,7 +372,7 @@ clocks {
    	domain-id = <0>;
    };
-	clki2c: clki2c {
+	clki2c: clki2c@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -382,7 +382,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkspi: clkspi {
+	clkspi: clkspi@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkaemifspi>;
@@ -392,7 +392,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkgpio: clkgpio {
+	clkgpio: clkgpio@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
@@ -402,7 +402,7 @@ clocks {
    	domain-id = <0>;
    };
-	clkkeymgr: clkkeymgr {
+	clkkeymgr: clkkeymgr@2350000 {
    	#clock-cells = <0>;
    	compatible = "ti,keystone,psc-clock";
    	clocks = <&clkmodrst0>;
diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi
index f39b969..f8375f4 100644
--- a/arch/arm/dts/keystone.dtsi
+++ b/arch/arm/dts/keystone.dtsi
@@ -25,11 +25,11 @@
    	stdout-path = &uart0;
    };
-	memory {
+	memory@80000000 {
    	reg = <0x80000000 0x40000000>;
    };
-	gic: interrupt-controller {
+	gic: interrupt-controller@0 {
    	compatible = "arm,cortex-a15-gic";
    	#interrupt-cells = <3>;
    	interrupt-controller;
@@ -270,7 +270,7 @@
    			  1 0 0x21000A00 0x00000100>;
    	};
-		kirq0: keystone_irq@26202a0 {
+		kirq0: keystone_irq_26202a0 {
    		compatible = "ti,keystone-irq";
    		interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
    		interrupt-controller;
-- 
2.5.0


    

Heiko Schocher

Tom Rini

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