[U-Boot] [PATCH 00/14] ARM: AM43xx: Update support for AM4372 SoC
This Patch series updates support for AM4372 EPOS and GP EVM boards. AM4372 is a low cost Cortex-A9 based application processor targeted at existing ARM9/ARM11 base of customers that need more processing capabilities. Currently there are two boards with AM4372 SoC: EPOS and GP EVM. Except for few differences like oscillator clock and SDRAM both EPOS and GP EVM boards are similar. EPOS EVM: OSC clk : 25MHz DDR : LPDDR2 @ 266MHz (MT42L256M32D2LG-25 WT:A) GP EVM: OSC clk : 24MHz DDR : DDR3 @ 400MHz(MT47H128M16RT-187E:C)
This patch series is applied on top of Mainline U-Boot Tree and two patches mentioned below: git://git.denx.de/u-boot.git master http://patchwork.ozlabs.org/patch/288175/ http://patchwork.ozlabs.org/patch/279755/
Testing: -> Boot tested on AM4372 EPOS and GP EVMs, Beaglebone Black. -> verified MAKEALL -s am33xx. -> Ran checkpatch on all patches.
Lokesh Vutla (12): ARM: AM43xx: Update the base addresses of modules ARM: AM43xx: Adapt to ti_armv7_common.h config file ARM: AM43xx: Add L2 Support ARM: AM43xx: Add extra ENV settings ARM: AM43xx: Select clk source for Timer2 ARM: AM43xx: Update Current Booting devices list ARM: AM43xx: mux: Update mux data ARM: AM43xx: clocks: Update DPLL details for EPOS EVM ARM: AM43xx: clocks: Add DPLL data for GP EVM ARM: AM43xx: EPOS_EVM: Add support for LPDDR2 ARM: AM43xx: GP_EVM: Add support for DDR3 ARM: AM43xx: Add Maintainer
Sekhar Nori (2): ARM: AM43XX: board: add support for reading onboard EEPROM ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support
arch/arm/cpu/armv7/am33xx/Makefile | 8 +- arch/arm/cpu/armv7/am33xx/clock.c | 12 +- arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 15 ++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 12 +- arch/arm/cpu/armv7/am33xx/emif4d5.c | 185 ++++++++++++++ arch/arm/include/asm/arch-am33xx/clock.h | 7 +- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 3 + arch/arm/include/asm/arch-am33xx/cpu.h | 22 +- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 34 +++ arch/arm/include/asm/arch-am33xx/hardware.h | 8 - arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 3 + arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 4 + arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 3 + arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 3 + arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 4 +- arch/arm/include/asm/arch-am33xx/omap.h | 2 + arch/arm/include/asm/arch-am33xx/spl.h | 12 +- arch/arm/include/asm/emif.h | 12 + board/ti/am43xx/board.c | 263 +++++++++++++++++++- board/ti/am43xx/board.h | 33 +++ board/ti/am43xx/mux.c | 29 ++- boards.cfg | 2 +- include/configs/am43xx_evm.h | 205 ++++++++------- 23 files changed, 737 insertions(+), 144 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/emif4d5.c
PRCM, timer base addresses and offsets are different from AM33xx. Updating the same.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-am33xx/cpu.h | 17 +++++++++++------ arch/arm/include/asm/arch-am33xx/hardware.h | 8 -------- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 3 +++ arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 3 +++ arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 3 +++ arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 3 +++ 6 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 52fa128..f463b27 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -237,6 +237,14 @@ struct cm_perpll { unsigned int cpswclkstctrl; /* offset 0x144 */ unsigned int lcdcclkstctrl; /* offset 0x148 */ }; + +/* Encapsulating Display pll registers */ +struct cm_dpll { + unsigned int resv1[2]; + unsigned int clktimer2clk; /* offset 0x08 */ + unsigned int resv2[10]; + unsigned int clklcdcpixelclk; /* offset 0x34 */ +}; #else /* Encapsulating core pll registers */ struct cm_wkuppll { @@ -392,15 +400,12 @@ struct cm_perpll { unsigned int resv40[7]; unsigned int cpgmac0clkctrl; /* offset 0xB20 */ }; -#endif /* CONFIG_AM43XX */
-/* Encapsulating Display pll registers */ struct cm_dpll { - unsigned int resv1[2]; - unsigned int clktimer2clk; /* offset 0x08 */ - unsigned int resv2[10]; - unsigned int clklcdcpixelclk; /* offset 0x34 */ + unsigned int resv1; + unsigned int clktimer2clk; /* offset 0x04 */ }; +#endif /* CONFIG_AM43XX */
/* Control Module RTC registers */ struct cm_rtc { diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index ee5fce0..b6db731 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -38,7 +38,6 @@ #define DM_TIMER7_BASE 0x4804A000
/* GPIO Base address */ -#define GPIO0_BASE 0x48032000 #define GPIO1_BASE 0x4804C000
/* BCH Error Location Module */ @@ -48,13 +47,6 @@ #define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_1_CFG_BASE 0x4D000000
-/* PLL related registers */ -#define CM_DPLL 0x44E00500 -#define CM_DEVICE 0x44E00700 -#define CM_RTC 0x44E00800 -#define CM_CEFUSE 0x44E00A00 -#define PRM_DEVICE 0x44E00F00 - /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index e4231c8..ad9d7dd 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -17,6 +17,7 @@ #define UART0_BASE 0x44E09000
/* GPIO Base address */ +#define GPIO0_BASE 0x48032000 #define GPIO2_BASE 0x481AC000
/* Watchdog Timer */ @@ -30,6 +31,8 @@ #define PRCM_BASE 0x44E00000 #define CM_PER 0x44E00000 #define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) #define PRM_RSTST (PRM_RSTCTRL + 8) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 3b665e6..4dbc789 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -17,6 +17,7 @@ #define UART0_BASE 0x44E09000
/* GPIO Base address */ +#define GPIO0_BASE 0x44E07000 #define GPIO2_BASE 0x481AC000
/* Watchdog Timer */ @@ -30,6 +31,8 @@ #define PRCM_BASE 0x44DF0000 #define CM_WKUP 0x44DF2800 #define CM_PER 0x44DF8800 +#define CM_DPLL 0x44DF4200 +#define CM_RTC 0x44df8500
#define PRM_RSTCTRL (PRCM_BASE + 0x4000) #define PRM_RSTST (PRM_RSTCTRL + 4) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index 4509a23..2322bc4 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -16,6 +16,7 @@ /* UART Base Address */ #define UART0_BASE 0x48020000
+#define GPIO0_BASE 0x48032000 /* Watchdog Timer */ #define WDT_BASE 0x481C7000
@@ -27,6 +28,8 @@ #define PRCM_BASE 0x48180000 #define CM_PER 0x44E00000 #define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) #define PRM_RSTST (PRM_RSTCTRL + 8) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h index 3c68064..b845203 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h @@ -26,6 +26,7 @@ #define UART1_BASE 0x48022000 #define UART2_BASE 0x48024000
+#define GPIO0_BASE 0x48032000 /* Watchdog Timer */ #define WDT_BASE 0x480C2000
@@ -34,6 +35,8 @@
/* PRCM Base Address */ #define PRCM_BASE 0x48180000 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) #define PRM_RSTST (PRM_RSTCTRL + 8)
HI Lokesh :)
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
PRCM, timer base addresses and offsets are different from AM33xx. Updating the same.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-am33xx/cpu.h | 17 +++++++++++------ arch/arm/include/asm/arch-am33xx/hardware.h | 8 -------- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 3 +++ arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 3 +++ arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 3 +++ arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 3 +++ 6 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 52fa128..f463b27 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -237,6 +237,14 @@ struct cm_perpll { unsigned int cpswclkstctrl; /* offset 0x144 */ unsigned int lcdcclkstctrl; /* offset 0x148 */ };
+/* Encapsulating Display pll registers */ +struct cm_dpll {
unsigned int resv1[2];unsigned int clktimer2clk; /* offset 0x08 */unsigned int resv2[10];unsigned int clklcdcpixelclk; /* offset 0x34 */+}; #else /* Encapsulating core pll registers */ struct cm_wkuppll { @@ -392,15 +400,12 @@ struct cm_perpll { unsigned int resv40[7]; unsigned int cpgmac0clkctrl; /* offset 0xB20 */ }; -#endif /* CONFIG_AM43XX */
-/* Encapsulating Display pll registers */ struct cm_dpll {
unsigned int resv1[2];unsigned int clktimer2clk; /* offset 0x08 */unsigned int resv2[10];unsigned int clklcdcpixelclk; /* offset 0x34 */
unsigned int resv1;unsigned int clktimer2clk; /* offset 0x04 */}; +#endif /* CONFIG_AM43XX */
/* Control Module RTC registers */ struct cm_rtc { diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index ee5fce0..b6db731 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -38,7 +38,6 @@ #define DM_TIMER7_BASE 0x4804A000
/* GPIO Base address */ -#define GPIO0_BASE 0x48032000
Going by the patch description this looks an unrelated change. Moreover, this base address looks wrong! GPIO0 is in wkup domain for both AM335x and AM437x. I wonder how the VTT control is working on AM335x. IIRC that was using a pin from GPIO0.
#define GPIO1_BASE 0x4804C000
/* BCH Error Location Module */ @@ -48,13 +47,6 @@ #define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_1_CFG_BASE 0x4D000000
-/* PLL related registers */ -#define CM_DPLL 0x44E00500 -#define CM_DEVICE 0x44E00700 -#define CM_RTC 0x44E00800 -#define CM_CEFUSE 0x44E00A00 -#define PRM_DEVICE 0x44E00F00
/* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index e4231c8..ad9d7dd 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -17,6 +17,7 @@ #define UART0_BASE 0x44E09000
/* GPIO Base address */ +#define GPIO0_BASE 0x48032000 #define GPIO2_BASE 0x481AC000
/* Watchdog Timer */ @@ -30,6 +31,8 @@ #define PRCM_BASE 0x44E00000 #define CM_PER 0x44E00000 #define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) #define PRM_RSTST (PRM_RSTCTRL + 8) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 3b665e6..4dbc789 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -17,6 +17,7 @@ #define UART0_BASE 0x44E09000
/* GPIO Base address */ +#define GPIO0_BASE 0x44E07000
Looks like this address is same for AM335x (what the code has right now is incorrect) and AM437x. So you can move it back to hardware.h if that's the general convention.
#define GPIO2_BASE 0x481AC000
/* Watchdog Timer */ @@ -30,6 +31,8 @@ #define PRCM_BASE 0x44DF0000 #define CM_WKUP 0x44DF2800 #define CM_PER 0x44DF8800 +#define CM_DPLL 0x44DF4200 +#define CM_RTC 0x44df8500
#define PRM_RSTCTRL (PRCM_BASE + 0x4000) #define PRM_RSTST (PRM_RSTCTRL + 4) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index 4509a23..2322bc4 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -16,6 +16,7 @@ /* UART Base Address */ #define UART0_BASE 0x48020000
+#define GPIO0_BASE 0x48032000
So that's where the current address came from. Still incorrect for AMxx.
Regards, Vaibhav
Hi Vibhav, Thanks for the review...:) On Wednesday 06 November 2013 05:58 PM, Vaibhav Bedia wrote:
HI Lokesh :)
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
PRCM, timer base addresses and offsets are different from AM33xx. Updating the same.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-am33xx/cpu.h | 17 +++++++++++------ arch/arm/include/asm/arch-am33xx/hardware.h | 8 -------- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 3 +++ arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 3 +++ arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 3 +++ arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 3 +++ 6 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 52fa128..f463b27 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -237,6 +237,14 @@ struct cm_perpll { unsigned int cpswclkstctrl; /* offset 0x144 */ unsigned int lcdcclkstctrl; /* offset 0x148 */ };
+/* Encapsulating Display pll registers */ +struct cm_dpll {
unsigned int resv1[2];unsigned int clktimer2clk; /* offset 0x08 */unsigned int resv2[10];unsigned int clklcdcpixelclk; /* offset 0x34 */+}; #else /* Encapsulating core pll registers */ struct cm_wkuppll { @@ -392,15 +400,12 @@ struct cm_perpll { unsigned int resv40[7]; unsigned int cpgmac0clkctrl; /* offset 0xB20 */ }; -#endif /* CONFIG_AM43XX */
-/* Encapsulating Display pll registers */ struct cm_dpll {
unsigned int resv1[2];unsigned int clktimer2clk; /* offset 0x08 */unsigned int resv2[10];unsigned int clklcdcpixelclk; /* offset 0x34 */
unsigned int resv1;unsigned int clktimer2clk; /* offset 0x04 */}; +#endif /* CONFIG_AM43XX */
/* Control Module RTC registers */ struct cm_rtc { diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index ee5fce0..b6db731 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -38,7 +38,6 @@ #define DM_TIMER7_BASE 0x4804A000
/* GPIO Base address */ -#define GPIO0_BASE 0x48032000
Going by the patch description this looks an unrelated change. Moreover, this base address looks wrong! GPIO0 is in wkup domain for both AM335x and AM437x. I wonder how the VTT control is working on AM335x. IIRC that was using a pin from GPIO0.
Should have added GPIO also in patch description.
#define GPIO1_BASE 0x4804C000
/* BCH Error Location Module */ @@ -48,13 +47,6 @@ #define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_1_CFG_BASE 0x4D000000
-/* PLL related registers */ -#define CM_DPLL 0x44E00500 -#define CM_DEVICE 0x44E00700 -#define CM_RTC 0x44E00800 -#define CM_CEFUSE 0x44E00A00 -#define PRM_DEVICE 0x44E00F00
/* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index e4231c8..ad9d7dd 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -17,6 +17,7 @@ #define UART0_BASE 0x44E09000
/* GPIO Base address */ +#define GPIO0_BASE 0x48032000 #define GPIO2_BASE 0x481AC000
/* Watchdog Timer */ @@ -30,6 +31,8 @@ #define PRCM_BASE 0x44E00000 #define CM_PER 0x44E00000 #define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) #define PRM_RSTST (PRM_RSTCTRL + 8) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 3b665e6..4dbc789 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -17,6 +17,7 @@ #define UART0_BASE 0x44E09000
/* GPIO Base address */ +#define GPIO0_BASE 0x44E07000
Looks like this address is same for AM335x (what the code has right now is incorrect) and AM437x. So you can move it back to hardware.h if that's the general convention.
#define GPIO2_BASE 0x481AC000
/* Watchdog Timer */ @@ -30,6 +31,8 @@ #define PRCM_BASE 0x44DF0000 #define CM_WKUP 0x44DF2800 #define CM_PER 0x44DF8800 +#define CM_DPLL 0x44DF4200 +#define CM_RTC 0x44df8500
#define PRM_RSTCTRL (PRCM_BASE + 0x4000) #define PRM_RSTST (PRM_RSTCTRL + 4) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index 4509a23..2322bc4 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -16,6 +16,7 @@ /* UART Base Address */ #define UART0_BASE 0x48020000
+#define GPIO0_BASE 0x48032000
So that's where the current address came from. Still incorrect for AMxx.
Yes you are correct. Just now I verified that there is asm/arch-am33xx/gpio.h file in which AM33XX_GPIO0_BASE is defined. This is used by AM33xx. I am not sure why GPIO_BASE is added again in hardware.h file. Any way I can reuse the GPIO base address from the above file instead of adding in hardware.h file. Thanks for the pointer.
Thanks and regards, Lokesh
Regards, Vaibhav
Use ti_armv7_common.h config file to inclde the common configs.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/am43xx/board.c | 2 +- include/configs/am43xx_evm.h | 130 +++++++++--------------------------------- 2 files changed, 28 insertions(+), 104 deletions(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 51b2576..dcd8cbb 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -44,7 +44,7 @@ void sdram_init(void)
int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0; } diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 64c4811..4815357 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -10,128 +10,52 @@ #define __CONFIG_AM43XX_EVM_H
#define CONFIG_AM43XX -#define CONFIG_OMAP -#define CONFIG_OMAP_COMMON
-#include <asm/arch/omap.h> - -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) - -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "U-Boot# " -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* commands to include */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_VERSION_VARIABLE - -/* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_CMD_ECHO - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - - /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) -/* Platform/Board specific defs */ -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ - #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 + +#include <asm/arch/omap.h>
/* NS16550 Configuration */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_CLK 48000000
-#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ -4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -#define CONFIG_ENV_IS_NOWHERE +/* SPL defines. */ +#define CONFIG_SPL_TEXT_BASE 0x40300350 +#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_YMODEM_SUPPORT
/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. */ -#define CONFIG_SYS_TEXT_BASE 0x80800000 - -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) #define CONFIG_SKIP_LOWLEVEL_INIT #endif
-/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (101 * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +/* Now bring in the rest of the common code. */ +#include <configs/ti_armv7_common.h>
-#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_YMODEM_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SYS_SPL_MALLOC_START 0x80a08000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK)
-/* Unsupported features */ -#undef CONFIG_USE_IRQ +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ + +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_CMD_USB #define CONFIG_USB_HOST
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Use ti_armv7_common.h config file to inclde the common configs.
[...]
+/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK)
I know this is slightly unrelated but i don't think hardcoding the osc freq is a good idea. We should be reading the PRCM register to detect the sysboot settings and then use that similar to the kernel. Follow up patch?
-/* Unsupported features */ -#undef CONFIG_USE_IRQ +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
I think the comment on base EVM is not applicable here ;)
Regards, Vaibhav
Hi Vaibhav,
On Wednesday 06 November 2013 06:04 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Use ti_armv7_common.h config file to inclde the common configs.
[...]
+/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK)
I know this is slightly unrelated but i don't think hardcoding the osc freq is a good idea. We should be reading the PRCM register to detect the sysboot settings and then use that similar to the kernel. Follow up patch?
This is how it is done in all other OMAPs and AMXX. But you are correct, it can be done from reading the register. Will discuss with Tom and update about a separate patch but not in this series..:)
Thanks and regards, Lokesh
-/* Unsupported features */ -#undef CONFIG_USE_IRQ +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
I think the comment on base EVM is not applicable here ;)
Regards, Vaibhav
AM4372 uses PL310 L2 Cache. Enable the configs for the same.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- include/configs/am43xx_evm.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4815357..b0269a7 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -30,6 +30,11 @@ #define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_YMODEM_SUPPORT
+/* Enabling L2 Cache */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Since SPL did pll and ddr initialization for us, * we don't need to do it twice.
Add Extra env settings. This is derived from am335x Extra ENV settings.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- include/configs/am43xx_evm.h | 63 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+)
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index b0269a7..6afb6b4 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -72,4 +72,67 @@ #define CONFIG_OMAP_USB_PHY #define CONFIG_AM437X_USB2PHY2_HOST
+#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "fdt_high=0xffffffff\0" \ + "rdaddr=0x81000000\0" \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ + "fi;\0" \ + "findfdt="\ + "if test $board_name = AM43EPOS; then " \ + "setenv fdtfile am43x-epos-evm.dtb; fi; " \ + "if test $board_name = AM43__GP; then " \ + "setenv fdtfile am43x-gp-evm.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree; fi; \0" + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run mmcboot;" + +#endif #endif /* __CONFIG_AM43XX_EVM_H */
From: Sekhar Nori nsekhar@ti.com
Add support for reading onboard EEPROM to enable board detection.
Signed-off-by: Sekhar Nori nsekhar@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-am33xx/omap.h | 2 ++ board/ti/am43xx/board.c | 46 +++++++++++++++++++++++++++++++ board/ti/am43xx/board.h | 32 +++++++++++++++++++++ include/configs/am43xx_evm.h | 7 +++++ 4 files changed, 87 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 2250721..10f05c9 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -27,5 +27,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 #define SRAM_SCRATCH_SPACE_ADDR 0x4033C000 +#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR +#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC #endif #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index dcd8cbb..4fc1a40 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -9,6 +9,8 @@ */
#include <common.h> +#include <i2c.h> +#include <asm/errno.h> #include <spl.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> @@ -17,6 +19,50 @@
DECLARE_GLOBAL_DATA_PTR;
+/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(struct am43xx_board_id *header) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM at 0x%x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, + sizeof(struct am43xx_board_id))) { + printf("Could not read the EEPROM\n"); + return -EIO; + } + + if (header->magic != 0xEE3355AA) { + /* + * read the eeprom using i2c again, + * but use only a 1 byte address + */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct am43xx_board_id))) { + printf("Could not read the EEPROM at 0x%x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return -EIO; + } + + if (header->magic != 0xEE3355AA) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header->magic); + return -EINVAL; + } + } + + strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); + am43xx_board_name[sizeof(header->name)] = 0; + + return 0; +} + #ifdef CONFIG_SPL_BUILD
const struct dpll_params dpll_ddr = { diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 8ca098b..9268895 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -12,6 +12,38 @@ #ifndef _BOARD_H_ #define _BOARD_H_
+#include <asm/arch/omap.h> + +static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; + +/* + * TI AM437x EVMs define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct am43xx_board_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +static inline int board_is_eposevm(void) +{ + return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN); +} + +static inline int board_is_gpevm(void) +{ + return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN); +} + void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); #endif diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 6afb6b4..456dcaa 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -25,6 +25,13 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000
+/* I2C Configuration */ +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + /* SPL defines. */ #define CONFIG_SPL_TEXT_BASE 0x40300350 #define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
From: Sekhar Nori nsekhar@ti.com
Add support for reading onboard EEPROM to enable board detection.
Signed-off-by: Sekhar Nori nsekhar@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-am33xx/omap.h | 2 ++ board/ti/am43xx/board.c | 46 +++++++++++++++++++++++++++++++ board/ti/am43xx/board.h | 32 +++++++++++++++++++++ include/configs/am43xx_evm.h | 7 +++++ 4 files changed, 87 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 2250721..10f05c9 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -27,5 +27,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 #define SRAM_SCRATCH_SPACE_ADDR 0x4033C000 +#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR +#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC #endif #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index dcd8cbb..4fc1a40 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -9,6 +9,8 @@ */
#include <common.h> +#include <i2c.h> +#include <asm/errno.h> #include <spl.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> @@ -17,6 +19,50 @@
DECLARE_GLOBAL_DATA_PTR;
+/*
- Read header information from EEPROM into global structure.
- */
+static int read_eeprom(struct am43xx_board_id *header) +{
/* Check if baseboard eeprom is available */if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {printf("Could not probe the EEPROM at 0x%x\n",CONFIG_SYS_I2C_EEPROM_ADDR);return -ENODEV;}/* read the eeprom using i2c */if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,sizeof(struct am43xx_board_id))) {printf("Could not read the EEPROM\n");return -EIO;}if (header->magic != 0xEE3355AA) {
Why is the header the same as AM335x? Shouldn't it be something like 0xEE3344AA or whatever?
/** read the eeprom using i2c again,* but use only a 1 byte address*/if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,sizeof(struct am43xx_board_id))) {printf("Could not read the EEPROM at 0x%x\n",CONFIG_SYS_I2C_EEPROM_ADDR);return -EIO;}if (header->magic != 0xEE3355AA) {
Same here.
Regards, Vaibhav
On Wednesday 06 November 2013 06:08 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
From: Sekhar Nori nsekhar@ti.com
Add support for reading onboard EEPROM to enable board detection.
Signed-off-by: Sekhar Nori nsekhar@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-am33xx/omap.h | 2 ++ board/ti/am43xx/board.c | 46 +++++++++++++++++++++++++++++++ board/ti/am43xx/board.h | 32 +++++++++++++++++++++ include/configs/am43xx_evm.h | 7 +++++ 4 files changed, 87 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 2250721..10f05c9 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -27,5 +27,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 #define SRAM_SCRATCH_SPACE_ADDR 0x4033C000 +#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR +#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC #endif #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index dcd8cbb..4fc1a40 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -9,6 +9,8 @@ */
#include <common.h> +#include <i2c.h> +#include <asm/errno.h> #include <spl.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> @@ -17,6 +19,50 @@
DECLARE_GLOBAL_DATA_PTR;
+/*
- Read header information from EEPROM into global structure.
- */
+static int read_eeprom(struct am43xx_board_id *header) +{
/* Check if baseboard eeprom is available */if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {printf("Could not probe the EEPROM at 0x%x\n",CONFIG_SYS_I2C_EEPROM_ADDR);return -ENODEV;}/* read the eeprom using i2c */if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,sizeof(struct am43xx_board_id))) {printf("Could not read the EEPROM\n");return -EIO;}if (header->magic != 0xEE3355AA) {Why is the header the same as AM335x? Shouldn't it be something like 0xEE3344AA or whatever?
No, the header is still same. It is 0xEE3355AA.
Thanks and regards, Lokesh
/** read the eeprom using i2c again,* but use only a 1 byte address*/if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,sizeof(struct am43xx_board_id))) {printf("Could not read the EEPROM at 0x%x\n",CONFIG_SYS_I2C_EEPROM_ADDR);return -EIO;}if (header->magic != 0xEE3355AA) {Same here.
Regards, Vaibhav
On Wed, Nov 6, 2013 at 8:25 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
On Wednesday 06 November 2013 06:08 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
From: Sekhar Nori nsekhar@ti.com
Add support for reading onboard EEPROM to enable board detection.
Signed-off-by: Sekhar Nori nsekhar@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-am33xx/omap.h | 2 ++ board/ti/am43xx/board.c | 46 +++++++++++++++++++++++++++++++ board/ti/am43xx/board.h | 32 +++++++++++++++++++++ include/configs/am43xx_evm.h | 7 +++++ 4 files changed, 87 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 2250721..10f05c9 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -27,5 +27,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 #define SRAM_SCRATCH_SPACE_ADDR 0x4033C000 +#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR +#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC #endif #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index dcd8cbb..4fc1a40 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -9,6 +9,8 @@ */
#include <common.h> +#include <i2c.h> +#include <asm/errno.h> #include <spl.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> @@ -17,6 +19,50 @@
DECLARE_GLOBAL_DATA_PTR;
+/*
- Read header information from EEPROM into global structure.
- */
+static int read_eeprom(struct am43xx_board_id *header) +{
/* Check if baseboard eeprom is available */if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {printf("Could not probe the EEPROM at 0x%x\n",CONFIG_SYS_I2C_EEPROM_ADDR);return -ENODEV;}/* read the eeprom using i2c */if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,sizeof(struct am43xx_board_id))) {printf("Could not read the EEPROM\n");return -EIO;}if (header->magic != 0xEE3355AA) {Why is the header the same as AM335x? Shouldn't it be something like 0xEE3344AA or whatever?
No, the header is still same. It is 0xEE3355AA.
My question was why ;) What's the point of adding the same magic value for a different SoC? Unless there's a good reason for doing so i think this needs to be fixed in the EEPROM programmer.
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
On 11/06/2013 11:39 AM, Vaibhav Bedia wrote:
On Wed, Nov 6, 2013 at 8:25 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
On Wednesday 06 November 2013 06:08 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
From: Sekhar Nori nsekhar@ti.com
Add support for reading onboard EEPROM to enable board detection.
Signed-off-by: Sekhar Nori nsekhar@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-am33xx/omap.h | 2 ++ board/ti/am43xx/board.c | 46 +++++++++++++++++++++++++++++++ board/ti/am43xx/board.h | 32 +++++++++++++++++++++ include/configs/am43xx_evm.h | 7 +++++ 4 files changed, 87 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 2250721..10f05c9 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -27,5 +27,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 #define SRAM_SCRATCH_SPACE_ADDR 0x4033C000 +#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR +#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC #endif #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index dcd8cbb..4fc1a40 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -9,6 +9,8 @@ */
#include <common.h> +#include <i2c.h> +#include <asm/errno.h> #include <spl.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> @@ -17,6 +19,50 @@
DECLARE_GLOBAL_DATA_PTR;
+/*
- Read header information from EEPROM into global structure.
- */
+static int read_eeprom(struct am43xx_board_id *header) +{
/* Check if baseboard eeprom is available */if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {printf("Could not probe the EEPROM at 0x%x\n",CONFIG_SYS_I2C_EEPROM_ADDR);return -ENODEV;}/* read the eeprom using i2c */if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,sizeof(struct am43xx_board_id))) {printf("Could not read the EEPROM\n");return -EIO;}if (header->magic != 0xEE3355AA) {Why is the header the same as AM335x? Shouldn't it be something like 0xEE3344AA or whatever?
No, the header is still same. It is 0xEE3355AA.
My question was why ;) What's the point of adding the same magic value for a different SoC? Unless there's a good reason for doing so i think this needs to be fixed in the EEPROM programmer.
A magic value is sufficiently magical, I don't think we'll get anyone to change it at this point.
- -- Tom
Hi Tom,
On Wed, Nov 6, 2013 at 4:37 PM, Tom Rini trini@ti.com wrote:
if (header->magic != 0xEE3355AA) {Why is the header the same as AM335x? Shouldn't it be something like 0xEE3344AA or whatever?
No, the header is still same. It is 0xEE3355AA.
My question was why ;) What's the point of adding the same magic value for a different SoC? Unless there's a good reason for doing so i think this needs to be fixed in the EEPROM programmer.
A magic value is sufficiently magical, I don't think we'll get anyone to change it at this point.
With almost half a dozen of AM335x board variants floating around this thing is bound to cause problems eventually. The EEPROM format can simply be updated to fix this. If there's a big resistance in doing this then we might as well live with it - but i would at least ask once ;)
Regards, Vaibhav
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On 11/07/2013 03:56 PM, Vaibhav Bedia wrote:
Hi Tom,
On Wed, Nov 6, 2013 at 4:37 PM, Tom Rini trini@ti.com wrote:
if (header->magic != 0xEE3355AA) {Why is the header the same as AM335x? Shouldn't it be something like 0xEE3344AA or whatever?
No, the header is still same. It is 0xEE3355AA.
My question was why ;) What's the point of adding the same magic value for a different SoC? Unless there's a good reason for doing so i think this needs to be fixed in the EEPROM programmer.
A magic value is sufficiently magical, I don't think we'll get anyone to change it at this point.
With almost half a dozen of AM335x board variants floating around this thing is bound to cause problems eventually. The EEPROM format can simply be updated to fix this. If there's a big resistance in doing this then we might as well live with it - but i would at least ask once ;)
The thing is, customers drop the EEPROM or come up with their own, see the Siemens am335x boards :)
- -- Tom
On Thu, Nov 7, 2013 at 4:06 PM, Tom Rini trini@ti.com wrote:
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On 11/07/2013 03:56 PM, Vaibhav Bedia wrote:
Hi Tom,
On Wed, Nov 6, 2013 at 4:37 PM, Tom Rini trini@ti.com wrote:
> + > + if (header->magic != 0xEE3355AA) {
Why is the header the same as AM335x? Shouldn't it be something like 0xEE3344AA or whatever?
No, the header is still same. It is 0xEE3355AA.
My question was why ;) What's the point of adding the same magic value for a different SoC? Unless there's a good reason for doing so i think this needs to be fixed in the EEPROM programmer.
A magic value is sufficiently magical, I don't think we'll get anyone to change it at this point.
With almost half a dozen of AM335x board variants floating around this thing is bound to cause problems eventually. The EEPROM format can simply be updated to fix this. If there's a big resistance in doing this then we might as well live with it - but i would at least ask once ;)
The thing is, customers drop the EEPROM or come up with their own, see the Siemens am335x boards :)
Customers fix a design and get rid of whatever they can ;)
I always considered the EEPROM as one of the ways of maintaining some sanity amongst the numerous board variants that go around internally :P
I'll leave this for the right folks to decide then :)
Regards, Vaibhav
From: Sekhar Nori nsekhar@ti.com
CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the board. These variables are used by findfdt.
Signed-off-by: Sekhar Nori nsekhar@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/am43xx/board.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 4fc1a40..723d0ca 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -98,6 +98,22 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + char safe_string[HDR_NAME_LEN + 1]; + struct am43xx_board_id header; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Now set variables based on the header. */ + strncpy(safe_string, (char *)header.name, sizeof(header.name)); + safe_string[sizeof(header.name)] = 0; + setenv("board_name", safe_string); + + strncpy(safe_string, (char *)header.version, sizeof(header.version)); + safe_string[sizeof(header.version)] = 0; + setenv("board_rev", safe_string); +#endif return 0; } #endif
Selecting the Master osc clk as Timer2 clock source.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index c4890f2..22963b7 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -18,6 +18,7 @@
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
const struct dpll_regs dpll_mpu_regs = { .cm_clkmode_dpll = CM_WKUP + 0x560, @@ -107,4 +108,7 @@ void enable_basic_clocks(void) };
do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + + /* Select the Master osc clk as Timer2 clock source */ + writel(0x1, &cmdpll->clktimer2clk); }
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Selecting the Master osc clk as Timer2 clock source.
I obviously missed the first round of patches for AM43xx here. Why is timer2 being used here? Don't we use the synctimer and timer1 in the kernel?
Regards, Vaibhav
Hi Vaibhav, On Wednesday 06 November 2013 06:10 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Selecting the Master osc clk as Timer2 clock source.
I obviously missed the first round of patches for AM43xx here. Why is timer2 being used here? Don't we use the synctimer and timer1 in the kernel?
In u-boot there is already code present to handle timer2 in arch/arm/cpu/armv7/omap-common/timer.c(Registers offsets are different for timer1 and timer2) . Trying to reuse the same here. This is how it is done in am335x also. Correct me if I am wrong.
Thanks and regards, Lokesh
Regards, Vaibhav
Hi Lokesh,
On Thu, Nov 7, 2013 at 8:43 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
Hi Vaibhav, On Wednesday 06 November 2013 06:10 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Selecting the Master osc clk as Timer2 clock source.
I obviously missed the first round of patches for AM43xx here. Why is timer2 being used here? Don't we use the synctimer and timer1 in the kernel?
In u-boot there is already code present to handle timer2 in arch/arm/cpu/armv7/omap-common/timer.c(Registers offsets are different for timer1 and timer2) . Trying to reuse the same here. This is how it is done in am335x also. Correct me if I am wrong.
On AM335x that timer is used in U-Boot in the delay loop and later gets used in the kernel as a system timer. On AM437x it might be a good idea to use synctimer since it has some stabilization period requirements and that's going to affect the kernel boot eventually.
Regards, Vaibhav
Hi Vaibhav, On Friday 08 November 2013 02:31 AM, Vaibhav Bedia wrote:
Hi Lokesh,
On Thu, Nov 7, 2013 at 8:43 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
Hi Vaibhav, On Wednesday 06 November 2013 06:10 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Selecting the Master osc clk as Timer2 clock source.
I obviously missed the first round of patches for AM43xx here. Why is timer2 being used here? Don't we use the synctimer and timer1 in the kernel?
In u-boot there is already code present to handle timer2 in arch/arm/cpu/armv7/omap-common/timer.c(Registers offsets are different for timer1 and timer2) . Trying to reuse the same here. This is how it is done in am335x also. Correct me if I am wrong.
On AM335x that timer is used in U-Boot in the delay loop and later gets used in the kernel as a system timer. On AM437x it might be a good idea to use synctimer since it has some stabilization period requirements and that's going to affect the kernel boot eventually.
OK, Correct me if I am wrong. On AM437X also this timer is used in U-Boot in delay loop only. Is there any documentation or any requirement saying that the synctimer needs some stabilization period? (AFAIK and discussed with Sekhar and Afzal, there is no such requirement.) If there is any such requirement for stabilization, then I should not use such timer in delay loop(So use time2 :) ). Should just enable the timer and leave it for stabilization. (There was a special case for RTC clock stabilization and was agreed to enable RTC in U-Boot) Let me know if I am not clear..:)
Thanks and regards, Lokesh
Regards, Vaibhav
Current Booting devices list is different from that of AM33xx. Updating the same.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-am33xx/spl.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 95de9aa..82116a9 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -13,11 +13,17 @@ #define BOOT_DEVICE_MMC1 6 #define BOOT_DEVICE_MMC2 5 #define BOOT_DEVICE_UART 0x43 -#define BOOT_DEVICE_MMC2_2 0xFF +#elif defined(CONFIG_AM43XX) +#define BOOT_DEVICE_NOR 1 +#define BOOT_DEVICE_NAND 5 +#define BOOT_DEVICE_MMC1 7 +#define BOOT_DEVICE_MMC2 8 +#define BOOT_DEVICE_SPI 10 +#define BOOT_DEVICE_UART 65 #else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 -#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) +#if defined(CONFIG_AM33XX) #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #elif defined(CONFIG_TI814X) @@ -28,8 +34,8 @@ #define BOOT_DEVICE_UART 65 #define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 -#define BOOT_DEVICE_MMC2_2 0xFF #endif +#define BOOT_DEVICE_MMC2_2 0xFF
#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
Updating the mux data for UART, and adding data for i2c0 and mmc.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 4 +++- board/ti/am43xx/mux.c | 24 ++++++++++++++++++++++-- 2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index 0206912..e95efdd 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -16,7 +16,9 @@ __raw_writel(value, (CTRL_BASE + offset));
/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 19) +#define DSPULLUDEN (0x1 << 27) /* DS0 mode Pull-Up/Down enable */ +#define DSPULLUDDIS (0x0 << 27) /* DS0 mode Pull-Up/Down Disable */ +#define SLEWCTRL (0x1 << 19) /* Slow slew rate selection */ #define RXACTIVE (0x1 << 18) #define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ #define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 700e9a7..818a046 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -12,8 +12,26 @@ #include "board.h"
static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */ - {OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */ + {OFFSET(uart0_rxd), + (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL | DSPULLUDEN)}, + {OFFSET(uart0_txd), + (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL | DSPULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE | DSPULLUDEN)}, + {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)}, + {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)}, + {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)}, + {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)}, + {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, {-1}, };
@@ -24,4 +42,6 @@ void enable_uart0_pin_mux(void)
void enable_board_pin_mux(void) { + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); }
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Updating the mux data for UART, and adding data for i2c0 and mmc.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 4 +++- board/ti/am43xx/mux.c | 24 ++++++++++++++++++++++-- 2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index 0206912..e95efdd 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -16,7 +16,9 @@ __raw_writel(value, (CTRL_BASE + offset));
/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 19) +#define DSPULLUDEN (0x1 << 27) /* DS0 mode Pull-Up/Down enable */ +#define DSPULLUDDIS (0x0 << 27) /* DS0 mode Pull-Up/Down Disable */ +#define SLEWCTRL (0x1 << 19) /* Slow slew rate selection */ #define RXACTIVE (0x1 << 18) #define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ #define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 700e9a7..818a046 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -12,8 +12,26 @@ #include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */{OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */
{OFFSET(uart0_rxd),(MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL | DSPULLUDEN)},{OFFSET(uart0_txd),(MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL | DSPULLUDEN)},{-1},+};
+static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{-1},
Hmm i don't think updating the DSPULL here is a good idea. Since not all the pins are used in U-Boot, this is just partially updating the pulls for the low power state. I would suggest leaving this bit for the kernel where things can be updated without updating the bootloader.
Regards, Vaibhav
On Wednesday 06 November 2013 06:13 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Updating the mux data for UART, and adding data for i2c0 and mmc.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 4 +++- board/ti/am43xx/mux.c | 24 ++++++++++++++++++++++-- 2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index 0206912..e95efdd 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -16,7 +16,9 @@ __raw_writel(value, (CTRL_BASE + offset));
/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 19) +#define DSPULLUDEN (0x1 << 27) /* DS0 mode Pull-Up/Down enable */ +#define DSPULLUDDIS (0x0 << 27) /* DS0 mode Pull-Up/Down Disable */ +#define SLEWCTRL (0x1 << 19) /* Slow slew rate selection */ #define RXACTIVE (0x1 << 18) #define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ #define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 700e9a7..818a046 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -12,8 +12,26 @@ #include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */{OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */
{OFFSET(uart0_rxd),(MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL | DSPULLUDEN)},{OFFSET(uart0_txd),(MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL | DSPULLUDEN)},{-1},+};
+static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{-1},Hmm i don't think updating the DSPULL here is a good idea. Since not all the pins are used in U-Boot, this is just partially updating the pulls for the low power state. I would suggest leaving this bit for the kernel where things can be updated without updating the bootloader.
These are the preferred settings given to me. Any way if kernel is updating it overwrites these settings, it shouldn't matter I guess..:)
Thanks and regards, Lokesh
Regards, Vaibhav
On Wed, Nov 6, 2013 at 8:32 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
On Wednesday 06 November 2013 06:13 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Updating the mux data for UART, and adding data for i2c0 and mmc.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 4 +++- board/ti/am43xx/mux.c | 24 ++++++++++++++++++++++-- 2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index 0206912..e95efdd 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -16,7 +16,9 @@ __raw_writel(value, (CTRL_BASE + offset));
/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 19) +#define DSPULLUDEN (0x1 << 27) /* DS0 mode Pull-Up/Down enable */ +#define DSPULLUDDIS (0x0 << 27) /* DS0 mode Pull-Up/Down Disable */ +#define SLEWCTRL (0x1 << 19) /* Slow slew rate selection */ #define RXACTIVE (0x1 << 18) #define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ #define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 700e9a7..818a046 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -12,8 +12,26 @@ #include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */{OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */
{OFFSET(uart0_rxd),(MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL | DSPULLUDEN)},{OFFSET(uart0_txd),(MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL | DSPULLUDEN)},{-1},+};
+static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{-1},Hmm i don't think updating the DSPULL here is a good idea. Since not all the pins are used in U-Boot, this is just partially updating the pulls for the low power state. I would suggest leaving this bit for the kernel where things can be updated without updating the bootloader.
These are the preferred settings given to me. Any way if kernel is updating it overwrites these settings, it shouldn't matter I guess..:)
It's better to clearly list down what configuration a particular entity in the system is responsible for. Doing partial updates her just makes issues harder to debug.
Regards, Vaibhav
On Wednesday 06 November 2013 10:11 PM, Vaibhav Bedia wrote:
On Wed, Nov 6, 2013 at 8:32 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
On Wednesday 06 November 2013 06:13 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Updating the mux data for UART, and adding data for i2c0 and mmc.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 4 +++- board/ti/am43xx/mux.c | 24 ++++++++++++++++++++++-- 2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index 0206912..e95efdd 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -16,7 +16,9 @@ __raw_writel(value, (CTRL_BASE + offset));
/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 19) +#define DSPULLUDEN (0x1 << 27) /* DS0 mode Pull-Up/Down enable */ +#define DSPULLUDDIS (0x0 << 27) /* DS0 mode Pull-Up/Down Disable */ +#define SLEWCTRL (0x1 << 19) /* Slow slew rate selection */ #define RXACTIVE (0x1 << 18) #define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ #define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 700e9a7..818a046 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -12,8 +12,26 @@ #include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */{OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */
{OFFSET(uart0_rxd),(MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL | DSPULLUDEN)},{OFFSET(uart0_txd),(MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL | DSPULLUDEN)},{-1},+};
+static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE | DSPULLUDEN)},{-1},Hmm i don't think updating the DSPULL here is a good idea. Since not all the pins are used in U-Boot, this is just partially updating the pulls for the low power state. I would suggest leaving this bit for the kernel where things can be updated without updating the bootloader.
These are the preferred settings given to me. Any way if kernel is updating it overwrites these settings, it shouldn't matter I guess..:)
It's better to clearly list down what configuration a particular entity in the system is responsible for. Doing partial updates her just makes issues harder to debug.
Ok, Ill update..
Thanks and regards, Lokesh
Regards, Vaibhav
Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM. Following are the DPLL locking frequencies at OPP NOM: MPU locks at 600MHz Core locks at 1000MHz Per locks at 960MHz DDR locks at 266MHz
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/am33xx/clock.c | 12 +++++++--- arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 15 ++++++++++++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 8 +------ arch/arm/include/asm/arch-am33xx/clock.h | 7 +++--- board/ti/am43xx/board.c | 38 +++++++++++++++++++++++++++--- board/ti/am43xx/board.h | 1 + board/ti/am43xx/mux.c | 5 ++++ 7 files changed, 69 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 8e5f3c6..0672798 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs, static void setup_dplls(void) { const struct dpll_params *params; - do_setup_dpll(&dpll_core_regs, &dpll_core); - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu); - do_setup_dpll(&dpll_per_regs, &dpll_per); + + params = get_dpll_core_params(); + do_setup_dpll(&dpll_core_regs, params); + + params = get_dpll_mpu_params(); + do_setup_dpll(&dpll_mpu_regs, params); + + params = get_dpll_per_params(); + do_setup_dpll(&dpll_per_regs, params); writel(0x300, &cmwkup->clkdcoldodpllper);
params = get_dpll_ddr_params(); diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index fabe259..92142c8 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -62,6 +62,21 @@ const struct dpll_params dpll_core = { const struct dpll_params dpll_per = { 960, OSC-1, 5, -1, -1, -1, -1};
+const struct dpll_params *get_dpll_mpu_params(void) +{ + return &dpll_mpu; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + return &dpll_core; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + return &dpll_per; +} + void setup_clocks_for_console(void) { clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 22963b7..97c00b4 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -48,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = { .cm_idlest_dpll = CM_WKUP + 0x5A4, .cm_clksel_dpll = CM_WKUP + 0x5AC, .cm_div_m2_dpll = CM_WKUP + 0x5B0, + .cm_div_m4_dpll = CM_WKUP + 0x5B8, };
-const struct dpll_params dpll_mpu = { - -1, -1, -1, -1, -1, -1, -1}; -const struct dpll_params dpll_core = { - -1, -1, -1, -1, -1, -1, -1}; -const struct dpll_params dpll_per = { - -1, -1, -1, -1, -1, -1, -1}; - void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 519249e..7637457 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs; extern const struct dpll_regs dpll_core_regs; extern const struct dpll_regs dpll_per_regs; extern const struct dpll_regs dpll_ddr_regs; -extern const struct dpll_params dpll_mpu; -extern const struct dpll_params dpll_core; -extern const struct dpll_params dpll_per; -extern const struct dpll_params dpll_ddr;
extern struct cm_wkuppll *const cmwkup;
+const struct dpll_params *get_dpll_mpu_params(void); +const struct dpll_params *get_dpll_core_params(void); +const struct dpll_params *get_dpll_per_params(void); const struct dpll_params *get_dpll_ddr_params(void); void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); void prcm_init(void); diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 723d0ca..e28e844 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -65,12 +65,44 @@ static int read_eeprom(struct am43xx_board_id *header)
#ifdef CONFIG_SPL_BUILD
-const struct dpll_params dpll_ddr = { - -1, -1, -1, -1, -1, -1, -1}; +const struct dpll_params epos_evm_dpll_ddr = { + 266, 24, 1, -1, 1, -1, -1}; +const struct dpll_params epos_evm_dpll_mpu = { + 600, 24, 1, -1, -1, -1, -1}; +const struct dpll_params epos_evm_dpll_core = { + 1000, 24, -1, -1, 10, 8, 4}; +const struct dpll_params epos_evm_dpll_per = { + 960, 24, 5, -1, -1, -1, -1};
const struct dpll_params *get_dpll_ddr_params(void) { - return &dpll_ddr; + if (board_is_eposevm()) + return &epos_evm_dpll_ddr; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + if (board_is_eposevm()) + return &epos_evm_dpll_mpu; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + struct am43xx_board_id header; + + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + if (board_is_eposevm()) + return &epos_evm_dpll_core; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + if (board_is_eposevm()) + return &epos_evm_dpll_per; }
void set_uart_mux_conf(void) diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 9268895..beee770 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -46,4 +46,5 @@ static inline int board_is_gpevm(void)
void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); #endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 818a046..341214d 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -45,3 +45,8 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); } + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +}
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM. Following are the DPLL locking frequencies at OPP NOM: MPU locks at 600MHz Core locks at 1000MHz Per locks at 960MHz DDR locks at 266MHz
Why is this not reading the eFuses to detect what speeds are actually supported on a device? If the eFuses are not currently blown it's much much safer to start off from the slowest OPP. Things might be working fine now but dialing to a high frequency without detecting the supported rates is going to come back to haunt us later.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/cpu/armv7/am33xx/clock.c | 12 +++++++--- arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 15 ++++++++++++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 8 +------ arch/arm/include/asm/arch-am33xx/clock.h | 7 +++--- board/ti/am43xx/board.c | 38 +++++++++++++++++++++++++++--- board/ti/am43xx/board.h | 1 + board/ti/am43xx/mux.c | 5 ++++ 7 files changed, 69 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 8e5f3c6..0672798 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs, static void setup_dplls(void) { const struct dpll_params *params;
do_setup_dpll(&dpll_core_regs, &dpll_core);do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);do_setup_dpll(&dpll_per_regs, &dpll_per);
params = get_dpll_core_params();do_setup_dpll(&dpll_core_regs, params);params = get_dpll_mpu_params();do_setup_dpll(&dpll_mpu_regs, params);params = get_dpll_per_params();do_setup_dpll(&dpll_per_regs, params); writel(0x300, &cmwkup->clkdcoldodpllper); params = get_dpll_ddr_params();diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index fabe259..92142c8 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -62,6 +62,21 @@ const struct dpll_params dpll_core = { const struct dpll_params dpll_per = { 960, OSC-1, 5, -1, -1, -1, -1};
+const struct dpll_params *get_dpll_mpu_params(void) +{
return &dpll_mpu;+}
+const struct dpll_params *get_dpll_core_params(void) +{
return &dpll_core;+}
+const struct dpll_params *get_dpll_per_params(void) +{
return &dpll_per;+}
void setup_clocks_for_console(void) { clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 22963b7..97c00b4 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -48,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = { .cm_idlest_dpll = CM_WKUP + 0x5A4, .cm_clksel_dpll = CM_WKUP + 0x5AC, .cm_div_m2_dpll = CM_WKUP + 0x5B0,
.cm_div_m4_dpll = CM_WKUP + 0x5B8,};
-const struct dpll_params dpll_mpu = {
-1, -1, -1, -1, -1, -1, -1};-const struct dpll_params dpll_core = {
-1, -1, -1, -1, -1, -1, -1};-const struct dpll_params dpll_per = {
-1, -1, -1, -1, -1, -1, -1};void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 519249e..7637457 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs; extern const struct dpll_regs dpll_core_regs; extern const struct dpll_regs dpll_per_regs; extern const struct dpll_regs dpll_ddr_regs; -extern const struct dpll_params dpll_mpu; -extern const struct dpll_params dpll_core; -extern const struct dpll_params dpll_per; -extern const struct dpll_params dpll_ddr;
extern struct cm_wkuppll *const cmwkup;
+const struct dpll_params *get_dpll_mpu_params(void); +const struct dpll_params *get_dpll_core_params(void); +const struct dpll_params *get_dpll_per_params(void); const struct dpll_params *get_dpll_ddr_params(void); void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); void prcm_init(void); diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 723d0ca..e28e844 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -65,12 +65,44 @@ static int read_eeprom(struct am43xx_board_id *header)
#ifdef CONFIG_SPL_BUILD
-const struct dpll_params dpll_ddr = {
-1, -1, -1, -1, -1, -1, -1};+const struct dpll_params epos_evm_dpll_ddr = {
266, 24, 1, -1, 1, -1, -1};+const struct dpll_params epos_evm_dpll_mpu = {
600, 24, 1, -1, -1, -1, -1};+const struct dpll_params epos_evm_dpll_core = {
1000, 24, -1, -1, 10, 8, 4};+const struct dpll_params epos_evm_dpll_per = {
960, 24, 5, -1, -1, -1, -1};const struct dpll_params *get_dpll_ddr_params(void) {
return &dpll_ddr;
if (board_is_eposevm())return &epos_evm_dpll_ddr;+}
+const struct dpll_params *get_dpll_mpu_params(void) +{
if (board_is_eposevm())return &epos_evm_dpll_mpu;+}
+const struct dpll_params *get_dpll_core_params(void) +{
struct am43xx_board_id header;enable_i2c0_pin_mux();i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);if (read_eeprom(&header) < 0)puts("Could not get board ID.\n");if (board_is_eposevm())return &epos_evm_dpll_core;+}
+const struct dpll_params *get_dpll_per_params(void) +{
if (board_is_eposevm())return &epos_evm_dpll_per;}
void set_uart_mux_conf(void) diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 9268895..beee770 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -46,4 +46,5 @@ static inline int board_is_gpevm(void)
void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); #endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 818a046..341214d 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -45,3 +45,8 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); }
+void enable_i2c0_pin_mux(void) +{
configure_module_pin_mux(i2c0_pin_mux);+}
This change looks a bit out of place... can you add why this is needed in the commit message.
Regards, Vaibhav
On Wednesday 06 November 2013 06:18 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM. Following are the DPLL locking frequencies at OPP NOM: MPU locks at 600MHz Core locks at 1000MHz Per locks at 960MHz DDR locks at 266MHz
Why is this not reading the eFuses to detect what speeds are actually supported on a device? If the eFuses are not currently blown it's much much safer to start off from the slowest OPP. Things might be working fine now but dialing to a high frequency without detecting the supported rates is going to come back to haunt us later.
Currently these values are not blown in eFuse. Both EPOS and GP evms support OPP NOM. So there is no harm in booting at OPP NOM here. Shekar can comment more on this.
Thanks and regards, Lokesh
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/cpu/armv7/am33xx/clock.c | 12 +++++++--- arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 15 ++++++++++++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 8 +------ arch/arm/include/asm/arch-am33xx/clock.h | 7 +++--- board/ti/am43xx/board.c | 38 +++++++++++++++++++++++++++--- board/ti/am43xx/board.h | 1 + board/ti/am43xx/mux.c | 5 ++++ 7 files changed, 69 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 8e5f3c6..0672798 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs, static void setup_dplls(void) { const struct dpll_params *params;
do_setup_dpll(&dpll_core_regs, &dpll_core);do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);do_setup_dpll(&dpll_per_regs, &dpll_per);
params = get_dpll_core_params();do_setup_dpll(&dpll_core_regs, params);params = get_dpll_mpu_params();do_setup_dpll(&dpll_mpu_regs, params);params = get_dpll_per_params();do_setup_dpll(&dpll_per_regs, params); writel(0x300, &cmwkup->clkdcoldodpllper); params = get_dpll_ddr_params();diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index fabe259..92142c8 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -62,6 +62,21 @@ const struct dpll_params dpll_core = { const struct dpll_params dpll_per = { 960, OSC-1, 5, -1, -1, -1, -1};
+const struct dpll_params *get_dpll_mpu_params(void) +{
return &dpll_mpu;+}
+const struct dpll_params *get_dpll_core_params(void) +{
return &dpll_core;+}
+const struct dpll_params *get_dpll_per_params(void) +{
return &dpll_per;+}
void setup_clocks_for_console(void) { clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 22963b7..97c00b4 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -48,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = { .cm_idlest_dpll = CM_WKUP + 0x5A4, .cm_clksel_dpll = CM_WKUP + 0x5AC, .cm_div_m2_dpll = CM_WKUP + 0x5B0,
.cm_div_m4_dpll = CM_WKUP + 0x5B8,};
-const struct dpll_params dpll_mpu = {
-1, -1, -1, -1, -1, -1, -1};-const struct dpll_params dpll_core = {
-1, -1, -1, -1, -1, -1, -1};-const struct dpll_params dpll_per = {
-1, -1, -1, -1, -1, -1, -1};void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 519249e..7637457 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs; extern const struct dpll_regs dpll_core_regs; extern const struct dpll_regs dpll_per_regs; extern const struct dpll_regs dpll_ddr_regs; -extern const struct dpll_params dpll_mpu; -extern const struct dpll_params dpll_core; -extern const struct dpll_params dpll_per; -extern const struct dpll_params dpll_ddr;
extern struct cm_wkuppll *const cmwkup;
+const struct dpll_params *get_dpll_mpu_params(void); +const struct dpll_params *get_dpll_core_params(void); +const struct dpll_params *get_dpll_per_params(void); const struct dpll_params *get_dpll_ddr_params(void); void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); void prcm_init(void); diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 723d0ca..e28e844 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -65,12 +65,44 @@ static int read_eeprom(struct am43xx_board_id *header)
#ifdef CONFIG_SPL_BUILD
-const struct dpll_params dpll_ddr = {
-1, -1, -1, -1, -1, -1, -1};+const struct dpll_params epos_evm_dpll_ddr = {
266, 24, 1, -1, 1, -1, -1};+const struct dpll_params epos_evm_dpll_mpu = {
600, 24, 1, -1, -1, -1, -1};+const struct dpll_params epos_evm_dpll_core = {
1000, 24, -1, -1, 10, 8, 4};+const struct dpll_params epos_evm_dpll_per = {
960, 24, 5, -1, -1, -1, -1};const struct dpll_params *get_dpll_ddr_params(void) {
return &dpll_ddr;
if (board_is_eposevm())return &epos_evm_dpll_ddr;+}
+const struct dpll_params *get_dpll_mpu_params(void) +{
if (board_is_eposevm())return &epos_evm_dpll_mpu;+}
+const struct dpll_params *get_dpll_core_params(void) +{
struct am43xx_board_id header;enable_i2c0_pin_mux();i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);if (read_eeprom(&header) < 0)puts("Could not get board ID.\n");if (board_is_eposevm())return &epos_evm_dpll_core;+}
+const struct dpll_params *get_dpll_per_params(void) +{
if (board_is_eposevm())return &epos_evm_dpll_per;}
void set_uart_mux_conf(void) diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 9268895..beee770 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -46,4 +46,5 @@ static inline int board_is_gpevm(void)
void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); #endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 818a046..341214d 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -45,3 +45,8 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); }
+void enable_i2c0_pin_mux(void) +{
configure_module_pin_mux(i2c0_pin_mux);+}
This change looks a bit out of place... can you add why this is needed in the commit message.
Regards, Vaibhav
Adding DPLLs Multiplier and DIvider values for GP EVM Following are the DPLL locking frequencies at OPP NOM MPU locks at 600MHz Core locks at 1000MHz Per locks at 960MHz DDR locks at 400MHz
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/am43xx/board.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index e28e844..a700d1f 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -74,16 +74,29 @@ const struct dpll_params epos_evm_dpll_core = { const struct dpll_params epos_evm_dpll_per = { 960, 24, 5, -1, -1, -1, -1};
+const struct dpll_params gp_evm_dpll_ddr = { + 400, 23, 1, -1, 1, -1, -1}; +const struct dpll_params gp_evm_dpll_mpu = { + 600, 23, 1, -1, -1, -1, -1}; +const struct dpll_params gp_evm_dpll_core = { + 1000, 23, -1, -1, 10, 8, 4}; +const struct dpll_params gp_evm_dpll_per = { + 960, 23, 5, -1, -1, -1, -1}; + const struct dpll_params *get_dpll_ddr_params(void) { if (board_is_eposevm()) return &epos_evm_dpll_ddr; + else + return &gp_evm_dpll_ddr; }
const struct dpll_params *get_dpll_mpu_params(void) { if (board_is_eposevm()) return &epos_evm_dpll_mpu; + else + return &gp_evm_dpll_mpu; }
const struct dpll_params *get_dpll_core_params(void) @@ -97,12 +110,16 @@ const struct dpll_params *get_dpll_core_params(void)
if (board_is_eposevm()) return &epos_evm_dpll_core; + else + return &gp_evm_dpll_core; }
const struct dpll_params *get_dpll_per_params(void) { if (board_is_eposevm()) return &epos_evm_dpll_per; + else + return &gp_evm_dpll_per; }
void set_uart_mux_conf(void)
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
Adding DPLLs Multiplier and DIvider values for GP EVM Following are the DPLL locking frequencies at OPP NOM MPU locks at 600MHz Core locks at 1000MHz Per locks at 960MHz DDR locks at 400MHz
Comment on getting the data from eFuse or falling back to lower freq applies here too.
Regards, Vaibhav
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/am33xx/Makefile | 8 +- arch/arm/cpu/armv7/am33xx/emif4d5.c | 183 ++++++++++++++++++++ arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 3 + arch/arm/include/asm/arch-am33xx/cpu.h | 5 + arch/arm/include/asm/arch-am33xx/ddr_defs.h | 26 +++ arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 1 + arch/arm/include/asm/emif.h | 12 ++ board/ti/am43xx/board.c | 59 +++++++ 8 files changed, 295 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/emif4d5.c
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index f6a297c..8414430 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -19,12 +19,16 @@ endif COBJS-$(CONFIG_TI816X) += clock_ti816x.o COBJS += sys_info.o COBJS += mem.o -COBJS += ddr.o -COBJS += emif4.o COBJS += board.o COBJS += mux.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += elm.o
+ifeq ($(CONFIG_AM43XX),) +COBJS += ddr.o +COBJS += emif4.o +endif +COBJS-$(CONFIG_AM43XX) += emif4d5.o + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c b/arch/arm/cpu/armv7/am33xx/emif4d5.c new file mode 100644 index 0000000..eea1fa3 --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c @@ -0,0 +1,183 @@ +/* + * emif4d5.c + * + * AM43XX emif4d5 configuration file + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/emif.h> + +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; +static struct cm_device_inst *cm_device = + (struct cm_device_inst *)CM_DEVICE_INST; +static struct ddr_cmdtctrl *ioctrl_reg = + (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR; +static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + return 0; +} + +static void config_vtp(void) +{ + writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE, + &vtpreg->vtp0ctrlreg); + writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN), + &vtpreg->vtp0ctrlreg); + writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN, + &vtpreg->vtp0ctrlreg); + + while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) != + VTP_CTRL_READY) + ; +} + +static void ext_phy_settings(const struct emif_regs *regs, + const u32 *ext_phy_ctrl_const_regs) +{ + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + u32 i = 0; + + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + writel(ext_phy_ctrl_const_regs[i], + emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_regs[i], + emif_ext_phy_ctrl_base++); + } +} + +static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) +{ + u32 mr; + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + + mr = readl(&emif->emif_lpddr2_mode_reg_data); + debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr); + if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && + ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && + ((mr & 0xff000000) >> 24) == (mr & 0xff)) + return mr & 0xff; + else + return mr; +} + +static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif->emif_lpddr2_mode_reg_data); +} + +static void configure_mr(u32 base, u32 cs) +{ + u32 mr_addr; + + while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) + ; + set_mr(base, cs, LPDDR2_MR10, 0x56); + + set_mr(base, cs, LPDDR2_MR1, 0x43); + set_mr(base, cs, LPDDR2_MR2, 0x2); + + mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; + set_mr(base, cs, mr_addr, 0x2); +} + +void do_sdram_init(const struct ctrl_ioregs *ioregs, + const struct emif_regs *regs, + const u32 *ext_phy_ctrl_const_regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + config_vtp(); + + writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); + while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0) + ; + + /* io settings */ + writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl); + writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl); + writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl); + writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl); + writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl); + writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl); + writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl); + writel(ioregs->emif_sdram_config_ext, + &ioctrl_reg->emif_sdram_config_ext); + writel(0x0, &ddrctrl->ddrioctrl); + + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(readl(&ddrctrl->ddrckectrl) | 0x3, &ddrctrl->ddrckectrl); + + /* + * disable initialization and refreshes for now until we + * finish programming EMIF regs. + */ + setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); + + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); + + writel(0x0, &emif->emif_pwr_mgmt_ctrl); + writel(0x0, &emif->emif_pwr_mgmt_ctrl_shdw); + writel(0x1, &emif->emif_iodft_tlgc); + writel(regs->zq_config, &emif->emif_zq_config); + + writel(regs->temp_alert_config, &emif->emif_temp_alert_config); + writel(regs->emif_rd_wr_lvl_rmp_win, &emif->emif_rd_wr_lvl_rmp_win); + writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); + + ext_phy_settings(regs, ext_phy_ctrl_const_regs); + + clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); + + writel(regs->sdram_config, &emif->emif_sdram_config); + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); + + configure_mr(EMIF1_BASE, 0); + configure_mr(EMIF1_BASE, 1); +} diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 02ed595..4c9352a 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -28,6 +28,9 @@ #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3)
+#define CM_DLL_CTRL_NO_OVERRIDE 0x0 +#define CM_DLL_READYST 0x4 + extern void enable_dmm_clocks(void); extern const struct dpll_params dpll_core_opp100; extern struct dpll_params dpll_mpu_opp100; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index f463b27..23af125 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -401,6 +401,11 @@ struct cm_perpll { unsigned int cpgmac0clkctrl; /* offset 0xB20 */ };
+struct cm_device_inst { + unsigned int cm_clkout1_ctrl; + unsigned int cm_dll_ctrl; +}; + struct cm_dpll { unsigned int resv1; unsigned int clktimer2clk; /* offset 0x04 */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index fe48b5f..1880415 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -126,6 +126,14 @@ #define K4B2G1646EBIH9_PHY_WR_DATA 0x76 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
+#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 +#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 + /** * Configure DMM */ @@ -291,6 +299,21 @@ struct ddr_cmdtctrl { unsigned int resv2[12]; unsigned int dt0ioctl; unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int resv3[4]; + unsigned int emif_sdram_config_ext; +}; + +struct ctrl_ioregs { + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int dt0ioctl; + unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int emif_sdram_config_ext; };
/** @@ -308,4 +331,7 @@ void config_ddr(unsigned int pll, unsigned int ioctrl, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr);
+void do_sdram_init(const struct ctrl_ioregs *ioregs, + const struct emif_regs *emif_regs, + const u32 *ext_phy_ctrl_const_regs); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 4dbc789..d82f050 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -63,5 +63,6 @@ #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) #define USBPHYOCPSCP_MODULE_EN (1 << 2) +#define CM_DEVICE_INST 0x44df4100
#endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 1b94a99..5edc3a4 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -690,6 +690,18 @@ struct emif_reg_struct { u32 emif_ddr_ext_phy_ctrl_23_shdw; u32 emif_ddr_ext_phy_ctrl_24; u32 emif_ddr_ext_phy_ctrl_24_shdw; + u32 emif_ddr_ext_phy_ctrl_25; + u32 emif_ddr_ext_phy_ctrl_25_shdw; + u32 emif_ddr_ext_phy_ctrl_26; + u32 emif_ddr_ext_phy_ctrl_26_shdw; + u32 emif_ddr_ext_phy_ctrl_27; + u32 emif_ddr_ext_phy_ctrl_27_shdw; + u32 emif_ddr_ext_phy_ctrl_28; + u32 emif_ddr_ext_phy_ctrl_28_shdw; + u32 emif_ddr_ext_phy_ctrl_29; + u32 emif_ddr_ext_phy_ctrl_29_shdw; + u32 emif_ddr_ext_phy_ctrl_30; + u32 emif_ddr_ext_phy_ctrl_30_shdw; };
struct dmm_lisa_map_regs { diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index a700d1f..83d184d 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -15,6 +15,8 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mux.h> +#include <asm/arch/ddr_defs.h> +#include <asm/emif.h> #include "board.h"
DECLARE_GLOBAL_DATA_PTR; @@ -83,6 +85,61 @@ const struct dpll_params gp_evm_dpll_core = { const struct dpll_params gp_evm_dpll_per = { 960, 23, 5, -1, -1, -1, -1};
+const struct ctrl_ioregs ioregs_lpddr2 = { + .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x1, +}; + +const struct emif_regs emif_regs_lpddr2 = { + .sdram_config = 0x808012BA, + .ref_ctrl = 0x0000040D, + .sdram_tim1 = 0xEA86B411, + .sdram_tim2 = 0x103A094A, + .sdram_tim3 = 0x0F6BA37F, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E084006, + .emif_rd_wr_exec_thresh = 0x00000405, + .emif_ddr_ext_phy_ctrl_1 = 0x04010040, + .emif_ddr_ext_phy_ctrl_2 = 0x00500050, + .emif_ddr_ext_phy_ctrl_3 = 0x00500050, + .emif_ddr_ext_phy_ctrl_4 = 0x00500050, + .emif_ddr_ext_phy_ctrl_5 = 0x00500050 +}; + +const u32 ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x00500050, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40001000, + 0x08102040 +}; + const struct dpll_params *get_dpll_ddr_params(void) { if (board_is_eposevm()) @@ -134,6 +191,8 @@ void set_mux_conf_regs(void)
void sdram_init(void) { + do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2, + ext_phy_ctrl_const_base_lpddr2); } #endif
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers.
Is there any public documentation to go with this? I would suggest sprinkling the code with comments to mention the different stages.
BTW, no IO powerdown setting for now?
[...]
+ifeq ($(CONFIG_AM43XX),) +COBJS += ddr.o +COBJS += emif4.o +endif +COBJS-$(CONFIG_AM43XX) += emif4d5.o
Are the steps really different enough to warrant a new file? Can't the changes be handled properly in the code? How has this been handled in OMAPx where DDR3 and LPDDR both are supported?
Regards, Vaibhav
On Wednesday 06 November 2013 06:27 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers.
Is there any public documentation to go with this? I would suggest sprinkling the code with comments to mention the different stages.
Yep ll add the comments in the code..
BTW, no IO powerdown setting for now?
You mean DDR IO settings?
[...]
+ifeq ($(CONFIG_AM43XX),) +COBJS += ddr.o +COBJS += emif4.o +endif +COBJS-$(CONFIG_AM43XX) += emif4d5.o
Are the steps really different enough to warrant a new file? Can't the changes be handled properly in the code? How has this been handled in OMAPx where DDR3 and LPDDR both are supported?
Initially Tom also suggested not to use a new file. I tried with not to add a new file, but I ended up with many #ifdefs. EMIF is new IP(reused from OMAP5) very different from AM33xx EMIF IP. So to make things more cleaner I had to use a new file..
Thanks and regards, Lokesh
Regards, Vaibhav
On Wed, Nov 6, 2013 at 8:45 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
On Wednesday 06 November 2013 06:27 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers.
Is there any public documentation to go with this? I would suggest sprinkling the code with comments to mention the different stages.
Yep ll add the comments in the code..
BTW, no IO powerdown setting for now?
You mean DDR IO settings?
Yeah. I assume you have configured the dynamic power down bit properly. Can't tell without looking at the TRM.
[...]
+ifeq ($(CONFIG_AM43XX),) +COBJS += ddr.o +COBJS += emif4.o +endif +COBJS-$(CONFIG_AM43XX) += emif4d5.o
Are the steps really different enough to warrant a new file? Can't the changes be handled properly in the code? How has this been handled in OMAPx where DDR3 and LPDDR both are supported?
Initially Tom also suggested not to use a new file. I tried with not to add a new file, but I ended up with many #ifdefs. EMIF is new IP(reused from OMAP5) very different from AM33xx EMIF IP. So to make things more cleaner I had to use a new file..
It really looks a step backward. The new IP should be an update to the old version and not just a complete overhaul of the programming model that folks are familiar with.
Regards, Vaibhav
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
On 11/06/2013 11:44 AM, Vaibhav Bedia wrote:
On Wed, Nov 6, 2013 at 8:45 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
On Wednesday 06 November 2013 06:27 PM, Vaibhav Bedia wrote:
[snip]
Are the steps really different enough to warrant a new file? Can't the changes be handled properly in the code? How has this been handled in OMAPx where DDR3 and LPDDR both are supported?
Initially Tom also suggested not to use a new file. I tried with not to add a new file, but I ended up with many #ifdefs. EMIF is new IP(reused from OMAP5) very different from AM33xx EMIF IP. So to make things more cleaner I had to use a new file..
It really looks a step backward. The new IP should be an update to the old version and not just a complete overhaul of the programming model that folks are familiar with.
It sounds like we need to re-think the EMIF code here since it's not all THAT different between the OMAP parts, the am33xx parts, the am43xx parts and the ti81xx parts (and even the am35xx parts, but I'm OK setting that aside).
And no, I'm not 100% happy with the OMAP code either, but that's mainly the bits where we say OMAP rev FOO means memory chip BAR.
- -- Tom
GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/am33xx/emif4d5.c | 8 ++- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 ++- board/ti/am43xx/board.c | 89 ++++++++++++++++++++++++++- 3 files changed, 101 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c b/arch/arm/cpu/armv7/am33xx/emif4d5.c index eea1fa3..8bac0f2 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4d5.c +++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c @@ -120,7 +120,7 @@ static void configure_mr(u32 base, u32 cs)
void do_sdram_init(const struct ctrl_ioregs *ioregs, const struct emif_regs *regs, - const u32 *ext_phy_ctrl_const_regs) + const u32 *ext_phy_ctrl_const_regs, u32 sdram_type) { struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
@@ -178,6 +178,8 @@ void do_sdram_init(const struct ctrl_ioregs *ioregs, writel(regs->sdram_config, &emif->emif_sdram_config); writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
- configure_mr(EMIF1_BASE, 0); - configure_mr(EMIF1_BASE, 1); + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) { + configure_mr(EMIF1_BASE, 0); + configure_mr(EMIF1_BASE, 1); + } } diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 1880415..796e9df 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -134,6 +134,14 @@ #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
+#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84 + /** * Configure DMM */ @@ -333,5 +341,5 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
void do_sdram_init(const struct ctrl_ioregs *ioregs, const struct emif_regs *emif_regs, - const u32 *ext_phy_ctrl_const_regs); + const u32 *ext_phy_ctrl_const_regs, u32 ddr_type); #endif /* _DDR_DEFS_H */ diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 83d184d..a943b45 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -140,6 +140,57 @@ const u32 ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x08102040 };
+const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x0043, +}; + +const struct emif_regs ddr3_emif_regs_400Mhz = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E084007, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00400040, + .emif_ddr_ext_phy_ctrl_3 = 0x00400040, + .emif_ddr_ext_phy_ctrl_4 = 0x00400040, + .emif_ddr_ext_phy_ctrl_5 = 0x00400040 +}; + +const u32 ext_phy_ctrl_const_base_ddr3[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x00400040, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00340034, + 0x00340034, + 0x00340034, + 0x00340034, + 0x00340034, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + const struct dpll_params *get_dpll_ddr_params(void) { if (board_is_eposevm()) @@ -189,10 +240,44 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); }
+static void enable_vtt_regulator(void) +{ + u32 temp; + + /*GPIO_VTTEN - GPIO0_21 PINMUX Setup*/ + writel(0x20009, CTRL_BASE + 0x0A60); + + writel(0x40002, PRCM_BASE + 0x2B68); + + /* Poll if module is functional */ + while ((readl(PRCM_BASE + 0x2B68) & 0x30000) != 0x0) + ; + + while ((readl(PRCM_BASE + 0x2B00) & 0x100) != 0x100) + ; + + /* enable module */ + writel(0x0, GPIO0_BASE + 0x0130); + + /*enable output for GPIO0_21*/ + writel((1 << 22), GPIO0_BASE + 0x0194); + temp = readl(GPIO0_BASE + 0x0134); + temp = temp & ~(1 << 22); + writel(temp, GPIO0_BASE + 0x0134); +} + void sdram_init(void) { - do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2, - ext_phy_ctrl_const_base_lpddr2); + if (board_is_eposevm()) { + do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2, + ext_phy_ctrl_const_base_lpddr2, + EMIF_SDRAM_TYPE_LPDDR2); + } else { + enable_vtt_regulator(); + do_sdram_init(&ioregs_ddr3, &ddr3_emif_regs_400Mhz, + ext_phy_ctrl_const_base_ddr3, + EMIF_SDRAM_TYPE_DDR3); + } } #endif
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers.
Temp alert? Is that really relevant here?
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/cpu/armv7/am33xx/emif4d5.c | 8 ++- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 ++- board/ti/am43xx/board.c | 89 ++++++++++++++++++++++++++- 3 files changed, 101 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c b/arch/arm/cpu/armv7/am33xx/emif4d5.c index eea1fa3..8bac0f2 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4d5.c +++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c @@ -120,7 +120,7 @@ static void configure_mr(u32 base, u32 cs)
void do_sdram_init(const struct ctrl_ioregs *ioregs, const struct emif_regs *regs,
const u32 *ext_phy_ctrl_const_regs)
const u32 *ext_phy_ctrl_const_regs, u32 sdram_type){ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
@@ -178,6 +178,8 @@ void do_sdram_init(const struct ctrl_ioregs *ioregs, writel(regs->sdram_config, &emif->emif_sdram_config); writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
configure_mr(EMIF1_BASE, 0);configure_mr(EMIF1_BASE, 1);
if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) {configure_mr(EMIF1_BASE, 0);configure_mr(EMIF1_BASE, 1);}} diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 1880415..796e9df 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -134,6 +134,14 @@ #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
+#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84
/**
- Configure DMM
*/ @@ -333,5 +341,5 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
void do_sdram_init(const struct ctrl_ioregs *ioregs, const struct emif_regs *emif_regs,
const u32 *ext_phy_ctrl_const_regs);
const u32 *ext_phy_ctrl_const_regs, u32 ddr_type);#endif /* _DDR_DEFS_H */ diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 83d184d..a943b45 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -140,6 +140,57 @@ const u32 ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x08102040 };
+const struct ctrl_ioregs ioregs_ddr3 = {
.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,.cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,.dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,.emif_sdram_config_ext = 0x0043,+};
+const struct emif_regs ddr3_emif_regs_400Mhz = {
.sdram_config = 0x638413B2,.ref_ctrl = 0x00000C30,.sdram_tim1 = 0xEAAAD4DB,.sdram_tim2 = 0x266B7FDA,.sdram_tim3 = 0x107F8678,.read_idle_ctrl = 0x00050000,.zq_config = 0x50074BE4,.temp_alert_config = 0x0,.emif_ddr_phy_ctlr_1 = 0x0E084007,.emif_ddr_ext_phy_ctrl_1 = 0x08020080,.emif_ddr_ext_phy_ctrl_2 = 0x00400040,.emif_ddr_ext_phy_ctrl_3 = 0x00400040,.emif_ddr_ext_phy_ctrl_4 = 0x00400040,.emif_ddr_ext_phy_ctrl_5 = 0x00400040+};
+const u32 ext_phy_ctrl_const_base_ddr3[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00400040,0x00350035,0x00350035,0x00350035,0x00350035,0x00350035,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00340034,0x00340034,0x00340034,0x00340034,0x00340034,0x0,0x0,0x40000000,0x08102040+};
const struct dpll_params *get_dpll_ddr_params(void) { if (board_is_eposevm()) @@ -189,10 +240,44 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); }
+static void enable_vtt_regulator(void) +{
u32 temp;/*GPIO_VTTEN - GPIO0_21 PINMUX Setup*/writel(0x20009, CTRL_BASE + 0x0A60);writel(0x40002, PRCM_BASE + 0x2B68);/* Poll if module is functional */while ((readl(PRCM_BASE + 0x2B68) & 0x30000) != 0x0);while ((readl(PRCM_BASE + 0x2B00) & 0x100) != 0x100);/* enable module */writel(0x0, GPIO0_BASE + 0x0130);/*enable output for GPIO0_21*/writel((1 << 22), GPIO0_BASE + 0x0194);temp = readl(GPIO0_BASE + 0x0134);temp = temp & ~(1 << 22);writel(temp, GPIO0_BASE + 0x0134);
That's a lot of direct register writes :P
Can't you use some proper APIs for doing the pinmux, enabling the modules and controlling the GPIO?
+}
void sdram_init(void) {
do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2,ext_phy_ctrl_const_base_lpddr2);
if (board_is_eposevm()) {do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2,ext_phy_ctrl_const_base_lpddr2,EMIF_SDRAM_TYPE_LPDDR2);} else {enable_vtt_regulator();
Hmm there must a smarter way of finding out whether the VTT regulator is present or not? You can always have DDR3 setups which don't use the regulator. Why not get this added to the EEPROM?
Regards, Vaibhav
On Wednesday 06 November 2013 06:32 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers.
Temp alert? Is that really relevant here?
Yes, Need to configure all the emif registers before accessing SDRAM.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/cpu/armv7/am33xx/emif4d5.c | 8 ++- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 ++- board/ti/am43xx/board.c | 89 ++++++++++++++++++++++++++- 3 files changed, 101 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c b/arch/arm/cpu/armv7/am33xx/emif4d5.c index eea1fa3..8bac0f2 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4d5.c +++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c @@ -120,7 +120,7 @@ static void configure_mr(u32 base, u32 cs)
void do_sdram_init(const struct ctrl_ioregs *ioregs, const struct emif_regs *regs,
const u32 *ext_phy_ctrl_const_regs)
const u32 *ext_phy_ctrl_const_regs, u32 sdram_type){ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
@@ -178,6 +178,8 @@ void do_sdram_init(const struct ctrl_ioregs *ioregs, writel(regs->sdram_config, &emif->emif_sdram_config); writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
configure_mr(EMIF1_BASE, 0);configure_mr(EMIF1_BASE, 1);
if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) {configure_mr(EMIF1_BASE, 0);configure_mr(EMIF1_BASE, 1);}} diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 1880415..796e9df 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -134,6 +134,14 @@ #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
+#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84
/**
- Configure DMM
*/ @@ -333,5 +341,5 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
void do_sdram_init(const struct ctrl_ioregs *ioregs, const struct emif_regs *emif_regs,
const u32 *ext_phy_ctrl_const_regs);
const u32 *ext_phy_ctrl_const_regs, u32 ddr_type);#endif /* _DDR_DEFS_H */ diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 83d184d..a943b45 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -140,6 +140,57 @@ const u32 ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x08102040 };
+const struct ctrl_ioregs ioregs_ddr3 = {
.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,.cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,.dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,.emif_sdram_config_ext = 0x0043,+};
+const struct emif_regs ddr3_emif_regs_400Mhz = {
.sdram_config = 0x638413B2,.ref_ctrl = 0x00000C30,.sdram_tim1 = 0xEAAAD4DB,.sdram_tim2 = 0x266B7FDA,.sdram_tim3 = 0x107F8678,.read_idle_ctrl = 0x00050000,.zq_config = 0x50074BE4,.temp_alert_config = 0x0,.emif_ddr_phy_ctlr_1 = 0x0E084007,.emif_ddr_ext_phy_ctrl_1 = 0x08020080,.emif_ddr_ext_phy_ctrl_2 = 0x00400040,.emif_ddr_ext_phy_ctrl_3 = 0x00400040,.emif_ddr_ext_phy_ctrl_4 = 0x00400040,.emif_ddr_ext_phy_ctrl_5 = 0x00400040+};
+const u32 ext_phy_ctrl_const_base_ddr3[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00400040,0x00350035,0x00350035,0x00350035,0x00350035,0x00350035,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00340034,0x00340034,0x00340034,0x00340034,0x00340034,0x0,0x0,0x40000000,0x08102040+};
const struct dpll_params *get_dpll_ddr_params(void) { if (board_is_eposevm()) @@ -189,10 +240,44 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); }
+static void enable_vtt_regulator(void) +{
u32 temp;/*GPIO_VTTEN - GPIO0_21 PINMUX Setup*/writel(0x20009, CTRL_BASE + 0x0A60);writel(0x40002, PRCM_BASE + 0x2B68);/* Poll if module is functional */while ((readl(PRCM_BASE + 0x2B68) & 0x30000) != 0x0);while ((readl(PRCM_BASE + 0x2B00) & 0x100) != 0x100);/* enable module */writel(0x0, GPIO0_BASE + 0x0130);/*enable output for GPIO0_21*/writel((1 << 22), GPIO0_BASE + 0x0194);temp = readl(GPIO0_BASE + 0x0134);temp = temp & ~(1 << 22);writel(temp, GPIO0_BASE + 0x0134);That's a lot of direct register writes :P
He he.. Completely missed it. Thanks for pointing it out. LL update it..:)
Can't you use some proper APIs for doing the pinmux, enabling the modules and controlling the GPIO?
+}
void sdram_init(void) {
do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2,ext_phy_ctrl_const_base_lpddr2);
if (board_is_eposevm()) {do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2,ext_phy_ctrl_const_base_lpddr2,EMIF_SDRAM_TYPE_LPDDR2);} else {enable_vtt_regulator();Hmm there must a smarter way of finding out whether the VTT regulator is present or not? You can always have DDR3 setups which don't use the regulator. Why not get this added to the EEPROM?
Hmm.. I am not sure. LL check it and update in V2.
Thanks and regards, Lokesh
Regards, Vaibhav
On Wed, Nov 6, 2013 at 8:54 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
On Wednesday 06 November 2013 06:32 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers.
Temp alert? Is that really relevant here?
Yes, Need to configure all the emif registers before accessing SDRAM.
Ok. What's done on an AM437x system when the temp goes beyond a threshold?
Regards, Vaibhav
Hi Vaibhav, On Wednesday 06 November 2013 07:24 PM, Lokesh Vutla wrote:
On Wednesday 06 November 2013 06:32 PM, Vaibhav Bedia wrote:
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers.
Temp alert? Is that really relevant here?
Yes, Need to configure all the emif registers before accessing SDRAM.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/cpu/armv7/am33xx/emif4d5.c | 8 ++- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 10 ++- board/ti/am43xx/board.c | 89 ++++++++++++++++++++++++++- 3 files changed, 101 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4d5.c b/arch/arm/cpu/armv7/am33xx/emif4d5.c index eea1fa3..8bac0f2 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4d5.c +++ b/arch/arm/cpu/armv7/am33xx/emif4d5.c @@ -120,7 +120,7 @@ static void configure_mr(u32 base, u32 cs)
void do_sdram_init(const struct ctrl_ioregs *ioregs, const struct emif_regs *regs,
const u32 *ext_phy_ctrl_const_regs)
const u32 *ext_phy_ctrl_const_regs, u32 sdram_type){ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
@@ -178,6 +178,8 @@ void do_sdram_init(const struct ctrl_ioregs *ioregs, writel(regs->sdram_config, &emif->emif_sdram_config); writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
configure_mr(EMIF1_BASE, 0);configure_mr(EMIF1_BASE, 1);
if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) {configure_mr(EMIF1_BASE, 0);configure_mr(EMIF1_BASE, 1);}} diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 1880415..796e9df 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -134,6 +134,14 @@ #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
+#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84
/**
- Configure DMM
*/ @@ -333,5 +341,5 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
void do_sdram_init(const struct ctrl_ioregs *ioregs, const struct emif_regs *emif_regs,
const u32 *ext_phy_ctrl_const_regs);
const u32 *ext_phy_ctrl_const_regs, u32 ddr_type);#endif /* _DDR_DEFS_H */ diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 83d184d..a943b45 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -140,6 +140,57 @@ const u32 ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x08102040 };
+const struct ctrl_ioregs ioregs_ddr3 = {
.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,.cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,.dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,.emif_sdram_config_ext = 0x0043,+};
+const struct emif_regs ddr3_emif_regs_400Mhz = {
.sdram_config = 0x638413B2,.ref_ctrl = 0x00000C30,.sdram_tim1 = 0xEAAAD4DB,.sdram_tim2 = 0x266B7FDA,.sdram_tim3 = 0x107F8678,.read_idle_ctrl = 0x00050000,.zq_config = 0x50074BE4,.temp_alert_config = 0x0,.emif_ddr_phy_ctlr_1 = 0x0E084007,.emif_ddr_ext_phy_ctrl_1 = 0x08020080,.emif_ddr_ext_phy_ctrl_2 = 0x00400040,.emif_ddr_ext_phy_ctrl_3 = 0x00400040,.emif_ddr_ext_phy_ctrl_4 = 0x00400040,.emif_ddr_ext_phy_ctrl_5 = 0x00400040+};
+const u32 ext_phy_ctrl_const_base_ddr3[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00400040,0x00350035,0x00350035,0x00350035,0x00350035,0x00350035,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00340034,0x00340034,0x00340034,0x00340034,0x00340034,0x0,0x0,0x40000000,0x08102040+};
const struct dpll_params *get_dpll_ddr_params(void) { if (board_is_eposevm()) @@ -189,10 +240,44 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); }
+static void enable_vtt_regulator(void) +{
u32 temp;/*GPIO_VTTEN - GPIO0_21 PINMUX Setup*/writel(0x20009, CTRL_BASE + 0x0A60);writel(0x40002, PRCM_BASE + 0x2B68);/* Poll if module is functional */while ((readl(PRCM_BASE + 0x2B68) & 0x30000) != 0x0);while ((readl(PRCM_BASE + 0x2B00) & 0x100) != 0x100);/* enable module */writel(0x0, GPIO0_BASE + 0x0130);/*enable output for GPIO0_21*/writel((1 << 22), GPIO0_BASE + 0x0194);temp = readl(GPIO0_BASE + 0x0134);temp = temp & ~(1 << 22);writel(temp, GPIO0_BASE + 0x0134);That's a lot of direct register writes :P
He he.. Completely missed it. Thanks for pointing it out. LL update it..:)
Can't you use some proper APIs for doing the pinmux, enabling the modules and controlling the GPIO?
+}
void sdram_init(void) {
do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2,ext_phy_ctrl_const_base_lpddr2);
if (board_is_eposevm()) {do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2,ext_phy_ctrl_const_base_lpddr2,EMIF_SDRAM_TYPE_LPDDR2);} else {enable_vtt_regulator();Hmm there must a smarter way of finding out whether the VTT regulator is present or not? You can always have DDR3 setups which don't use the regulator. Why not get this added to the EEPROM?
I checked with hardware folks. There is no register or some way to tell if VTT is present. It is not added in EEPROM also and I have no answer why it is not added in EEPROM..:( It is specific to boards using DDR3. So its good to have it in board files as I did it here instead of adding this check in emif file.
Thanks and regards, Lokesh
Hmm.. I am not sure. LL check it and update in V2.
Thanks and regards, Lokesh
Regards, Vaibhav
On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla lokeshvutla@ti.com wrote: [...]
I checked with hardware folks. There is no register or some way to tell if VTT is present. It is not added in EEPROM also and I have no answer why it is not added in EEPROM..:( It is specific to boards using DDR3. So its good to have it in board files as I did it here instead of adding this check in emif file.
That EEPROM is clearly not getting used the way i think it should be :\ I would have made a lot of noise to get details like this added there.
You should at least check for the GP EVM (if possible) and then enable VTT. Doing this unconditionally is bound to cause problems later on. I would also put in a big comment over there so that folks who design their own board with DDR3 don't miss this fact.
Regards, Vaibhav
Hi Vaibhav,
On 11/13/2013 7:38 PM, Vaibhav Bedia wrote:
On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla lokeshvutla@ti.com wrote: [...]
I checked with hardware folks. There is no register or some way to tell if VTT is present. It is not added in EEPROM also and I have no answer why it is not added in EEPROM..:( It is specific to boards using DDR3. So its good to have it in board files as I did it here instead of adding this check in emif file.
That EEPROM is clearly not getting used the way i think it should be :\ I would have made a lot of noise to get details like this added there.
The EEPROM was designed as a way to differentiate between different TI EVMs, not as a generic way to differentiate between various possible board hook-ups. Even if we did define it that way, why would all boards using AM437x have an onboard EEPROM?
We could request this information be placed in EEPROM and see if hardware folks oblige, but I don't see how that's going to be used beyond TI EVMs.
Thanks, Sekhar
Hi Sekhar :)
On Wed, Nov 13, 2013 at 11:08 AM, Sekhar Nori nsekhar@ti.com wrote:
Hi Vaibhav,
On 11/13/2013 7:38 PM, Vaibhav Bedia wrote:
On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla lokeshvutla@ti.com wrote: [...]
I checked with hardware folks. There is no register or some way to tell if VTT is present. It is not added in EEPROM also and I have no answer why it is not added in EEPROM..:( It is specific to boards using DDR3. So its good to have it in board files as I did it here instead of adding this check in emif file.
That EEPROM is clearly not getting used the way i think it should be :\ I would have made a lot of noise to get details like this added there.
The EEPROM was designed as a way to differentiate between different TI EVMs, not as a generic way to differentiate between various possible board hook-ups. Even if we did define it that way, why would all boards using AM437x have an onboard EEPROM?
We could request this information be placed in EEPROM and see if hardware folks oblige, but I don't see how that's going to be used beyond TI EVMs.
I understand the intent of customers to get rid of all the components they can to lower the cost. But if one just thinks about this a bit more, the current solution does a half-hearted attempt to differentiate the boards variants. It doesn't really capture the differences that are there and that is leading to hard coding to a certain extent.
From AM335x boards we should now have a decent idea of what
things change across boards that go into production. I don't think it makes sense to throw away all that knowledge and go ahead assuming we will never make a change. The request for change is just to future proof the current code and have the EEPROM actually help us do our jobs. Why? Because life's too short to keep worrying about why a board rev that a you pick up from a neighbor's desk doesn't boot, hooking up the JTAG to trace the DDR setup code, figure out what needs to change in the boot-loader, add in the appropriate check and then get to the task at hand ;)
Regards, Vaibhav
On Wed, Nov 13, 2013 at 12:50:50PM -0500, Vaibhav Bedia wrote:
Hi Sekhar :)
On Wed, Nov 13, 2013 at 11:08 AM, Sekhar Nori nsekhar@ti.com wrote:
Hi Vaibhav,
On 11/13/2013 7:38 PM, Vaibhav Bedia wrote:
On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla lokeshvutla@ti.com wrote: [...]
I checked with hardware folks. There is no register or some way to tell if VTT is present. It is not added in EEPROM also and I have no answer why it is not added in EEPROM..:( It is specific to boards using DDR3. So its good to have it in board files as I did it here instead of adding this check in emif file.
That EEPROM is clearly not getting used the way i think it should be :\ I would have made a lot of noise to get details like this added there.
The EEPROM was designed as a way to differentiate between different TI EVMs, not as a generic way to differentiate between various possible board hook-ups. Even if we did define it that way, why would all boards using AM437x have an onboard EEPROM?
We could request this information be placed in EEPROM and see if hardware folks oblige, but I don't see how that's going to be used beyond TI EVMs.
I understand the intent of customers to get rid of all the components they can to lower the cost. But if one just thinks about this a bit more, the current solution does a half-hearted attempt to differentiate the boards variants. It doesn't really capture the differences that are there and that is leading to hard coding to a certain extent.
From AM335x boards we should now have a decent idea of what things change across boards that go into production. I don't think it makes sense to throw away all that knowledge and go ahead assuming we will never make a change. The request for change is just to future proof the current code and have the EEPROM actually help us do our jobs. Why? Because life's too short to keep worrying about why a board rev that a you pick up from a neighbor's desk doesn't boot, hooking up the JTAG to trace the DDR setup code, figure out what needs to change in the boot-loader, add in the appropriate check and then get to the task at hand ;)
In theory, one could also learn from the customers that did keep the EEPROM about what additional information they programmed in.
I think however, the most likely outcome here is that we'll be able to only rely on the board name (and rev) part of the EEPROM being populated and the board code should be clear and well commented about non-obvious things such as design choice A means B is required.
On Wed, Nov 13, 2013 at 09:08:29AM -0500, Vaibhav Bedia wrote:
On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla lokeshvutla@ti.com wrote: [...]
I checked with hardware folks. There is no register or some way to tell if VTT is present. It is not added in EEPROM also and I have no answer why it is not added in EEPROM..:( It is specific to boards using DDR3. So its good to have it in board files as I did it here instead of adding this check in emif file.
That EEPROM is clearly not getting used the way i think it should be :\ I would have made a lot of noise to get details like this added there.
You should at least check for the GP EVM (if possible) and then enable VTT. Doing this unconditionally is bound to cause problems later on. I would also put in a big comment over there so that folks who design their own board with DDR3 don't miss this fact.
I agree, the code should be doing a check for what board we're on and enabling VTT, and a good comment about what's going on here.
Adding Maintainer for AM43xx.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- boards.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/boards.cfg b/boards.cfg index 5e10125..52db48d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -263,7 +263,7 @@ Active arm armv7 am33xx ti am335x Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=1,NAND Tom Rini trini@ti.com Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=1,NAND Tom Rini trini@ti.com Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini trini@ti.com -Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 - +Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla lokeshvutla@ti.com Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter mporter@ti.com Active arm armv7 am33xx ti ti816x ti816x_evm - - Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen voice.shen@atmel.com
participants (4)
-
Lokesh Vutla -
Sekhar Nori -
Tom Rini -
Vaibhav Bedia