[PATCH 0/5] ARM: khadas-vim3: enable PCIe and NVMe
This adds the missing bits to enable PCIe and NVMe support in U-Boot for the Khadas VIM3 & VIM3L board.
This serie depends on [1].
[1] https://patchwork.ozlabs.org/project/uboot/cover/20210325144921.1791892-1-na...
Neil Armstrong (5): clk: meson-g12a: add PCIe gates phy: meson-g12a-usb3-pcie: add support for PCIe ops arm: dts: meson-khadas-vim3: enable PCIe in U-boot configs: khadas-vim3: enable PCIe and NVMe configs: meson64: add NVME boot target
arch/arm/dts/meson-khadas-vim3-u-boot.dtsi | 4 ++ configs/khadas-vim3_defconfig | 5 ++ configs/khadas-vim3l_defconfig | 5 ++ drivers/clk/meson/g12a.c | 2 + drivers/phy/meson-g12a-usb3-pcie.c | 81 ++++++++++++++++++++-- include/configs/meson64.h | 7 ++ 6 files changed, 100 insertions(+), 4 deletions(-)
Add missing gates used for PCIe.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/clk/meson/g12a.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 5058db1a47..e4fed8ddfb 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -120,7 +120,9 @@ static struct meson_gate gates[NUM_CLKS] = { MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26), MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3), MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16), + MESON_GATE(CLKID_PCIE_COMB, HHI_GCLK_MPEG1, 24), MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 25), + MESON_GATE(CLKID_PCIE_PHY, HHI_GCLK_MPEG1, 27), MESON_GATE(CLKID_HTX_PCLK, HHI_GCLK_MPEG2, 4), MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8), MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
Add the PCIe part of the G12A USB3 PCIe Combo PHY driver.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/phy/meson-g12a-usb3-pcie.c | 81 ++++++++++++++++++++++++++++-- 1 file changed, 77 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/meson-g12a-usb3-pcie.c b/drivers/phy/meson-g12a-usb3-pcie.c index 0433d93474..8f72b5a6a7 100644 --- a/drivers/phy/meson-g12a-usb3-pcie.c +++ b/drivers/phy/meson-g12a-usb3-pcie.c @@ -23,6 +23,9 @@ #include <linux/compat.h> #include <linux/bitfield.h>
+#define PHY_TYPE_PCIE 2 +#define PHY_TYPE_USB3 4 + #define PHY_R0 0x00 #define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0) #define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5) @@ -55,6 +58,8 @@ #define PHY_R5_PHY_CR_ACK BIT(16) #define PHY_R5_PHY_BS_OUT BIT(17)
+#define PCIE_RESET_DELAY 500 + struct phy_g12a_usb3_pcie_priv { struct regmap *regmap; #if CONFIG_IS_ENABLED(CLK) @@ -202,8 +207,6 @@ static int phy_meson_g12a_usb3_init(struct phy *phy) unsigned int data; int ret;
- /* TOFIX Handle PCIE mode */ - ret = reset_assert_bulk(&priv->resets); udelay(1); ret |= reset_deassert_bulk(&priv->resets); @@ -296,9 +299,79 @@ static int phy_meson_g12a_usb3_exit(struct phy *phy) return reset_assert_bulk(&priv->resets); }
+static int phy_meson_g12a_usb3_pcie_init(struct phy *phy) +{ + if (phy->id == PHY_TYPE_USB3) + return phy_meson_g12a_usb3_init(phy); + + return 0; +} + +static int phy_meson_g12a_usb3_pcie_exit(struct phy *phy) +{ + if (phy->id == PHY_TYPE_USB3) + return phy_meson_g12a_usb3_exit(phy); + + return 0; +} + +static int phy_meson_g12a_usb3_pcie_power_on(struct phy *phy) +{ + struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev); + + if (phy->id == PHY_TYPE_USB3) + return 0; + + regmap_update_bits(priv->regmap, PHY_R0, + PHY_R0_PCIE_POWER_STATE, + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c)); + + return 0; +} + +static int phy_meson_g12a_usb3_pcie_power_off(struct phy *phy) +{ + struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev); + + if (phy->id == PHY_TYPE_USB3) + return 0; + + regmap_update_bits(priv->regmap, PHY_R0, + PHY_R0_PCIE_POWER_STATE, + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d)); + + return 0; +} + +static int phy_meson_g12a_usb3_pcie_reset(struct phy *phy) +{ + struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev); + int ret; + + if (phy->id == PHY_TYPE_USB3) + return 0; + + ret = reset_assert_bulk(&priv->resets); + if (ret) + return ret; + + udelay(PCIE_RESET_DELAY); + + ret = reset_deassert_bulk(&priv->resets); + if (ret) + return ret; + + udelay(PCIE_RESET_DELAY); + + return 0; +} + struct phy_ops meson_g12a_usb3_pcie_phy_ops = { - .init = phy_meson_g12a_usb3_init, - .exit = phy_meson_g12a_usb3_exit, + .init = phy_meson_g12a_usb3_pcie_init, + .exit = phy_meson_g12a_usb3_pcie_exit, + .power_on = phy_meson_g12a_usb3_pcie_power_on, + .power_off = phy_meson_g12a_usb3_pcie_power_off, + .reset = phy_meson_g12a_usb3_pcie_reset, };
int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev)
Enable PCIe by default in u-boot, this should eventually be made dynamic in the runtime board config depending on the MCU configuration.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- arch/arm/dts/meson-khadas-vim3-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi b/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi index 81fd5be378..24dbf8ca2c 100644 --- a/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi +++ b/arch/arm/dts/meson-khadas-vim3-u-boot.dtsi @@ -10,6 +10,10 @@ }; };
+&pcie { + status = "okay"; +}; + &sd_emmc_c { status = "okay"; pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>;
Now we have PCIe, let's also enable NVMe to access an eventual NVMe SSDs connected on the M.2 slot.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- configs/khadas-vim3_defconfig | 5 +++++ configs/khadas-vim3l_defconfig | 5 +++++ 2 files changed, 10 insertions(+)
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig index bc17430569..5bf821bd38 100644 --- a/configs/khadas-vim3_defconfig +++ b/configs/khadas-vim3_defconfig @@ -85,3 +85,8 @@ CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PCI=y +CONFIG_CMD_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MESON=y +CONFIG_NVME=y diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig index c1877922c7..f066eb8c61 100644 --- a/configs/khadas-vim3l_defconfig +++ b/configs/khadas-vim3l_defconfig @@ -85,3 +85,8 @@ CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PCI=y +CONFIG_CMD_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MESON=y +CONFIG_NVME=y
Let's add a boot target for NVMe so we can do a full boot over NVMe.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- include/configs/meson64.h | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 7e97f89052..17ebccd2c4 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -58,6 +58,12 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif
+#ifdef CONFIG_CMD_NVME + #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) +#else + #define BOOT_TARGET_NVME(func) +#endif + #ifndef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(ROMUSB, romusb, na) \ @@ -65,6 +71,7 @@ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_NVME(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) #endif
On 08/04/2021 09:50, Neil Armstrong wrote:
This adds the missing bits to enable PCIe and NVMe support in U-Boot for the Khadas VIM3 & VIM3L board.
This serie depends on [1].
[1] https://patchwork.ozlabs.org/project/uboot/cover/20210325144921.1791892-1-na...
Neil Armstrong (5): clk: meson-g12a: add PCIe gates phy: meson-g12a-usb3-pcie: add support for PCIe ops arm: dts: meson-khadas-vim3: enable PCIe in U-boot configs: khadas-vim3: enable PCIe and NVMe configs: meson64: add NVME boot target
arch/arm/dts/meson-khadas-vim3-u-boot.dtsi | 4 ++ configs/khadas-vim3_defconfig | 5 ++ configs/khadas-vim3l_defconfig | 5 ++ drivers/clk/meson/g12a.c | 2 + drivers/phy/meson-g12a-usb3-pcie.c | 81 ++++++++++++++++++++-- include/configs/meson64.h | 7 ++ 6 files changed, 100 insertions(+), 4 deletions(-)
Applied to u-boot-amlogic
participants (1)
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Neil Armstrong