[U-Boot] [PATCH 01/33] ARM64: zynqmp: Move kernel and fdt offsets and sizes to board config file

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Michal Simek

7 Apr 2016 7 Apr '16

7:05 p.m.

From: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com

Move kernel and fdt offsets and sizes to board config file as the flash size varies across boards

Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

include/configs/xilinx_zynqmp.h | 3 +-- include/configs/xilinx_zynqmp_ep.h | 7 +++++++ 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8cea61080d49..a60325517647 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -165,8 +165,7 @@ "kernel_addr=0x80000\0" \ "fdt_addr=0x7000000\0" \ "fdt_high=0x10000000\0" \ - "kernel_size=0x2000000\0" \ - "fdt_size=0x80000\0" \ + CONFIG_KERNEL_FDT_OFST_SIZE \ "sdbootdev=0\0"\ "sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \ "load mmc $sdbootdev:$partid $kernel_addr Image && " \ diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index aa58b62531d4..4a83eee6d0b8 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -24,6 +24,13 @@

#define COUNTER_FREQUENCY 4000000

+#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=ep108\0" + #include <configs/xilinx_zynqmp.h>

#endif /* __CONFIG_ZYNQMP_EP_H */

-- 1.9.1

Show replies by date

Michal Simek

7 Apr 7 Apr

7:05 p.m.

New subject: [U-Boot] [PATCH 02/33] ARM64: zynqmp: Use C pre-processor for includes in dts

From: Alistair Francis alistair.francis@xilinx.com

Change the dtsi include code to use the C pre-processor #include instead of the device tree /include/. This brings all ZynqMP device trees inline with each other.

Signed-off-by: Alistair Francis alistair.francis@xilinx.com Reviewed-by: Sören Brinkmann soren.brinkmann@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp-ep108.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index 754604ea7251..d952de189f3a 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -10,8 +10,8 @@

/dts-v1/;

-/include/ "zynqmp.dtsi" -/include/ "zynqmp-ep108-clk.dtsi" +#include "zynqmp.dtsi" +#include "zynqmp-ep108-clk.dtsi"

/ { model = "ZynqMP EP108";

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 03/33] ARM64: zynqmp: Add missing mmc aliases

Add missing mmc aliases.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp-ep108.dts | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index d952de189f3a..f34555a0a44a 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -17,6 +17,8 @@ model = "ZynqMP EP108";

aliases { + mmc0 = &sdhci0; + mmc1 = &sdhci1; serial0 = &uart0; spi0 = &qspi; spi1 = &spi0;

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 04/33] ARM64: zynqmp: dt: Change qspi node compatible string

From: Ranjit Waghmode ranjit.waghmode@xilinx.com

This patch makes compatible string as "m25p80" for qspi node in ep108 device tree file

Signed-off-by: Ranjit Waghmode ranjit.waghmode@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp-ep108.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index f34555a0a44a..b6d30e87c2b6 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -74,7 +74,7 @@ &qspi { status = "okay"; flash@0 { - compatible = "n25q512a11"; + compatible = "m25p80"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>;

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 05/33] ARM64: zynqmp: Add 8-bit bus width property.

From: P L Sai Krishna lakshmi.sai.krishna.potthuri@xilinx.com

This patch add 8-bit bus width property to eMMC node.

Signed-off-by: P L Sai Krishna lakshmis@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp-ep108.dts | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index b6d30e87c2b6..ee9d0fe7a432 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -107,6 +107,7 @@

&sdhci0 { status = "okay"; + bus-width = <8>; };

&sdhci1 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 06/33] ARM64: zynqmp: Correct IRQ nr for the SMMU

From: "Edgar E. Iglesias" edgar.iglesias@xilinx.com

Signed-off-by: Edgar E. Iglesias edgar.iglesias@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 8733604a5738..4cfecec85a75 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -454,11 +454,11 @@ reg = <0x0 0xfd800000 0x20000>; #global-interrupts = <1>; interrupt-parent = <&gic>; - interrupts = <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, - <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>; + interrupts = <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, + <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; };

spi0: spi@ff040000 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 07/33] ARM64: zynqmp: Hook up the GEMs to the SMMU

From: "Edgar E. Iglesias" edgar.iglesias@xilinx.com

Signed-off-by: Edgar E. Iglesias edgar.iglesias@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 4cfecec85a75..66abe6fe0bcf 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -310,6 +310,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; jumbo-max-len = <10240>; jumbo-supported; }; @@ -323,6 +324,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; jumbo-max-len = <10240>; jumbo-supported; }; @@ -336,6 +338,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; jumbo-max-len = <10240>; jumbo-supported; }; @@ -349,6 +352,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; jumbo-max-len = <10240>; jumbo-supported; }; @@ -459,6 +463,10 @@ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; + mmu-masters = < &gem0 0x874 + &gem1 0x875 + &gem2 0x876 + &gem3 0x877 >; };

spi0: spi@ff040000 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 08/33] ARM64: zynqmp: Sync GEM nodes with Linux

Remove jumbo properties which are handled in the driver directly and use mainline compatible string which is already handled by the driver.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 66abe6fe0bcf..7ac21f2f8765 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -302,7 +302,7 @@ };

gem0: ethernet@ff0b0000 { - compatible = "cdns,gem"; + compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; @@ -311,12 +311,10 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; - jumbo-max-len = <10240>; - jumbo-supported; };

gem1: ethernet@ff0c0000 { - compatible = "cdns,gem"; + compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; @@ -325,12 +323,10 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; - jumbo-max-len = <10240>; - jumbo-supported; };

gem2: ethernet@ff0d0000 { - compatible = "cdns,gem"; + compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; @@ -339,12 +335,10 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; - jumbo-max-len = <10240>; - jumbo-supported; };

gem3: ethernet@ff0e0000 { - compatible = "cdns,gem"; + compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; @@ -353,8 +347,6 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; - jumbo-max-len = <10240>; - jumbo-supported; };

gpio: gpio@ff0a0000 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 09/33] ARM64: zynqmp: Added broken-tuning property to SD, eMMC nodes

From: P L Sai Krishna lakshmi.sai.krishna.potthuri@xilinx.com

This patch adds broken-tuning property to SD and eMMC nodes.

Signed-off-by: P L Sai Krishna lakshmis@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 7ac21f2f8765..0e6d4040a469 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -434,6 +434,7 @@ interrupts = <0 48 4>; reg = <0x0 0xff160000 0x1000>; clock-names = "clk_xin", "clk_ahb"; + broken-tuning; };

sdhci1: sdhci@ff170000 { @@ -443,6 +444,7 @@ interrupts = <0 49 4>; reg = <0x0 0xff170000 0x1000>; clock-names = "clk_xin", "clk_ahb"; + broken-tuning; };

smmu: smmu@fd800000 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 10/33] ARM64: zynqmp: DT: Add power domains

From: Soren Brinkmann soren.brinkmann@xilinx.com

Add power-domains to the DT and attach devices to them. The power-domains are all logical domains as understood by firmware. Each PD is identified by a unique identifier that the platform firmware understands.

Signed-off-by: Soren Brinkmann soren.brinkmann@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 210 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 210 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 0e6d4040a469..9a53ad62b971 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -45,6 +45,176 @@ }; };

+ power-domains { + compatible = "xlnx,zynqmp-genpd"; + + pd_usb0: pd-usb0 { + #power-domain-cells = <0x0>; + pd-id = <0x16>; + }; + + pd_usb1: pd-usb1 { + #power-domain-cells = <0x0>; + pd-id = <0x17>; + }; + + pd_sata: pd-sata { + #power-domain-cells = <0x0>; + pd-id = <0x1c>; + }; + + pd_spi0: pd-spi0 { + #power-domain-cells = <0x0>; + pd-id = <0x23>; + }; + + pd_spi1: pd-spi1 { + #power-domain-cells = <0x0>; + pd-id = <0x24>; + }; + + pd_uart0: pd-uart0 { + #power-domain-cells = <0x0>; + pd-id = <0x21>; + }; + + pd_uart1: pd-uart1 { + #power-domain-cells = <0x0>; + pd-id = <0x22>; + }; + + pd_eth0: pd-eth0 { + #power-domain-cells = <0x0>; + pd-id = <0x1d>; + }; + + pd_eth1: pd-eth1 { + #power-domain-cells = <0x0>; + pd-id = <0x1e>; + }; + + pd_eth2: pd-eth2 { + #power-domain-cells = <0x0>; + pd-id = <0x1f>; + }; + + pd_eth3: pd-eth3 { + #power-domain-cells = <0x0>; + pd-id = <0x20>; + }; + + pd_i2c0: pd-i2c0 { + #power-domain-cells = <0x0>; + pd-id = <0x25>; + }; + + pd_i2c1: pd-i2c1 { + #power-domain-cells = <0x0>; + pd-id = <0x26>; + }; + + pd_dp: pd-dp { + /* fixme: what to attach to */ + #power-domain-cells = <0x0>; + pd-id = <0x29>; + }; + + pd_gdma: pd-gdma { + #power-domain-cells = <0x0>; + pd-id = <0x2a>; + }; + + pd_adma: pd-adma { + #power-domain-cells = <0x0>; + pd-id = <0x2b>; + }; + + pd_ttc0: pd-ttc0 { + #power-domain-cells = <0x0>; + pd-id = <0x18>; + }; + + pd_ttc1: pd-ttc1 { + #power-domain-cells = <0x0>; + pd-id = <0x19>; + }; + + pd_ttc2: pd-ttc2 { + #power-domain-cells = <0x0>; + pd-id = <0x1a>; + }; + + pd_ttc3: pd-ttc3 { + #power-domain-cells = <0x0>; + pd-id = <0x1b>; + }; + + pd_sd0: pd-sd0 { + #power-domain-cells = <0x0>; + pd-id = <0x27>; + }; + + pd_sd1: pd-sd1 { + #power-domain-cells = <0x0>; + pd-id = <0x28>; + }; + + pd_nand: pd-nand { + #power-domain-cells = <0x0>; + pd-id = <0x2c>; + }; + + pd_qspi: pd-qspi { + #power-domain-cells = <0x0>; + pd-id = <0x2d>; + }; + + pd_gpio: pd-gpio { + #power-domain-cells = <0x0>; + pd-id = <0x2e>; + }; + + pd_can0: pd-can0 { + #power-domain-cells = <0x0>; + pd-id = <0x2f>; + }; + + pd_can1: pd-can1 { + #power-domain-cells = <0x0>; + pd-id = <0x30>; + }; + + pd_ddr: pd-ddr { + #power-domain-cells = <0x0>; + pd-id = <0x37>; + }; + + pd_apll: pd-apll { + #power-domain-cells = <0x0>; + pd-id = <0x32>; + }; + + pd_vpll: pd-vpll { + #power-domain-cells = <0x0>; + pd-id = <0x33>; + }; + + pd_dpll: pd-dpll { + #power-domain-cells = <0x0>; + pd-id = <0x34>; + }; + + pd_rpll: pd-rpll { + #power-domain-cells = <0x0>; + pd-id = <0x35>; + }; + + pd_iopll: pd-iopll { + #power-domain-cells = <0x0>; + pd-id = <0x36>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0 143 4>, @@ -106,6 +276,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + power-domains = <&pd_can0>; };

can1: can@ff070000 { @@ -117,6 +288,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + power-domains = <&pd_can1>; };

/* GDMA */ @@ -128,6 +300,7 @@ interrupts = <0 124 4>; xlnx,id = <0>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; };

fpd_dma_chan2: dma@fd510000 { @@ -138,6 +311,7 @@ interrupts = <0 125 4>; xlnx,id = <1>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; };

fpd_dma_chan3: dma@fd520000 { @@ -148,6 +322,7 @@ interrupts = <0 126 4>; xlnx,id = <2>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; };

fpd_dma_chan4: dma@fd530000 { @@ -158,6 +333,7 @@ interrupts = <0 127 4>; xlnx,id = <3>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; };

fpd_dma_chan5: dma@fd540000 { @@ -168,6 +344,7 @@ interrupts = <0 128 4>; xlnx,id = <4>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; };

fpd_dma_chan6: dma@fd550000 { @@ -178,6 +355,7 @@ interrupts = <0 129 4>; xlnx,id = <5>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; };

fpd_dma_chan7: dma@fd560000 { @@ -188,6 +366,7 @@ interrupts = <0 130 4>; xlnx,id = <6>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; };

fpd_dma_chan8: dma@fd570000 { @@ -198,6 +377,7 @@ interrupts = <0 131 4>; xlnx,id = <7>; xlnx,bus-width = <128>; + power-domains = <&pd_gdma>; };

gpu: gpu@fd4b0000 { @@ -218,6 +398,7 @@ interrupts = <0 77 4>; xlnx,id = <0>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; };

lpd_dma_chan2: dma@ffa90000 { @@ -228,6 +409,7 @@ interrupts = <0 78 4>; xlnx,id = <1>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; };

lpd_dma_chan3: dma@ffaa0000 { @@ -238,6 +420,7 @@ interrupts = <0 79 4>; xlnx,id = <2>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; };

lpd_dma_chan4: dma@ffab0000 { @@ -248,6 +431,7 @@ interrupts = <0 80 4>; xlnx,id = <3>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; };

lpd_dma_chan5: dma@ffac0000 { @@ -258,6 +442,7 @@ interrupts = <0 81 4>; xlnx,id = <4>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; };

lpd_dma_chan6: dma@ffad0000 { @@ -268,6 +453,7 @@ interrupts = <0 82 4>; xlnx,id = <5>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; };

lpd_dma_chan7: dma@ffae0000 { @@ -278,6 +464,7 @@ interrupts = <0 83 4>; xlnx,id = <6>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; };

lpd_dma_chan8: dma@ffaf0000 { @@ -288,6 +475,7 @@ interrupts = <0 84 4>; xlnx,id = <7>; xlnx,bus-width = <64>; + power-domains = <&pd_adma>; };

nand0: nand@ff100000 { @@ -299,6 +487,7 @@ interrupts = <0 14 4>; #address-cells = <2>; #size-cells = <1>; + power-domains = <&pd_nand>; };

gem0: ethernet@ff0b0000 { @@ -311,6 +500,7 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + power-domains = <&pd_eth0>; };

gem1: ethernet@ff0c0000 { @@ -323,6 +513,7 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + power-domains = <&pd_eth1>; };

gem2: ethernet@ff0d0000 { @@ -335,6 +526,7 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + power-domains = <&pd_eth2>; };

gem3: ethernet@ff0e0000 { @@ -347,6 +539,7 @@ #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + power-domains = <&pd_eth3>; };

gpio: gpio@ff0a0000 { @@ -356,6 +549,7 @@ interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff0a0000 0x1000>; + power-domains = <&pd_gpio>; };

i2c0: i2c@ff020000 { @@ -366,6 +560,7 @@ reg = <0x0 0xff020000 0x1000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&pd_i2c0>; };

i2c1: i2c@ff030000 { @@ -376,6 +571,7 @@ reg = <0x0 0xff030000 0x1000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&pd_i2c1>; };

pcie: pcie@fd0e0000 { @@ -408,6 +604,7 @@ reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&pd_qspi>; };

rtc: rtc@ffa60000 { @@ -425,6 +622,7 @@ reg = <0x0 0xfd0c0000 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; + power-domains = <&pd_sata>; };

sdhci0: sdhci@ff160000 { @@ -435,6 +633,7 @@ reg = <0x0 0xff160000 0x1000>; clock-names = "clk_xin", "clk_ahb"; broken-tuning; + power-domains = <&pd_sd0>; };

sdhci1: sdhci@ff170000 { @@ -445,6 +644,7 @@ reg = <0x0 0xff170000 0x1000>; clock-names = "clk_xin", "clk_ahb"; broken-tuning; + power-domains = <&pd_sd1>; };

smmu: smmu@fd800000 { @@ -472,6 +672,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&pd_spi0>; };

spi1: spi@ff050000 { @@ -483,6 +684,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&pd_spi1>; };

ttc0: timer@ff110000 { @@ -492,6 +694,7 @@ interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x1000>; timer-width = <32>; + power-domains = <&pd_ttc0>; };

ttc1: timer@ff120000 { @@ -501,6 +704,7 @@ interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x1000>; timer-width = <32>; + power-domains = <&pd_ttc1>; };

ttc2: timer@ff130000 { @@ -510,6 +714,7 @@ interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x1000>; timer-width = <32>; + power-domains = <&pd_ttc2>; };

ttc3: timer@ff140000 { @@ -519,6 +724,7 @@ interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x1000>; timer-width = <32>; + power-domains = <&pd_ttc3>; };

uart0: serial@ff000000 { @@ -528,6 +734,7 @@ interrupts = <0 21 4>; reg = <0x0 0xff000000 0x1000>; clock-names = "uart_clk", "pclk"; + power-domains = <&pd_uart0>; };

uart1: serial@ff010000 { @@ -537,6 +744,7 @@ interrupts = <0 22 4>; reg = <0x0 0xff010000 0x1000>; clock-names = "uart_clk", "pclk"; + power-domains = <&pd_uart1>; };

usb0: usb@fe200000 { @@ -546,6 +754,7 @@ interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x40000>; clock-names = "clk_xin", "clk_ahb"; + power-domains = <&pd_usb0>; };

usb1: usb@fe300000 { @@ -555,6 +764,7 @@ interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x40000>; clock-names = "clk_xin", "clk_ahb"; + power-domains = <&pd_usb1>; };

watchdog0: watchdog@fd4d0000 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 11/33] ARM64: zynqmp: Add missing interrupt-parent to PMU node

ZynqMP is not using global interrupt-parent setting that's why it has to be listed in every node separately. PMU node missed it and this patch is adding it.

Reported-by: John Linn John.Linn@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 9a53ad62b971..a09bbbfa4373 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -217,6 +217,7 @@

pmu { compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>,

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 12/33] ARM64: zynqmp: Add CCI-400 node

Add CCI-400 node to DTSI.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index a09bbbfa4373..48505fa6daff 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -292,6 +292,25 @@ power-domains = <&pd_can1>; };

+ cci: cci@fd6e0000 { + compatible = "arm,cci-400"; + reg = <0x0 0xfd6e0000 0x9000>; + ranges = <0x0 0x0 0xfd6e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupt-parent = <&gic>; + interrupts = <0 123 4>, + <0 123 4>, + <0 123 4>, + <0 123 4>, + <0 123 4>; + }; + }; + /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled";

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 13/33] ARM64: zynqmp: Added clocks to DT

From: VNSL Durga vnsl.durga.challa@xilinx.com

ZynqMP DMA's main clock and apb clock are added in zynqmp DT.

Signed-off-by: VNSL Durga vnsldurg@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Punnaiah Choudary Kalluri punnaia@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 48505fa6daff..45209309c054 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -318,6 +318,7 @@ reg = <0x0 0xfd500000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <0>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -329,6 +330,7 @@ reg = <0x0 0xfd510000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <1>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -340,6 +342,7 @@ reg = <0x0 0xfd520000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <2>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -351,6 +354,7 @@ reg = <0x0 0xfd530000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <3>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -362,6 +366,7 @@ reg = <0x0 0xfd540000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <4>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -373,6 +378,7 @@ reg = <0x0 0xfd550000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <5>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -384,6 +390,7 @@ reg = <0x0 0xfd560000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <6>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -395,6 +402,7 @@ reg = <0x0 0xfd570000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <7>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>;

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 14/33] ARM64: zynqmp: Add ddrc node in dts

From: Naga Sureshkumar Relli naga.sureshkumar.relli@xilinx.com

This patch adds ddrc memory controller node in dts. size mentioned in dts is 0x30000, because we need to access DDR_QOS INTR registers located at fd090208 from this driver.

Signed-off-by: Naga Sureshkumar Relli nagasure@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 45209309c054..b68fb1a4a5fe 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -506,6 +506,13 @@ power-domains = <&pd_adma>; };

+ mc: memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0x0 0xfd070000 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; + nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled";

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 15/33] ARM64: zynqmp: Add interrupt-controller property to gpio nodes

GPIO driver supports an input interrupt that's why gpio node itself can be labeled as interrupt controller.

Reported-by: John Linn linnj@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b68fb1a4a5fe..48506086f5bb 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -581,6 +581,8 @@ compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; + #interrupt-cells = <2>; + interrupt-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff0a0000 0x1000>;

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 16/33] ARM64: zynqmp: Extend pcie node to support legacy interrupts

From: Bharat Kumar Gogada bharat.kumar.gogada@xilinx.com

Modifying device tree node to support legacy interrupts.

Signed-off-by: Bharat Kumar Gogada bharatku@xilinx.com Signed-off-by: Ravi Kiran Gummaluri rgummal@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 48506086f5bb..ec6fc6a66841 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -629,6 +629,16 @@ <0x0 0xe0000000 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; };

qspi: spi@ff0f0000 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 17/33] ARM64: zynqmp: Fix coding style for pcie

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index ec6fc6a66841..98c07dcc8d6e 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -619,10 +619,10 @@ #interrupt-cells = <1>; device_type = "pci"; interrupt-parent = <&gic>; - interrupts = < 0 118 4>, - < 0 116 4>, - < 0 115 4>, /* MSI_1 [63...32] */ - < 0 114 4 >; /* MSI_0 [31...0] */ + interrupts = <0 118 4>, + <0 116 4>, + <0 115 4>, /* MSI_1 [63...32] */ + <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "intx", "msi_1", "msi_0"; reg = <0x0 0xfd0e0000 0x1000>, <0x0 0xfd480000 0x1000>,

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 18/33] ARM64: zynqmp: Add backward compatible string for uart

Mainline kernel has no r1p12 compatible string that's why console stops to work with the latest DTS files. Append generic compatible string. Keep in your mind that using this generic compatible string not all uart features will be available.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 98c07dcc8d6e..f9249aa7b076 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -775,7 +775,7 @@ };

uart0: serial@ff000000 { - compatible = "cdns,uart-r1p12"; + compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; @@ -785,7 +785,7 @@ };

uart1: serial@ff010000 { - compatible = "cdns,uart-r1p12"; + compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>;

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 19/33] ARM64: zynqmp: Align node address with parent node for dpdma

Use right addresses for channel names

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index f9249aa7b076..2690aa2afa26 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -904,22 +904,22 @@ clock-names = "axi_clk"; dma-channels = <6>; #dma-cells = <1>; - dma-video0channel@43c10000 { + dma-video0channel@fd4c0000 { compatible = "xlnx,video0"; }; - dma-video1channel@43c10000 { + dma-video1channel@fd4c0000 { compatible = "xlnx,video1"; }; - dma-video2channel@43c10000 { + dma-video2channel@fd4c0000 { compatible = "xlnx,video2"; }; - dma-graphicschannel@43c10000 { + dma-graphicschannel@fd4c0000 { compatible = "xlnx,graphics"; }; - dma-audio0channel@43c10000 { + dma-audio0channel@fd4c0000 { compatible = "xlnx,audio0"; }; - dma-audio1channel@43c10000 { + dma-audio1channel@fd4c0000 { compatible = "xlnx,audio1"; }; };

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 20/33] ARM64: zynqmp: Use correct addresses in node names

From: Hyun Kwon hyun.kwon@xilinx.com

Reflect actual silicon addresses in DT node names.

Signed-off-by: Hyun Kwon hyun.kwon@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 2690aa2afa26..5001ccc8d8f0 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -842,7 +842,7 @@ }; };

- xlnx_dp: dp@43c00000 { + xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x1000>; @@ -887,7 +887,7 @@ dma-names = "tx"; };

- xlnx_dp_sub: dp_sub@43c0a000 { + xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 21/33] ARM64: zynqmp: dp: Add default properties to zynqmp.dtsi

From: Hyun Kwon hyun.kwon@xilinx.com

Add some default properties to zynqmp.dtsi.

Signed-off-by: Hyun Kwon hyun.kwon@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 5001ccc8d8f0..a1804b8da31d 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -858,6 +858,7 @@ xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; + xlnx,max-pclock-frequency = <300000>; };

xlnx_dp_snd_card: dp_snd_card { @@ -893,6 +894,8 @@ reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; + xlnx,vid-fmt = "yuyv"; + xlnx,gfx-fmt = "rgb565"; };

xlnx_dpdma: dma@fd4c0000 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 22/33] ARM64: zynqmp: Align register description

Separate register space and put it on more lines.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index a1804b8da31d..e2f7b53858a3 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -648,7 +648,8 @@ interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; - reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; + reg = <0x0 0xff0f0000 0x1000>, + <0x0 0xc0000000 0x8000000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_qspi>; @@ -891,7 +892,9 @@ xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; - reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>; + reg = <0x0 0xfd4aa000 0x1000>, + <0x0 0xfd4ab000 0x1000>, + <0x0 0xfd4ac000 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv";

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 23/33] ARM64: zynqmp: Add serdes address space dp driver

For run time serdes adjustment.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index e2f7b53858a3..324d71b98902 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -846,7 +846,8 @@ xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; - reg = <0x0 0xfd4a0000 0x1000>; + reg = <0x0 0xfd4a0000 0x1000>, + <0x0 0xfd400000 0x20000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk";

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 24/33] ARM64: zynqmp: Fix DWC3 binding with the kernel

Use the same binding as is used in mainline Linux kernel.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp-ep108.dts | 10 ++++++++++ arch/arm/dts/zynqmp.dtsi | 42 ++++++++++++++++++++++++++++++++---------- 2 files changed, 42 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index ee9d0fe7a432..1928b0bca002 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -23,6 +23,8 @@ spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; + usb0 = &usb0; + usb1 = &usb1; };

chosen { @@ -154,12 +156,20 @@

&usb0 { status = "okay"; +}; + +&dwc3_0 { + status = "okay"; dr_mode = "peripheral"; maximum-speed = "high-speed"; };

&usb1 { status = "okay"; +}; + +&dwc3_1 { + status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 324d71b98902..8413f16ee374 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -796,23 +796,45 @@ };

usb0: usb@fe200000 { - compatible = "snps,dwc3"; + #address-cells = <2>; + #size-cells = <1>; status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 65 4>; - reg = <0x0 0xfe200000 0x40000>; - clock-names = "clk_xin", "clk_ahb"; + compatible = "xlnx,zynqmp-dwc3"; + clock-names = "bus_clk", "ref_clk"; + clocks = <&clk125>, <&clk125>; power-domains = <&pd_usb0>; + ranges; + + dwc3_0: dwc3@fe200000 { + compatible = "snps,dwc3"; + status = "disabled"; + reg = <0x0 0xfe200000 0x40000>; + interrupt-parent = <&gic>; + interrupts = <0 65 4>; + /* snps,quirk-frame-length-adjustment = <0x20>; */ + snps,refclk_fladj; + }; };

usb1: usb@fe300000 { - compatible = "snps,dwc3"; + #address-cells = <2>; + #size-cells = <1>; status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 70 4>; - reg = <0x0 0xfe300000 0x40000>; - clock-names = "clk_xin", "clk_ahb"; + compatible = "xlnx,zynqmp-dwc3"; + clock-names = "bus_clk", "ref_clk"; + clocks = <&clk125>, <&clk125>; power-domains = <&pd_usb1>; + ranges; + + dwc3_1: dwc3@fe300000 { + compatible = "snps,dwc3"; + status = "disabled"; + reg = <0x0 0xfe300000 0x40000>; + interrupt-parent = <&gic>; + interrupts = <0 70 4>; + /* snps,quirk-frame-length-adjustment = <0x20>; */ + snps,refclk_fladj; + }; };

watchdog0: watchdog@fd4d0000 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 25/33] ARM64: zynqmp: Use 64bit size cell format for memory node

Enable option to support more then 4GB memories in single size block.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp-ep108.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index 1928b0bca002..7fa0694fcd98 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -33,7 +33,7 @@

memory { device_type = "memory"; - reg = <0x0 0x0 0x40000000>; + reg = <0x0 0x0 0x0 0x40000000>; }; };

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 8413f16ee374..fb95b4828b90 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -10,7 +10,7 @@ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; - #size-cells = <1>; + #size-cells = <2>;

cpus { #address-cells = <1>; @@ -247,7 +247,7 @@ compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; - ranges; + ranges = <0 0 0 0 0xffffffff>;

gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; @@ -266,7 +266,7 @@ compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; - ranges; + ranges = <0 0 0 0 0xffffffff>;

can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0";

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 26/33] ARM64: zynqmp: Added OOB timing settings in zynqmp-ep108.dts

From: Anurag Kumar Vulisha anurag.kumar.vulisha@xilinx.com

This patch adds the sata port phy OOB timing values in the sata device-tree node.

Signed-off-by: Anurag Kumar Vulisha anuragku@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp-ep108.dts | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index 7fa0694fcd98..e48a360baa72 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -105,6 +105,15 @@ &sata { status = "okay"; ceva,broken-gen2; + /* SATA Phy OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; + ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; + ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; + ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; + ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; + ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; };

&sdhci0 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 27/33] ARM64: zynqmp: Add missing nand node for ep108

From: Punnaiah Choudary Kalluri punnaiah.choudary.kalluri@xilinx.com

Add missing nand node for ep108.

Signed-off-by: Punnaiah Choudary Kalluri punnaia@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynqmp-ep108-clk.dtsi | 4 ++++ arch/arm/dts/zynqmp-ep108.dts | 31 +++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+)

diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi index f86452655391..48bb426dafaf 100644 --- a/arch/arm/dts/zynqmp-ep108-clk.dtsi +++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi @@ -62,6 +62,10 @@ clocks = <&i2c_clk>; };

+&nand0 { + clocks = <&misc_clk &misc_clk>; +}; + &qspi { clocks = <&misc_clk &misc_clk>; }; diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index e48a360baa72..0bbf9a759756 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -73,6 +73,37 @@ }; };

+&nand0 { + status = "okay"; + arasan,has-mdma; + num-cs = <1>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1C00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xFCC00000>; + }; +}; + &qspi { status = "okay"; flash@0 {

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 28/33] ARM64: zynqmp: Do not setup DM_ETH/GPIO/MMC by default for all boards

There are mini configurations which need to be fit to OCM that's why these options shouldn't be enabled by default.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/Kconfig | 2 -- configs/xilinx_zynqmp_ep_defconfig | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f18dbe683c16..c8e033789393 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -591,8 +591,6 @@ config ARCH_ZYNQMP select ARM64 select DM select OF_CONTROL - select DM_ETH - select DM_MMC select DM_SERIAL

config TEGRA diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 91ae10ab211b..c6e75d444763 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -26,8 +26,10 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y CONFIG_NAND_ARASAN=y +CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y CONFIG_USB=y CONFIG_USB_GADGET=y

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 29/33] ARM64: zynqmp: Extend early malloc space to be able to run DM drivers

DM drivers need more malloc space for early DM models allocation. Use 4k instead of 1k.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

configs/xilinx_zynqmp_ep_defconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index c6e75d444763..9f72abaabb05 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep" CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"

-- 1.9.1

Michal Simek

7:05 p.m.

New subject: [U-Boot] [PATCH 30/33] ARM64: zynqmp: Make DDR detection code work on 32bit system

Define u64 types to be usable on 32bit system because of 64bit address and size cells and 32bit shifts in the code.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

board/xilinx/zynqmp/zynqmp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 087578cb6b9c..529476b08268 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -63,8 +63,8 @@ static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf, int address_cells = fdt_address_cells(fdt, parent_offset); int size_cells = fdt_size_cells(fdt, parent_offset); char *p = buf; - phys_addr_t val; - phys_size_t vals; + u64 val; + u64 vals;

debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n", __func__, address_cells, size_cells, buf, cell); @@ -166,7 +166,7 @@ int dram_init(void)

gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);

- debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size); + debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);

return 0; }

-- 1.9.1

Michal Simek

7:06 p.m.

New subject: [U-Boot] [PATCH 31/33] ARM64: zynqmp: Add support for ZCU102 platform

Add new board support.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/Makefile | 4 +- arch/arm/dts/zynqmp-clk.dtsi | 202 +++++++++++ arch/arm/dts/zynqmp-zcu102-revB.dts | 42 +++ arch/arm/dts/zynqmp-zcu102.dts | 630 +++++++++++++++++++++++++++++++++ configs/xilinx_zynqmp_zcu102_defconfig | 32 ++ include/configs/xilinx_zynqmp_zcu102.h | 56 +++ 6 files changed, 965 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynqmp-clk.dtsi create mode 100644 arch/arm/dts/zynqmp-zcu102-revB.dts create mode 100644 arch/arm/dts/zynqmp-zcu102.dts create mode 100644 configs/xilinx_zynqmp_zcu102_defconfig create mode 100644 include/configs/xilinx_zynqmp_zcu102.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 01cf030d3f97..da3be7044ebb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -81,7 +81,9 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ - zynqmp-ep108.dtb + zynqmp-ep108.dtb \ + zynqmp-zcu102.dtb \ + zynqmp-zcu102-revB.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi new file mode 100644 index 000000000000..341890975929 --- /dev/null +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -0,0 +1,202 @@ +/* + * Clock specification for Xilinx ZynqMP + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&amba { + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk200: clk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + clk250: clk250 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + clk300: clk300 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + clk600: clk600 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + dp_aclk: clock0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-accuracy = <100>; + }; + + dp_aud_clk: clock1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-accuracy = <100>; + }; + + dpdma_clk: dpdma_clk { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <533000000>; + }; + + drm_clock: drm_clock { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <262750000>; + clock-accuracy = <0x64>; + }; +}; + +&can0 { + clocks = <&clk100 &clk100>; +}; + +&can1 { + clocks = <&clk100 &clk100>; +}; + +&fpd_dma_chan1 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan2 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan3 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan4 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan5 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan6 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan7 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan8 { + clocks = <&clk600>, <&clk100>; +}; + +&nand0 { + clocks = <&clk100 &clk100>; +}; + +&gem0 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem1 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem2 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem3 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gpio { + clocks = <&clk100>; +}; + +&i2c0 { + clocks = <&clk100>; +}; + +&i2c1 { + clocks = <&clk100>; +}; + +&qspi { + clocks = <&clk300 &clk300>; +}; + +&sata { + clocks = <&clk250>; +}; + +&sdhci0 { + clocks = <&clk200 &clk200>; +}; + +&sdhci1 { + clocks = <&clk200 &clk200>; +}; + +&spi0 { + clocks = <&clk200 &clk200>; +}; + +&spi1 { + clocks = <&clk200 &clk200>; +}; + +&uart0 { + clocks = <&clk100 &clk100>; +}; + +&uart1 { + clocks = <&clk100 &clk100>; +}; + +&usb0 { + clocks = <&clk250>, <&clk250>; +}; + +&usb1 { + clocks = <&clk250>, <&clk250>; +}; + +&xilinx_drm { + clocks = <&drm_clock>; +}; + +&xlnx_dp { + clocks = <&dp_aclk>, <&dp_aud_clk>; +}; + +&xlnx_dpdma { + clocks = <&dpdma_clk>; +}; + +&xlnx_dp_snd_codec0 { + clocks = <&dp_aud_clk>; +}; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts new file mode 100644 index 000000000000..765108e43789 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -0,0 +1,42 @@ +/* + * dts file for Xilinx ZynqMP ZCU102 RevB + * + * (C) Copyright 2016, Xilinx, Inc. + * + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "zynqmp-zcu102.dts" + +/ { + model = "ZynqMP ZCU102 RevB"; +}; + +&gem3 { + phy-handle = <&phyc>; + phyc: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; + /* Cleanup from RevA */ + /delete-node/ phy@21; +}; + +/* Different qspi 512Mbit version */ + +/* Fix collision with u61 */ +&i2c0 { + i2cswitch@75 { + i2c@2 { + max15303@1b { /* u8 */ + compatible = "max15303"; + reg = <0x1b>; + }; + /delete-node/ max15303@20; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102.dts new file mode 100644 index 000000000000..6c116a2f957c --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu102.dts @@ -0,0 +1,630 @@ +/* + * dts file for Xilinx ZynqMP ZCU102 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP ZCU102 RevA"; + compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem3 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@21 { + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u97: gpio@20 { + /* + * Enable all GTs to out from U-Boot + * i2c mw 20 6 0 - setup IO to output + * i2c mw 20 2 ef - setup output values on pins 0-7 + * i2c mw 20 3 ff - setup output values on pins 10-17 + */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - PS_GTR_LAN_SEL0 + * 1 - PS_GTR_LAN_SEL1 + * 2 - PS_GTR_LAN_SEL2 + * 3 - PS_GTR_LAN_SEL3 + * 4 - PCI_CLK_DIR_SEL + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7, 10 - 17 - not connected + */ + + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + output-high; /* PCIE = 0, DP = 1 */ + line-name = "sel0"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + output-high; /* PCIE = 0, DP = 1 */ + line-name = "sel1"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + output-high; /* PCIE = 0, USB0 = 1 */ + line-name = "sel2"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + output-high; /* PCIE = 0, SATA = 1 */ + line-name = "sel3"; + }; + }; + + tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - VCCPSPLL_EN + * 1 - MGTRAVCC_EN + * 2 - MGTRAVTT_EN + * 3 - VCCPSDDRPLL_EN + * 4 - MIO26_PMU_INPUT_LS + * 5 - PL_PMBUS_ALERT + * 6 - PS_PMBUS_ALERT + * 7 - MAXIM_PMBUS_ALERT + * 10 - PL_DDR4_VTERM_EN + * 11 - PL_DDR4_VPP_2V5_EN + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON + * 13 - PS_DIMM_SUSPEND_EN + * 14 - PS_DDR4_VTERM_EN + * 15 - PS_DDR4_VPP_2V5_EN + * 16 - 17 - not connected + */ + }; + + i2cswitch@75 { /* u60 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { /* i2c mw 75 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + ina226@40 { /* u76 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + ina226@41 { /* u77 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u78 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u87 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u85 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u86 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u93 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u88 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u15 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u92 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { /* i2c mw 75 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* PL_PMBUS */ + ina226@40 { /* u79 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u81 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u80 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u84 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u16 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u74 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u75 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* i2c mw 75 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* MAXIM_PMBUS - 00 */ + max15301@a { /* u46 */ + compatible = "max15301"; + reg = <0xa>; + }; + max15303@b { /* u4 */ + compatible = "max15303"; + reg = <0xb>; + }; + max15303@10 { /* u13 */ + compatible = "max15303"; + reg = <0x10>; + }; + max15301@13 { /* u47 */ + compatible = "max15301"; + reg = <0x13>; + }; + max15303@14 { /* u7 */ + compatible = "max15303"; + reg = <0x14>; + }; + max15303@15 { /* u6 */ + compatible = "max15303"; + reg = <0x15>; + }; + max15303@16 { /* u10 */ + compatible = "max15303"; + reg = <0x16>; + }; + max15303@17 { /* u9 */ + compatible = "max15303"; + reg = <0x17>; + }; + max15301@18 { /* u63 */ + compatible = "max15301"; + reg = <0x18>; + }; + max15303@1a { /* u49 */ + compatible = "max15303"; + reg = <0x1a>; + }; + max15303@1d { /* u18 */ + compatible = "max15303"; + reg = <0x1d>; + }; + max15303@20 { /* u8 */ + compatible = "max15303"; + status = "disabled"; /* unreachable */ + reg = <0x20>; + }; + +/* drivers/hwmon/pmbus/Kconfig:86: be called max20751. +drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o +*/ + max20751@72 { /* u95 FIXME - not detected */ + compatible = "max20751"; + reg = <0x72>; + }; + max20751@73 { /* u96 FIXME - not detected */ + compatible = "max20751"; + reg = <0x73>; + }; + }; + /* Bus 3 is not connected */ + }; + + /* FIXME PL connection - u55 , PMOD - j160 */ + /* FIXME MSP430F - u41 - not detected */ +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + /* FIXME PL i2c via PCA9306 - u45 */ + /* FIXME MSP430 - u41 - not detected */ + i2cswitch@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { /* i2c mw 74 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom@54 { /* u23 */ + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { /* i2c mw 74 0 2 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator1@36 { /* SI5341 - u69 */ + compatible = "si5341"; + reg = <0x36>; + }; + + }; + i2c@2 { /* i2c mw 74 0 4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator2@5d { /* USER SI570 - u42 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { /* i2c mw 74 0 8 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; /* copy from zc702 */ + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { /* i2c mw 74 0 10 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator4@69 {/* SI5328 - u20 */ + compatible = "silabs,si5328"; + reg = <0x69>; + }; + }; + /* 5 - 7 unconnected */ + }; + + i2cswitch@75 { + compatible = "nxp,pca9548"; /* u135 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* HPC0_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* HPC1_IIC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { /* i2c mw 75 0 8 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + dev@19 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x19>; + }; + dev@30 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x30>; + }; + dev@35 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x35>; + }; + dev@36 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x36>; + }; + dev@51 { /* u-boot detection - maybe SPD */ + compatible = "xxx"; + reg = <0x51>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SEP 3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SEP 2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SEP 1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SEP 0 */ + }; + }; +}; + +&pcie { +/* status = "okay"; */ +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; /* for 1.0 silicon */ +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&xilinx_drm { + status = "okay"; + clocks = <&si570_1>; +}; + +&xlnx_dp { + status = "okay"; +}; + +&xlnx_dp_sub { + status = "okay"; + xlnx,vid-clk-pl; +}; + +&xlnx_dp_snd_pcm0 { + status = "okay"; +}; + +&xlnx_dp_snd_pcm1 { + status = "okay"; +}; + +&xlnx_dp_snd_card { + status = "okay"; +}; + +&xlnx_dp_snd_codec0 { + status = "okay"; +}; + +&xlnx_dpdma { + status = "okay"; +}; diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig new file mode 100644 index 000000000000..5900516b0d10 --- /dev/null +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_GPIO=y +CONFIG_ZYNQMP_USB=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h new file mode 100644 index 000000000000..4f580207bb30 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -0,0 +1,56 @@ +/* + * Configuration for Xilinx ZynqMP zcu102 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU102_H +#define __CONFIG_ZYNQMP_ZCU102_H + +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_I2C1 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 18 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ + {1, {I2C_NULL_HOP} }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ + } + +#define CONFIG_SYS_I2C_ZYNQ +#define CONFIG_AHCI +#define CONFIG_SATA_CEVA + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZCU102" + +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x180000\0" \ + "fdt_offset=0x100000\0" \ + "kernel_size=0x1e00000\0" \ + "fdt_size=0x80000\0" \ + "board=zcu102\0" + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZCU102_H */

-- 1.9.1

Michal Simek

7:06 p.m.

New subject: [U-Boot] [PATCH 32/33] ARM64: zynqmp: Add support for zc1751 with DC cards

Support ZynqMP zc1751 with DC cards.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/Makefile | 5 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 211 ++++++++++++++++++++ arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 236 +++++++++++++++++++++++ arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 121 ++++++++++++ configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 33 ++++ configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 32 +++ configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 20 ++ include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h | 31 +++ include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h | 28 +++ include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h | 30 +++ 10 files changed, 746 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts create mode 100644 arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts create mode 100644 arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts create mode 100644 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig create mode 100644 configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig create mode 100644 configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig create mode 100644 include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h create mode 100644 include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h create mode 100644 include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index da3be7044ebb..54a318a290a8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -83,7 +83,10 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-ep108.dtb \ zynqmp-zcu102.dtb \ - zynqmp-zcu102-revB.dtb + zynqmp-zcu102-revB.dtb \ + zynqmp-zc1751-xm015-dc1.dtb \ + zynqmp-zc1751-xm016-dc2.dtb \ + zynqmp-zc1751-xm019-dc5.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts new file mode 100644 index 000000000000..c68a41bea79a --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -0,0 +1,211 @@ +/* + * dts file for Xilinx ZynqMP zc1751-xm015-dc1 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP zc1751-xm015-dc1 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem3 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0 { + reg = <0>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + eeprom@55 { + compatible = "at,24c64"; /* 24AA64 */ + reg = <0x55>; + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA phy OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +/* eMMC */ +&sdhci0 { + status = "okay"; + bus-width = <8>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; /* for 1.0 silicon */ +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&xilinx_drm { + status = "okay"; +}; + +&xlnx_dp { + status = "okay"; +}; + +&xlnx_dp_sub { + status = "okay"; + xlnx,vid-clk-pl; +}; + +&xlnx_dp_snd_pcm0 { + status = "okay"; +}; + +&xlnx_dp_snd_pcm1 { + status = "okay"; +}; + +&xlnx_dp_snd_card { + status = "okay"; +}; + +&xlnx_dp_snd_codec0 { + status = "okay"; +}; + +&xlnx_dpdma { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts new file mode 100644 index 000000000000..3fdfcc8a11ae --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -0,0 +1,236 @@ +/* + * dts file for Xilinx ZynqMP zc1751-xm016-dc2 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP zc1751-xm016-dc2 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + can0 = &can0; + can1 = &can1; + ethernet0 = &gem2; + gpio0 = &gpio; + i2c0 = &i2c0; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + spi0 = &spi0; + spi1 = &spi1; + usb0 = &usb1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem2 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@5 { + reg = <5>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u26: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* IRQ not connected */ + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&nand0 { + status = "okay"; + arasan,has-mdma; + num-cs = <2>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1C00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xFCC00000>; + }; + + partition@6 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x1 0x0 0x400000>; + }; + partition@7 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x1 0x400000 0x1400000>; + }; + partition@8 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x1 0x1800000 0x400000>; + }; + partition@9 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x1 0x1C00000 0x1400000>; + }; + partition@10 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x1 0x3000000 0x400000>; + }; + partition@11 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x1 0x3400000 0xFCC00000>; + }; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; + num-cs = <1>; + spi0_flash0: spi0_flash0@0 { + compatible = "m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + spi0_flash0@00000000 { + label = "spi0_flash0"; + reg = <0x0 0x100000>; + }; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <1>; + spi1_flash0: spi1_flash0@0 { + compatible = "mtd_dataflash"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + + spi1_flash0@00000000 { + label = "spi1_flash0"; + reg = <0x0 0x84000>; + }; + }; +}; + +/* ULPI SMSC USB3320 */ +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts new file mode 100644 index 000000000000..d754f9f9040a --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -0,0 +1,121 @@ +/* + * dts file for Xilinx ZynqMP zc1751-xm019-dc5 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Siva Durga Prasad siva.durga.paladugu@xilinx.com + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +/ { + model = "ZynqMP zc1751-xm019-dc5 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem1; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + bootargs = "earlycon=cdns,mmio,0xff000000,115200n8"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem1 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0 { + reg = <0>; + }; +}; + +&gpio { + status = "okay"; +}; + +/* FIXME: Add device */ +&i2c0 { + status = "okay"; +}; + +/* FIXME: Add device */ +&i2c1 { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig new file mode 100644 index 000000000000..6d716fe945df --- /dev/null +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -0,0 +1,33 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_GPIO=y +CONFIG_ZYNQMP_USB=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig new file mode 100644 index 000000000000..c4da7b110fbb --- /dev/null +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_GPIO=y +CONFIG_ZYNQMP_USB=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MMC=y +CONFIG_NAND_ARASAN=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SST=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig new file mode 100644 index 000000000000..296fd66f9fb0 --- /dev/null +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_GPIO=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_DM_MMC=y +CONFIG_DM_ETH=y diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h new file mode 100644 index 000000000000..7aa993688158 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h @@ -0,0 +1,31 @@ +/* + * Configuration for Xilinx ZynqMP zc1751 XM015 DC1 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H +#define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_ZYNQ_I2C1 +#define CONFIG_SYS_I2C_ZYNQ +#define CONFIG_AHCI +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1" + +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=zc1751-dc1\0" + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h new file mode 100644 index 000000000000..2727dc6e0708 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h @@ -0,0 +1,28 @@ +/* + * Configuration for Xilinx ZynqMP zc1751 XM016 DC2 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H +#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H + +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_SYS_I2C_ZYNQ +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR} + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2" + +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=zc1751-dc2\0" + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h new file mode 100644 index 000000000000..d9409bad6552 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h @@ -0,0 +1,30 @@ +/* + * Configuration for Xilinx ZynqMP zc1751 XM019 DC5 + * + * (C) Copyright 2015 Xilinx, Inc. + * Siva Durga Prasad siva.durga.paladugu@xilinx.com + * Michal Simek michal.simek@xilinx.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H +#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_I2C1 +#define CONFIG_SYS_I2C_ZYNQ + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5" + +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=zc1751-dc5\0" + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */

-- 1.9.1

Michal Simek

7:06 p.m.

New subject: [U-Boot] [PATCH 33/33] ARM64: zynqmp: Clean header after moving stuff to Kconfig

Moving stuff to Kconfig by script is keep some empty lines or comment in the file. Remove them.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

include/configs/xilinx_zynqmp.h | 3 --- 1 file changed, 3 deletions(-)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index a60325517647..f7b4643708f4 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -17,7 +17,6 @@

#define CONFIG_SYS_NO_FLASH

- /* Generic Interrupt Controller Definitions */ #define CONFIG_GICV2 #define GICD_BASE 0xF9010000 @@ -44,8 +43,6 @@

#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE

-/* Flat Device Tree Definitions */ - /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ #if !defined(COUNTER_FREQUENCY) # define COUNTER_FREQUENCY 100000000

-- 1.9.1

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Michal Simek