[PATCH v2 0/5] Adding support for KSZ9131 and add it to Toradex boards
Hello,
This patch series enables support for the new KSZ9131 PHY. This PHY is a successor of the KSZ9031 and mostly software compatible but fixes some problems the KSZ9031 had.
The patch series also takes care skew values are correctly set on Toradex boards where we will change to KSZ9131. On Verdin this Series corrects wrong values that are currently in.
Overview of the series: Patches 1-2: Add KSZ9131 functionality Patches 3-6: Add KSZ9131 skew values for Toradex boards.
Changes in v2: - Dropped duplicate patch 'ARM: dts: verdin-imx8mm: Remove unsupported rxc/txc MAC dly properties' of [1], that in the meantime already got merged.
[1] https://patchwork.ozlabs.org/patch/1238012/
Philippe Schenker (5): net: phy: micrel: Use defines for PHY_IDs and MASK net: phy: micrel: Add basic support for KSZ9131 verdin-imx8mm: Change board phy skew values for our ksz9031 board: verdin-imx8mm: Add KSZ9131 phy skew settings board: apalis_imx6: Add KSZ9131 phy skew settings
board/toradex/apalis_imx6/apalis_imx6.c | 89 +++++++++++++++++---- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 63 +++++++++++++-- drivers/net/phy/micrel_ksz90x1.c | 62 +++++++++++++- include/micrel.h | 11 +++ 4 files changed, 200 insertions(+), 25 deletions(-)
Signed-off-by: Philippe Schenker philippe.schenker@toradex.com ---
drivers/net/phy/micrel_ksz90x1.c | 4 ++-- include/micrel.h | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index 0105fc5af1e..f83650b8ef6 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -383,8 +383,8 @@ static int ksz9031_config(struct phy_device *phydev)
static struct phy_driver ksz9031_driver = { .name = "Micrel ksz9031", - .uid = 0x221620, - .mask = 0xfffff0, + .uid = PHY_ID_KSZ9031, + .mask = MII_KSZ9x31_SILICON_REV_MASK, .features = PHY_GBIT_FEATURES, .config = &ksz9031_config, .startup = &ksz90xx_startup, diff --git a/include/micrel.h b/include/micrel.h index 3e6b5312d85..1d121c2825b 100644 --- a/include/micrel.h +++ b/include/micrel.h @@ -23,6 +23,11 @@ #define MII_KSZ9031_FLP_BURST_TX_LO 0x3 #define MII_KSZ9031_FLP_BURST_TX_HI 0x4
+#define MII_KSZ9x31_SILICON_REV_MASK 0xfffff0 + +#define PHY_ID_KSZ9031 0x00221620 + + /* Registers */ #define MMD_ACCESS_CONTROL 0xd #define MMD_ACCESS_REG_DATA 0xe
Signed-off-by: Philippe Schenker philippe.schenker@toradex.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
This adds basic support for the new Micrel KSZ9131 phy.
Signed-off-by: Philippe Schenker philippe.schenker@toradex.com ---
drivers/net/phy/micrel_ksz90x1.c | 58 ++++++++++++++++++++++++++++++++ include/micrel.h | 2 ++ 2 files changed, 60 insertions(+)
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index f83650b8ef6..f0032e8ce16 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -393,9 +393,67 @@ static struct phy_driver ksz9031_driver = { .readext = &ksz9031_phy_extread, };
+/* + * KSZ9131 + */ +static int ksz9131_config(struct phy_device *phydev) +{ + /* TBD: Implement Skew values for dts */ + + /* add an option to disable the gigabit feature of this PHY */ + if (env_get("disable_giga")) { + unsigned features; + unsigned bmcr; + + /* disable speed 1000 in features supported by the PHY */ + features = phydev->drv->features; + features &= ~(SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full); + phydev->advertising = phydev->supported = features; + + /* disable speed 1000 in Basic Control Register */ + bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + bmcr &= ~(1 << 6); + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr); + + /* disable speed 1000 in 1000Base-T Control Register */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0); + + /* start autoneg */ + genphy_config_aneg(phydev); + genphy_restart_aneg(phydev); + + return 0; + } + + return genphy_config(phydev); +} + +static struct phy_driver ksz9131_driver = { + .name = "Micrel ksz9031", + .uid = PHY_ID_KSZ9131, + .mask = MII_KSZ9x31_SILICON_REV_MASK, + .features = PHY_GBIT_FEATURES, + .config = &ksz9131_config, + .startup = &ksz90xx_startup, + .shutdown = &genphy_shutdown, + .writeext = &ksz9031_phy_extwrite, + .readext = &ksz9031_phy_extread, +}; + +int ksz9xx1_phy_get_id(struct phy_device *phydev) +{ + unsigned int phyid; + + get_phy_id(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, &phyid); + + return phyid; +} + int phy_micrel_ksz90x1_init(void) { phy_register(&ksz9021_driver); phy_register(&ksz9031_driver); + phy_register(&ksz9131_driver); return 0; } diff --git a/include/micrel.h b/include/micrel.h index 1d121c2825b..f5126f29929 100644 --- a/include/micrel.h +++ b/include/micrel.h @@ -26,6 +26,7 @@ #define MII_KSZ9x31_SILICON_REV_MASK 0xfffff0
#define PHY_ID_KSZ9031 0x00221620 +#define PHY_ID_KSZ9131 0x00221640
/* Registers */ @@ -40,5 +41,6 @@ int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr, int regnum, u16 mode, u16 val); int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr, int regnum, u16 mode); +int ksz9xx1_phy_get_id(struct phy_device *phydev);
#endif
This adds basic support for the new Micrel KSZ9131 phy. Signed-off-by: Philippe Schenker philippe.schenker@toradex.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
This patches uses the existing functions for interacting with the KSZ9031 and uses the values appropriate for our board.
Signed-off-by: Philippe Schenker philippe.schenker@toradex.com Tested-by: Igor Opaniuk igor.opaniuk@toradex.com Acked-by: Igor Opaniuk igor.opaniuk@toradex.com ---
board/toradex/verdin-imx8mm/verdin-imx8mm.c | 32 +++++++++++++++------ 1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 16b9fa1ec18..3177ba53907 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <miiphy.h> #include <netdev.h> +#include <micrel.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -32,14 +33,29 @@ static int setup_fec(void)
int board_phy_config(struct phy_device *phydev) { - /* enable rgmii rxc skew and phy mode select to RGMII copper */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); - - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + /* + * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by + * default. The MAC and the layout don't add a skew between + * clock and data. + * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for + * the TXC path to get the required clock skews. + */ + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0070); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x7777); + /* tx data pad skew - devaddr = 0x02, register = 0x06 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03f4);
if (phydev->drv->config) phydev->drv->config(phydev);
This patches uses the existing functions for interacting with the KSZ9031 and uses the values appropriate for our board. Signed-off-by: Philippe Schenker philippe.schenker@toradex.com Tested-by: Igor Opaniuk igor.opaniuk@toradex.com Acked-by: Igor Opaniuk igor.opaniuk@toradex.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
This patch determines which phy is placed on the board with the PHY ID then it sets the same settings for KSZ9031 as before but for KSZ9131 it enables both RXC and TXC delay lines in the PHY. This will compensate the missing delay from the MAC. Other skew settings are not needed as the traces on board are routed exactly the same length
Signed-off-by: Philippe Schenker philippe.schenker@toradex.com Tested-by: Igor Opaniuk igor.opaniuk@toradex.com Acked-by: Igor Opaniuk igor.opaniuk@toradex.com ---
board/toradex/verdin-imx8mm/verdin-imx8mm.c | 79 +++++++++++++++------ 1 file changed, 56 insertions(+), 23 deletions(-)
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 3177ba53907..57c4befcfdd 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -33,29 +33,62 @@ static int setup_fec(void)
int board_phy_config(struct phy_device *phydev) { - /* - * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by - * default. The MAC and the layout don't add a skew between - * clock and data. - * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for - * the TXC path to get the required clock skews. - */ - /* control data pad skew - devaddr = 0x02, register = 0x04 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0070); - /* rx data pad skew - devaddr = 0x02, register = 0x05 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x7777); - /* tx data pad skew - devaddr = 0x02, register = 0x06 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03f4); + int tmp; + + switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) { + case PHY_ID_KSZ9031: + /* + * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by + * default. The MAC and the layout don't add a skew between + * clock and data. + * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for + * the TXC path to get the required clock skews. + */ + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0070); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x7777); + /* tx data pad skew - devaddr = 0x02, register = 0x06 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x03f4); + break; + case PHY_ID_KSZ9131: + default: + /* read rxc dll control - devaddr = 0x2, register = 0x4c */ + tmp = ksz9031_phy_extended_read(phydev, 0x02, + MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL, + MII_KSZ9031_MOD_DATA_NO_POST_INC); + /* disable rxdll bypass (enable 2ns skew delay on RXC) */ + tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS; + /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */ + tmp = ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL, + MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp); + /* read txc dll control - devaddr = 0x02, register = 0x4d */ + tmp = ksz9031_phy_extended_read(phydev, 0x02, + MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL, + MII_KSZ9031_MOD_DATA_NO_POST_INC); + /* disable txdll bypass (enable 2ns skew delay on TXC) */ + tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS; + /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */ + tmp = ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL, + MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp); + break; + }
if (phydev->drv->config) phydev->drv->config(phydev);
This patch determines which phy is placed on the board with the PHY ID then it sets the same settings for KSZ9031 as before but for KSZ9131 it enables both RXC and TXC delay lines in the PHY. This will compensate the missing delay from the MAC. Other skew settings are not needed as the traces on board are routed exactly the same length Signed-off-by: Philippe Schenker philippe.schenker@toradex.com Tested-by: Igor Opaniuk igor.opaniuk@toradex.com Acked-by: Igor Opaniuk igor.opaniuk@toradex.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
This patch adds skew register settings for KSZ9131. It checks first which phy is on the board and then applies the correct skew settings.
Skew settings calculation for the KSZ9131: The i.MX6 SoC has an output skew tolerance of -100ps to 900ps. All PCB traces where routed exactly the same length so we can calculate the skew settings without taking the length into consideration. The traces are all length matched.
RXC skew (PHY to MAC): - We use the 2ns DLL controlled delay on the PHY - We do not use the skew registers
This results in the following values:
RXC PHY fixed Delay 2000ps PHY Added Delay 0ps T_setup_R min 2.00ns T_setup_R typ 2.00ns T_setup_R max 2.00ns T_hold_R min 1.60ns T_hold_R typ 2.00ns T_hold_R max 2.40ns
That means we are well within RGMII specs.
TXC skew (MAC to PHY): - We use the 2ns DLL controlled delay on the PHY - We then subtract ~0.6ns with TXD[0:3] and TXC clock pad skew register in a resulting ~1.4ns delay.
This results in the following values under consideration of the tolerances:
TXC min TXC typ TXC max MAC min -100ps -100ps -100ps MAC max 900ps 900ps 900ps PHY fixed Delay 2000ps 2000ps 2000ps PHY added Delay -340ps -600ps -859ps T_setup_T min 1.56ns 1.30ns 1.04ns T_setup_T typ 2.06ns 1.80ns 1.54ns T_setup_T max 2.56ns 2.30ns 2.04ns T_hold_T min 1.04ns 1.30ns 1.56ns T_hold_T typ 1.94ns 2.20ns 2.46ns T_hold_T max 2.84ns 3.10ns 3.36ns
This shows that T_hold_T min and T_setup_T min times are out of spec for RGMII timing. However the KSZ9131 has a minimal value for this time of 0.8ns which is met under all circumstances.
Signed-off-by: Philippe Schenker philippe.schenker@toradex.com
---
board/toradex/apalis_imx6/apalis_imx6.c | 89 ++++++++++++++++++++----- include/micrel.h | 4 ++ 2 files changed, 77 insertions(+), 16 deletions(-)
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 3f85f1ac89b..8c4a359c750 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -137,22 +137,79 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
int mx6_rgmii_rework(struct phy_device *phydev) { - /* control data pad skew - devaddr = 0x02, register = 0x04 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* rx data pad skew - devaddr = 0x02, register = 0x05 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* tx data pad skew - devaddr = 0x02, register = 0x05 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); + int tmp; + + switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) { + case PHY_ID_KSZ9131: + /* read rxc dll control - devaddr = 0x02, register = 0x4c */ + tmp = ksz9031_phy_extended_read(phydev, 0x02, + MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL, + MII_KSZ9031_MOD_DATA_NO_POST_INC); + /* disable rxdll bypass (enable 2ns skew delay on RXC) */ + tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS; + /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + tmp); + /* read txc dll control - devaddr = 0x02, register = 0x4d */ + tmp = ksz9031_phy_extended_read(phydev, 0x02, + MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL, + MII_KSZ9031_MOD_DATA_NO_POST_INC); + /* disable rxdll bypass (enable 2ns skew delay on TXC) */ + tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS; + /* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + tmp); + + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x007d); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x7777); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0xdddd); + /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0007); + break; + case PHY_ID_KSZ9031: + default: + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x03FF); + break; + } + return 0; }
diff --git a/include/micrel.h b/include/micrel.h index f5126f29929..a2593c5b10c 100644 --- a/include/micrel.h +++ b/include/micrel.h @@ -25,6 +25,10 @@
#define MII_KSZ9x31_SILICON_REV_MASK 0xfffff0
+#define MII_KSZ9131_RXTXDLL_BYPASS BIT(12) +#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL 0x4c +#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL 0x4d + #define PHY_ID_KSZ9031 0x00221620 #define PHY_ID_KSZ9131 0x00221640
This patch adds skew register settings for KSZ9131. It checks first which phy is on the board and then applies the correct skew settings. Skew settings calculation for the KSZ9131: The i.MX6 SoC has an output skew tolerance of -100ps to 900ps. All PCB traces where routed exactly the same length so we can calculate the skew settings without taking the length into consideration. The traces are all length matched. RXC skew (PHY to MAC):
- We use the 2ns DLL controlled delay on the PHY
- We do not use the skew registers
This results in the following values: RXC PHY fixed Delay 2000ps PHY Added Delay 0ps T_setup_R min 2.00ns T_setup_R typ 2.00ns T_setup_R max 2.00ns T_hold_R min 1.60ns T_hold_R typ 2.00ns T_hold_R max 2.40ns That means we are well within RGMII specs. TXC skew (MAC to PHY):
- We use the 2ns DLL controlled delay on the PHY
- We then subtract ~0.6ns with TXD[0:3] and TXC clock pad skew register in a resulting ~1.4ns delay.
This results in the following values under consideration of the tolerances: TXC min TXC typ TXC max MAC min -100ps -100ps -100ps MAC max 900ps 900ps 900ps PHY fixed Delay 2000ps 2000ps 2000ps PHY added Delay -340ps -600ps -859ps T_setup_T min 1.56ns 1.30ns 1.04ns T_setup_T typ 2.06ns 1.80ns 1.54ns T_setup_T max 2.56ns 2.30ns 2.04ns T_hold_T min 1.04ns 1.30ns 1.56ns T_hold_T typ 1.94ns 2.20ns 2.46ns T_hold_T max 2.84ns 3.10ns 3.36ns This shows that T_hold_T min and T_setup_T min times are out of spec for RGMII timing. However the KSZ9131 has a minimal value for this time of 0.8ns which is met under all circumstances. Signed-off-by: Philippe Schenker philippe.schenker@toradex.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
participants (2)
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Philippe Schenker -
sbabic＠denx.de