[U-Boot] [PATCH 0/6] ARM: DRA7: Add support for RevH evm
DRA74-evm RevH and later versions uses 4GB DDR and populates this info in EEPROM. This series reads EEPROM and populates emif settings for 4GB ddr. If eeprom is not available or evm revision is < H, then it fall backs to default emif settings.
This series depends on the ti common eeprom driver series posted recently. https://www.mail-archive.com/u-boot%40lists.denx.de/msg204549.html
Tested on DRA7 RevH: http://pastebin.ubuntu.com/15291175/ DRA7 RevG: http://pastebin.ubuntu.com/15291197/
Lokesh Vutla (6): ti: common: dra7: Add standard access for board description EEPROM ARM: DRA7: Enable EEPROM support ARM: DRA7: Move emif settings to board specific files ARM: DRA7: EMIF: Add 4GB DDR settings ARM: DRA7: configs: Prepare for detecting memory > 2GB ARM: DRA7-evm: Update memory info in banks
arch/arm/cpu/armv7/omap5/Kconfig | 1 + arch/arm/cpu/armv7/omap5/sdram.c | 149 +-------------------- board/ti/common/board_detect.c | 64 +++++++++ board/ti/common/board_detect.h | 56 ++++++++ board/ti/dra7xx/Kconfig | 3 + board/ti/dra7xx/evm.c | 279 ++++++++++++++++++++++++++++++++++++++- include/configs/dra7xx_evm.h | 9 ++ 7 files changed, 410 insertions(+), 151 deletions(-)
DRA7 EVM revH and later EVMs have EEPROM populated that can contain board description information such as name, revision, DDR definition, etc. Adding support for this EEPROM format.
Acked-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/common/board_detect.c | 64 ++++++++++++++++++++++++++++++++++++++++++ board/ti/common/board_detect.h | 56 ++++++++++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+)
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index 6cf4859..e0ae1a5 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -160,6 +160,50 @@ already_read: return 0; }
+int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr) +{ + int rc, offset = 0; + struct dra7_eeprom dra7_ep; + struct ti_common_eeprom *ep; + + ep = TI_EEPROM_DATA; + if (ep->header == DRA7_EEPROM_HEADER_MAGIC) + goto already_read; + + /* Initialize with a known bad marker for i2c fails.. */ + ep->header = 0xADEAD12C; + ep->name[0] = 0x0; + ep->version[0] = 0x0; + ep->serial[0] = 0x0; + ep->emif1_size = 0; + ep->emif2_size = 0; + + rc = ti_i2c_eeprom_get(bus_addr, dev_addr, DRA7_EEPROM_HEADER_MAGIC, + sizeof(dra7_ep), (uint8_t *)&dra7_ep); + if (rc) + return rc; + + ep->header = dra7_ep.header; + strlcpy(ep->name, dra7_ep.name, TI_EEPROM_HDR_NAME_LEN + 1); + ti_eeprom_string_cleanup(ep->name); + + offset = dra7_ep.version_major - 1; + + /* Rev F is skipped */ + if (offset >= 5) + offset = offset + 1; + snprintf(ep->version, TI_EEPROM_HDR_REV_LEN + 1, "%c.%d", + 'A' + offset, dra7_ep.version_minor); + ti_eeprom_string_cleanup(ep->version); + ep->emif1_size = (u64)dra7_ep.emif1_size; + ep->emif2_size = (u64)dra7_ep.emif2_size; + strlcpy(ep->config, dra7_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1); + ti_eeprom_string_cleanup(ep->config); + +already_read: + return 0; +} + bool __maybe_unused board_ti_is(char *name_tag) { struct ti_common_eeprom *ep = TI_EEPROM_DATA; @@ -230,6 +274,26 @@ fail: memset(mac_addr, 0, TI_EEPROM_HDR_ETH_ALEN); }
+u64 __maybe_unused board_ti_get_emif1_size(void) +{ + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + + if (ep->header != DRA7_EEPROM_HEADER_MAGIC) + return 0; + + return ep->emif1_size; +} + +u64 __maybe_unused board_ti_get_emif2_size(void) +{ + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + + if (ep->header != DRA7_EEPROM_HEADER_MAGIC) + return 0; + + return ep->emif2_size; +} + void __maybe_unused set_board_info_env(char *name) { char *unknown = "unknown"; diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h index c17ab34..eb17f6f 100644 --- a/board/ti/common/board_detect.h +++ b/board/ti/common/board_detect.h @@ -44,6 +44,37 @@ struct ti_am_eeprom { char mac_addr[TI_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN]; } __attribute__ ((__packed__));
+/* DRA7 EEPROM MAGIC Header identifier */ +#define DRA7_EEPROM_HEADER_MAGIC 0xAA5533EE +#define DRA7_EEPROM_HDR_NAME_LEN 16 +#define DRA7_EEPROM_HDR_CONFIG_LEN 4 + +/** + * struct dra7_eeprom - This structure holds data read in from the DRA7 EVM + * EEPROMs. + * @header: This holds the magic number + * @name: The name of the board + * @version_major: Board major version + * @version_minor: Board minor version + * @config: Board specific config options + * @emif1_size: Size of DDR attached to EMIF1 + * @emif2_size: Size of DDR attached to EMIF2 + * + * The data is this structure is read from the EEPROM on the board. + * It is used for board detection which is based on name. It is used + * to configure specific DRA7 boards. This allows booting of multiple + * DRA7 boards with a single MLO and u-boot. + */ +struct dra7_eeprom { + u32 header; + char name[DRA7_EEPROM_HDR_NAME_LEN]; + u16 version_major; + u16 version_minor; + char config[DRA7_EEPROM_HDR_CONFIG_LEN]; + u32 emif1_size; + u32 emif2_size; +} __attribute__ ((__packed__)); + /** * struct ti_common_eeprom - Null terminated, usable EEPROM contents. * header: Magic number @@ -52,6 +83,8 @@ struct ti_am_eeprom { * @serial: NULL terminated serial number * @config: NULL terminated Board specific config options * @mac_addr: MAC addresses + * @emif1_size: Size of the ddr available on emif1 + * @emif2_size: Size of the ddr available on emif2 */ struct ti_common_eeprom { u32 header; @@ -60,6 +93,8 @@ struct ti_common_eeprom { char serial[TI_EEPROM_HDR_SERIAL_LEN + 1]; char config[TI_EEPROM_HDR_CONFIG_LEN + 1]; char mac_addr[TI_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN]; + u64 emif1_size; + u64 emif2_size; };
#define TI_EEPROM_DATA ((struct ti_common_eeprom *)\ @@ -76,6 +111,13 @@ struct ti_common_eeprom { int ti_i2c_eeprom_am_get(int bus_addr, int dev_addr);
/** + * ti_i2c_eeprom_dra7_get() - Consolidated eeprom data for DRA7 TI EVMs + * @bus_addr: I2C bus address + * @dev_addr: I2C slave address + */ +int ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr); + +/** * board_ti_is() - Board detection logic for TI EVMs * @name_tag: Tag used in eeprom for the board * @@ -130,6 +172,20 @@ char *board_ti_get_name(void); void board_ti_get_eth_mac_addr(int index, u8 mac_addr[TI_EEPROM_HDR_ETH_ALEN]);
/** + * board_ti_get_emif1_size() - Get size of the DDR on emif1 for TI EVMs + * + * Return: NULL if eeprom was'nt read or emif1_size is not available. + */ +u64 board_ti_get_emif1_size(void); + +/** + * board_ti_get_emif2_size() - Get size of the DDR on emif2 for TI EVMs + * + * Return: NULL if eeprom was'nt read or emif2_size is not available. + */ +u64 board_ti_get_emif2_size(void); + +/** * set_board_info_env() - Setup commonly used board information environment vars * @name: Name of the board *
On Sat, Mar 05, 2016 at 05:35:13PM +0530, Lokesh Vutla wrote:
DRA7 EVM revH and later EVMs have EEPROM populated that can contain board description information such as name, revision, DDR definition, etc. Adding support for this EEPROM format.
Acked-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
Enable EEPROM support for DRA74-evm.
Acked-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/Kconfig | 1 + board/ti/dra7xx/Kconfig | 3 ++ board/ti/dra7xx/evm.c | 59 +++++++++++++++++++++++++++++++++++++--- include/configs/dra7xx_evm.h | 4 +++ 4 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index f265b34..026bf24 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -12,6 +12,7 @@ config TARGET_OMAP5_UEVM
config TARGET_DRA7XX_EVM bool "TI DRA7XX" + select TI_I2C_BOARD_DETECT
config TARGET_BEAGLE_X15 bool "BeagleBoard X15" diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig index 80341d9..b642113 100644 --- a/board/ti/dra7xx/Kconfig +++ b/board/ti/dra7xx/Kconfig @@ -17,4 +17,7 @@ config CONS_INDEX The DRA7xx (and AM57x) SoC has a total of 6 UARTs available to it. Depending on your specific board you may want something other than UART1 here. + +source "board/ti/common/Kconfig" + endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index eebec88..a47122b 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -13,6 +13,7 @@ #include <common.h> #include <palmas.h> #include <sata.h> +#include <linux/string.h> #include <asm/gpio.h> #include <usb.h> #include <linux/usb/gadget.h> @@ -27,6 +28,11 @@ #include <ti-usb-phy-uboot.h>
#include "mux_data.h" +#include "../common/board_detect.h" + +#define board_is_dra74x_evm() board_ti_is("5777xCPU") +#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \ + (strncmp("H", board_ti_get_rev(), 1) <= 0)
#ifdef CONFIG_DRIVER_TI_CPSW #include <cpsw.h> @@ -37,8 +43,10 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO 7_11 */ #define GPIO_DDR_VTT_EN 203
+#define SYSINFO_BOARD_NAME_MAX_LEN 37 + const struct omap_sysinfo sysinfo = { - "Board: DRA7xx\n" + "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" };
/** @@ -57,16 +65,59 @@ int board_init(void) int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (omap_revision() == DRA722_ES1_0) - setenv("board_name", "dra72x"); + char *name = "unknown"; + + if (is_dra72x()) + name = "dra72x"; else - setenv("board_name", "dra7xx"); + name = "dra7xx"; + + set_board_info_env(name);
omap_die_id_serial(); #endif return 0; }
+#ifdef CONFIG_SPL_BUILD +void do_board_detect(void) +{ + int rc; + + rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (rc) + printf("ti_i2c_eeprom_init failed %d\n", rc); +} + +#else + +void do_board_detect(void) +{ + char *bname = NULL; + int rc; + + rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (rc) + printf("ti_i2c_eeprom_init failed %d\n", rc); + + if (board_is_dra74x_evm()) { + bname = "DRA74x EVM"; + /* If EEPROM is not populated */ + } else { + if (is_dra72x()) + bname = "DRA72x EVM"; + else + bname = "DRA74x EVM"; + } + + if (bname) + snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, + "Board: %s REV %s\n", bname, board_ti_get_rev()); +} +#endif /* CONFIG_SPL_BUILD */ + void set_muxconf_regs_essential(void) { do_set_mux32((*ctrl)->control_padconf_core_base, diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 0196280..e79250b 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -341,4 +341,8 @@ #endif #endif /* NOR support */
+/* EEPROM */ +#define CONFIG_EEPROM_CHIP_ADDRESS 0x50 +#define CONFIG_EEPROM_BUS_ADDRESS 0 + #endif /* __CONFIG_DRA7XX_EVM_H */
On Sat, Mar 05, 2016 at 05:35:14PM +0530, Lokesh Vutla wrote:
Enable EEPROM support for DRA74-evm.
Acked-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM.
Acked-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/sdram.c | 149 +-------------------------------------- board/ti/dra7xx/evm.c | 129 +++++++++++++++++++++++++++++++++ 2 files changed, 131 insertions(+), 147 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index c386e64..7dc5bb7 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -137,81 +137,6 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { .emif_rd_wr_exec_thresh = 0x40000305 };
-const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { - .sdram_config_init = 0x61851ab2, - .sdram_config = 0x61851ab2, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, - .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400B, - .emif_ddr_phy_ctlr_1 = 0x0E24400B, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, - .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { - .sdram_config_init = 0x61851B32, - .sdram_config = 0x61851B32, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, - .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400B, - .emif_ddr_phy_ctlr_1 = 0x0E24400B, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, - .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { - .sdram_config_init = 0x61862B32, - .sdram_config = 0x61862B32, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x0000514C, - .ref_ctrl_final = 0x0000144A, - .sdram_tim1 = 0xD113781C, - .sdram_tim2 = 0x305A7FDA, - .sdram_tim3 = 0x409F86A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x5007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400D, - .emif_ddr_phy_ctlr_1 = 0x0E24400D, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, - .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, - .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, - .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, @@ -220,53 +145,6 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .is_ma_present = 0x1 };
-/* - * DRA752 EVM board has 1.5 GB of memory - * EMIF1 --> 2Gb * 2 = 512MB - * EMIF2 --> 2Gb * 4 = 1GB - * so mapping 1GB interleaved and 512MB non-interleaved - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x80640300, - .dmm_lisa_map_2 = 0xC0500220, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - -/* - * DRA752 EVM EMIF1 ONLY CONFIGURATION - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x80500100, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - -/* - * DRA752 EVM EMIF2 ONLY CONFIGURATION - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x80600200, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - -/* - * DRA722 EVM EMIF1 CONFIGURATION - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x80600100, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { switch (omap_revision()) { @@ -280,25 +158,9 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_532_mhz_2cs_es2; break; case OMAP5432_ES2_0: + default: *regs = &emif_regs_ddr3_532_mhz_1cs_es2; break; - case DRA752_ES1_0: - case DRA752_ES1_1: - case DRA752_ES2_0: - switch (emif_nr) { - case 1: - *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; - break; - case 2: - *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1; - break; - } - break; - case DRA722_ES1_0: - *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; - break; - default: - *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; } }
@@ -313,16 +175,9 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs case OMAP5430_ES2_0: case OMAP5432_ES1_0: case OMAP5432_ES2_0: + default: *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; break; - case DRA752_ES1_0: - case DRA752_ES1_1: - case DRA752_ES2_0: - *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; - break; - case DRA722_ES1_0: - default: - *dmm_lisa_regs = &lisa_map_2G_x_2; }
} diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index a47122b..c493c64 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -19,6 +19,7 @@ #include <linux/usb/gadget.h> #include <asm/arch/gpio.h> #include <asm/arch/dra7xx_iodelay.h> +#include <asm/emif.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sata.h> @@ -49,6 +50,134 @@ const struct omap_sysinfo sysinfo = { "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" };
+static const struct emif_regs emif1_ddr3_532_mhz_1cs = { + .sdram_config_init = 0x61851ab2, + .sdram_config = 0x61851ab2, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x427F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const struct emif_regs emif2_ddr3_532_mhz_1cs = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x427F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { + .sdram_config_init = 0x61862B32, + .sdram_config = 0x61862B32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x0000514C, + .ref_ctrl_final = 0x0000144A, + .sdram_tim1 = 0xD113781C, + .sdram_tim2 = 0x30717FE3, + .sdram_tim3 = 0x409F86A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400D, + .emif_ddr_phy_ctlr_1 = 0x0E24400D, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, + .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, + .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + case DRA752_ES2_0: + switch (emif_nr) { + case 1: + *regs = &emif1_ddr3_532_mhz_1cs; + break; + case 2: + *regs = &emif2_ddr3_532_mhz_1cs; + break; + } + break; + case DRA722_ES1_0: + *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; + break; + default: + *regs = &emif1_ddr3_532_mhz_1cs; + } +} + +static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x80640300, + .dmm_lisa_map_2 = 0xC0500220, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80600100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + case DRA752_ES2_0: + *dmm_lisa_regs = &lisa_map_dra7_1536MB; + break; + case DRA722_ES1_0: + default: + *dmm_lisa_regs = &lisa_map_2G_x_2; + } +} + /** * @brief board_init *
On Sat, Mar 05, 2016 at 05:35:15PM +0530, Lokesh Vutla wrote:
The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM.
Acked-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same.
Acked-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/dra7xx/evm.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 80 insertions(+), 3 deletions(-)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index c493c64..d142ccc 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -34,6 +34,8 @@ #define board_is_dra74x_evm() board_ti_is("5777xCPU") #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \ (strncmp("H", board_ti_get_rev(), 1) <= 0) +#define board_ti_get_emif_size() board_ti_get_emif1_size() + \ + board_ti_get_emif2_size()
#ifdef CONFIG_DRIVER_TI_CPSW #include <cpsw.h> @@ -125,18 +127,78 @@ static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .emif_rd_wr_exec_thresh = 0x00000305 };
+const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { + .sdram_config_init = 0x61851ab2, + .sdram_config = 0x61851ab2, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x30BF7FDA, + .sdram_tim3 = 0x427F8BA8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x427F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) { + u64 ram_size; + + ram_size = board_ti_get_emif_size(); + switch (omap_revision()) { case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: switch (emif_nr) { case 1: - *regs = &emif1_ddr3_532_mhz_1cs; + if (ram_size > CONFIG_MAX_MEM_MAPPED) + *regs = &emif1_ddr3_532_mhz_1cs_2G; + else + *regs = &emif1_ddr3_532_mhz_1cs; break; case 2: - *regs = &emif2_ddr3_532_mhz_1cs; + if (ram_size > CONFIG_MAX_MEM_MAPPED) + *regs = &emif2_ddr3_532_mhz_1cs_2G; + else + *regs = &emif2_ddr3_532_mhz_1cs; break; } break; @@ -164,13 +226,28 @@ static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { .is_ma_present = 0x1 };
+const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80740300, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { + u64 ram_size; + + ram_size = board_ti_get_emif_size(); + switch (omap_revision()) { case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: - *dmm_lisa_regs = &lisa_map_dra7_1536MB; + if (ram_size > CONFIG_MAX_MEM_MAPPED) + *dmm_lisa_regs = &lisa_map_dra7_2GB; + else + *dmm_lisa_regs = &lisa_map_dra7_1536MB; break; case DRA722_ES1_0: default:
On Sat, Mar 05, 2016 at 05:35:16PM +0530, Lokesh Vutla wrote:
The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same.
Acked-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
Enable configs that are required for detecting memory > 2GB.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- include/configs/dra7xx_evm.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index e79250b..45bda4f 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -19,6 +19,11 @@ #define CONFIG_IODELAY_RECALIBRATION #endif
+#define CONFIG_VERY_BIG_RAM +#define CONFIG_PHYS_64BIT +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_MAX_MEM_MAPPED 0x80000000 + #ifndef CONFIG_QSPI_BOOT /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC
On Sat, Mar 05, 2016 at 05:35:17PM +0530, Lokesh Vutla wrote:
Enable configs that are required for detecting memory > 2GB.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
This needs to be either folded into 4/6 or re-ordered to not break bisectability.
Contents: Reviewed-by: Tom Rini trini@konsulko.com
On Tuesday 08 March 2016 05:06 AM, Tom Rini wrote:
On Sat, Mar 05, 2016 at 05:35:17PM +0530, Lokesh Vutla wrote:
Enable configs that are required for detecting memory > 2GB.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
This needs to be either folded into 4/6 or re-ordered to not break bisectability.
Okay Ill reorder 4 and 5 and resend.
Thanks and regards, Lokesh
Contents: Reviewed-by: Tom Rini trini@konsulko.com
Updating the memory banks properly so that DT is populated accordingly. And updating this only after DDR is properly detected by eeprom, so that git bisect is still maintained.
Acked-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/dra7xx/evm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index d142ccc..4c6dfa0 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -268,6 +268,20 @@ int board_init(void) return 0; }
+void dram_init_banksize(void) +{ + u64 ram_size; + + ram_size = board_ti_get_emif_size(); + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = get_effective_memsize(); + if (ram_size > CONFIG_MAX_MEM_MAPPED) { + gd->bd->bi_dram[1].start = 0x200000000; + gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; + } +} + int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
On Sat, Mar 05, 2016 at 05:35:18PM +0530, Lokesh Vutla wrote:
Updating the memory banks properly so that DT is populated accordingly. And updating this only after DDR is properly detected by eeprom, so that git bisect is still maintained.
Acked-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
participants (3)
-
Lokesh Vutla -
Lokesh Vutla -
Tom Rini