Add cpu support for nds32 arch. Included support of common cpu setting, core n1213, SoC ag101.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- arch/nds32/config.mk | 34 +++ arch/nds32/cpu/Makefile | 52 ++++ arch/nds32/cpu/cpu.c | 197 +++++++++++++++ arch/nds32/cpu/lowlevel_init.S | 159 ++++++++++++ arch/nds32/cpu/n1213/Makefile | 51 ++++ arch/nds32/cpu/n1213/ag101/Makefile | 50 ++++ arch/nds32/cpu/n1213/ag101/cpu.c | 197 +++++++++++++++ arch/nds32/cpu/n1213/ag101/ftsmc020.c | 51 ++++ arch/nds32/cpu/n1213/ag101/timer.c | 213 ++++++++++++++++ arch/nds32/cpu/n1213/lowlevel_init.S | 159 ++++++++++++ arch/nds32/cpu/n1213/start.S | 447 +++++++++++++++++++++++++++++++++ arch/nds32/cpu/n1213/u-boot.lds | 68 +++++ arch/nds32/cpu/start.S | 447 +++++++++++++++++++++++++++++++++ 13 files changed, 2125 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/config.mk create mode 100644 arch/nds32/cpu/Makefile create mode 100644 arch/nds32/cpu/cpu.c create mode 100644 arch/nds32/cpu/lowlevel_init.S create mode 100644 arch/nds32/cpu/n1213/Makefile create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c create mode 100644 arch/nds32/cpu/n1213/ag101/ftsmc020.c create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c create mode 100644 arch/nds32/cpu/n1213/lowlevel_init.S create mode 100644 arch/nds32/cpu/n1213/start.S create mode 100644 arch/nds32/cpu/n1213/u-boot.lds create mode 100644 arch/nds32/cpu/start.S

diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk new file mode 100644 index 0000000..89568c2 --- /dev/null +++ b/arch/nds32/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2010 +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +CROSS_COMPILE ?= nds32le-linux- + +STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common +PLATFORM_CPPFLAGS += -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-8 + +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/nds32/cpu/Makefile b/arch/nds32/cpu/Makefile new file mode 100644 index 0000000..818795a --- /dev/null +++ b/arch/nds32/cpu/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2010 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = cpu.o interrupts.o +SOBJS = lowlevel_init.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/nds32/cpu/cpu.c b/arch/nds32/cpu/cpu.c new file mode 100644 index 0000000..e8b15cb --- /dev/null +++ b/arch/nds32/cpu/cpu.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include <common.h> +#include <command.h> + +/* + * setup up stack if necessary + */ +/* it makes no sense to use the caches if the MMU also isn't used */ +void cpu_init(void) +{ + _andesboot_real_end = _andesboot_end + CONFIG_STACKSIZE; +} + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +void cleanup_before_linux(void) +{ +#ifdef CONFIG_MMU + unsigned long i; +#endif + + disable_interrupts(); + +#ifdef CONFIG_MMU + /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); + + /* flush I/D-cache */ + invalidate_icac(); + invalidate_dcac(); +#endif +} + +void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + extern void reset_cpu(ulong addr); + + disable_interrupts(); + + /* + * reset to the base addr of andesboot. + * currently no ROM loader at addr 0. + * do not use reset_cpu(0); + */ + reset_cpu(TEXT_BASE); + + /*NOTREACHED*/ +} + +static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) +{ + if( cache == ICACHE) + return 8 << ( ( ( GET_ICM_CFG() & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1); + else + return 8 << ( ( ( GET_DCM_CFG() & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1); +} + +void dcache_flush_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + + while (end > start) { + __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" :: "r"(start)); + __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" :: "r"(start)); + start += line_size; + } +} + +void icache_inval_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(ICACHE); + while (end > start) { + __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" :: "r"(start)); + start += line_size; + } +} + +void flush_cache(unsigned long addr, unsigned long size) +{ + dcache_flush_range( addr , addr + size ); + icache_inval_range( addr , addr + size ); +} + +void icache_enable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "ori $p0, $p0, 0x01 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +void icache_disable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "li $p1, ~0x01 \n\t" + "and $p0, $p0, $p1 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +int icache_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "andi %0, $p0, 0x01 \n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} + +void dcache_enable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "ori $p0, $p0, 0x02 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +void dcache_disable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "li $p1, ~0x02 \n\t" + "and $p0, $p0, $p1 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +int dcache_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "andi %0, $p0, 0x02 \n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} diff --git a/arch/nds32/cpu/lowlevel_init.S b/arch/nds32/cpu/lowlevel_init.S new file mode 100644 index 0000000..f7fa12b --- /dev/null +++ b/arch/nds32/cpu/lowlevel_init.S @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.text + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +.globl lowlevel_init +lowlevel_init: + move $r10, $lp + jal mem_init + jal remap + + ret $r10 + +mem_init: + move $r11, $lp + li $r0, 0x90200000 + li $r1, 0x10000052 + swi $r1, [$r0] + li $r1, 0x00151151 + swi $r1, [$r0+0x4] + + li $r0, 0x90100018 + li $r1, 0x100b0000 + swi $r1, [$r0] + li $r0, 0x98100030 + lwi $r1, [$r0] + li $r2, 0x00010000 + or $r1, $r1, $r2 + swi $r1, [$r0] +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + lwi $r1, [$r0] + li $r2, 0x00e00000 + or $r1, $r1, $r2 + swi $r1, [$r0] + li $r0, 0x98100028 + lwi $r1, [$r0] + li $r2, 0x00000010 + or $r1, $r1, $r2 + swi $r1, [$r0] + li $r0, 0x9810004c + lwi $r1, [$r0] + li $r2, 0x0007f000 + or $r1, $r1, $r2 + swi $r1, [$r0] +#endif + li $r0, 0x90300000 + li $r1, 0x00011312 + swi $r1, [$r0] + li $r1, 0x00480180 + swi $r1, [$r0+0x4] + li $r1, 0x00002326 + swi $r1, [$r0+0x8] + li $r1, 0x00000010 + swi $r1, [$r0+0xc] +1: + lwi $r1, [$r0+0xc] + andi $r1, $r1, 0x1c + bnez $r1, 1b + + li $r1, 0x00000004 + swi $r1, [$r0+0xc] +2: + lwi $r1, [$r0+0xc] + bnez $r1, 2b + + li $r1, 0x00000008 + swi $r1, [$r0+0xc] +3: + lwi $r1, [$r0+0xc] + bnez $r1, 3b + + move $lp, $r11 + ret + +remap: + move $r11, $lp +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + bal 2f +relo_base: + move $r0, $lp +#else +relo_base: + mfusr $r0, $pc +#endif + + /* relocation, copy ROM code to SDRAM(current is at 0x10000000) */ + li $r4, 0x10000000 + li $r5, 0x0 + la $r1, relo_base + sub $r2, $r0, $r1 + sethi $r6, hi20(andesboot_end) + ori $r6, $r6, lo12(andesboot_end) + add $r6, $r6, $r2 +1: + lwi $r7, [$r5] + swi $r7, [$r4] + addi $r5, $r5, #4 + addi $r4, $r4, #4 + blt $r5, $r6, 1b + + /* Remapping */ + li $r0, 0x90300000 + li $r1, 0x00001100 + swi $r1, [$r0+0x10] + li $r1, 0x0 + swi $r1, [$r0+0x14] + swi $r1, [$r0+0x18] + swi $r1, [$r0+0x1c] + li $r1, 0x00001000 + swi $r1, [$r0+0x10] + + li $r0, 0x90100088 + lwi $r1, [$r0] + ori $r1, $r1, 0x1 + swi $r1, [$r0] + + li $r0, 0x90200000 +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + li $r1, 0x10400062 + swi $r1, [$r0+0x8] + li $r1, 0x000ff3ff + swi $r1, [$r0+0xc] +#else + li $r1, 0x10400062 + swi $r1, [$r0] +#endif + + move $lp, $r11 +2: + ret + +.globl show_led +show_led: + li $r8, 0x902ffffc ! 0x902ffffc + swi $r7, [$r8] + ret +#endif diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile new file mode 100644 index 0000000..8aa4a9d --- /dev/null +++ b/arch/nds32/cpu/n1213/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2010 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +SOBJS = lowlevel_init.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile new file mode 100644 index 0000000..4a10ecd --- /dev/null +++ b/arch/nds32/cpu/n1213/ag101/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# Copyright (C) 2010 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y = cpu.o ftsmc020.o timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c new file mode 100644 index 0000000..0c852b6 --- /dev/null +++ b/arch/nds32/cpu/n1213/ag101/cpu.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include <common.h> +#include <command.h> + +/* + * setup up stack if necessary + */ +/* it makes no sense to use the caches if the MMU also isn't used */ +void cpu_init(void) +{ + _andesboot_real_end = _andesboot_end + CONFIG_STACKSIZE; +} + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ +#ifdef CONFIG_MMU + unsigned long i; +#endif + + disable_interrupts(); + +#ifdef CONFIG_MMU + /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); + + /* flush I/D-cache */ + invalidate_icac(); + invalidate_dcac(); +#endif +} + +void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + extern void reset_cpu(ulong addr); + + disable_interrupts(); + + /* + * reset to the base addr of andesboot. + * currently no ROM loader at addr 0. + * do not use reset_cpu(0); + */ + reset_cpu(TEXT_BASE); + + /*NOTREACHED*/ +} + +static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) +{ + if( cache == ICACHE) + return 8 << ( ( ( GET_ICM_CFG() & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1); + else + return 8 << ( ( ( GET_DCM_CFG() & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1); +} + +void dcache_flush_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + + while (end > start) { + __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" :: "r"(start)); + __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" :: "r"(start)); + start += line_size; + } +} + +void icache_inval_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(ICACHE); + while (end > start) { + __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" :: "r"(start)); + start += line_size; + } +} + +void flush_cache(unsigned long addr, unsigned long size) +{ + dcache_flush_range( addr , addr + size ); + icache_inval_range( addr , addr + size ); +} + +void icache_enable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "ori $p0, $p0, 0x01 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +void icache_disable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "li $p1, ~0x01 \n\t" + "and $p0, $p0, $p1 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +int icache_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "andi %0, $p0, 0x01 \n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} + +void dcache_enable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "ori $p0, $p0, 0x02 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +void dcache_disable(void) +{ + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "li $p1, ~0x02 \n\t" + "and $p0, $p0, $p1 \n\t" + "mtsr $p0, $mr8 \n\t" + "isb \n\t" + ); +} + +int dcache_status(void) +{ + int ret; + + __asm__ __volatile__ ( + "mfsr $p0, $mr8 \n\t" + "andi %0, $p0, 0x02 \n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} diff --git a/arch/nds32/cpu/n1213/ag101/ftsmc020.c b/arch/nds32/cpu/n1213/ag101/ftsmc020.c new file mode 100644 index 0000000..7646537 --- /dev/null +++ b/arch/nds32/cpu/n1213/ag101/ftsmc020.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang ratbert@faraday-tech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftsmc020.h> + +struct ftsmc020_config { + unsigned int config; + unsigned int timing; +}; + +static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; + +static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE; + +static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg) +{ + if (bank > 3) { + printf("bank # %u invalid\n", bank); + return; + } + + writel(cfg->config, &smc->bank[bank].cr); + writel(cfg->timing, &smc->bank[bank].tpr); +} + +void ftsmc020_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(config); i++) + ftsmc020_setup_bank(i, &config[i]); +} diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c new file mode 100644 index 0000000..1e5c3c2 --- /dev/null +++ b/arch/nds32/cpu/n1213/ag101/timer.c @@ -0,0 +1,213 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang ratbert@faraday-tech.com + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftpmu010.h> +#include <asm/arch/fttmr010.h> + +static ulong timestamp; +static ulong lastdec; + +static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; +static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + +int timer_init(void) +{ + unsigned int oscc; + unsigned int cr; + + debug("%s()\n", __func__); + + /* disable timers */ + writel(0, &tmr->cr); + +#ifdef CONFIG_EXT_CLK + /* + * use 32768Hz oscillator for RTC, WDT, TIMER + */ + + /* enable the 32768Hz oscillator */ + oscc = readl(&pmu->OSCC); + oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); + writel(oscc, &pmu->OSCC); + + /* wait until ready */ + while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) + ; + + /* select 32768Hz oscillator */ + oscc = readl(&pmu->OSCC); + oscc |= FTPMU010_OSCC_OSCL_RTCLSEL; + writel(oscc, &pmu->OSCC); +#endif + + /* setup timer */ + writel(TIMER_LOAD_VAL, &tmr->timer3_load); + writel(TIMER_LOAD_VAL, &tmr->timer3_counter); + writel(0, &tmr->timer3_match1); + writel(0, &tmr->timer3_match2); + + /* we don't want timer to issue interrupts */ + writel(FTTMR010_TM3_MATCH1 | + FTTMR010_TM3_MATCH2 | + FTTMR010_TM3_OVERFLOW, + &tmr->interrupt_mask); + + cr = readl(&tmr->cr); +#ifdef CONFIG_EXT_CLK + cr |= FTTMR010_TM3_CLOCK; /* use external clock */ +#endif + cr |= FTTMR010_TM3_ENABLE; + writel(cr, &tmr->cr); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +/* + * reset time + */ +void reset_timer_masked(void) +{ + /* capure current decrementer value time */ +#ifdef CONFIG_EXT_CLK + lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); +#else + lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_HZ); +#endif + timestamp = 0; /* start "advancing" time stamp from 0 */ + + debug("%s(): lastdec = %lx\n", __func__, lastdec); +} + +void reset_timer(void) +{ + debug("%s()\n", __func__); + reset_timer_masked(); +} + +/* + * return timer ticks + */ +ulong get_timer_masked(void) +{ + /* current tick value */ +#ifdef CONFIG_EXT_CLK + ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); +#else + ulong now = readl(&tmr->timer3_counter) / (CONFIG_SYS_HZ); +#endif + + debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); + + if (lastdec >= now) { + /* + * normal mode (non roll) + * move stamp fordward with absoulte diff ticks + */ + timestamp += lastdec - now; + } else { + /* + * we have overflow of the count down timer + * + * nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and + * cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + + lastdec = now; + + debug("%s() returns %lx\n", __func__, timestamp); + + return timestamp; +} + +/* + * return difference between timer ticks and base + */ +ulong get_timer(ulong base) +{ + debug("%s(%lx)\n", __func__, base); + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + debug("%s(%lx)\n", __func__, t); + timestamp = t; +} + +/* delay x useconds AND preserve advance timestamp value */ +void __udelay(unsigned long usec) +{ + long tmo = usec * (CONFIG_SYS_HZ / 1000) / 1000; + unsigned long now, last = readl(&tmr->timer3_counter); + + debug("%s(%lu)\n", __func__, usec); + while (tmo > 0) { + now = readl(&tmr->timer3_counter); + if (now > last) /* count down timer overflow */ + tmo -= TIMER_LOAD_VAL + last - now; + else + tmo -= last - now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + debug("%s()\n", __func__); + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + debug("%s()\n", __func__); +#ifdef CONFIG_EXT_CLK + return CONFIG_SYS_HZ; +#else + return CONFIG_SYS_CLK_FREQ; +#endif +} diff --git a/arch/nds32/cpu/n1213/lowlevel_init.S b/arch/nds32/cpu/n1213/lowlevel_init.S new file mode 100644 index 0000000..f7fa12b --- /dev/null +++ b/arch/nds32/cpu/n1213/lowlevel_init.S @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.text + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +.globl lowlevel_init +lowlevel_init: + move $r10, $lp + jal mem_init + jal remap + + ret $r10 + +mem_init: + move $r11, $lp + li $r0, 0x90200000 + li $r1, 0x10000052 + swi $r1, [$r0] + li $r1, 0x00151151 + swi $r1, [$r0+0x4] + + li $r0, 0x90100018 + li $r1, 0x100b0000 + swi $r1, [$r0] + li $r0, 0x98100030 + lwi $r1, [$r0] + li $r2, 0x00010000 + or $r1, $r1, $r2 + swi $r1, [$r0] +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + lwi $r1, [$r0] + li $r2, 0x00e00000 + or $r1, $r1, $r2 + swi $r1, [$r0] + li $r0, 0x98100028 + lwi $r1, [$r0] + li $r2, 0x00000010 + or $r1, $r1, $r2 + swi $r1, [$r0] + li $r0, 0x9810004c + lwi $r1, [$r0] + li $r2, 0x0007f000 + or $r1, $r1, $r2 + swi $r1, [$r0] +#endif + li $r0, 0x90300000 + li $r1, 0x00011312 + swi $r1, [$r0] + li $r1, 0x00480180 + swi $r1, [$r0+0x4] + li $r1, 0x00002326 + swi $r1, [$r0+0x8] + li $r1, 0x00000010 + swi $r1, [$r0+0xc] +1: + lwi $r1, [$r0+0xc] + andi $r1, $r1, 0x1c + bnez $r1, 1b + + li $r1, 0x00000004 + swi $r1, [$r0+0xc] +2: + lwi $r1, [$r0+0xc] + bnez $r1, 2b + + li $r1, 0x00000008 + swi $r1, [$r0+0xc] +3: + lwi $r1, [$r0+0xc] + bnez $r1, 3b + + move $lp, $r11 + ret + +remap: + move $r11, $lp +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + bal 2f +relo_base: + move $r0, $lp +#else +relo_base: + mfusr $r0, $pc +#endif + + /* relocation, copy ROM code to SDRAM(current is at 0x10000000) */ + li $r4, 0x10000000 + li $r5, 0x0 + la $r1, relo_base + sub $r2, $r0, $r1 + sethi $r6, hi20(andesboot_end) + ori $r6, $r6, lo12(andesboot_end) + add $r6, $r6, $r2 +1: + lwi $r7, [$r5] + swi $r7, [$r4] + addi $r5, $r5, #4 + addi $r4, $r4, #4 + blt $r5, $r6, 1b + + /* Remapping */ + li $r0, 0x90300000 + li $r1, 0x00001100 + swi $r1, [$r0+0x10] + li $r1, 0x0 + swi $r1, [$r0+0x14] + swi $r1, [$r0+0x18] + swi $r1, [$r0+0x1c] + li $r1, 0x00001000 + swi $r1, [$r0+0x10] + + li $r0, 0x90100088 + lwi $r1, [$r0] + ori $r1, $r1, 0x1 + swi $r1, [$r0] + + li $r0, 0x90200000 +#ifdef __NDS32_N1213_43U1H__ /* AG101 */ + li $r1, 0x10400062 + swi $r1, [$r0+0x8] + li $r1, 0x000ff3ff + swi $r1, [$r0+0xc] +#else + li $r1, 0x10400062 + swi $r1, [$r0] +#endif + + move $lp, $r11 +2: + ret + +.globl show_led +show_led: + li $r8, 0x902ffffc ! 0x902ffffc + swi $r7, [$r8] + ret +#endif diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S new file mode 100644 index 0000000..ba9d9e6 --- /dev/null +++ b/arch/nds32/cpu/n1213/start.S @@ -0,0 +1,447 @@ +/* + * Andesboot - Startup Code for Whitiger core + * + * Copyright (c) 2001 Marius Gröger mag@sysgo.de + * Copyright (c) 2002 Alex Züpke azu@sysgo.de + * Copyright (c) 2002 Gary Jennejohn gj@denx.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin nobuhiro@andestech.com + * Copyright (C) 2010 Macpaul macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <version.h> +#include <nds32_common.h> + +!======================================================================== +! Jump vector table for EVIC mode +!======================================================================== + +#define ENA_DCAC 2UL +#define DIS_DCAC ~ENA_DCAC +#define ICAC_MEM_kbfISET (0x07) ! I Cache sets per way +#define ICAC_MEM_kbfIWAY (0x07<<3) ! I cache ways +#define ICAC_MEM_kbfISZ (0x07<<6) ! I cache line size +#define DCAC_MEM_kbfDSET (0x07) ! D Cache sets per way +#define DCAC_MEM_kbfDWAY (0x07<<3) ! D cache ways +#define DCAC_MEM_kbfDSZ (0x07<<6) ! D cache line size + +#define psw $ir0 +#define EIT_INTR_PSW $ir1 /* interruption $PSW */ +#define EIT_PREV_IPSW $ir2 /* previous ... */ +#define EIT_IVB $ir3 /* intr vector base address */ +#define EIT_EVA $ir4 /* MMU related Exception Virtual Address register */ +#define EIT_PREV_EVA $ir5 /* previous $eva */ +#define EIT_ITYPE $ir6 /* interruption type */ +#define EIT_PREV_ITYPE $ir7 /* prev intr type */ +#define EIT_MACH_ERR $ir8 /* machine error log */ +#define EIT_INTR_PC $ir9 /* Interruption PC */ +#define EIT_PREV_IPC $ir10 /* previous $IPC */ +#define EIT_OVL_INTR_PC $ir11 /* overflow interruption PC */ +#define EIT_PREV_P0 $ir12 /* prev $P0 */ +#define EIT_PREV_P1 $ir13 /* prev $p1 */ +#define CR_ICAC_MEM $cr1 /* Insn cache/memory config register */ +#define CR_DCAC_MEM $cr2 /* Data cache/memory config register */ +#define MR_CAC_CTL $mr8 + + +.globl _start + +_start: b reset + b TLB_fill + b TLB_not_present + b TLB_misc + b TLB_VLPT_miss + b cache_parity_error + b debug + b general_exception + b internal_interrupt ! H0I + b internal_interrupt ! H1I + b internal_interrupt ! H2I + b internal_interrupt ! H3I + b internal_interrupt ! H4I + b internal_interrupt ! H5I + + .balign 16 + + +!======================================================================== +! Andesboot Startup Code (reset vector) +! +! 1. bootstrap +! 1.1 reset - start of Andesboot +! 1.2 to superuser mode - as is when reset +! 1.3 Turn off watchdog timer +! 2. Do critical init when reboot (not from mem) +! 3. Relocate andesboot to ram +! 4. Setup stack +! 5. Jump to second stage (start_andesboot) +!======================================================================== + +! Note: TEXT_BASE is defined by the (board-dependent) linker script +_TEXT_BASE: + .word TEXT_BASE + +.globl _andesboot_start +_andesboot_start: + .word _start + +! Note: andesboot_end is defined by the (board-dependent) linker script +.globl _andesboot_end +_andesboot_end: + .word andesboot_end + +! _andesboot_real_end is the first usable RAM address behind Andesboot +! and the various stacks +.globl _andesboot_real_end +_andesboot_real_end: + .word 0x0badc0de + + +!============================================= +! The bootstrap code of Andesboot +!============================================= + +reset: + +load_lli: +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + jal load_lowlevel_init + jral $p0 +#endif + + ! Set the Whitiger core to superuser mode + ! According to spec, it is already when reset + +#define WD_CR 0xC +#define WdEnable 0x1 + + ! Turn off the watchdog, according to Faraday FTWDT010 spec + li $p0, (NDS32_COMMON_WATCHDOG_BASE+WD_CR) ! Get the address of the WD CR + lwi $p1, [$p0] ! Get the WD configuration + andi $p1, $p1, 0x1f ! Wipe out useless bits + li $r0, ~WdEnable + and $p1, $p1, $r0 ! Set WD disable + sw $p1, [$p0] ! Write back to WD CR + + ! Disable Interrupts by clear GIE in $PSW reg + setgie.d + +! Do CPU critical regs init only at reboot, not when booting from ram +#ifdef CONFIG_INIT_CRITICAL + bal cpu_init_crit ! Do CPU critical regs init +#endif +.align 2 +relocate: + ! relocate andesboot to RAM + jal 2f + !la $r0, _start ! $r0 = source start address + !l.w $r2, _andesboot_start ! Andesboot start address + !l.w $r3, _andesboot_end ! Andesboot end address + !sub $r2, $r3, $r2 ! $r2 = size of Andesboot + !l.w $r1, _TEXT_BASE ! $r1 = destination start address + move $r0, $lp + la $p0, _start + la $p1, relocate+4 + sub $p0, $p1, $p0 + sub $r0, $r0, $p0 + + la $p0, _andesboot_end + sub $p0, $p0, $p1 + move $r3, $lp + lw $r3, [$r3+$p0] ! _andesboot_end + addi $p0, $p0, -4 + move $r2, $lp + lw $r2, [$r2+$p0] ! _andesboot_start + sub $r2, $r3, $r2 + addi $p0, $p0, -4 + move $r1, $lp + lw $r1, [$r1+$p0] ! _TEXT_BASE + + ! $r0 = source address + ! $r1 = destination address + ! $r2 = size to copy +copy_loop: + lmw.bim $r3, [$r0], $r10 + smw.bim $r3, [$r1], $r10 + addi $r2, $r2, -32 + bgez $r2, copy_loop + + ! Set up the stack + l.w $p0, _andesboot_end ! Defined by the board linker script + li $p1, CONFIG_STACKSIZE ! (128*1024) defined in config.h + add $sp, $p0, $p1 + + bal flib_init_bss_memory + + ! Jump to start_andesboot (2nd phase) + l.w $p0, __start_andesboot + br $p0 + +__start_andesboot: .word start_andesboot + +!========================================================================= +! Initialize CPU critical registers +! +! 1. Setup control registers +! 1.1 Mask all IRQs +! 1.2 Flush cache and TLB +! 1.3 Disable MMU and cache +! 2. Setup memory timing +!========================================================================= + +cpu_init_crit: + !push ra + move $r0, $lp + ! Disable Interrupts by clear GIE in $PSW reg + setgie.d + + ! Flush caches and TLB + + ! Invalidate caches + bal invalidate_icac + bal invalidate_dcac + + ! Flush TLB + mfsr $p0, $MMU_CFG + andi $p0, $p0, 0x3 ! MMPS + li $p1, 0x2 ! TLB MMU + bne $p0, $p1, 1f + tlbop FlushAll ! Flush TLB + +1: + ! Disable MMU, Dcache + ! Whitiger is MMU disabled when reset + ! Disable the D$ + mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg + li $p1, DIS_DCAC + and $p0, $p0, $p1 ! Set DC_EN bit + mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg + isb + + ! RAM is initialized in the dram_init()(board/nds32/cpe.c) + ! Remove the memsetup.S in the board directory. + !pop ra + + move $lp, $r0 +2: + ret + +flib_init_bss_memory: + smw.adm $r4, [$sp], $r6, #0x1 + + la $r4, __bss_start + la $r5, __bss_end + move $r6, #0 +1: + swi.p $r6, [$r4], #4 + blt $r4, $r5, 1b ! Check if done.. + + lmw.bim $r4, [$sp], $r6, #0x1 + ret + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +load_lowlevel_init: + la $r6, lowlevel_init + la $r7, load_lli + 4 + sub $p0, $r6, $r7 + add $p0, $p0, $lp +ret +#endif + +!======================================================= +! Invalidate I$ +!======================================================= +invalidate_icac: + mfsr $t0, CR_ICAC_MEM ! read $cr1(I CAC/MEM cfg. reg.) configuration + andi $p0, $t0, ICAC_MEM_kbfISZ ! Get the ISZ field + beqz $p0, end_flush_icache ! if $p0=0, then no I CAC existed + srli $p0, $p0, 6 ! get $p0 the index of I$ block + addi $t1, $p0, 2 ! $t1= bit width of I cache line size(ISZ) + li $t4, 1 + sll $t5, $t4, $t1 ! get $t5 cache line size + andi $p1, $t0, ICAC_MEM_kbfISET ! get the ISET field + addi $t2, $p1, 6 ! $t2= bit width of ISET + andi $p1, $t0, ICAC_MEM_kbfIWAY ! get bitfield of Iway + srli $p1, $p1, 3 + addi $p1, $p1, 1 ! then $p1 is I way number + add $t3, $t2, $t1 ! SHIFT + sll $p1, $p1, $t3 ! GET the total cache size +ICAC_LOOP: + sub $p1, $p1, $t5 + cctl $p1, L1I_IX_INVAL + bnez $p1, ICAC_LOOP +end_flush_icache: + ret +!======================================================= +! Invalidate D$ +!======================================================= +invalidate_dcac: + mfsr $t0, CR_DCAC_MEM ! read $cr2(D CAC/MEM cfg. reg.) configuration + andi $p0, $t0, DCAC_MEM_kbfDSZ ! Get the DSZ field + beqz $p0, end_flush_dcache ! if $p0=0, then no D CAC existed + srli $p0, $p0, 6 ! get $p0 the index of D$ block + addi $t1, $p0, 2 ! $t1= bit width of D cache line size(DSZ) + li $t4, 1 + sll $t5, $t4, $t1 ! get $t5 cache line size + andi $p1, $t0, DCAC_MEM_kbfDSET ! get the DSET field + addi $t2, $p1, 6 ! $t2= bit width of DSET + andi $p1, $t0, DCAC_MEM_kbfDWAY ! get bitfield of D way + srli $p1, $p1, 3 + addi $p1, $p1, 1 ! then $p1 is D way number + add $t3, $t2, $t1 ! SHIFT + sll $p1, $p1, $t3 ! GET the total cache size +DCAC_LOOP: + sub $p1, $p1, $t5 + cctl $p1, L1D_IX_INVAL + bnez $p1, DCAC_LOOP +end_flush_dcache: + ret + +!======================================================================== +! Interrupt handling +!======================================================================== + +/* + * exception handlers + */ + .align 5 + + .macro SAVE_ALL + ! FIXME: Other way to get PC? + ! FIXME: Update according to the newest spec!! +1: la $r28, 1 + push $r28 + mfsr $r28, psw ! $psw + push $r28 + mfsr $r28, EIT_EVA ! $ir1 $EVA + push $r28 + mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE + push $r28 + mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error + push $r28 + mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW + push $r28 + mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW + push $r28 + mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA + push $r28 + mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE + push $r28 + mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC + push $r28 + mfsr $r28, EIT_PREV_IPC ! $ir10 prev Interruption PC + push $r28 + mfsr $r28, EIT_OVL_INTR_PC ! $ir11:OVerflowed interruption PC + push $r28 + mfusr $r28, $d1.lo + push $r28 + mfusr $r28, $d1.hi + push $r28 + mfusr $r28, $d0.lo + push $r28 + mfusr $r28, $d0.hi + push $r28 + pushm $r0,$r30 /* we will also store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp */ + addi $sp, $sp, -4 ! make room for implicit pt_regs parameters + .endm + + .align 5 +TLB_fill: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 1 ! Determine interruption type + bal do_interruption + + .align 5 +TLB_not_present: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 2 ! Determine interruption type + bal do_interruption + + .align 5 +TLB_misc: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 3 ! Determine interruption type + bal do_interruption + + .align 5 +TLB_VLPT_miss: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 4 ! Determine interruption type + bal do_interruption + + .align 5 +cache_parity_error: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 5 ! Determine interruption type + bal do_interruption + + .align 5 +debug: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 6 ! Determine interruption type + bal do_interruption + + .align 5 +general_exception: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 7 ! Determine interruption type + bal do_interruption + + .align 5 +internal_interrupt: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 8 ! Determine interruption type + bal do_interruption + + .align 5 + +!=========================================== +!void reset_cpu(ulong addr); +! $r0: input address to jump to +!=========================================== +.globl reset_cpu +reset_cpu: +! No need to disable MMU because we never enable it! + + bal invalidate_icac + bal invalidate_dcac + mfsr $p0, $MMU_CFG + andi $p0, $p0, 0x3 ! MMPS + li $p1, 0x2 ! TLB MMU + bne $p0, $p1, 1f + tlbop FlushAll ! Flush TLB +1: + mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg + li $p1, DIS_DCAC + and $p0, $p0, $p1 ! Clear the DC_EN bit + mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg + br $r0 ! Jump to the input address diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds new file mode 100644 index 0000000..3515ce0 --- /dev/null +++ b/arch/nds32/cpu/n1213/u-boot.lds @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32") +OUTPUT_ARCH(nds32) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/nds32/cpu/n1213/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; + + . = ALIGN(4); + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + + andesboot_end = .; + + . = 0x02000000; + .u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) } +} diff --git a/arch/nds32/cpu/start.S b/arch/nds32/cpu/start.S new file mode 100644 index 0000000..ba9d9e6 --- /dev/null +++ b/arch/nds32/cpu/start.S @@ -0,0 +1,447 @@ +/* + * Andesboot - Startup Code for Whitiger core + * + * Copyright (c) 2001 Marius Gröger mag@sysgo.de + * Copyright (c) 2002 Alex Züpke azu@sysgo.de + * Copyright (c) 2002 Gary Jennejohn gj@denx.de + * + * Copyright (C) 2006 Andes Technology Corporation + * Copyright (C) 2006 Shawn Lin nobuhiro@andestech.com + * Copyright (C) 2010 Macpaul macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <version.h> +#include <nds32_common.h> + +!======================================================================== +! Jump vector table for EVIC mode +!======================================================================== + +#define ENA_DCAC 2UL +#define DIS_DCAC ~ENA_DCAC +#define ICAC_MEM_kbfISET (0x07) ! I Cache sets per way +#define ICAC_MEM_kbfIWAY (0x07<<3) ! I cache ways +#define ICAC_MEM_kbfISZ (0x07<<6) ! I cache line size +#define DCAC_MEM_kbfDSET (0x07) ! D Cache sets per way +#define DCAC_MEM_kbfDWAY (0x07<<3) ! D cache ways +#define DCAC_MEM_kbfDSZ (0x07<<6) ! D cache line size + +#define psw $ir0 +#define EIT_INTR_PSW $ir1 /* interruption $PSW */ +#define EIT_PREV_IPSW $ir2 /* previous ... */ +#define EIT_IVB $ir3 /* intr vector base address */ +#define EIT_EVA $ir4 /* MMU related Exception Virtual Address register */ +#define EIT_PREV_EVA $ir5 /* previous $eva */ +#define EIT_ITYPE $ir6 /* interruption type */ +#define EIT_PREV_ITYPE $ir7 /* prev intr type */ +#define EIT_MACH_ERR $ir8 /* machine error log */ +#define EIT_INTR_PC $ir9 /* Interruption PC */ +#define EIT_PREV_IPC $ir10 /* previous $IPC */ +#define EIT_OVL_INTR_PC $ir11 /* overflow interruption PC */ +#define EIT_PREV_P0 $ir12 /* prev $P0 */ +#define EIT_PREV_P1 $ir13 /* prev $p1 */ +#define CR_ICAC_MEM $cr1 /* Insn cache/memory config register */ +#define CR_DCAC_MEM $cr2 /* Data cache/memory config register */ +#define MR_CAC_CTL $mr8 + + +.globl _start + +_start: b reset + b TLB_fill + b TLB_not_present + b TLB_misc + b TLB_VLPT_miss + b cache_parity_error + b debug + b general_exception + b internal_interrupt ! H0I + b internal_interrupt ! H1I + b internal_interrupt ! H2I + b internal_interrupt ! H3I + b internal_interrupt ! H4I + b internal_interrupt ! H5I + + .balign 16 + + +!======================================================================== +! Andesboot Startup Code (reset vector) +! +! 1. bootstrap +! 1.1 reset - start of Andesboot +! 1.2 to superuser mode - as is when reset +! 1.3 Turn off watchdog timer +! 2. Do critical init when reboot (not from mem) +! 3. Relocate andesboot to ram +! 4. Setup stack +! 5. Jump to second stage (start_andesboot) +!======================================================================== + +! Note: TEXT_BASE is defined by the (board-dependent) linker script +_TEXT_BASE: + .word TEXT_BASE + +.globl _andesboot_start +_andesboot_start: + .word _start + +! Note: andesboot_end is defined by the (board-dependent) linker script +.globl _andesboot_end +_andesboot_end: + .word andesboot_end + +! _andesboot_real_end is the first usable RAM address behind Andesboot +! and the various stacks +.globl _andesboot_real_end +_andesboot_real_end: + .word 0x0badc0de + + +!============================================= +! The bootstrap code of Andesboot +!============================================= + +reset: + +load_lli: +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + jal load_lowlevel_init + jral $p0 +#endif + + ! Set the Whitiger core to superuser mode + ! According to spec, it is already when reset + +#define WD_CR 0xC +#define WdEnable 0x1 + + ! Turn off the watchdog, according to Faraday FTWDT010 spec + li $p0, (NDS32_COMMON_WATCHDOG_BASE+WD_CR) ! Get the address of the WD CR + lwi $p1, [$p0] ! Get the WD configuration + andi $p1, $p1, 0x1f ! Wipe out useless bits + li $r0, ~WdEnable + and $p1, $p1, $r0 ! Set WD disable + sw $p1, [$p0] ! Write back to WD CR + + ! Disable Interrupts by clear GIE in $PSW reg + setgie.d + +! Do CPU critical regs init only at reboot, not when booting from ram +#ifdef CONFIG_INIT_CRITICAL + bal cpu_init_crit ! Do CPU critical regs init +#endif +.align 2 +relocate: + ! relocate andesboot to RAM + jal 2f + !la $r0, _start ! $r0 = source start address + !l.w $r2, _andesboot_start ! Andesboot start address + !l.w $r3, _andesboot_end ! Andesboot end address + !sub $r2, $r3, $r2 ! $r2 = size of Andesboot + !l.w $r1, _TEXT_BASE ! $r1 = destination start address + move $r0, $lp + la $p0, _start + la $p1, relocate+4 + sub $p0, $p1, $p0 + sub $r0, $r0, $p0 + + la $p0, _andesboot_end + sub $p0, $p0, $p1 + move $r3, $lp + lw $r3, [$r3+$p0] ! _andesboot_end + addi $p0, $p0, -4 + move $r2, $lp + lw $r2, [$r2+$p0] ! _andesboot_start + sub $r2, $r3, $r2 + addi $p0, $p0, -4 + move $r1, $lp + lw $r1, [$r1+$p0] ! _TEXT_BASE + + ! $r0 = source address + ! $r1 = destination address + ! $r2 = size to copy +copy_loop: + lmw.bim $r3, [$r0], $r10 + smw.bim $r3, [$r1], $r10 + addi $r2, $r2, -32 + bgez $r2, copy_loop + + ! Set up the stack + l.w $p0, _andesboot_end ! Defined by the board linker script + li $p1, CONFIG_STACKSIZE ! (128*1024) defined in config.h + add $sp, $p0, $p1 + + bal flib_init_bss_memory + + ! Jump to start_andesboot (2nd phase) + l.w $p0, __start_andesboot + br $p0 + +__start_andesboot: .word start_andesboot + +!========================================================================= +! Initialize CPU critical registers +! +! 1. Setup control registers +! 1.1 Mask all IRQs +! 1.2 Flush cache and TLB +! 1.3 Disable MMU and cache +! 2. Setup memory timing +!========================================================================= + +cpu_init_crit: + !push ra + move $r0, $lp + ! Disable Interrupts by clear GIE in $PSW reg + setgie.d + + ! Flush caches and TLB + + ! Invalidate caches + bal invalidate_icac + bal invalidate_dcac + + ! Flush TLB + mfsr $p0, $MMU_CFG + andi $p0, $p0, 0x3 ! MMPS + li $p1, 0x2 ! TLB MMU + bne $p0, $p1, 1f + tlbop FlushAll ! Flush TLB + +1: + ! Disable MMU, Dcache + ! Whitiger is MMU disabled when reset + ! Disable the D$ + mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg + li $p1, DIS_DCAC + and $p0, $p0, $p1 ! Set DC_EN bit + mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg + isb + + ! RAM is initialized in the dram_init()(board/nds32/cpe.c) + ! Remove the memsetup.S in the board directory. + !pop ra + + move $lp, $r0 +2: + ret + +flib_init_bss_memory: + smw.adm $r4, [$sp], $r6, #0x1 + + la $r4, __bss_start + la $r5, __bss_end + move $r6, #0 +1: + swi.p $r6, [$r4], #4 + blt $r4, $r5, 1b ! Check if done.. + + lmw.bim $r4, [$sp], $r6, #0x1 + ret + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +load_lowlevel_init: + la $r6, lowlevel_init + la $r7, load_lli + 4 + sub $p0, $r6, $r7 + add $p0, $p0, $lp +ret +#endif + +!======================================================= +! Invalidate I$ +!======================================================= +invalidate_icac: + mfsr $t0, CR_ICAC_MEM ! read $cr1(I CAC/MEM cfg. reg.) configuration + andi $p0, $t0, ICAC_MEM_kbfISZ ! Get the ISZ field + beqz $p0, end_flush_icache ! if $p0=0, then no I CAC existed + srli $p0, $p0, 6 ! get $p0 the index of I$ block + addi $t1, $p0, 2 ! $t1= bit width of I cache line size(ISZ) + li $t4, 1 + sll $t5, $t4, $t1 ! get $t5 cache line size + andi $p1, $t0, ICAC_MEM_kbfISET ! get the ISET field + addi $t2, $p1, 6 ! $t2= bit width of ISET + andi $p1, $t0, ICAC_MEM_kbfIWAY ! get bitfield of Iway + srli $p1, $p1, 3 + addi $p1, $p1, 1 ! then $p1 is I way number + add $t3, $t2, $t1 ! SHIFT + sll $p1, $p1, $t3 ! GET the total cache size +ICAC_LOOP: + sub $p1, $p1, $t5 + cctl $p1, L1I_IX_INVAL + bnez $p1, ICAC_LOOP +end_flush_icache: + ret +!======================================================= +! Invalidate D$ +!======================================================= +invalidate_dcac: + mfsr $t0, CR_DCAC_MEM ! read $cr2(D CAC/MEM cfg. reg.) configuration + andi $p0, $t0, DCAC_MEM_kbfDSZ ! Get the DSZ field + beqz $p0, end_flush_dcache ! if $p0=0, then no D CAC existed + srli $p0, $p0, 6 ! get $p0 the index of D$ block + addi $t1, $p0, 2 ! $t1= bit width of D cache line size(DSZ) + li $t4, 1 + sll $t5, $t4, $t1 ! get $t5 cache line size + andi $p1, $t0, DCAC_MEM_kbfDSET ! get the DSET field + addi $t2, $p1, 6 ! $t2= bit width of DSET + andi $p1, $t0, DCAC_MEM_kbfDWAY ! get bitfield of D way + srli $p1, $p1, 3 + addi $p1, $p1, 1 ! then $p1 is D way number + add $t3, $t2, $t1 ! SHIFT + sll $p1, $p1, $t3 ! GET the total cache size +DCAC_LOOP: + sub $p1, $p1, $t5 + cctl $p1, L1D_IX_INVAL + bnez $p1, DCAC_LOOP +end_flush_dcache: + ret + +!======================================================================== +! Interrupt handling +!======================================================================== + +/* + * exception handlers + */ + .align 5 + + .macro SAVE_ALL + ! FIXME: Other way to get PC? + ! FIXME: Update according to the newest spec!! +1: la $r28, 1 + push $r28 + mfsr $r28, psw ! $psw + push $r28 + mfsr $r28, EIT_EVA ! $ir1 $EVA + push $r28 + mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE + push $r28 + mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error + push $r28 + mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW + push $r28 + mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW + push $r28 + mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA + push $r28 + mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE + push $r28 + mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC + push $r28 + mfsr $r28, EIT_PREV_IPC ! $ir10 prev Interruption PC + push $r28 + mfsr $r28, EIT_OVL_INTR_PC ! $ir11:OVerflowed interruption PC + push $r28 + mfusr $r28, $d1.lo + push $r28 + mfusr $r28, $d1.hi + push $r28 + mfusr $r28, $d0.lo + push $r28 + mfusr $r28, $d0.hi + push $r28 + pushm $r0,$r30 /* we will also store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp */ + addi $sp, $sp, -4 ! make room for implicit pt_regs parameters + .endm + + .align 5 +TLB_fill: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 1 ! Determine interruption type + bal do_interruption + + .align 5 +TLB_not_present: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 2 ! Determine interruption type + bal do_interruption + + .align 5 +TLB_misc: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 3 ! Determine interruption type + bal do_interruption + + .align 5 +TLB_VLPT_miss: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 4 ! Determine interruption type + bal do_interruption + + .align 5 +cache_parity_error: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 5 ! Determine interruption type + bal do_interruption + + .align 5 +debug: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 6 ! Determine interruption type + bal do_interruption + + .align 5 +general_exception: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 7 ! Determine interruption type + bal do_interruption + + .align 5 +internal_interrupt: + SAVE_ALL + move $r0, $sp ! To get the kernel stack + li $r1, 8 ! Determine interruption type + bal do_interruption + + .align 5 + +!=========================================== +!void reset_cpu(ulong addr); +! $r0: input address to jump to +!=========================================== +.globl reset_cpu +reset_cpu: +! No need to disable MMU because we never enable it! + + bal invalidate_icac + bal invalidate_dcac + mfsr $p0, $MMU_CFG + andi $p0, $p0, 0x3 ! MMPS + li $p1, 0x2 ! TLB MMU + bne $p0, $p1, 1f + tlbop FlushAll ! Flush TLB +1: + mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg + li $p1, DIS_DCAC + and $p0, $p0, $p1 ! Clear the DC_EN bit + mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg + br $r0 ! Jump to the input address

Add generic header files support for nds32 architecture.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- arch/nds32/include/asm/andesboot.h | 242 +++++++++++++++++++++++ arch/nds32/include/asm/bitops.h | 150 ++++++++++++++ arch/nds32/include/asm/byteorder.h | 36 ++++ arch/nds32/include/asm/config.h | 26 +++ arch/nds32/include/asm/global_data.h | 76 +++++++ arch/nds32/include/asm/io.h | 348 +++++++++++++++++++++++++++++++++ arch/nds32/include/asm/mach-types.h | 29 +++ arch/nds32/include/asm/memory.h | 19 ++ arch/nds32/include/asm/posix_types.h | 84 ++++++++ arch/nds32/include/asm/processor.h | 25 +++ arch/nds32/include/asm/ptrace.h | 22 ++ arch/nds32/include/asm/ptregs.h | 82 ++++++++ arch/nds32/include/asm/setup.h | 272 +++++++++++++++++++++++++ arch/nds32/include/asm/string.h | 57 ++++++ arch/nds32/include/asm/types.h | 67 +++++++ arch/nds32/include/asm/u-boot-nds32.h | 76 +++++++ arch/nds32/include/asm/u-boot.h | 69 +++++++ arch/nds32/include/asm/unaligned.h | 31 +++ 18 files changed, 1712 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/include/asm/andesboot.h create mode 100644 arch/nds32/include/asm/bitops.h create mode 100644 arch/nds32/include/asm/byteorder.h create mode 100644 arch/nds32/include/asm/config.h create mode 100644 arch/nds32/include/asm/global_data.h create mode 100644 arch/nds32/include/asm/io.h create mode 100644 arch/nds32/include/asm/mach-types.h create mode 100644 arch/nds32/include/asm/memory.h create mode 100644 arch/nds32/include/asm/posix_types.h create mode 100644 arch/nds32/include/asm/processor.h create mode 100644 arch/nds32/include/asm/ptrace.h create mode 100644 arch/nds32/include/asm/ptregs.h create mode 100644 arch/nds32/include/asm/setup.h create mode 100644 arch/nds32/include/asm/string.h create mode 100644 arch/nds32/include/asm/types.h create mode 100644 arch/nds32/include/asm/u-boot-nds32.h create mode 100644 arch/nds32/include/asm/u-boot.h create mode 100644 arch/nds32/include/asm/unaligned.h

diff --git a/arch/nds32/include/asm/andesboot.h b/arch/nds32/include/asm/andesboot.h new file mode 100644 index 0000000..8d7a402 --- /dev/null +++ b/arch/nds32/include/asm/andesboot.h @@ -0,0 +1,242 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ANDESBOOT_H_ +#define _ANDESBOOT_H_ 1 + +#undef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ +#include <config.h> +#include <asm/types.h> +#include <asm/u-boot.h> +#include <stdarg.h> +#include <common.h> +#include <flash.h> +#include <image.h> + +#ifdef DEBUG +#define debug(fmt,args...) printf (fmt ,##args) +#else +#define debug(fmt,args...) +#endif + +/* + * The environment storages is simply a list of '\0'-terminated + * "name=value" strings, the end of the list marked by a double '\0'. + * New entries are always added at the end. Deleting an entry shifts + * the remaining entries to the front. Replacing an entry is a + * combination of deleting the old and adding the new value. + * + * The environment is preceeded by a 32 bit CRC over the data part. + */ +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +/* common/crc32.c */ +/* uint32_t crc32 (uint32_t, const unsigned char *, uint); */ +/* uint32_t crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len); */ + +/* + * Don't define some stuff private to andesboot target code + */ +#ifndef HOST_TOOLS + +/* board/.../env.c */ +int board_env_getchar(bd_t * bd, int index, uchar *c); +int board_env_save (bd_t * bd, env_t *data, int size); +int board_env_copy (bd_t * bd, env_t *data, int size); +uchar * board_env_getaddr(bd_t * bd, int index); + +/* + * Function Prototypes + */ +void hang (void); +void start_andesboot (void); +void main_loop (void); +int run_command (const char *cmd, int flag); +int readline (const char *const prompt); +void reset_cmd_timeout(void); + +/* board/.../... */ +/* + * removed according to a320 +int board_init(bd_t *); +int dram_init(bd_t *bd); +*/ + +/* common/display_options.c */ +/* + * removed according to a320 +void display_banner(bd_t *bd); +void display_dram_config(bd_t *bd); +void display_flash_config(ulong size); +*/ + +/* common/cmd_nvedit.c */ +/* int env_init (void); */ +void env_relocate (void); +char *getenv (char *); +int setenv (char *, char *); + +/* $(CPU)/serial.c */ +int serial_init (void); +void serial_setbrg (void); +void serial_putc (const char); +void serial_puts (const char *); +void serial_addr (unsigned int); +int serial_getc (void); +int serial_tstc (void); + +/* common/string.c */ +char * strcpy (char * dest,const char *src); +char * strncpy (char * dest,const char *src, size_t count); +size_t strlen (const char *); +size_t strnlen (const char * s, size_t count); +int strncmp (const char * cs, const char * ct, size_t count); +int strcmp (const char * cs, const char * ct); +void * memcpy (void * dest, const void *src, size_t count); +int memcmp (const void * dest, const void *src, size_t count); +void * memset (void * s, int c, size_t count); + +void * memmove (void * dest, const void *src, size_t count); +char * strchr (const char * s, int c); + +/* common/vsprintf.c */ +ulong simple_strtoul (const char *cp,char **endp,unsigned int base); +long simple_strtol (const char *cp,char **endp,unsigned int base); +void panic (const char *fmt, ...); +int sprintf (char * buf, const char *fmt, ...); +int vsprintf (char *buf, const char *fmt, va_list args); + +void udelay (unsigned long); + +int ctrlc (void); +int had_ctrlc (void); +void clear_ctrlc (void); +int disable_ctrlc (int); + +int console_assign (int file, char *devname); + +/* cache */ +int icache_status (void); +void icache_enable (void); +void icache_disable(void); +int dcache_status (void); +void dcache_enable (void); +void dcache_disable(void); + +#define DEFINE_GET_SYS_REG(reg) \ + inline static unsigned long GET_##reg(void) { \ + unsigned long val; \ + __asm__ volatile ( "mfsr %0, $"#reg :"=&r" (val) ::"memory"); \ + return val; \ + } + +enum cache_t{ ICACHE, DCACHE}; +DEFINE_GET_SYS_REG( ICM_CFG); +DEFINE_GET_SYS_REG( DCM_CFG); +#define ICM_CFG_offISZ 6 /* I-cache line size */ +#define ICM_CFG_mskISZ ( 0x7UL << ICM_CFG_offISZ ) +#define DCM_CFG_offDSZ 6 /* D-cache line size */ +#define DCM_CFG_mskDSZ ( 0x7UL << DCM_CFG_offDSZ ) + +/* common/cmd_bootm.c */ +void print_image_hdr (image_header_t *hdr); + +/* cpu/.../interrupt.c */ +void enable_interrupts (void); +int disable_interrupts (void); +int interrupt_init (void); +void reset_timer (void); +ulong get_timer (ulong base); +void set_timer (ulong t); +void reset_timer_masked (void); +ulong get_timer_masked (void); +void udelay_masked (unsigned long usec); + +/* cpu/.../cpu.c */ +/* + * removed according to a320 +void cpu_init(void); +void cleanup_before_linux(void); +*/ + +extern ulong load_addr; + +/* + * STDIO based functions (can always be used) + */ + +/* serial stuff */ +int serial_printf (const char *fmt, ...); + +/* stdin */ +int getc(void); +int tstc(void); + +/* stdout */ +void putc(const char c); +void puts(const char *s); +int printf(const char *fmt, ...); + +/* stderr */ +#define eputc(c) fputc(stderr, c) +#define eputs(s) fputs(stderr, s) +#define eprintf(fmt,args...) fprintf(stderr,fmt ,##args) + +/* + * FILE based functions (can only be used AFTER relocation!) + */ + +#define stdin 0 +#define stdout 1 +#define stderr 2 +#define MAX_FILES 3 + +int fprintf(int file, const char *fmt, ...); +void fputs(int file, const char *s); +void fputc(int file, const char c); +int ftstc(int file); +int fgetc(int file); + +/* Byte swapping stuff */ +#define SWAP16(x) ((((x) & 0xff) << 8) | ((x) >> 8)) +#define SWAP16c(x) ((((x) & 0xff) << 8) | ((x) >> 8)) +#define SWAP32(x) ( \ + (((x) >> 24) & 0x000000ff) | \ + (((x) >> 8) & 0x0000ff00) | \ + (((x) << 8) & 0x00ff0000) | \ + (((x) << 24) & 0xff000000) ) + +#endif /* HOST_TOOLS */ + +#endif /* _ANDESBOOT_H_ */ diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h new file mode 100644 index 0000000..f658a03 --- /dev/null +++ b/arch/nds32/include/asm/bitops.h @@ -0,0 +1,150 @@ +/* + * Copyright 1995, Russell King. + * Various bits and pieces copyrights include: + * Linus Torvalds (test_bit). + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + * + * Please note that the code in this file should never be included + * from user space. Many of these are not implemented in assembler + * since they would be too costly. Also, they require priviledged + * instructions (which are not available from user mode) to ensure + * that they are atomic. + */ + +#ifndef __ASM_NDS_BITOPS_H +#define __ASM_NDS_BITOPS_H + +#ifdef __KERNEL__ + +#define smp_mb__before_clear_bit() do { } while (0) +#define smp_mb__after_clear_bit() do { } while (0) + +/* + * Function prototypes to keep gcc -Wall happy. + */ +extern void set_bit(int nr, volatile void * addr); + +static inline void __set_bit(int nr, volatile void *addr) +{ + ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); +} + +extern void clear_bit(int nr, volatile void * addr); + +static inline void __clear_bit(int nr, volatile void *addr) +{ + ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); +} + +extern void change_bit(int nr, volatile void * addr); + +static inline void __change_bit(int nr, volatile void *addr) +{ + ((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7)); +} + +extern int test_and_set_bit(int nr, volatile void * addr); + +static inline int __test_and_set_bit(int nr, volatile void *addr) +{ + unsigned int mask = 1 << (nr & 7); + unsigned int oldval; + + oldval = ((unsigned char *) addr)[nr >> 3]; + ((unsigned char *) addr)[nr >> 3] = oldval | mask; + return oldval & mask; +} + +extern int test_and_clear_bit(int nr, volatile void * addr); + +static inline int __test_and_clear_bit(int nr, volatile void *addr) +{ + unsigned int mask = 1 << (nr & 7); + unsigned int oldval; + + oldval = ((unsigned char *) addr)[nr >> 3]; + ((unsigned char *) addr)[nr >> 3] = oldval & ~mask; + return oldval & mask; +} + +extern int test_and_change_bit(int nr, volatile void * addr); + +static inline int __test_and_change_bit(int nr, volatile void *addr) +{ + unsigned int mask = 1 << (nr & 7); + unsigned int oldval; + + oldval = ((unsigned char *) addr)[nr >> 3]; + ((unsigned char *) addr)[nr >> 3] = oldval ^ mask; + return oldval & mask; +} + +extern int find_first_zero_bit(void * addr, unsigned size); +extern int find_next_zero_bit(void * addr, int size, int offset); + +/* + * This routine doesn't need to be atomic. + */ +static inline int test_bit(int nr, const void * addr) +{ + return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); +} + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long word) +{ + int k; + + word = ~word; + k = 31; + if (word & 0x0000ffff) { k -= 16; word <<= 16; } + if (word & 0x00ff0000) { k -= 8; word <<= 8; } + if (word & 0x0f000000) { k -= 4; word <<= 4; } + if (word & 0x30000000) { k -= 2; word <<= 2; } + if (word & 0x40000000) { k -= 1; } + return k; +} + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +/* + * redefined in include/linux/bitops.h + * #define ffs(x) generic_ffs(x) + */ + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#define ext2_set_bit test_and_set_bit +#define ext2_clear_bit test_and_clear_bit +#define ext2_test_bit test_bit +#define ext2_find_first_zero_bit find_first_zero_bit +#define ext2_find_next_zero_bit find_next_zero_bit + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_NDS_BITOPS_H */ diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h new file mode 100644 index 0000000..0b48be4 --- /dev/null +++ b/arch/nds32/include/asm/byteorder.h @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/byteorder.h + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * ARM Endian-ness. In little endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + * + * When in big endian mode, byte accesses appear as: + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ + +#ifndef __ASM_NDS_BYTEORDER_H +#define __ASM_NDS_BYTEORDER_H + +#include <asm/types.h> + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __NDSEB__ +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h new file mode 100644 index 0000000..213d18f --- /dev/null +++ b/arch/nds32/include/asm/config.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h new file mode 100644 index 0000000..b8f2e77 --- /dev/null +++ b/arch/nds32/include/asm/global_data.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - so far no one uses the macros defined in this head file. + **************************************************************/ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + unsigned long fb_base; /* base address of frame buffer */ +#ifdef CONFIG_VFD + unsigned char vfd_type; /* display type */ +#endif + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#ifdef CONFIG_GLOBAL_DATA_NOT_REG8 +extern volatile gd_t g_gd; +#define DECLARE_GLOBAL_DATA_PTR static volatile gd_t *gd = &g_gd +#else +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("$r8") +#endif + +#endif /* __ASM_GBL_DATA_H */ diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h new file mode 100644 index 0000000..c5fba4e --- /dev/null +++ b/arch/nds32/include/asm/io.h @@ -0,0 +1,348 @@ +/* + * linux/include/asm-nds/io.h + * + * Copyright (C) 1996-2000 Russell King + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + */ +#ifndef __ASM_NDS_IO_H +#define __ASM_NDS_IO_H + +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc... include asm/io.h + **************************************************************/ + +#ifdef __KERNEL__ + +#include <linux/types.h> +#include <asm/byteorder.h> +#include <asm/memory.h> +#if 0 /* XXX###XXX */ +#include <asm/arch/hardware.h> +#endif /* XXX###XXX */ + +static inline void sync(void) +{ +} + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + +/* + * Generic virtual read/write. Note that we don't support half-word + * read/writes. We define __arch_*[bl] here, and leave __arch_*w + * to the architecture specific code. + */ +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) + +#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) + +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v,a) __arch_putb(v,a) +#define __raw_writew(v,a) __arch_putw(v,a) +#define __raw_writel(v,a) __arch_putl(v,a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) + +#define writeb(v,a) __arch_putb(v,a) +#define writew(v,a) __arch_putw(v,a) +#define writel(v,a) __arch_putl(v,a) + +#define readb(a) __arch_getb(a) +#define readw(a) __arch_getw(a) +#define readl(a) __arch_getl(a) + +/* + * The compiler seems to be incapable of optimising constants + * properly. Spell it out to the compiler in some cases. + * These are only valid for small values of "off" (< 1<<12) + */ +#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) +#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) +#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) + +#define __raw_base_readb(base,off) __arch_base_getb(base,off) +#define __raw_base_readw(base,off) __arch_base_getw(base,off) +#define __raw_base_readl(base,off) __arch_base_getl(base,off) + +/* + * Now, pick up the machine-defined IO definitions + * #include <asm/arch/io.h> + */ + +/* + * IO port access primitives + * ------------------------- + * + * The ARM doesn't have special IO access instructions; all IO is memory + * mapped. Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * Note that for a big endian machine, this implies that the following + * big endian mode connectivity is in place, as described by numerious + * ARM documents: + * + * PCI: D0-D7 D8-D15 D16-D23 D24-D31 + * ARM: D24-D31 D16-D23 D8-D15 D0-D7 + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. + * + * Note that we prevent GCC re-ordering or caching values in expressions + * by introducing sequence points into the in*() definitions. Note that + * __raw_* do not guarantee this behaviour. + * + * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. + */ +#ifdef __io +#define outb(v,p) __raw_writeb(v,__io(p)) +#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) + +#define outsb(p,d,l) __raw_writesb(__io(p),d,l) +#define outsw(p,d,l) __raw_writesw(__io(p),d,l) +#define outsl(p,d,l) __raw_writesl(__io(p),d,l) + +#define insb(p,d,l) __raw_readsb(__io(p),d,l) +#define insw(p,d,l) __raw_readsw(__io(p),d,l) +#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#endif + +#define outb_p(val,port) outb((val),(port)) +#define outw_p(val,port) outw((val),(port)) +#define outl_p(val,port) outl((val),(port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port,from,len) outsb(port,from,len) +#define outsw_p(port,from,len) outsw(port,from,len) +#define outsl_p(port,from,len) outsl(port,from,len) +#define insb_p(port,to,len) insb(port,to,len) +#define insw_p(port,to,len) insw(port,to,len) +#define insl_p(port,to,len) insl(port,to,len) + +/* + * ioremap and friends. + * + * ioremap takes a PCI memory address, as specified in + * linux/Documentation/IO-mapping.txt. If you want a + * physical address, use __ioremap instead. + */ +extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); +extern void __iounmap(void *addr); + +/* + * Generic ioremap support. + * + * Define: + * iomem_valid_addr(off,size) + * iomem_to_phys(off) + */ +#ifdef iomem_valid_addr +#define __arch_ioremap(off,sz,nocache) \ + ({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off),_size,0); \ + _ret; \ + }) + +#define __arch_iounmap __iounmap +#endif + +#define ioremap(off,sz) __arch_ioremap((off),(sz),0) +#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) +#define iounmap(_addr) __arch_iounmap(_addr) + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +extern void consistent_sync(void *vaddr, size_t size, int rw); + +/* + * String version of IO memory access ops: + */ +extern void _memcpy_fromio(void *, unsigned long, size_t); +extern void _memcpy_toio(unsigned long, const void *, size_t); +extern void _memset_io(unsigned long, int, size_t); + +extern void __readwrite_bug(const char *fn); + +/* + * If this architecture has PCI memory IO, then define the read/write + * macros. These should only be used with the cookie passed from + * ioremap. + */ +#ifdef __mem_pci + +#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) + +#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) +#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) + +#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) +#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) +#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) + +#define eth_io_copy_and_sum(s,c,l,b) \ + eth_copy_and_sum((s),__mem_pci(c),(l),(b)) + +static inline int +check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#elif !defined(readb) + +#define readb(addr) (__readwrite_bug("readb"),0) +#define readw(addr) (__readwrite_bug("readw"),0) +#define readl(addr) (__readwrite_bug("readl"),0) +#define writeb(v,addr) __readwrite_bug("writeb") +#define writew(v,addr) __readwrite_bug("writew") +#define writel(v,addr) __readwrite_bug("writel") + +#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") + +#define check_signature(io,sig,len) (0) + +#endif /* __mem_pci */ + +/* + * If this architecture has ISA IO, then define the isa_read/isa_write + * macros. + */ +#ifdef __mem_isa + +#define isa_readb(addr) __raw_readb(__mem_isa(addr)) +#define isa_readw(addr) __raw_readw(__mem_isa(addr)) +#define isa_readl(addr) __raw_readl(__mem_isa(addr)) +#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) +#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) +#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) +#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + eth_copy_and_sum((a),__mem_isa(b),(c),(d)) + +static inline int +isa_check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (isa_readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#else /* __mem_isa */ + +#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) +#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) +#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) +#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") +#define isa_writew(val,addr) __readwrite_bug("isa_writew") +#define isa_writel(val,addr) __readwrite_bug("isa_writel") +#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") +#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") +#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + __readwrite_bug("isa_eth_io_copy_and_sum") + +#define isa_check_signature(io,sig,len) (0) + +#endif /* __mem_isa */ +#endif /* __KERNEL__ */ +#endif /* __ASM_NDS_IO_H */ diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h new file mode 100644 index 0000000..a6f1c93 --- /dev/null +++ b/arch/nds32/include/asm/mach-types.h @@ -0,0 +1,29 @@ +/* + * This was automagically generated from arch/nds/tools/mach-types! + * Do NOT edit + */ + +#ifndef __ASM_NDS32_MACH_TYPE_H +#define __ASM_NDS32_MACH_TYPE_H + +#ifndef __ASSEMBLY__ +/* The type of machine we're running on */ +extern unsigned int __machine_arch_type; +#endif + +/* see arch/arm/kernel/arch.c for a description of these */ +#define MACH_TYPE_ADPAG101 0 + +#ifdef CONFIG_ARCH_ADPAG101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADPAG101 +# endif +# define machine_is_adpag101() (machine_arch_type == MACH_TYPE_ADPAG101) +#else +# define machine_is_adpag101() (0) +#endif + +#endif /* __ASM_NDS32_MACH_TYPE_H */ diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h new file mode 100644 index 0000000..b8cff9b --- /dev/null +++ b/arch/nds32/include/asm/memory.h @@ -0,0 +1,19 @@ +/* + * linux/include/asm-arm/memory.h + * + * Copyright (C) 2000-2002 Russell King + * + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Note: this file should not be included by non-asm/.h files + */ +#ifndef __ASM_NDS_MEMORY_H +#define __ASM_NDS_MEMORY_H + +#endif /* __ASM_NDS_MEMORY_H */ diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h new file mode 100644 index 0000000..246167d --- /dev/null +++ b/arch/nds32/include/asm/posix_types.h @@ -0,0 +1,84 @@ +/* + * linux/include/asm-arm/posix_types.h + * + * Copyright (C) 1996-1998 Russell King. + * + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + * 05-03-2010 Modified for arch NDS32 + */ +#ifndef __ARCH_NDS_POSIX_TYPES_H +#define __ARCH_NDS_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) + +#undef __FD_CLR +#define __FD_CLR(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) + +#undef __FD_ISSET +#define __FD_ISSET(fd, fdsetp) \ + ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ + (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) + +#endif + +#endif /* __ARCH_NDS_POSIX_TYPES_H */ diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h new file mode 100644 index 0000000..19fdcc0 --- /dev/null +++ b/arch/nds32/include/asm/processor.h @@ -0,0 +1,25 @@ +/* + * linux/include/asm-arm/processor.h + * + * Copyright (C) 1995-2002 Russell King + * + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_NDS_PROCESSOR_H +#define __ASM_NDS_PROCESSOR_H + +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - so far some files include /asm/processor.h, but + * no one uses the macros defined in this head file. + **************************************************************/ + +#endif /* __ASM_ARM_PROCESSOR_H */ diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h new file mode 100644 index 0000000..fb804cb --- /dev/null +++ b/arch/nds32/include/asm/ptrace.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - included in common.h + */ + +#ifndef __ASM_NDS_PTRACE_H +#define __ASM_NDS_PTRACE_H + +#include <asm/ptregs.h> + +#endif /* __ASM_NDS_PTRACE_H */ diff --git a/arch/nds32/include/asm/ptregs.h b/arch/nds32/include/asm/ptregs.h new file mode 100644 index 0000000..8fda5d3 --- /dev/null +++ b/arch/nds32/include/asm/ptregs.h @@ -0,0 +1,82 @@ +/* + * linux/include/asm-arm/proc-armv/ptrace.h + * + * Copyright (C) 1996-1999 Russell King + * + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PTREGS_H +#define __PTREGS_H + +#define USR_MODE 0x00 +#define SU_MODE 0x01 +#define HV_MODE 0x10 +#define MODE_MASK (0x03<<3) +#define GIE_BIT 0x01 + +#ifndef __ASSEMBLY__ + +/* this struct defines the way the registers are stored on the + stack during a system call. */ + +struct pt_regs { + long uregs[39]; +}; + +#define PTREGS(reg) [reg] +#define R0 uregs[1] /* R0 */ +#define R1 uregs[2] +#define R2 uregs[3] +#define R3 uregs[4] +#define R4 uregs[5] +#define R5 uregs[6] +#define R6 uregs[7] +#define R7 uregs[8] +#define R8 uregs[9] +#define R9 uregs[10] +#define R10 uregs[11] +#define R11 uregs[12] +#define R12 uregs[13] +#define R13 uregs[14] +#define R14 uregs[15] +#define R15 uregs[16] +#define R16 uregs[17] +#define R17 uregs[18] +#define R18 uregs[19] +#define R19 uregs[20] +#define R20 uregs[21] +#define R21 uregs[22] +#define R22 uregs[23] +#define R23 uregs[24] +#define R24 uregs[25] +#define R25 uregs[26] +#define R26 uregs[27] +#define R27 uregs[28] +#define FP uregs[29] /* R28 */ +#define GP uregs[30] /* R29 */ +#define RA uregs[31] /* R30 */ +#define SP uregs[32] /* R31 */ +#define D0HI uregs[33] +#define D0LO uregs[34] +#define D1HI uregs[35] +#define D1LO uregs[36] +#define PSW uregs[37] /* IR0 */ +#define PC uregs[38] /* PC */ + + +#define processor_mode(regs) \ + (((regs)->PSW & MODE_MASK)>>3) + +#define interrupts_enabled(regs) \ + ((regs)->PSW & GIE_BIT) + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/nds32/include/asm/setup.h b/arch/nds32/include/asm/setup.h new file mode 100644 index 0000000..4a01228 --- /dev/null +++ b/arch/nds32/include/asm/setup.h @@ -0,0 +1,272 @@ +/* + * linux/include/asm/setup.h + * + * Copyright (C) 1997-1999 Russell King + * + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Structure passed to kernel to tell it about the + * hardware it's running on. See linux/Documentation/arm/Setup + * for more info. + * + * NOTE: + * This file contains two ways to pass information from the boot + * loader to the kernel. The old struct param_struct is deprecated, + * but it will be kept in the kernel for 5 years from now + * (2001). This will allow boot loaders to convert to the new struct + * tag way. + */ + +#ifndef __ASM_NDS_SETUP_H +#define __ASM_NDS_SETUP_H + +/* + * Usage: + * - do not go blindly adding fields, add them at the end + * - when adding fields, don't rely on the address until + * a patch from me has been released + * - unused fields should be zero (for future expansion) + * - this structure is relatively short-lived - only + * guaranteed to contain useful data in setup_arch() + */ +#define COMMAND_LINE_SIZE 1024 + +/* This is the old deprecated way to pass parameters to the kernel */ +struct param_struct { + union { + struct { + unsigned long page_size; /* 0 */ + unsigned long nr_pages; /* 4 */ + unsigned long ramdisk_size; /* 8 */ + unsigned long flags; /* 12 */ +#define FLAG_READONLY 1 +#define FLAG_RDLOAD 4 +#define FLAG_RDPROMPT 8 + unsigned long rootdev; /* 16 */ + unsigned long video_num_cols; /* 20 */ + unsigned long video_num_rows; /* 24 */ + unsigned long video_x; /* 28 */ + unsigned long video_y; /* 32 */ + unsigned long memc_control_reg; /* 36 */ + unsigned char sounddefault; /* 40 */ + unsigned char adfsdrives; /* 41 */ + unsigned char bytes_per_char_h; /* 42 */ + unsigned char bytes_per_char_v; /* 43 */ + unsigned long pages_in_bank[4]; /* 44 */ + unsigned long pages_in_vram; /* 60 */ + unsigned long initrd_start; /* 64 */ + unsigned long initrd_size; /* 68 */ + unsigned long rd_start; /* 72 */ + unsigned long system_rev; /* 76 */ + unsigned long system_serial_low; /* 80 */ + unsigned long system_serial_high; /* 84 */ + unsigned long mem_fclk_21285; /* 88 */ + } s; + char unused[256]; + } u1; + union { + char paths[8][128]; + struct { + unsigned long magic; + char n[1024 - sizeof(unsigned long)]; + } s; + } u2; + char commandline[COMMAND_LINE_SIZE]; +}; + +/* + * The new way of passing information: a list of tagged entries + */ + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; /* bit 0 = read-only */ + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 + +struct tag_mem32 { + u32 size; + u32 start; /* physical start address */ +}; + +/* VGA text type displays */ +#define ATAG_VIDEOTEXT 0x54410003 + +struct tag_videotext { + u8 x; + u8 y; + u16 video_page; + u8 video_mode; + u8 video_cols; + u16 video_ega_bx; + u8 video_lines; + u8 video_isvga; + u16 video_points; +}; + +/* describes how the ramdisk will be used in kernel */ +#define ATAG_RDIMG 0x54410004 + +struct tag_mem_range { + u32 addr; + u32 size; + struct tag_mem_range * next; +}; + +struct tag_ramdisk { + u32 flags; /* bit 0 = load, bit 1 = prompt */ + u32 size; /* decompressed ramdisk size in _kilo_ bytes */ + u32 start; /* starting block of floppy-based RAM disk image */ +}; + +/* describes where the compressed ramdisk image lives */ +#define ATAG_INITRD 0x54410005 + +struct tag_initrd { + u32 start; /* physical start address */ + u32 size; /* size of compressed ramdisk image in bytes */ +}; + +/* board serial number. "64 bits should be enough for everybody" */ +#define ATAG_SERIAL 0x54410006 + +struct tag_serialnr { + u32 low; + u32 high; +}; + +/* board revision */ +#define ATAG_REVISION 0x54410007 + +struct tag_revision { + u32 rev; +}; + +/* initial values for vesafb-type framebuffers. see struct screen_info + * in include/linux/tty.h + */ +#define ATAG_VIDEOLFB 0x54410008 + +struct tag_videolfb { + u16 lfb_width; + u16 lfb_height; + u16 lfb_depth; + u16 lfb_linelength; + u32 lfb_base; + u32 lfb_size; + u8 red_size; + u8 red_pos; + u8 green_size; + u8 green_pos; + u8 blue_size; + u8 blue_pos; + u8 rsvd_size; + u8 rsvd_pos; +}; + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410009 + +struct tag_cmdline { + char cmdline[1]; /* this is the minimum size */ +}; + +/* acorn RiscPC specific information */ +#define ATAG_ACORN 0x41000101 + +struct tag_acorn { + u32 memc_control_reg; + u32 vram_pages; + u8 sounddefault; + u8 adfsdrives; +}; + +/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ +#define ATAG_MEMCLK 0x41000402 + +struct tag_memclk { + u32 fmemclk; +}; + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem32 mem; + struct tag_videotext videotext; + struct tag_ramdisk ramdisk; + struct tag_initrd initrd; + struct tag_serialnr serialnr; + struct tag_revision revision; + struct tag_videolfb videolfb; + struct tag_cmdline cmdline; + struct tag_mem_range mem_range; + /* + * Acorn specific + */ + struct tag_acorn acorn; + + /* + * DC21285 specific + */ + struct tag_memclk memclk; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(const struct tag *); +}; + +#define __tag __attribute__((unused, __section__(".taglist"))) +#define __tagtable(tag, fn) \ +static struct tagtable __tagtable_##fn __tag = { tag, fn } + +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t,base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +/* + * Memory map description + */ +#define NR_BANKS 8 + +struct meminfo { + int nr_banks; + unsigned long end; + struct { + unsigned long start; + unsigned long size; + int node; + } bank[NR_BANKS]; +}; + +extern struct meminfo meminfo; + +#endif diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h new file mode 100644 index 0000000..85ad363 --- /dev/null +++ b/arch/nds32/include/asm/string.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_NDS_STRING_H +#define __ASM_NDS_STRING_H + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#undef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char * s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char * strchr(const char * s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +#undef __HAVE_ARCH_MEMSET +extern void * memset(void *, int, __kernel_size_t); + +#ifdef CONFIG_MARCO_MEMSET +extern void __memzero(void *ptr, __kernel_size_t n); + +#define memset(p,v,n) \ + ({ \ + if ((n) != 0) { \ + if (__builtin_constant_p((v)) && (v) == 0) \ + __memzero((p),(n)); \ + else \ + memset((p),(v),(n)); \ + } \ + (p); \ + }) + +#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) +#else +extern void memzero(void *ptr, __kernel_size_t n); +#endif + +#endif /* __ASM_NDS_STRING_H */ diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h new file mode 100644 index 0000000..c12b3f4 --- /dev/null +++ b/arch/nds32/include/asm/types.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_NDS_TYPES_H +#define __ASM_NDS_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +typedef volatile unsigned char vuchar; +typedef volatile unsigned long vulong; +typedef volatile unsigned short vushort; + +#include <stddef.h> + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +#endif /* __KERNEL__ */ + +#endif diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h new file mode 100644 index 0000000..82cb4cf --- /dev/null +++ b/arch/nds32/include/asm/u-boot-nds32.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _U_BOOT_NDS32_H_ +#define _U_BOOT_NDS32_H_ 1 + +/* for the following variables, see start.S */ +extern ulong _andesboot_start; /* code start */ +extern ulong _andesboot_end; /* code end */ +extern ulong _andesboot_real_end; /* first usable RAM address */ + +/* _bss_start and _bss_end + * extern ulong _bss_start: code + data end == BSS start + * extern ulong _bss_end: BSS end + */ + +extern ulong IRQ_STACK_START; /* top of IRQ stack */ +extern ulong FIQ_STACK_START; /* top of FIQ stack */ + +/* cpu/.../cpu.c */ +void cpu_init(void); +int cleanup_before_linux(void); + +/* cpu/.../arch/cpu.c */ +int arch_cpu_init(void); +int arch_misc_init(void); + +/* board/.../... */ +int board_init(void); +int dram_init (void); +void setup_serial_tag (struct tag **params); +void setup_revision_tag (struct tag **params); + +/* ------------------------------------------------------------ */ +/* Here is a list of some prototypes which are incompatible to */ +/* the U-Boot implementation */ +/* To be fixed! */ +/* ------------------------------------------------------------ */ +/* common/cmd_nvedit.c */ +int setenv (char *, char *); + +/* cpu/.../interrupt.c */ +int arch_interrupt_init (void); +void reset_timer_masked (void); +ulong get_timer_masked (void); +void udelay_masked (unsigned long usec); + +/* cpu/.../timer.c */ +int timer_init (void); + +#endif /* _U_BOOT_ARM_H_ */ diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h new file mode 100644 index 0000000..929d367 --- /dev/null +++ b/arch/nds32/include/asm/u-boot.h @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * Copyright (C) 2010 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +#include <environment.h> + +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + + env_t *bi_env; + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + + struct /* RAM configuration */ + { + unsigned long start; + unsigned long size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; + + /* removed according to arm */ + /* struct bd_info_ext bi_ext; */ /* board specific extension */ +} bd_t; + +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +#endif /* _U_BOOT_H_ */ diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h new file mode 100644 index 0000000..4160041 --- /dev/null +++ b/arch/nds32/include/asm/unaligned.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Andes Technology Corporation + * Copyright (C) 2010 Macpaul Lin (macpaul@andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef _ASM_NDS_UNALIGNED_H +#define _ASM_NDS_UNALIGNED_H + +#include <compiler.h> +/* + * Select endianness + */ +#ifndef __NDSEB__ +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif /* __NDSEB__ */ + +#include <asm/byteorder.h> + +#include <linux/unaligned/le_byteshift.h> +#include <linux/unaligned/be_byteshift.h> +#include <linux/unaligned/generic.h> + +#endif /* _ASM_NDS_UNALIGNED_H */

Add standalone program related support for nds32 architecture.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- examples/standalone/nds32.lds | 64 +++++++++++++++++++++++++++++++++++++ examples/standalone/stubs.c | 17 +++++++++- examples/standalone/x86-testapp.c | 12 +++++++ 3 files changed, 92 insertions(+), 1 deletions(-) create mode 100644 examples/standalone/nds32.lds

diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds new file mode 100644 index 0000000..1a90873 --- /dev/null +++ b/examples/standalone/nds32.lds @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Tech Crop. nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32") +OUTPUT_ARCH(nds32) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; + + . = ALIGN(4); + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + + _end = .; + + . = 0x02000000; + .u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) } +} diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 2d2e709..a763d0d 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -167,8 +167,23 @@ gd_t *global_data; " jmp %%g1\n" \ " nop\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" ); - +#elif defined(CONFIG_NDS32) +/* + * r16 holds the pointer to the global_data. gp is call clobbered. + * not support reduced register (16 GPR). + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" lwi $r16, [$gp + (%0)]\n" \ +" lwi $r16, [$r16 + (%1)]\n" \ +" jr $r16\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16" ); #else +/*" addi $sp, $sp, -24\n" \ +" br $r16\n" */ + #error stubs definition missing for this architecture #endif

diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c index e8603d9..9f80a5d 100644 --- a/examples/standalone/x86-testapp.c +++ b/examples/standalone/x86-testapp.c @@ -52,6 +52,16 @@ asm volatile ( \ " lw $25, %1($25)\n" \ " jr $25\n" \ : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9"); +#elif defined(__nds32__) +#define EXPORT_FUNC(x) \ +asm volatile ( \ +" .globl mon_" #x "\n" \ +"mon_" #x ":\n" \ +" lwi $r16, [$gp + (%0)]\n" \ +" lwi $r16, [$r16 + (%1)]\n" \ +" jr $r16\n" \ + : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16"); + #else #error [No stub code for this arch] #endif @@ -72,6 +82,8 @@ int main(void) register volatile xxx_t *pq asm("r8"); #elif defined(__mips__) register volatile xxx_t *pq asm("k0"); +#elif defined(__nds32__) + register volatile xxx_t *pq asm("$r16"); #endif char buf[32];

Add adp-ag101 board related settings to u-boot.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- MAINTAINERS | 11 ++ MAKEALL | 9 + Makefile | 10 + board/AndesTech/adp-ag101/Makefile | 51 ++++++ board/AndesTech/adp-ag101/adp-ag101.c | 77 ++++++++ board/AndesTech/adp-ag101/config.mk | 42 +++++ include/configs/adp-ag101.h | 319 +++++++++++++++++++++++++++++++++ 7 files changed, 519 insertions(+), 0 deletions(-) create mode 100644 board/AndesTech/adp-ag101/Makefile create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c create mode 100644 board/AndesTech/adp-ag101/config.mk create mode 100644 include/configs/adp-ag101.h

diff --git a/MAINTAINERS b/MAINTAINERS index 4b91b0f..4783d93 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1039,5 +1039,16 @@ Brent Kandetzki brentk@teleco.com IP04 BF532

######################################################################### +# NDS32 Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Macpaul Lin macpaul@andestech.com + + ADP-AG101 N1213 (AG101 SoC) + +######################################################################### # End of MAINTAINERS list # ######################################################################### diff --git a/MAKEALL b/MAKEALL index 2133559..c288f7b 100755 --- a/MAKEALL +++ b/MAKEALL @@ -959,6 +959,14 @@ LIST_sh=" \

LIST_sparc="gr_xc3s_1500 gr_cpci_ax2000 gr_ep2s60 grsim grsim_leon2"

+######################################################################### +## NDS32 Systems +######################################################################### + +LIST_nds32=" \ + adp-ag101 \ +" + #-----------------------------------------------------------------------

#----- for now, just run PowerPC by default ----- @@ -1017,6 +1025,7 @@ do |coldfire \ |microblaze \ |mips|mips_el \ + |nds32|nds32el \ |nios2 \ |ppc|powerpc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \ |sh|sh2|sh3|sh4 \ diff --git a/Makefile b/Makefile index 9cea069..dd03d38 100644 --- a/Makefile +++ b/Makefile @@ -497,6 +497,16 @@ lcname = $(shell echo $(1) | sed -e 's/(.*)_config/\L\1/') ucname = $(shell echo $(1) | sed -e 's/(.*)_config/\U\1/')

#======================================================================== +# ANDES +#======================================================================== + +######################################################################### +## NDS32 adp-ag101 (n1213h hard core SoC) +######################################################################### +adp-ag101_config: unconfig + @$(MKCONFIG) $(@:_config=) nds32 n1213 $(@:_config=) AndesTech ag101 + +#======================================================================== # PowerPC #========================================================================

diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile new file mode 100644 index 0000000..3002b6d --- /dev/null +++ b/board/AndesTech/adp-ag101/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) 2010 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := adp-ag101.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c new file mode 100644 index 0000000..083df5b --- /dev/null +++ b/board/AndesTech/adp-ag101/adp-ag101.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> + +#include <asm/arch/ftsmc020.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ADPAG101; + gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x100; + + ftsmc020_init(); /* initialize Flash */ + return 0; +} + +int dram_init(void) +{ + unsigned long sdram_base = PHYS_SDRAM_0; + unsigned long expected_size = PHYS_SDRAM_0_SIZE; + unsigned long actual_size; + + actual_size = get_ram_size((void *)sdram_base, expected_size); + + gd->bd->bi_dram[0].start = sdram_base; + gd->bd->bi_dram[0].size = actual_size; + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ftmac100_initialize(bd); +} + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/AndesTech/adp-ag101/config.mk b/board/AndesTech/adp-ag101/config.mk new file mode 100644 index 0000000..0b95960 --- /dev/null +++ b/board/AndesTech/adp-ag101/config.mk @@ -0,0 +1,42 @@ +# +# Copyright (C) 2010 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus +# +# see http://www.faraday-tech.com/ for more information + +# A320 has 1 bank of 64 MB DRAM +# +# 1000'0000 to 1400'0000 +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 +# +# we load ourself to 13f8'0000 +# +# download area is 1200'0000 + +PLATFORM_RELFLAGS += -gdwarf-2 +TEXT_BASE = 0x03200000 +LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds +EXTERN_LIB += $(shell $(CC) -print-file-name=include)/../static/el/libgcc.a diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h new file mode 100644 index 0000000..311593f --- /dev/null +++ b/include/configs/adp-ag101.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/ag101.h> + +/*----------------------------------------------------------------------- + * CPU and Board Configuration Options + */ +#define CONFIG_ADP_AG101P + +#define CONFIG_USE_INTERRUPT + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/*----------------------------------------------------------------------- + * Timer + */ +/* a320evb: CONFIG_SYS_HZ: 1000 + * ag101: CONFIG_SYS_HZ: APB_CLK (ag101 original timer clock frequency) + * + * CONFIG_SYS_HZ = APB_CLK = SYS_CLK = CONFIG_SYS_CLK_FREQ /2 + * the PWM Timer 4 uses a counter of 15625 for 10 ms, so we need + * it to wrap 100 times (total 1562500) to get 1 sec. + * #define CONFIG_HZ 1562500 + * 1562500*25=3906250 + */ +#define CONFIG_SYS_HZ APB_CLK /* ag101 original timer clock frequency */ +#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ + +/* + * System Clock + * Suggested frequency lists: + * 16000000 -> 16.000000 MHz + * 18432000 -> 18.432000 MHz + * 22118400 -> 22.118400 MHz + * 83000000 -> 83.000000 MHz + * 33000000 -> 33.000000 MHz + * 36864000 -> 36.864000 MHz + * 48000000 -> 48.000000 MHz CONFIG_ADP_AG101 + * 40000000 -> 40.000000 MHz CONFIG_ADP_AG101P + */ +#ifdef CONFIG_ADP_AG101 +#define CONFIG_SYS_CLK_FREQ 48000000 +#endif + +#ifdef CONFIG_ADP_AG101P +#define CONFIG_SYS_CLK_FREQ 39062500 +#endif + +/* + * Use Externel CLOCK or PCLK + */ +#undef CONFIG_EXT_CLK + +#ifndef CONFIG_EXT_CLK +#define CONFIG_PCLK +#endif + +#ifdef CONFIG_EXT_CLK +#define TIMER_CLOCK 32768 /* EXT_CLK */ +#else +#define TIMER_CLOCK CONFIG_SYS_HZ /* PCLK */ +#endif + +#define TIMER_LOAD_VAL 0xffffffff + +/*----------------------------------------------------------------------- + * Real Time Clock + */ +#define CONFIG_RTC_FTRTC010 + +/* + * Real Time Clock Divider + * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) + */ +#ifdef CONFIG_ADP_AG101 +#define OSC_5MHZ (5*1000000) +#define OSC_CLK (2*OSC_5MHZ) +#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) +#endif + +#ifdef CONFIG_ADP_AG101P +#define OSC_5MHZ (5*1000000) +#define OSC_CLK (4*OSC_5MHZ) +#define RTC_DIV_COUNT (0.5) /* Why?? */ +#endif + +/*----------------------------------------------------------------------- + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 0x99600000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 + +#ifdef CONFIG_ADP_AG101 +#define CONFIG_SYS_NS16550_CLK (46080000 * 20) / 25 /* AG101 */ +#endif + +#ifdef CONFIG_ADP_AG101P +#define CONFIG_SYS_NS16550_CLK (18432000 * 20) / 25 /* AG101P */ +#endif + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Ethernet + */ +#define CONFIG_NET_MULTI +#define CONFIG_FTMAC100 + +#define CONFIG_BOOTDELAY 3 + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/*----------------------------------------------------------------------- + * size in bytes reserved for initial data +*/ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/*----------------------------------------------------------------------- + * SDRAM controller configuration + */ +#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ + FTSDMC020_TP0_TRP(1) | \ + FTSDMC020_TP0_TRCD(1) | \ + FTSDMC020_TP0_TRF(3) | \ + FTSDMC020_TP0_TWR(1) | \ + FTSDMC020_TP0_TCL(2)) + +#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \ + FTSDMC020_TP1_INI_REFT(8) | \ + FTSDMC020_TP1_REF_INTV(0x180)) + +#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \ + FTSDMC020_BANK_DDW_X16 | \ + FTSDMC020_BANK_DSZ_256M | \ + FTSDMC020_BANK_MBW_32 | \ + FTSDMC020_BANK_SIZE_64M) + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ + +/* + * Load address and memory test area should agree with + * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x0Cf00000 + +/* memtest works on 63 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x00200000 + +/*----------------------------------------------------------------------- + * Static memory controller configuration + */ + +#include <asm/arch/ftsmc020.h> + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +#ifdef CONFIG_ADP_AG101 +/* + * FLASH on ADP_AG101P is connected to BANK1 + * Just disalbe the other BANK to avoid detection error. + */ +#define FTSMC020_BANK0_CONFIG (0x00) +#define FTSMC020_BANK0_TIMING (0x00) + + +#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) +#endif + +#ifdef CONFIG_ADP_AG101P +/* + * FLASH on ADP_AG101P is connected to BANK0 + * Just disalbe the other BANK to avoid detection error. + */ +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (0x00) +#define FTSMC020_BANK1_TIMING (0x00) + +#endif + + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* support JEDEC */ +/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ +#define PHYS_FLASH_1 0x80400000 + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +/* max number of memory banks */ +/* + * There are 4 banks supported for this Controller, + * but we have only 1 bank connected to flash on board + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_FLASH_SECT_SIZE (0x10000*2*2) + +/* environments */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x1C0000) +#define CONFIG_ENV_SIZE CONFIG_FLASH_SECT_SIZE +#define CONFIG_ENV_OVERWRITE + +#endif /* __CONFIG_H */

Add missing codes according to original datasheet. This patch also makes ftrtc010 could be adapted to PCLK and EXT_CLK.

Signed-off-by: Macpaul Lin macpaul@andestech.com --- drivers/rtc/ftrtc010.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c index 7738a7a..4569595 100644 --- a/drivers/rtc/ftrtc010.c +++ b/drivers/rtc/ftrtc010.c @@ -34,6 +34,13 @@ struct ftrtc010 { unsigned int alarm_hour; /* 0x18 */ unsigned int record; /* 0x1c */ unsigned int cr; /* 0x20 */ + unsigned int wsec; /* 0x24 */ + unsigned int wmin; /* 0x28 */ + unsigned int whour; /* 0x2c */ + unsigned int wday; /* 0x30 */ + unsigned int intr; /* 0x34 */ + unsigned int div; /* 0x38 */ + unsigned int rev; /* 0x3c */ };

/* @@ -85,7 +92,11 @@ int rtc_get(struct rtc_time *tmp) debug("%s(): record register: %x\n", __func__, readl(&rtc->record));

+#ifdef CONFIG_PCLK + now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT; +#else /* CONFIG_EXT_CLK */ now = ftrtc010_time() + readl(&rtc->record); +#endif

to_tm(now, tmp);