[U-Boot] [Patch V2 0/4] add LS1043AQDS support
Hi all,
Here are the changes for V2 patchset. Please help to review them.
- Fix pcie compile errors for LS1021A. - Add LS1043ARDB and LS1043AQDS dtb support in U-Boot.
[Patch V2 1/4] pci/layerscape: add support for LS1043A PCIe LUT [Patch V2 2/4] armv8/ls1043ardb: dts: add dtb support [Patch V2 3/4] armv8/ls1043aqds: add LS1043AQDS board support [Patch V2 4/4] armv8/ls1043aqds: dts: add dtb support
Thanks, Qianyu
From: Mingkai Hu Mingkai.Hu@freescale.com
The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register.
Signed-off-by: Mingkai Hu Mingkai.Hu@freescale.com Signed-off-by: Gong Qianyu Qianyu.Gong@freescale.com --- V2: - Fix compile errors for ls1021a.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 8 ++++++++ drivers/pci/pcie_layerscape.c | 14 +++++++------- 5 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 87bb937..fe361da 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -44,6 +44,7 @@ #define CONFIG_SYS_FSL_CCSR_SCFG_LE #define CONFIG_SYS_FSL_ESDHC_LE #define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
@@ -113,6 +114,7 @@ #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_PEX_LUT_BE
#define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d941437..f52815d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -60,6 +60,10 @@ #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x10000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC
/* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 6a70d44..e700af0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -78,6 +78,10 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x80000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC
/* Device Configuration */ #define DCFG_BASE 0x01e00000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 5ed456e..8691906 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -23,6 +23,14 @@ #define scfg_out32(a, v) out_be32(a, v) #endif
+#ifdef CONFIG_SYS_FSL_PEX_LUT_LE +#define pex_lut_in32(a) in_le32(a) +#define pex_lut_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) +#define pex_lut_in32(a) in_be32(a) +#define pex_lut_out32(a, v) out_be32(a, v) +#endif + struct cpu_type { char name[15]; u32 soc_ver; diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 4cee038..8471678 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -13,6 +13,7 @@ #include <malloc.h> #ifdef CONFIG_FSL_LAYERSCAPE #include <asm/arch/fdt.h> +#include <asm/arch/soc.h> #endif
#ifndef CONFIG_SYS_PCI_MEMORY_BUS @@ -57,11 +58,6 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C
-/* LUT registers */ -#define PCIE_LUT_BASE 0x80000 -#define PCIE_LUT_LCTRL0 0x7F8 -#define PCIE_LUT_DBG 0x7FC - #define PCIE_DBI_RO_WR_EN 0x8bc
#define PCIE_LINK_CAP 0x7c @@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
return 1; } -#else +#elif defined(CONFIG_FSL_LAYERSCAPE) static int ls_pcie_link_state(struct ls_pcie *pcie) { u32 state;
- state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & + state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & LTSSM_STATE_MASK; if (state < LTSSM_PCIE_L0) { debug("....PCIe link error. LTSSM=0x%02x.\n", state); @@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
for (pf = 0; pf < PCIE_PF_NUM; pf++) { for (vf = 0; vf <= PCIE_VF_NUM; vf++) { +#ifdef CONFIG_FSL_LAYERSCAPE writel(PCIE_LCTRL0_VAL(pf, vf), pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif ls_pcie_ep_setup_bars(pcie->dbi); ls_pcie_ep_setup_atu(pcie, info); } }
/* Disable CFG2 */ +#ifdef CONFIG_FSL_LAYERSCAPE writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif } else { ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); ls_pcie_ep_setup_atu(pcie, info);
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 4cee038..8471678 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -13,6 +13,7 @@ #include <malloc.h> #ifdef CONFIG_FSL_LAYERSCAPE #include <asm/arch/fdt.h> +#include <asm/arch/soc.h> #endif
#ifndef CONFIG_SYS_PCI_MEMORY_BUS @@ -57,11 +58,6 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C
-/* LUT registers */ -#define PCIE_LUT_BASE 0x80000 -#define PCIE_LUT_LCTRL0 0x7F8 -#define PCIE_LUT_DBG 0x7FC
#define PCIE_DBI_RO_WR_EN 0x8bc
#define PCIE_LINK_CAP 0x7c @@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
return 1;} -#else +#elif defined(CONFIG_FSL_LAYERSCAPE) static int ls_pcie_link_state(struct ls_pcie *pcie) { u32 state;
state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & LTSSM_STATE_MASK; if (state < LTSSM_PCIE_L0) { debug("....PCIe link error. LTSSM=0x%02x.\n", state);@@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
for (pf = 0; pf < PCIE_PF_NUM; pf++) { for (vf = 0; vf <= PCIE_VF_NUM; vf++) {+#ifdef CONFIG_FSL_LAYERSCAPE writel(PCIE_LCTRL0_VAL(pf, vf), pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif
It looks really weird to have "#ifdef CONFIG_FSL_LAYERSCAPE" inside a file whose name suggests is layerscape-specific. What chips use this file that are not CONFIG_FSL_LAYERSCAPE?
-Scott
+Simon,
Hi,
On Thu, Nov 5, 2015 at 7:45 AM, Scott Wood scottwood@freescale.com wrote:
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 4cee038..8471678 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -13,6 +13,7 @@ #include <malloc.h> #ifdef CONFIG_FSL_LAYERSCAPE #include <asm/arch/fdt.h> +#include <asm/arch/soc.h> #endif
#ifndef CONFIG_SYS_PCI_MEMORY_BUS @@ -57,11 +58,6 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C
-/* LUT registers */ -#define PCIE_LUT_BASE 0x80000 -#define PCIE_LUT_LCTRL0 0x7F8 -#define PCIE_LUT_DBG 0x7FC
#define PCIE_DBI_RO_WR_EN 0x8bc
#define PCIE_LINK_CAP 0x7c @@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
return 1;} -#else +#elif defined(CONFIG_FSL_LAYERSCAPE) static int ls_pcie_link_state(struct ls_pcie *pcie) { u32 state;
state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & LTSSM_STATE_MASK; if (state < LTSSM_PCIE_L0) { debug("....PCIe link error. LTSSM=0x%02x.\n", state);@@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
for (pf = 0; pf < PCIE_PF_NUM; pf++) { for (vf = 0; vf <= PCIE_VF_NUM; vf++) {+#ifdef CONFIG_FSL_LAYERSCAPE writel(PCIE_LCTRL0_VAL(pf, vf), pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif
It looks really weird to have "#ifdef CONFIG_FSL_LAYERSCAPE" inside a file whose name suggests is layerscape-specific. What chips use this file that are not CONFIG_FSL_LAYERSCAPE?
-Scott
Can we start converting the driver to use DM PCI? We should not continue using legacy PCI codes since right now DM PCI is in a good shape. These #ifdef in the driver should really go into device tree as needed.
Regards, Bin
Hi,
On 4 November 2015 at 22:00, Bin Meng bmeng.cn@gmail.com wrote:
+Simon,
Hi,
On Thu, Nov 5, 2015 at 7:45 AM, Scott Wood scottwood@freescale.com wrote:
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 4cee038..8471678 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -13,6 +13,7 @@ #include <malloc.h> #ifdef CONFIG_FSL_LAYERSCAPE #include <asm/arch/fdt.h> +#include <asm/arch/soc.h> #endif
#ifndef CONFIG_SYS_PCI_MEMORY_BUS @@ -57,11 +58,6 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C
-/* LUT registers */ -#define PCIE_LUT_BASE 0x80000 -#define PCIE_LUT_LCTRL0 0x7F8 -#define PCIE_LUT_DBG 0x7FC
#define PCIE_DBI_RO_WR_EN 0x8bc
#define PCIE_LINK_CAP 0x7c @@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
return 1;} -#else +#elif defined(CONFIG_FSL_LAYERSCAPE) static int ls_pcie_link_state(struct ls_pcie *pcie) { u32 state;
state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & LTSSM_STATE_MASK; if (state < LTSSM_PCIE_L0) { debug("....PCIe link error. LTSSM=0x%02x.\n", state);@@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
for (pf = 0; pf < PCIE_PF_NUM; pf++) { for (vf = 0; vf <= PCIE_VF_NUM; vf++) {+#ifdef CONFIG_FSL_LAYERSCAPE writel(PCIE_LCTRL0_VAL(pf, vf), pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif
It looks really weird to have "#ifdef CONFIG_FSL_LAYERSCAPE" inside a file whose name suggests is layerscape-specific. What chips use this file that are not CONFIG_FSL_LAYERSCAPE?
-Scott
Can we start converting the driver to use DM PCI? We should not continue using legacy PCI codes since right now DM PCI is in a good shape. These #ifdef in the driver should really go into device tree as needed.
Agreed. In fact I have a series to add a few improvements, will try to get that out in the next week.
Regards, Simon
Reuse dts files from ls1043a linux kernel. Some parts in dts files may not be needed by U-Boot.
Signed-off-by: Gong Qianyu Qianyu.Gong@freescale.com --- V2: - New Patch.
arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1043a-rdb.dts | 169 +++++++++++++++++++ arch/arm/dts/fsl-ls1043a.dtsi | 346 +++++++++++++++++++++++++++++++++++++++ configs/ls1043ardb_defconfig | 2 + 4 files changed, 518 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ddc6a05..3f3a739 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -83,6 +83,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \ fsl-ls2085a-rdb.dtb +dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts new file mode 100644 index 0000000..51b5e9f --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -0,0 +1,169 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * Mingkai Hu Mingkai.hu@freescale.com + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "fsl-ls1043a.dtsi" + +/ { + model = "LS1043A RDB Board"; +}; + +&i2c0 { + status = "okay"; + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + adt7461a@4c { + compatible = "adt7461a"; + reg = <0x4c>; + }; + eeprom@56 { + compatible = "at24,24c512"; + reg = <0x52>; + }; + + eeprom@57 { + compatible = "at24,24c512"; + reg = <0x53>; + }; + + rtc@68 { + compatible = "pericom,pt7c4338"; + reg = <0x68>; + }; +}; + +&ifc { + status = "okay"; + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + + nor@0,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + /* 1MB for RCW and PBI Image */ + reg = <0x00000000 0x00100000>; + label = "NOR bank0 RCW Image"; + }; + + partition@100000 { + /* 1MB for bank0 u-boot Image */ + reg = <0x00100000 0x00100000>; + label = "NOR bank0 U-Boot Image"; + }; + + partition@200000 { + /* 1 MB for bank0 u-boot Env */ + reg = <0x00200000 0x00100000>; + label = "NOR bank0 U-Boot Env"; + }; + + partition@300000 { + /* 1MB for FMan ucode */ + reg = <0x00300000 0x00100000>; + label = "NOR bank0 FMan ucode"; + }; + + partition@1100000 { + /* 40MB for bank0 FIT Image */ + reg = <0x01100000 0x2800000>; + label = "NOR bank0 FIT Image"; + }; + + partition@4000000 { + /* 1MB for bank4 RCW and PBI Image */ + reg = <0x04000000 0x100000>; + label = "NOR bank4 RCW Image"; + }; + + partition@4100000 { + /* 1MB for bank4 u-boot Image */ + reg = <0x04100000 0x100000>; + label = "NOR bank4 U-Boot Image"; + }; + + partition@4200000 { + /* 1 MB for bank4 u-boot Env */ + reg = <0x04200000 0x100000>; + label = "NOR bank4 U-Boot Env"; + }; + + partition@4300000 { + /* 1 MB for bank4 FMan ucode */ + reg = <0x04300000 0x100000>; + label = "NOR bank4 FMan ucode"; + }; + + partition@5100000 { + /* 40MB for bank4 FIT Image */ + reg = <0x05100000 0x2800000>; + label = "NOR bank4 FIT Image"; + }; + }; + + nand@1,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x0 0x10000>; + + partition@0 { + /* This location must not be altered */ + /* 1MB for u-boot Bootloader Image */ + reg = <0x0 0x00100000>; + label = "NAND U-Boot Image"; + read-only; + }; + + partition@140000 { + /* 1MB for DTB Image */ + reg = <0x00140000 0x002000>; + label = "NAND U-Boot Env"; + }; + + partition@200000 { + /* 20MB for FIT Image */ + reg = <0x00200000 0x01400000>; + label = "NAND FIT Image"; + }; + }; + + cpld: board-control@2,0 { + compatible = "fsl,ls1043ardb-cpld", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 2 0 0x100>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi new file mode 100644 index 0000000..3d34837 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -0,0 +1,346 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2014-2015, Freescale Semiconductor + * + * Mingkai Hu Mingkai.hu@freescale.com + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/memreserve/ 0x80000000 0x00010000; + +/ { + compatible = "fsl,ls1043a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&cluster1_clk>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&cluster1_clk>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&cluster1_clk>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&cluster1_clk>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x1>, /* Physical Secure PPI */ + <1 14 0x1>, /* Physical Non-Secure PPI */ + <1 11 0x1>, /* Virtual PPI */ + <1 10 0x1>; /* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 106 0x4>, + <0 107 0x4>, + <0 95 0x4>, + <0 97 0x4>; + }; + + gic: interrupt-controller@1400000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x1000>, /* GICC */ + <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + }; + + msi1: msi-controller1@1571000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1571000 0x0 0x4>, + <0x0 0x1571004 0x0 0x4>; + reg-names = "msiir", "msir"; + msi-controller; + interrupts = <0 116 0x4>; + }; + + msi2: msi-controller2@1572000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1572000 0x0 0x4>, + <0x0 0x1572004 0x0 0x4>; + reg-names = "msiir", "msir"; + msi-controller; + interrupts = <0 126 0x4>; + }; + + msi3: msi-controller3@1573000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1573000 0x0 0x4>, + <0x0 0x1573004 0x0 0x4>; + reg-names = "msiir", "msir"; + msi-controller; + interrupts = <0 160 0x4>; + }; + + tzasc: tzasc@1500000 { + reg = <0x0 0x1500000 0x0 0x10000>; + interrupts = <0 93 0x4>; + status = "disabled"; + }; + + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <0 43 0x4>; + }; + + sfp: sfp@1e80000 { + reg = <0x00 0x1e80000 0x0 0x10000>; + status = "disabled"; + }; + + snvs: snvs@1e90000 { + reg = <0x00 0x1e90000 0x0 0x10000>; + status = "disabled"; + }; + + serdes1: serdes1@1ea0000 { + reg = <0x00 0x1ea0000 0x0 0x10000>; + status = "disabled"; + }; + + clockgen: clocking@1ee1000 { + ranges = <0x0 0x0 0x1ee1000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + cga_pll1: pll1@800 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0x800 0x10>; + clocks = <&sysclk>; + clock-output-names = "cga-pll1", "cga-pll1-div2", + "cga-pll1-div3", "cga-pll1-div4"; + }; + + cga_pll2: pll2@820 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0x820 0x10>; + clocks = <&sysclk>; + clock-output-names = "cga-pll2", "cga-pll2-div2", + "cga-pll2-div3", "cga-pll2-div4"; + }; + + platform_clk: pll@c00 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0xc00 0x10>; + clocks = <&sysclk>; + clock-output-names = "platform-clk", "platform-clk-div2"; + }; + + cluster1_clk: clk0c0@0 { + compatible = "fsl,qoriq-core-mux-2.0"; + #clock-cells = <0>; + reg = <0x0 0x10>; + clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4", + "pll2cga", "pll2cga-div2", "pll2cga-div4"; + clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>, + <&cga_pll2 0>, <&cga_pll2 1>, <&cga_pll2 2>; + clock-output-names = "cluster1-clk"; + + }; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <0 56 0x4>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <0 57 0x4>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = <0 58 0x4>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c3: i2c@21b0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21b0000 0x0 0x10000>; + interrupts = <0 59 0x4>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + duart0: serial@21c0500 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = <0 54 0x4>; + clock-frequency = <400000000>; + }; + + duart1: serial@21c0600 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = <0 54 0x4>; + clock-frequency = <400000000>; + }; + + duart2: serial@21d0500 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = <0 55 0x4>; + clock-frequency = <400000000>; + }; + + duart3: serial@21d0600 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = <0 55 0x4>; + clock-frequency = <400000000>; + }; + + pcie@3400000 { + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 0x4>, /* controller interrupt */ + <0 117 0x4>; /* PME interrupt */ + interrupt-names = "intr", "pme"; + num-atus = <6>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, + <0000 0 0 2 &gic 0 111 0x4>, + <0000 0 0 3 &gic 0 112 0x4>, + <0000 0 0 4 &gic 0 113 0x4>; + }; + + pcie@3500000 { + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 128 0x4>, + <0 127 0x4>; + interrupt-names = "intr", "pme"; + num-atus = <6>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, + <0000 0 0 2 &gic 0 121 0x4>, + <0000 0 0 3 &gic 0 122 0x4>, + <0000 0 0 4 &gic 0 123 0x4>; + }; + + pcie@3600000 { + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 162 0x4>, + <0 161 0x4>; + interrupt-names = "intr", "pme"; + num-atus = <6>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi3>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, + <0000 0 0 2 &gic 0 155 0x4>, + <0000 0 0 3 &gic 0 156 0x4>, + <0000 0 0 4 &gic 0 157 0x4>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + /* DRAM space 1 - 2 GB DRAM */ + }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; +}; diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index ae84d2e..f77fbbf 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -2,3 +2,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_ARM=y CONFIG_TARGET_LS1043ARDB=y CONFIG_FSL_LAYERSCAPE=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_OF_CONTROL=y
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
Reuse dts files from ls1043a linux kernel. Some parts in dts files may not be needed by U-Boot.
Signed-off-by: Gong Qianyu Qianyu.Gong@freescale.com
V2:
- New Patch.
arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1043a-rdb.dts | 169 +++++++++++++++++++ arch/arm/dts/fsl-ls1043a.dtsi | 346 +++++++++++++++++++++++++++++++++++++++ configs/ls1043ardb_defconfig | 2 + 4 files changed, 518 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ddc6a05..3f3a739 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -83,6 +83,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \ fsl-ls2085a-rdb.dtb +dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a- rdb.dts new file mode 100644 index 0000000..51b5e9f --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -0,0 +1,169 @@ +/*
- Device Tree Include file for Freescale Layerscape-1043A family SoC.
- Copyright (C) 2015, Freescale Semiconductor
- Mingkai Hu Mingkai.hu@freescale.com
- This file is licensed under the terms of the GNU General Public
- License version 2. This program is licensed "as is" without any
- warranty of any kind, whether express or implied.
- */
+/dts-v1/; +/include/ "fsl-ls1043a.dtsi"
+/ {
model = "LS1043A RDB Board";+};
+&i2c0 {
status = "okay";ina220@40{compatible = "ti,ina220";reg = <0x40>;shunt-resistor = <1000>;};adt7461a@4c{compatible = "adt7461a";reg = <0x4c>;};eeprom@56{compatible = "at24,24c512";reg = <0x52>;};eeprom@57{compatible = "at24,24c512";reg = <0x53>;};rtc@68{compatible = "pericom,pt7c4338";reg = <0x68>;};+};
+&ifc {
status = "okay";#address-cells = <2>;#size-cells = <1>;/* NOR, NAND Flashes and FPGA on board */ranges = <0x0 0x0 0x0 0x60000000 0x080000000x2 0x0 0x0 0x7e800000 0x000100000x3 0x0 0x0 0x7fb00000 0x00000100>;nor@0,0 {compatible = "cfi-flash";#address-cells = <1>;#size-cells = <1>;reg = <0x0 0x0 0x8000000>;bank-width = <2>;device-width = <1>;partition@0{/* 1MB for RCW and PBI Image */reg = <0x00000000 0x00100000>;label = "NOR bank0 RCW Image";};partition@100000{/* 1MB for bank0 u-boot Image */reg = <0x00100000 0x00100000>;label = "NOR bank0 U-Boot Image";};partition@200000{/* 1 MB for bank0 u-boot Env */reg = <0x00200000 0x00100000>;label = "NOR bank0 U-Boot Env";};partition@300000{/* 1MB for FMan ucode */reg = <0x00300000 0x00100000>;label = "NOR bank0 FMan ucode";};partition@1100000{/* 40MB for bank0 FIT Image */reg = <0x01100000 0x2800000>;label = "NOR bank0 FIT Image";};partition@4000000{/* 1MB for bank4 RCW and PBI Image */reg = <0x04000000 0x100000>;label = "NOR bank4 RCW Image";};partition@4100000{/* 1MB for bank4 u-boot Image */reg = <0x04100000 0x100000>;label = "NOR bank4 U-Boot Image";};partition@4200000{/* 1 MB for bank4 u-boot Env */reg = <0x04200000 0x100000>;label = "NOR bank4 U-Boot Env";};partition@4300000{/* 1 MB for bank4 FMan ucode */reg = <0x04300000 0x100000>;label = "NOR bank4 FMan ucode";};partition@5100000{/* 40MB for bank4 FIT Image */reg = <0x05100000 0x2800000>;label = "NOR bank4 FIT Image";};};nand@1,0 {compatible = "fsl,ifc-nand";#address-cells = <1>;#size-cells = <1>;reg = <0x2 0x0 0x10000>;partition@0{/* This location must not be altered *//* 1MB for u-boot Bootloader Image */reg = <0x0 0x00100000>;label = "NAND U-Boot Image";read-only;};partition@140000{/* 1MB for DTB Image */reg = <0x00140000 0x002000>;label = "NAND U-Boot Env";};partition@200000{/* 20MB for FIT Image */reg = <0x00200000 0x01400000>;label = "NAND FIT Image";};};
Why are the partitions defined here rather than in an environment variable?
clockgen: clocking@1ee1000{ranges = <0x0 0x0 0x1ee1000 0x1000>;#address-cells = <1>;#size-cells = <1>;sysclk: sysclk {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <100000000>;clock-output-names = "sysclk";};cga_pll1: pll1@800{compatible = "fsl,qoriq-core-pll-2.0";#clock-cells = <1>;reg = <0x800 0x10>;clocks = <&sysclk>;clock-output-names = "cga-pll1", "cga-pll1-div2","cga-pll1-div3", "cga-pll1-div4";};cga_pll2: pll2@820{compatible = "fsl,qoriq-core-pll-2.0";#clock-cells = <1>;reg = <0x820 0x10>;clocks = <&sysclk>;clock-output-names = "cga-pll2", "cga-pll2-div2","cga-pll2-div3", "cga-pll2-div4";};platform_clk: pll@c00{compatible = "fsl,qoriq-core-pll-2.0";#clock-cells = <1>;reg = <0xc00 0x10>;clocks = <&sysclk>;clock-output-names = "platform-clk", "platform-clk-div2";};cluster1_clk: clk0c0@0{compatible = "fsl,qoriq-core-mux-2.0";#clock-cells = <0>;reg = <0x0 0x10>;clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4","pll2cga", "pll2cga-div2", "pll2cga-div4";clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>,<&cga_pll2 0>, <&cga_pll2 1>, <&cga_pll2 2>;clock-output-names = "cluster1-clk";};};
This binding is deprecated. Please don't add any more users of it (especially broken users that lack compatible, reg, etc), and more generally please use the latest version of the Linux ls1043a device tree rather than things that have never been accepted in upstream Linux.
-Scott
-----Original Message----- From: Wood Scott-B07421 Sent: Thursday, November 05, 2015 7:51 AM To: Gong Qianyu-B52263 Cc: u-boot@lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui-B21989; Song Wenbin-B53747; Wood Scott- B07421; Kushwaha Prabhakar-B32579 Subject: Re: [Patch V2 2/4] armv8/ls1043ardb: dts: add dtb support
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
Reuse dts files from ls1043a linux kernel. Some parts in dts files may not be needed by U-Boot.
Signed-off-by: Gong Qianyu Qianyu.Gong@freescale.com
V2:
- New Patch.
arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1043a-rdb.dts | 169 +++++++++++++++++++ arch/arm/dts/fsl-ls1043a.dtsi | 346 +++++++++++++++++++++++++++++++++++++++ configs/ls1043ardb_defconfig | 2 + 4 files changed, 518 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ddc6a05..3f3a739 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -83,6 +83,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \ fsl-ls2085a-rdb.dtb +dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a- rdb.dts new file mode 100644 index 0000000..51b5e9f --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -0,0 +1,169 @@ +/*
- Device Tree Include file for Freescale Layerscape-1043A family SoC.
- Copyright (C) 2015, Freescale Semiconductor
- Mingkai Hu Mingkai.hu@freescale.com
- This file is licensed under the terms of the GNU General Public
- License version 2. This program is licensed "as is" without any
- warranty of any kind, whether express or implied.
- */
+/dts-v1/; +/include/ "fsl-ls1043a.dtsi"
+/ {
model = "LS1043A RDB Board";+};
+&i2c0 {
status = "okay";ina220@40{compatible = "ti,ina220";reg = <0x40>;shunt-resistor = <1000>;};adt7461a@4c{compatible = "adt7461a";reg = <0x4c>;};eeprom@56{compatible = "at24,24c512";reg = <0x52>;};eeprom@57{compatible = "at24,24c512";reg = <0x53>;};rtc@68{compatible = "pericom,pt7c4338";reg = <0x68>;};+};
+&ifc {
status = "okay";#address-cells = <2>;#size-cells = <1>;/* NOR, NAND Flashes and FPGA on board */ranges = <0x0 0x0 0x0 0x60000000 0x080000000x2 0x0 0x0 0x7e800000 0x000100000x3 0x0 0x0 0x7fb00000 0x00000100>;nor@0,0 {compatible = "cfi-flash";#address-cells = <1>;#size-cells = <1>;reg = <0x0 0x0 0x8000000>;bank-width = <2>;device-width = <1>;partition@0{/* 1MB for RCW and PBI Image */reg = <0x00000000 0x00100000>;label = "NOR bank0 RCW Image";};partition@100000{/* 1MB for bank0 u-boot Image */reg = <0x00100000 0x00100000>;label = "NOR bank0 U-Boot Image";};partition@200000{/* 1 MB for bank0 u-boot Env */reg = <0x00200000 0x00100000>;label = "NOR bank0 U-Boot Env";};partition@300000{/* 1MB for FMan ucode */reg = <0x00300000 0x00100000>;label = "NOR bank0 FMan ucode";};partition@1100000{/* 40MB for bank0 FIT Image */reg = <0x01100000 0x2800000>;label = "NOR bank0 FIT Image";};partition@4000000{/* 1MB for bank4 RCW and PBI Image */reg = <0x04000000 0x100000>;label = "NOR bank4 RCW Image";};partition@4100000{/* 1MB for bank4 u-boot Image */reg = <0x04100000 0x100000>;label = "NOR bank4 U-Boot Image";};partition@4200000{/* 1 MB for bank4 u-boot Env */reg = <0x04200000 0x100000>;label = "NOR bank4 U-Boot Env";};partition@4300000{/* 1 MB for bank4 FMan ucode */reg = <0x04300000 0x100000>;label = "NOR bank4 FMan ucode";};partition@5100000{/* 40MB for bank4 FIT Image */reg = <0x05100000 0x2800000>;label = "NOR bank4 FIT Image";};};nand@1,0 {compatible = "fsl,ifc-nand";#address-cells = <1>;#size-cells = <1>;reg = <0x2 0x0 0x10000>;partition@0{/* This location must not be altered *//* 1MB for u-boot Bootloader Image */reg = <0x0 0x00100000>;label = "NAND U-Boot Image";read-only;};partition@140000{/* 1MB for DTB Image */reg = <0x00140000 0x002000>;label = "NAND U-Boot Env";};partition@200000{/* 20MB for FIT Image */reg = <0x00200000 0x01400000>;label = "NAND FIT Image";};};Why are the partitions defined here rather than in an environment variable?
clockgen: clocking@1ee1000{ranges = <0x0 0x0 0x1ee1000 0x1000>;#address-cells = <1>;#size-cells = <1>;sysclk: sysclk {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <100000000>;clock-output-names = "sysclk";};cga_pll1: pll1@800{compatible = "fsl,qoriq-core-pll-2.0";#clock-cells = <1>;reg = <0x800 0x10>;clocks = <&sysclk>;clock-output-names = "cga-pll1", "cga-pll1-div2","cga-pll1-div3", "cga-pll1-div4";};cga_pll2: pll2@820{compatible = "fsl,qoriq-core-pll-2.0";#clock-cells = <1>;reg = <0x820 0x10>;clocks = <&sysclk>;clock-output-names = "cga-pll2", "cga-pll2-div2","cga-pll2-div3", "cga-pll2-div4";};platform_clk: pll@c00{compatible = "fsl,qoriq-core-pll-2.0";#clock-cells = <1>;reg = <0xc00 0x10>;clocks = <&sysclk>;clock-output-names = "platform-clk", "platform-clk-div2";
};cluster1_clk: clk0c0@0{compatible = "fsl,qoriq-core-mux-2.0";#clock-cells = <0>;reg = <0x0 0x10>;clock-names = "pll1cga", "pll1cga-div2","pll1cga-div4",
"pll2cga", "pll2cga-div2","pll2cga-div4";
clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll12>,
<&cga_pll2 0>, <&cga_pll2 1>, <&cga_pll22>;
clock-output-names = "cluster1-clk";};};This binding is deprecated. Please don't add any more users of it (especially broken users that lack compatible, reg, etc), and more generally please use the latest version of the Linux ls1043a device tree rather than things that have never been accepted in upstream Linux.
-Scott
OK. I will update the dts according to the upstreaming ls1043a kernel dts. Thanks for your review.
Regards, Qianyu
From: Shaohui Xie Shaohui.Xie@freescale.com
Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com Signed-off-by: Mingkai Hu Mingkai.Hu@freescale.com Signed-off-by: Hou Zhiqiang B48286@freescale.com Signed-off-by: Gong Qianyu Qianyu.Gong@freescale.com --- V2: - No change.
arch/arm/Kconfig | 9 + arch/arm/include/asm/arch-fsl-layerscape/fdt.h | 3 + board/freescale/ls1043aqds/Kconfig | 15 + board/freescale/ls1043aqds/MAINTAINERS | 9 + board/freescale/ls1043aqds/Makefile | 9 + board/freescale/ls1043aqds/README | 96 ++++ board/freescale/ls1043aqds/ddr.c | 131 ++++++ board/freescale/ls1043aqds/ddr.h | 60 +++ board/freescale/ls1043aqds/eth.c | 517 +++++++++++++++++++++ board/freescale/ls1043aqds/ls1043aqds.c | 333 +++++++++++++ board/freescale/ls1043aqds/ls1043aqds_pbi.cfg | 14 + board/freescale/ls1043aqds/ls1043aqds_qixis.h | 39 ++ board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg | 7 + board/freescale/ls1043aqds/ls1043aqds_rcw_sd.cfg | 8 + configs/ls1043aqds_defconfig | 3 + configs/ls1043aqds_nand_defconfig | 4 + configs/ls1043aqds_nor_ddr3_defconfig | 2 + configs/ls1043aqds_sdcard_defconfig | 4 + include/configs/ls1043aqds.h | 390 ++++++++++++++++ 19 files changed, 1653 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3992f69..49e39fe 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -627,6 +627,14 @@ config TARGET_LS1021ATWR select CPU_V7 select SUPPORT_SPL
+config TARGET_LS1043AQDS + bool "Support ls1043aqds" + select ARM64 + select ARMV8_MULTIENTRY + select SUPPORT_SPL + help + Support for Freescale LS1043AQDS platform. + config TARGET_LS1043ARDB bool "Support ls1043ardb" select ARM64 @@ -751,6 +759,7 @@ source "board/freescale/ls2085aqds/Kconfig" source "board/freescale/ls2085ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" +source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h index 4da73ab..e3989a8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h @@ -11,4 +11,7 @@ void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); void append_mmu_masters(void *blob, const char *smmu_path, const char *master_name, u32 *stream_ids, int count); void fdt_fixup_smmu_pcie(void *blob); +#ifdef CONFIG_SYS_DPAA_FMAN +void fdt_fixup_board_enet(void *fdt); +#endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */ diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig new file mode 100644 index 0000000..7e27f8f --- /dev/null +++ b/board/freescale/ls1043aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1043AQDS + +config SYS_BOARD + default "ls1043aqds" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1043aqds" + +endif diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS new file mode 100644 index 0000000..e952ad9 --- /dev/null +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -0,0 +1,9 @@ +LS1043AQDS BOARD +M: Mingkai Hu Mingkai.Hu@freescale.com +S: Maintained +F: board/freescale/ls1043aqds/ +F: include/configs/ls1043aqds.h +F: configs/ls1043aqds_defconfig +F: configs/ls1043aqds_nor_ddr3_defconfig +F: configs/ls1043aqds_nand_defconfig +F: configs/ls1043aqds_sdcard_defconfig diff --git a/board/freescale/ls1043aqds/Makefile b/board/freescale/ls1043aqds/Makefile new file mode 100644 index 0000000..f727bfd --- /dev/null +++ b/board/freescale/ls1043aqds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ddr.o +obj-y += eth.o +obj-y += ls1043aqds.o diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README new file mode 100644 index 0000000..a890f9a --- /dev/null +++ b/board/freescale/ls1043aqds/README @@ -0,0 +1,96 @@ +Overview +-------- +The LS1043A Development System (QDS) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1043A +LayerScape Architecture processor. The LS1043AQDS provides SW development +platform for the Freescale LS1043A processor series, with a complete +debugging environment. + +LS1043A SoC Overview +-------------------- +The LS1043A integrated multicore processor combines four ARM Cortex-A53 +processor cores with datapath acceleration optimized for L2/3 packet +processing, single pass security offload and robust traffic management +and quality of service. + +The LS1043A SoC includes the following function and features: + - Four 64-bit ARM Cortex-A53 CPUs + - 1 MB unified L2 Cache + - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the + the following functions: + - Packet parsing, classification, and distribution (FMan) + - Queue management for scheduling, packet sequencing, and congestion + management (QMan) + - Hardware buffer management for buffer allocation and de-allocation (BMan) + - Cryptography acceleration (SEC) + - Ethernet interfaces by FMan + - Up to 1 x XFI supporting 10G interface + - Up to 1 x QSGMII + - Up to 4 x SGMII supporting 1000Mbps + - Up to 2 x SGMII supporting 2500Mbps + - Up to 2 x RGMII supporting 1000Mbps + - High-speed peripheral interfaces + - Three PCIe 2.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controllers + - Additional peripheral interfaces + - Three high-speed USB 3.0 controllers with integrated PHY + - Enhanced secure digital host controller (eSDXC/eMMC) + - Quad Serial Peripheral Interface (QSPI) Controller + - Serial peripheral interface (SPI) controller + - Four I2C controllers + - Two DUARTs + - Integrated flash controller supporting NAND and NOR flash + - QorIQ platform's trust architecture 2.1 + + LS1043AQDS board Overview + ----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - QSGMII + - SATA 3.0 + - XFI + - DDR Controller + - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s + -IFC/Local Bus + - One in-socket 128 MB NOR flash 16-bit data bus + - One 512 MB NAND flash with ECC support + - PromJet Port + - FPGA connection + - USB 3.0 + - Three high speed USB 3.0 ports + - First USB 3.0 port configured as Host with Type-A connector + - The other two USB 3.0 ports configured as OTG with micro-AB connector + - SDHC port connects directly to an adapter card slot, featuring: + — Optional clock feedback paths, and optional high-speed voltage translation assistance + — SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC + — eMMC memory devices + - DSPI: Onboard support for three SPI flash memory devices + - 4 I2C controllers + - One SATA onboard connectors + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +Booting Options +--------------- +a) Promjet Boot +b) NOR boot +c) NAND boot +d) SD boot diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c new file mode 100644 index 0000000..705e384 --- /dev/null +++ b/board/freescale/ls1043aqds/ddr.c @@ -0,0 +1,131 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#ifdef CONFIG_FSL_DEEP_SLEEP +#include <fsl_sleep.h> +#endif +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->cpo_override = pbsp->cpo_override; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->cswl_override = DDR_CSWL_CS0; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + return fsl_ddr_sdram_size(); +#else + puts("Initializing DDR....using SPD\n"); + + dram_size = fsl_ddr_sdram(); +#endif + +#ifdef CONFIG_FSL_DEEP_SLEEP + fsl_dp_ddr_restore(); +#endif + + return dram_size; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h new file mode 100644 index 0000000..8adb660 --- /dev/null +++ b/board/freescale/ls1043aqds/ddr.h @@ -0,0 +1,60 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo_override; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,}, + {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, +#else +#error DDR type not defined +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c new file mode 100644 index 0000000..811b83b --- /dev/null +++ b/board/freescale/ls1043aqds/eth.c @@ -0,0 +1,517 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <fsl_dtsec.h> +#include <malloc.h> +#include <asm/arch/fsl_serdes.h> + +#include "../common/qixis.h" +#include "../common/fman.h" +#include "ls1043aqds_qixis.h" + +#define EMI_NONE 0xFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT2 3 +#define EMI1_SLOT3 4 +#define EMI1_SLOT4 5 +#define EMI2 6 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "LS1043AQDS_MDIO_RGMII1", + "LS1043AQDS_MDIO_RGMII2", + "LS1043AQDS_MDIO_SLOT1", + "LS1043AQDS_MDIO_SLOT2", + "LS1043AQDS_MDIO_SLOT3", + "LS1043AQDS_MDIO_SLOT4", + "LS1043AQDS_MDIO_10GC", + "NULL", +}; + +/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ +static u8 lane_to_slot[] = {1, 2, 3, 4}; + +static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name; + + if (muxval > EMI2) + return NULL; + + name = ls1043aqds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct ls1043aqds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void ls1043aqds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + + if (muxval < 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + ls1043aqds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + ls1043aqds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, + regnum, value); +} + +static int ls1043aqds_mdio_reset(struct mii_dev *bus) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) +{ + struct ls1043aqds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate ls1043aqds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate ls1043aqds private data\n"); + free(bus); + return -1; + } + + bus->read = ls1043aqds_mdio_read; + bus->write = ls1043aqds_mdio_write; + bus->reset = ls1043aqds_mdio_reset; + sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + struct fixed_link f_link; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + if (port == FM1_DTSEC9) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s1_p1"); + } else if (port == FM1_DTSEC2) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s2_p1"); + } else if (port == FM1_DTSEC5) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s3_p1"); + } else if (port == FM1_DTSEC6) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s4_p1"); + } + } else if (fm_info_get_enet_if(port) == + PHY_INTERFACE_MODE_SGMII_2500) { + /* 2.5G SGMII interface */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 1000; + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for 2.5G SGMII */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "sgmii-2500"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { + switch (mdio_mux[port]) { + case EMI1_SLOT1: + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p1"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p2"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p3"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p4"); + break; + default: + break; + } + break; + case EMI1_SLOT2: + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p1"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p2"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p3"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p4"); + break; + default: + break; + } + break; + default: + break; + } + fdt_delprop(fdt, offset, "phy-connection-type"); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "qsgmii"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && + port == FM1_10GEC1) { + /* XFI interface */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for XFI */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + switch (mdio_mux[i]) { + case EMI1_SLOT1: + fdt_status_okay_by_alias(fdt, "emi1_slot1"); + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + case EMI1_SLOT4: + fdt_status_okay_by_alias(fdt, "emi1_slot4"); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_XGMII: + break; + default: + break; + } + } +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x1555: + /* XFI on lane A, MAC 9*/ + fm_info_set_phy_address(FM1_10GEC1, 9); + break; + case 0x2555: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + break; + case 0x4555: + case 0x4558: + /* QSGMII on lane A, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S1); + break; + case 0x1355: + /* XFI on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_10GEC1, 9); + /* SGMII on lane B, MAC 2*/ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x2355: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* SGMII on lane B, MAC 2*/ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x3335: + /* SGMII on lane C, MAC 5 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + case 0x3355: + case 0x3358: + /* SGMII on lane B, MAC 2 */ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + case 0x3555: + case 0x3558: + /* SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x1455: + /* XFI on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_10GEC1, 9); + /* QSGMII on lane B, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S2); + break; + case 0x2455: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* QSGMII on lane B, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S2); + break; + case 0x2255: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* 2.5G SGMII on lane B, MAC 2 */ + fm_info_set_phy_address(FM1_DTSEC2, 2); + break; + case 0x3333: + /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC9, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, + SGMII_CARD_PORT1_PHY_ADDR); + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", + srds_s1); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_SGMII) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_2500_FM1_DTSEC1 + idx); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_A); + } + + if (lane < 0) + break; + + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII1; + else if (i == FM1_DTSEC4) + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + idx = i - FM1_10GEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC9 + idx); + if (lane < 0) + break; + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c new file mode 100644 index 0000000..6866882 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -0,0 +1,333 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/fdt.h> +#include <asm/arch/soc.h> +#include <ahci.h> +#include <hwconfig.h> +#include <mmc.h> +#include <scsi.h> +#include <fm_eth.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_ifc.h> +#include <spl.h> + +#include "../common/qixis.h" +#include "ls1043aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +enum { + MUX_TYPE_GPIO, +}; + +/* LS1043AQDS serdes mux */ +#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */ +#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */ +#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */ +#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */ +#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */ +#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ +#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ +#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ + +int checkboard(void) +{ + char buf[64]; +#ifndef CONFIG_SD_BOOT + u8 sw; +#endif + + puts("Board: LS1043AQDS\n"); + +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0x15) + printf("IFCCard\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + + printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", + QIXIS_READ(id), QIXIS_READ(arch)); + + printf("FPGA: v%d (%s), build %d\n", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + return 0; +} + +bool if_board_diff_clk(void) +{ + u8 diff_conf = QIXIS_READ(brdcfg[11]); + + return diff_conf & 0x40; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0f) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + if (if_board_diff_clk()) + return get_board_sys_clk(); + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + + return 66666666; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +int dram_init(void) +{ + /* + * When resuming from deep sleep, the I2C channel may not be + * in the default channel. So, switch to the default channel + * before accessing DDR SPD. + */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + gd->ram_size = initdram(0); + + return 0; +} + +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + +void board_retimer_init(void) +{ + u8 reg; + + /* Retimer is connected to I2C1_CH7_CH5 */ + reg = I2C_MUX_CH7; + i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); + reg = I2C_MUX_CH5; + i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); + + /* Access to Control/Shared register */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Read device revision and ID */ + i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Reset Channel Registers */ + i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); + reg |= 0x4; + i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); + reg |= 0x24; + i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); + + /* Select VCO Divider to full rate (000) */ + i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + reg &= 0x8f; + i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + + /* Selects active PFD MUX Input as Re-timed Data (001) */ + i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + reg &= 0x3f; + reg |= 0x20; + i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); + reg = 0xb2; + i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); + reg = 0x90; + i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); + reg = 0xb3; + i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); + reg = 0xcd; + i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifdef CONFIG_FSL_DEEP_SLEEP +/* determine if it is a warm boot */ +bool is_warm_boot(void) +{ +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} +#endif + +int config_board_mux(int ctrl_type) +{ + u8 reg14; + + reg14 = QIXIS_READ(brdcfg[14]); + + switch (ctrl_type) { + case MUX_TYPE_GPIO: + reg14 = (reg14 & (~0x30)) | 0x20; + break; + default: + puts("Unsupported mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[14], reg14); + + return 0; +} + +int config_serdes_mux(void) +{ + return 0; +} + + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + if (hwconfig("gpio")) + config_board_mux(MUX_TYPE_GPIO); + + return 0; +} +#endif + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *) + CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to enable barrier + * transaction */ + out_le32(&cci->ctrl_ord, + CCI400_CTRLORD_EN_BARRIER); + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + board_retimer_init(); + +#ifdef CONFIG_SYS_FSL_SERDES + config_serdes_mux(); +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + return 0; +} +#endif + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg b/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg new file mode 100644 index 0000000..f072274 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg @@ -0,0 +1,14 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Alt base register +09570158 00001000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#flush PBI data +096100c0 000fffff diff --git a/board/freescale/ls1043aqds/ls1043aqds_qixis.h b/board/freescale/ls1043aqds/ls1043aqds_qixis.h new file mode 100644 index 0000000..8783be8 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_qixis.h @@ -0,0 +1,39 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043AQDS_QIXIS_H__ +#define __LS1043AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1043AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg new file mode 100644 index 0000000..935ffc0 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +0810000f 0c000000 00000000 00000000 +14550002 80004012 e0106000 61002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd.cfg new file mode 100644 index 0000000..17a5dd0 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable IFC; disable QSPI +0810000f 0c000000 00000000 00000000 +14550002 80004012 60040000 61002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig new file mode 100644 index 0000000..ee5bea2 --- /dev/null +++ b/configs/ls1043aqds_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig new file mode 100644 index 0000000..377ca74 --- /dev/null +++ b/configs/ls1043aqds_nand_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig new file mode 100644 index 0000000..7b1951f --- /dev/null +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y diff --git a/configs/ls1043aqds_sdcard_defconfig b/configs/ls1043aqds_sdcard_defconfig new file mode 100644 index 0000000..0fdb959 --- /dev/null +++ b/configs/ls1043aqds_sdcard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h new file mode 100644 index 0000000..a73d661 --- /dev/null +++ b/include/configs/ls1043aqds.h @@ -0,0 +1,390 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043AQDS_H__ +#define __LS1043AQDS_H__ + +#include "ls1043a_common.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x82000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x60100000 +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#define CONFIG_SYS_DDR_RAW_TIMING +#endif + +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_HAS_SERDES + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHYLIB_10G +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +/* PHY address on QSGMII riser card on slot 1 */ +#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 +#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 +#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 +#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 +/* PHY address on QSGMII riser card on slot 2 */ +#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 +#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 +#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA +#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB +#endif + +#define CONFIG_SYS_QE_FW_ADDR 0x60600000 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd.cfg +#endif + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0xe) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ + CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) +#endif + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x44 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* + * QIXIS Timing parameters for IFC GPCM + */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ + FTIM0_GPCM_TEADC(0x20) | \ + FTIM0_GPCM_TEAHC(0x10)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0xf0)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC +#define I2C_MUX_CH5 0xD +#define I2C_MUX_CH7 0xF + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_INA220 +/* The lowest and highest voltage allowed for LS1043AQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +#define CONFIG_SYS_FSL_ERRATUM_A008402 + +#define CONFIG_CMD_MII +#define CONFIG_CMDLINE_TAG + +#define CONFIG_MISC_INIT_R + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (30 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_CMD_BOOTZ + +#endif /* __LS1043AQDS_H__ */
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h index 4da73ab..e3989a8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h @@ -11,4 +11,7 @@ void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); void append_mmu_masters(void *blob, const char *smmu_path, const char *master_name, u32 *stream_ids, int count); void fdt_fixup_smmu_pcie(void *blob); +#ifdef CONFIG_SYS_DPAA_FMAN +void fdt_fixup_board_enet(void *fdt); +#endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
Why are you ifdeffing a prototype?
-Scott
Reuse the dts files from ls1043a linux kernel.
Signed-off-by: Gong Qianyu Qianyu.Gong@freescale.com --- V2: - New Patch.
arch/arm/dts/Makefile | 3 +- arch/arm/dts/fsl-ls1043a-qds.dts | 204 +++++++++++++++++++++++++++++++++++++++ configs/ls1043aqds_defconfig | 2 + 3 files changed, 208 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3f3a739..2aa9a00 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -83,7 +83,8 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \ fsl-ls2085a-rdb.dtb -dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-rdb.dtb +dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \ + fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-qds.dts new file mode 100644 index 0000000..4bf9b1b --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-qds.dts @@ -0,0 +1,204 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * Mingkai Hu Mingkai.hu@freescale.com + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "fsl-ls1043a.dtsi" + +/ { + model = "LS1043A QDS Board"; +}; + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "philips,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + /* IRQ10_B */ + interrupts = <0 150 0x4>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "at24,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "at24,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + /* 1MB for RCW and PBI Image */ + reg = <0x00000000 0x00100000>; + label = "NOR bank0 RCW Image"; + }; + + partition@100000 { + /* 1MB for bank0 u-boot Image */ + reg = <0x00100000 0x00100000>; + label = "NOR bank0 U-Boot Image"; + }; + + partition@200000 { + /* 1 MB for bank0 u-boot Env */ + reg = <0x00200000 0x00100000>; + label = "NOR bank0 U-Boot Env"; + }; + + partition@300000 { + /* 1MB for FMan ucode */ + reg = <0x00300000 0x00100000>; + label = "NOR bank0 FMan ucode"; + }; + + partition@1100000 { + /* 40MB for bank0 FIT Image */ + reg = <0x01100000 0x2800000>; + label = "NOR bank0 FIT Image"; + }; + + partition@4000000 { + /* 1MB for bank4 RCW and PBI Image */ + reg = <0x04000000 0x100000>; + label = "NOR bank4 RCW Image"; + }; + + partition@4100000 { + /* 1MB for bank4 u-boot Image */ + reg = <0x04100000 0x100000>; + label = "NOR bank4 U-Boot Image"; + }; + + partition@4200000 { + /* 1 MB for bank4 u-boot Env */ + reg = <0x04200000 0x100000>; + label = "NOR bank4 U-Boot Env"; + }; + + partition@4300000 { + /* 1 MB for bank4 FMan ucode */ + reg = <0x04300000 0x100000>; + label = "NOR bank4 FMan ucode"; + }; + + partition@5100000 { + /* 40MB for bank4 FIT Image */ + reg = <0x05100000 0x2800000>; + label = "NOR bank4 FIT Image"; + }; + }; + + nand@2,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x0 0x10000>; + + partition@0 { + /* This location must not be altered */ + /* 1MB for u-boot Bootloader Image */ + reg = <0x0 0x00100000>; + label = "NAND U-Boot Image"; + read-only; + }; + + partition@140000 { + /* 1MB for DTB Image */ + reg = <0x00140000 0x002000>; + label = "NAND U-Boot Env"; + }; + + partition@200000 { + /* 20MB for FIT Image */ + reg = <0x00200000 0x01400000>; + label = "NAND FIT Image"; + }; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0x3 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 3 0 0x100>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index ee5bea2..cf163d6 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -1,3 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds" +CONFIG_OF_CONTROL=y
participants (5)
-
Bin Meng -
Gong Q.Y. -
Gong Qianyu
-
Scott Wood -
Simon Glass