Only a certain set of PLLM/D values are recommended to configure the DDR at the required speeds for a given clock input frequency. Updating these values as specified in Data Sheet[1] Table 5-18

[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/ks2_evm/board_k2g.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 8f16845..40edbaa 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -66,7 +66,7 @@ static struct pll_init_data tetris_pll_config[NUM_SPDS] = {

static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; -static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10}; +static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16};

struct pll_init_data *get_pll_init_data(int pll) {