[PATCH] arm: dts: rmobile: r8a774a1: Synchronize DTs with Linux 5.10
DTS files apart from r8a774a1-hihope-rzg2m-u-boot.dts and r8a774a1-u-boot.dtsi have been imported from linux 5.10 commit 2c85ebc57b3e1817 ("Linux 5.10").
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com --- arch/arm/dts/hihope-common.dtsi | 377 ++++++++++++++++++ arch/arm/dts/hihope-rev4.dtsi | 124 ++++++ arch/arm/dts/hihope-rzg2-ex.dtsi | 92 +++++ arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts | 21 + arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts | 27 ++ arch/arm/dts/r8a774a1-hihope-rzg2m.dts | 37 ++ arch/arm/dts/r8a774a1-u-boot.dtsi | 55 +++ 7 files changed, 733 insertions(+) create mode 100644 arch/arm/dts/hihope-common.dtsi create mode 100644 arch/arm/dts/hihope-rev4.dtsi create mode 100644 arch/arm/dts/hihope-rzg2-ex.dtsi create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m.dts create mode 100644 arch/arm/dts/r8a774a1-u-boot.dtsi
diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi new file mode 100644 index 0000000000..b1eb6a0802 --- /dev/null +++ b/arch/arm/dts/hihope-common.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and + * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &scif2; + serial1 = &hscif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + hdmi0-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con: endpoint { + remote-endpoint = <&rcar_dw_hdmi0_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; + + led2 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; + + led3 { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + led4 { + gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sound_card: sound { + compatible = "audio-graph-card"; + + label = "rcar-sound"; + + dais = <&rsnd_port>; + }; + + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + x302_clk: x302-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33000000>; + }; + + x304_clk: x304-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&du { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&gpio6 { + usb1-reset { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-low; + line-name = "usb1-reset"; + }; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint>; + }; + }; + }; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + versaclock5: clock-generator@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x304_clk>; + clock-names = "xin"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; + function = "sdhi3"; + power-source = <1800>; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + mux { + groups = "usb1"; + function = "usb1"; + }; + + ovc { + pins = "GP_6_27"; + bias-pull-up; + }; + }; + + usb30_pins: usb30 { + groups = "usb30"; + function = "usb30"; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi2 { + status = "okay"; + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&usb_extal_clk { + clock-frequency = <50000000>; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&vbus0_usb2>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb3_peri0 { + phys = <&usb3_phy0>; + phy-names = "usb"; + + companion = <&xhci0>; + + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3s0_clk { + clock-frequency = <100000000>; +}; + +&xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/dts/hihope-rev4.dtsi b/arch/arm/dts/hihope-rev4.dtsi new file mode 100644 index 0000000000..30e929997a --- /dev/null +++ b/arch/arm/dts/hihope-rev4.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and + * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include "hihope-common.dtsi" + +/ { + audio_clkout: audio-clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2000/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + wlan_en_reg: regulator-wlan_en { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <70000>; + + gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + x1801_clk: x1801-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&hscif0 { + bluetooth { + compatible = "ti,wl1837-st"; + enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + status = "okay"; + + cs2000: clk_multiplier@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x1801_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&pfc { + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a"; + function = "audio_clk"; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <12288000 11289600>; + + /* update <audio_clk_b> to <cs2000> */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, + <&cpg CPG_CORE CPG_AUDIO_CLK_I>; + + rsnd_port: port { + rsnd_endpoint: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint>; + frame-master = <&rsnd_endpoint>; + + playback = <&ssi2>; + }; + }; +}; diff --git a/arch/arm/dts/hihope-rzg2-ex.dtsi b/arch/arm/dts/hihope-rzg2-ex.dtsi new file mode 100644 index 0000000000..7745012d4b --- /dev/null +++ b/arch/arm/dts/hihope-rzg2-ex.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/ { + aliases { + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pciec0 { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + can0_pins: can0 { + groups = "can0_data_a"; + function = "can0"; + }; + + can1_pins: can1 { + groups = "can1_data"; + function = "can1"; + }; + + pwm0_pins: pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts new file mode 100644 index 0000000000..f0e4a1f25d --- /dev/null +++ b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to + * sub board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include "r8a774a1-hihope-rzg2m.dts" +#include "hihope-rzg2-ex.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2M with sub board"; + compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", + "renesas,r8a774a1"; +}; + +/* SW43 should be OFF, if in ON state SATA port will be activated */ +&pciec1 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts new file mode 100644 index 0000000000..b735e97221 --- /dev/null +++ b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Hihope RZ/G2M board + * + * Copyright (C) 2021 Renesas Electronics Corporation + */ + +#include "r8a774a1-hihope-rzg2m-ex.dts" +#include "r8a774a1-u-boot.dtsi" + +&gpio3 { + bt_reg_on{ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "bt-reg-on"; + }; +}; + +&gpio4 { + wlan_reg_on{ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "wlan-reg-on"; + }; +}; diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m.dts new file mode 100644 index 0000000000..a574c85a50 --- /dev/null +++ b/arch/arm/dts/r8a774a1-hihope-rzg2m.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774a1.dtsi" +#include "hihope-rev4.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2M main board based on r8a774a1"; + compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", + "dclkin.0", "dclkin.1", "dclkin.2"; +}; diff --git a/arch/arm/dts/r8a774a1-u-boot.dtsi b/arch/arm/dts/r8a774a1-u-boot.dtsi new file mode 100644 index 0000000000..f826c41c3b --- /dev/null +++ b/arch/arm/dts/r8a774a1-u-boot.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot on RZ/G2 R8A774A1 SoC + * + * Copyright (C) 2021 Renesas Electronics Corporation + */ + +#include "r8a779x-u-boot.dtsi" + +&extalr_clk { + u-boot,dm-pre-reloc; +}; + +/delete-node/ &audma0; +/delete-node/ &audma1; +/delete-node/ &can0; +/delete-node/ &can1; +/delete-node/ &canfd; +/delete-node/ &csi20; +/delete-node/ &csi40; +/delete-node/ &du; +/delete-node/ &fcpf0; +/delete-node/ &fcpvb0; +/delete-node/ &fcpvd0; +/delete-node/ &fcpvd1; +/delete-node/ &fcpvd2; +/delete-node/ &fcpvi0; +/delete-node/ &hdmi0; +/delete-node/ &lvds0; +/delete-node/ &rcar_sound; +/delete-node/ &sdhi2; +/delete-node/ &sound_card; +/delete-node/ &vin0; +/delete-node/ &vin1; +/delete-node/ &vin2; +/delete-node/ &vin3; +/delete-node/ &vin4; +/delete-node/ &vin5; +/delete-node/ &vin6; +/delete-node/ &vin7; +/delete-node/ &vspb; +/delete-node/ &vspd0; +/delete-node/ &vspd1; +/delete-node/ &vspd2; +/delete-node/ &vspi0; + +/ { + /delete-node/ hdmi0-out; +}; + +/ { + soc { + /delete-node/ fdp1@fe940000; + }; +};
DTS files apart from r8a774b1-hihope-rzg2n-u-boot.dts and r8a774b1-u-boot.dtsi have been imported from linux 5.10 commit 2c85ebc57b3e1817b6c ("Linux 5.10").
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com --- arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts | 21 ++++++++ arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts | 27 ++++++++++ arch/arm/dts/r8a774b1-hihope-rzg2n.dts | 41 ++++++++++++++ arch/arm/dts/r8a774b1-u-boot.dtsi | 53 +++++++++++++++++++ 4 files changed, 142 insertions(+) create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts new file mode 100644 index 0000000000..58812b41ac --- /dev/null +++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to + * sub board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include "r8a774b1-hihope-rzg2n.dts" +#include "hihope-rzg2-ex.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2N with sub board"; + compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n", + "renesas,r8a774b1"; +}; + +/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */ +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts new file mode 100644 index 0000000000..0bdc6909bf --- /dev/null +++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include "r8a774b1-hihope-rzg2n-ex.dts" +#include "r8a774b1-u-boot.dtsi" + +&gpio3 { + bt_reg_on{ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "bt-reg-on"; + }; +}; + +&gpio4 { + wlan_reg_on{ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "wlan-reg-on"; + }; +}; diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n.dts b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts new file mode 100644 index 0000000000..b90790a95b --- /dev/null +++ b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0 + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774b1.dtsi" +#include "hihope-rev4.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2N main board based on r8a774b1"; + compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +&sdhi3 { + mmc-hs400-1_8v; +}; diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi b/arch/arm/dts/r8a774b1-u-boot.dtsi new file mode 100644 index 0000000000..6fab78e776 --- /dev/null +++ b/arch/arm/dts/r8a774b1-u-boot.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot on RZ/G2 R8A774B1 SoC + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include "r8a779x-u-boot.dtsi" + +&extalr_clk { + u-boot,dm-pre-reloc; +}; + +/delete-node/ &audma0; +/delete-node/ &audma1; +/delete-node/ &can0; +/delete-node/ &can1; +/delete-node/ &canfd; +/delete-node/ &csi20; +/delete-node/ &csi40; +/delete-node/ &du; +/delete-node/ &fcpf0; +/delete-node/ &fcpvb0; +/delete-node/ &fcpvd0; +/delete-node/ &fcpvd1; +/delete-node/ &fcpvi0; +/delete-node/ &hdmi0; +/delete-node/ &lvds0; +/delete-node/ &rcar_sound; +/delete-node/ &sdhi2; +/delete-node/ &sound_card; +/delete-node/ &vin0; +/delete-node/ &vin1; +/delete-node/ &vin2; +/delete-node/ &vin3; +/delete-node/ &vin4; +/delete-node/ &vin5; +/delete-node/ &vin6; +/delete-node/ &vin7; +/delete-node/ &vspb; +/delete-node/ &vspd0; +/delete-node/ &vspd1; +/delete-node/ &vspi0; + +/ { + /delete-node/ hdmi0-out; +}; + +/ { + soc { + /delete-node/ fdp1@fe940000; + }; +};
DTS files apart from r8a774e1-hihope-rzg2h-u-boot.dts and r8a774e1-u-boot.dtsi have been imported from linux 5.10 commit 2c85ebc57b3e1817b6 ("Linux 5.10").
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com --- arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts | 20 + arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts | 27 + arch/arm/dts/r8a774e1-hihope-rzg2h.dts | 41 + arch/arm/dts/r8a774e1-u-boot.dtsi | 59 + arch/arm/dts/r8a774e1.dtsi | 1342 ++++++++++++++++- 5 files changed, 1461 insertions(+), 28 deletions(-) create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts new file mode 100644 index 0000000000..a0f98fd62c --- /dev/null +++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H sub board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include "r8a774e1-hihope-rzg2h.dts" +#include "hihope-rzg2-ex.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2H with sub board"; + compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h", + "renesas,r8a774e1"; +}; + +/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */ +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts new file mode 100644 index 0000000000..d7afb55d8b --- /dev/null +++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include "r8a774e1-hihope-rzg2h-ex.dts" +#include "r8a774e1-u-boot.dtsi" + +&gpio3 { + bt_reg_on{ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "bt-reg-on"; + }; +}; + +&gpio4 { + wlan_reg_on{ + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "wlan-reg-on"; + }; +}; diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts new file mode 100644 index 0000000000..e3a78c9c58 --- /dev/null +++ b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H main board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774e1.dtsi" +#include "hihope-rev4.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2H main board based on r8a774e1"; + compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x80000000>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +&sdhi3 { + mmc-hs400-1_8v; +}; diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi b/arch/arm/dts/r8a774e1-u-boot.dtsi new file mode 100644 index 0000000000..5fe432c3f7 --- /dev/null +++ b/arch/arm/dts/r8a774e1-u-boot.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include "r8a779x-u-boot.dtsi" + +&extalr_clk { + u-boot,dm-pre-reloc; +}; + +/delete-node/ &audma0; +/delete-node/ &audma1; +/delete-node/ &can0; +/delete-node/ &can1; +/delete-node/ &canfd; +/delete-node/ &csi20; +/delete-node/ &csi40; +/delete-node/ &du; +/delete-node/ &fcpf0; +/delete-node/ &fcpf1; +/delete-node/ &fcpvb0; +/delete-node/ &fcpvb1; +/delete-node/ &fcpvd0; +/delete-node/ &fcpvd1; +/delete-node/ &fcpvi0; +/delete-node/ &fcpvi1; +/delete-node/ &hdmi0; +/delete-node/ &lvds0; +/delete-node/ &rcar_sound; +/delete-node/ &sdhi2; +/delete-node/ &sound_card; +/delete-node/ &vin0; +/delete-node/ &vin1; +/delete-node/ &vin2; +/delete-node/ &vin3; +/delete-node/ &vin4; +/delete-node/ &vin5; +/delete-node/ &vin6; +/delete-node/ &vin7; +/delete-node/ &vspbc; +/delete-node/ &vspbd; +/delete-node/ &vspd0; +/delete-node/ &vspd1; +/delete-node/ &vspi0; +/delete-node/ &vspi1; + +/ { + /delete-node/ hdmi0-out; +}; + +/ { + soc { + /delete-node/ fdp1@fe940000; + /delete-node/ fdp1@fe944000; + }; +}; diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi index 0f86cfd524..213f186092 100644 --- a/arch/arm/dts/r8a774e1.dtsi +++ b/arch/arm/dts/r8a774e1.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for the r8a774e1 SoC * - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2021 Renesas Electronics Corp. */
#include <dt-bindings/interrupt-controller/irq.h> @@ -28,6 +28,12 @@ clock-frequency = <0>; };
+ audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; @@ -127,6 +133,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; @@ -141,6 +148,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -154,6 +162,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -167,6 +176,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -180,6 +190,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; #cooling-cells = <2>; dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; @@ -194,6 +205,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -206,6 +218,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -218,6 +231,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -236,6 +250,28 @@ cache-unified; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + + CPU_SLEEP_1: cpu-sleep-1 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <700>; + exit-latency-us = <700>; + min-residency-us = <5000>; + }; + }; };
extal_clk: extal { @@ -427,7 +463,7 @@ resets = <&cpg 905>; };
- pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774e1"; reg = <0 0xe6060000 0 0x50c>; }; @@ -838,18 +874,61 @@ };
hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a774e1", + "renesas,rcar-gen3-usbhs"; reg = <0 0xe6590000 0 0x200>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a774e1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + };
- /* placeholder */ + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a774e1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; };
usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a774e1-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; #phy-cells = <0>; status = "disabled"; - - /* placeholder */ };
dmac0: dma-controller@e6700000 { @@ -1203,11 +1282,73 @@ };
pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; #pwm-cells = <2>; status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + };
- /* placeholder */ + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; };
scif0: serial@e6e60000 { @@ -1372,7 +1513,260 @@ status = "disabled"; };
+ vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin7>; + }; + }; + }; + }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ @@ -1380,71 +1774,569 @@ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774E1_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; status = "disabled";
- /* placeholder */ + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + };
rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; + }; ssi2: ssi-2 { - /* placeholder */ + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; }; }; };
+ audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, + <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, + <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, + <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, + <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, + <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, + <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, + <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, + <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, + <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, + <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, + <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, + <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, + <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, + <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; + }; + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a774e1", + "renesas,rcar-gen3-xhci"; reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; status = "disabled"; - - /* placeholder */ };
usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a774e1-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; reg = <0 0xee020000 0 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; status = "disabled"; - - /* placeholder */ };
ohci0: usb@ee080000 { + compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; status = "disabled"; - - /* placeholder */ };
ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; reg = <0 0xee0a0000 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; status = "disabled"; - - /* placeholder */ };
ehci0: usb@ee080100 { + compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; status = "disabled"; - - /* placeholder */ };
ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; reg = <0 0xee0a0100 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; status = "disabled"; - - /* placeholder */ };
usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a774e1", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <1>; status = "disabled"; - - /* placeholder */ };
usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a774e1", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <1>; status = "disabled"; - - /* placeholder */ };
sdhi0: mmc@ee100000 { @@ -1499,6 +2391,18 @@ status = "disabled"; };
+ sata: sata@ee300000 { + compatible = "renesas,sata-r8a774e1", + "renesas,rcar-gen3-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 815>; + iommus = <&ipmmu_hc 2>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -1517,53 +2421,435 @@ };
pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774e1", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; #address-cells = <3>; #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a774e1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, + <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, + <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774e1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@ee800000 { + compatible = "renesas,r8a774e1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; status = "disabled"; + }; + + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 624>; + + renesas,fcp = <&fcpvb1>; + }; + + vspbd: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + vspi1: vsp@fe9b0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9b0000 0 0x8000>; + interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 630>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 630>; + + renesas,fcp = <&fcpvi1>; + };
- /* placeholder */ + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; + }; + + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 615>; + }; + + fcpf1: fcp@fe951000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe951000 0 0x200>; + clocks = <&cpg CPG_MOD 614>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 614>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 607>; + }; + + fcpvb1: fcp@fe92f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 606>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 611>; + }; + + fcpvi1: fcp@fe9bf000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9bf000 0 0x200>; + clocks = <&cpg CPG_MOD 610>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 610>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 602>; + }; + + csi20: csi2@fea80000 { + compatible = "renesas,r8a774e1-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a774e1-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + }; + }; };
hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a774e1-hdmi", + "renesas,rcar-gen3-hdmi"; reg = <0 0xfead0000 0 0x10000>; + interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A774E1_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 729>; status = "disabled";
- /* placeholder */ - ports { #address-cells = <1>; #size-cells = <0>;
port@0 { reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; }; port@1 { reg = <1>; }; port@2 { + /* HDMI sound */ reg = <2>; }; }; };
du: display@feb00000 { + compatible = "renesas,du-r8a774e1"; reg = <0 0xfeb00000 0 0x80000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.3"; status = "disabled";
- /* placeholder */ + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; + ports { #address-cells = <1>; #size-cells = <0>;
port@0 { reg = <0>; + du_out_rgb: endpoint { + }; }; port@1 { reg = <1>; + du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; + }; }; port@2 { reg = <2>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a774e1-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; }; }; };
participants (1)
-
Biju Das