[U-Boot] rk3399 sdram data training read gate is looping forever

Hi,
I'm trying to bring-up rk3399 SBC with 1GB DDR3 933MHZ capable, and observed an sdram_init issue where data_training_rg transfer is looping forever. The denali_pi[80], and denali_pi[74] seems to be proper values while setting up the particular ranks.
Can anyone encounter similar issue? let me know for any inputs.
Log:
U-Boot SPL board init uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'root_driver' - not found syscon: rockchip_rk3399_pmugrf 4 syscon: rockchip_rk3399_pmusgrf 5 syscon: rockchip_rk3399_cic 6 syscon: rockchip_rk3399_grf 1 uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_pmugrf' - -1 -1 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 -1 'rockchip_rk3399_grf' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - found uclass_find_device_by_seq: 0 1 - -1 -1 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 -1 'rockchip_rk3399_grf' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_pinctrl' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - found uclass_find_device_by_seq: 0 1 - -1 -1 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 1 'rockchip_rk3399_grf' - found uclass_find_device_by_seq: 0 2 - -1 -1 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 1 'rockchip_rk3399_grf' - not found rk3399_pinctrl_probe: grf=ff770000, pmugrf=ff320000 uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_dmc' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 2 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - found uclass_find_device_by_seq: 0 1 - -1 2 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 1 'rockchip_rk3399_grf' - found uclass_find_device_by_seq: 0 2 - -1 2 'rockchip_rk3399_pmugrf' - found uclass_find_device_by_seq: 0 3 - -1 2 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 1 'rockchip_rk3399_grf' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_cru' - -1 -1 'rockchip_rk3399_pmucru' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_cru' - -1 0 'rockchip_rk3399_pmucru' - found uclass_find_device_by_seq: 0 1 - -1 -1 'rockchip_rk3399_cru' - -1 0 'rockchip_rk3399_pmucru' - not found PLL at ff760000: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz PLL at ff760020: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz PLL at ff760080: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz PLL at ff760060: fbdiv=64, refdiv=1, postdiv1=2, postdiv2=2, vco=1536000 khz, output=384000 khz con reg ffa80000 ffa80800 ffa82000 ffa84000 ffa88000 ffa88800 ffa8a000 ffa8c000 cru ff760000, cic ff620000, grf ff320000, sgrf ff330000, pmucru ff750000 clk_set_rate(clk=ff8ee498, rate=933000000) PLL at ff760040: fbdiv=116, refdiv=1, postdiv1=3, postdiv2=1, vco=2784000 khz, output=928000 khz Starting SDRAM initialization... freq 933, channnels 2 DRAM (pctl_cfg): phy locked after 1 ms pctl_cfg done! call data_training call data_training_wl data_training_wl while(1) data_training_wl while(1) call data_training_rg data_training_rg while(1) data_training_rg while(1) data_training_rg while(1) data_training_rg while(1) data_training_rg while(1) data_training_rg while(1) data_training_rg while(1) data_training_rg while(1)

Hi Jagan,
On Sat, 5 Jan 2019 at 12:58, Jagan Teki jagan@amarulasolutions.com wrote:
Hi,
I'm trying to bring-up rk3399 SBC with 1GB DDR3 933MHZ capable, and observed an sdram_init issue where data_training_rg transfer is looping forever. The denali_pi[80], and denali_pi[74] seems to be proper values while setting up the particular ranks.
Can anyone encounter similar issue? let me know for any inputs.
Log:
I have not seen this so far.
Regards, Simon

On Tue, Jan 8, 2019 at 6:08 AM Simon Glass sjg@chromium.org wrote:
Hi Jagan,
On Sat, 5 Jan 2019 at 12:58, Jagan Teki jagan@amarulasolutions.com wrote:
Hi,
I'm trying to bring-up rk3399 SBC with 1GB DDR3 933MHZ capable, and observed an sdram_init issue where data_training_rg transfer is looping forever. The denali_pi[80], and denali_pi[74] seems to be proper values while setting up the particular ranks.
Can anyone encounter similar issue? let me know for any inputs.
Log:
I have not seen this so far.
In fact I have reused existing rk3399-sdram-ddr3-1866.dtsi (which seems to be 2GB) since this SBC using similar frequency. The only difference between other supported sdram dtsi's from Mainline would be that it is single channel and 1GB size.
For single channel I have updated the num_channel as index c46c1996be..85e99d81c2 100644 --- a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi +++ b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi @@ -37,7 +37,7 @@ 0x00000000 933 3 - 2 + 1 9 1 0x00000600
But not clear for any changes wrt to 1GB vs 2GB? Any help where to debug please let me know.
participants (2)
-
Jagan Teki
-
Simon Glass