[U-Boot] socfpga: socdk and socrates share SPI flash config, move it to shared place
Both Socrates and SocDK share same QSPI and SPI flash configuration. Move the common configuration into common place.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi index 234a901..c40ade5 100644 --- a/arch/arm/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -37,4 +37,30 @@ cpu1-start-addr = <0xffd080c4>; }; }; + + aliases { + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; + }; +}; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; }; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index ea30483..2a64b3c 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -14,12 +14,6 @@ bootargs = "console=ttyS0,115200"; };
- aliases { - spi0 = "/spi@ff705000"; /* QSPI */ - spi1 = "/spi@fff00000"; - spi2 = "/spi@fff01000"; - }; - memory { name = "memory"; device_type = "memory"; @@ -44,22 +38,3 @@ status = "okay"; };
-&qspi { - status = "okay"; - - flash0: n25q00@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q00"; - reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; - m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; - }; -};
On Monday, April 20, 2015 at 02:16:02 PM, Pavel Machek wrote:
Both Socrates and SocDK share same QSPI and SPI flash configuration. Move the common configuration into common place.
Signed-off-by: Pavel Machek pavel@denx.de
Is my understanding correct that now all SoCFPGA CV boards will be forced to have this SPI flash ? I believe this is incorrect.
Best regards, Marek Vasut
On 20.04.2015 14:39, Marek Vasut wrote:
On Monday, April 20, 2015 at 02:16:02 PM, Pavel Machek wrote:
Both Socrates and SocDK share same QSPI and SPI flash configuration. Move the common configuration into common place.
Signed-off-by: Pavel Machek pavel@denx.de
Is my understanding correct that now all SoCFPGA CV boards will be forced to have this SPI flash ? I believe this is incorrect.
Yes. Defining such a SPI flash is board specific and shouldn't be moved to the common dtsi file.
Thanks, Stefan
SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 8e1f88c..70701f0 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -25,6 +25,10 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; };
regulator_3_3v: 3-3-v-regulator { @@ -77,3 +81,23 @@ &usb1 { status = "okay"; }; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +};
On Thursday, April 23, 2015 at 09:14:01 AM, Pavel Machek wrote:
SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.
Signed-off-by: Pavel Machek pavel@denx.de
Applied, thanks.
Can you please cook one for Arria V too while at it, so we're consistent ?
Best regards, Marek Vasut
On Fri 2015-04-24 05:22:55, Marek Vasut wrote:
On Thursday, April 23, 2015 at 09:14:01 AM, Pavel Machek wrote:
SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.
Signed-off-by: Pavel Machek pavel@denx.de
Applied, thanks.
Can you please cook one for Arria V too while at it, so we're consistent ?
Ok (if you are sure it has same hardware?). Should something like socfpga_devel_board.dtsi be created so we don't have to copy same piece of dts 3 times? Pavel
On Friday, April 24, 2015 at 03:16:35 PM, Pavel Machek wrote:
On Fri 2015-04-24 05:22:55, Marek Vasut wrote:
On Thursday, April 23, 2015 at 09:14:01 AM, Pavel Machek wrote:
SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.
Signed-off-by: Pavel Machek pavel@denx.de
Applied, thanks.
Can you please cook one for Arria V too while at it, so we're consistent ?
Ok (if you are sure it has same hardware?).
Yeah, from this point of view, CV and AV are almost identical. Basically, it's the FPGA which differs, AV is closer to stratix in my opinion.
Should something like socfpga_devel_board.dtsi be created so we don't have to copy same piece of dts 3 times?
No, this is board specific. I have a feeling we'll have to just deal with three copies in this case.
Best regards, Marek Vasut
Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 4e529a1..1b86897 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -25,6 +25,10 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; };
regulator_3_3v: 3-3-v-regulator { @@ -72,3 +76,23 @@ &usb1 { status = "okay"; }; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +};
On Saturday, April 25, 2015 at 09:36:16 PM, Pavel Machek wrote:
Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 4e529a1..1b86897 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts
I was just curious about this, but why are your patches missing diffstat ?
btw. I presume that there is no opposition to this patch, in my opinion it's perfectly OK.
Best regards, Marek Vasut
On Mon 2015-04-27 03:08:27, Marek Vasut wrote:
On Saturday, April 25, 2015 at 09:36:16 PM, Pavel Machek wrote:
Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 4e529a1..1b86897 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts
I was just curious about this, but why are your patches missing diffstat ?
diffstat was never required part of a patch.
btw. I presume that there is no opposition to this patch, in my opinion it's perfectly OK.
So this means "thank you, applied"? Pavel
On Monday, April 27, 2015 at 08:09:41 AM, Pavel Machek wrote:
On Mon 2015-04-27 03:08:27, Marek Vasut wrote:
On Saturday, April 25, 2015 at 09:36:16 PM, Pavel Machek wrote:
Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 4e529a1..1b86897 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts
I was just curious about this, but why are your patches missing diffstat ?
diffstat was never required part of a patch.
Would be nice to have though.
btw. I presume that there is no opposition to this patch, in my opinion it's perfectly OK.
So this means "thank you, applied"?
No, that's "applied, thanks" ;-)
Best regards, Marek Vasut
participants (3)
-
Marek Vasut -
Pavel Machek -
Stefan Roese