SPEAr Architecture support added. It contains the support for following SPEAr blocks - Timer - System controller - Misc registers

Signed-off-by: Vipin vipin.kumar@st.com --- cpu/arm926ejs/spear/Makefile | 52 ++++++++++ cpu/arm926ejs/spear/reset.c | 54 +++++++++++ cpu/arm926ejs/spear/timer.c | 153 ++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/hardware.h | 66 +++++++++++++ include/asm-arm/arch-spear/spr_gpt.h | 85 +++++++++++++++++ include/asm-arm/arch-spear/spr_misc.h | 130 +++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_syscntl.h | 38 ++++++++ 7 files changed, 578 insertions(+), 0 deletions(-) create mode 100755 cpu/arm926ejs/spear/Makefile create mode 100755 cpu/arm926ejs/spear/reset.c create mode 100755 cpu/arm926ejs/spear/timer.c create mode 100644 include/asm-arm/arch-spear/hardware.h create mode 100755 include/asm-arm/arch-spear/spr_gpt.h create mode 100644 include/asm-arm/arch-spear/spr_misc.h create mode 100644 include/asm-arm/arch-spear/spr_syscntl.h

diff --git a/cpu/arm926ejs/spear/Makefile b/cpu/arm926ejs/spear/Makefile new file mode 100755 index 0000000..bf8dfa8 --- /dev/null +++ b/cpu/arm926ejs/spear/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS := reset.o \ + timer.o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/spear/reset.c b/cpu/arm926ejs/spear/reset.c new file mode 100755 index 0000000..73ad86d --- /dev/null +++ b/cpu/arm926ejs/spear/reset.c @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_syscntl.h> + +void reset_cpu(ulong ignored) +{ + struct syscntl_regs *syscntl_regs_p = + (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; + + printf("System is going to reboot ...\n"); + + /* + * This 1 second delay will allow the above message + * to be printed before reset + */ + udelay((1000 * 1000)); + + /* Going into slow mode before resetting SOC */ + writel(0x02, &syscntl_regs_p->scctrl); + + /* + * Writing any value to the system status register will + * reset the SoC + */ + writel(0x00, &syscntl_regs_p->scsysstat); + + /* system will restart */ + while (1) + ; +} diff --git a/cpu/arm926ejs/spear/timer.c b/cpu/arm926ejs/spear/timer.c new file mode 100755 index 0000000..06858b4 --- /dev/null +++ b/cpu/arm926ejs/spear/timer.c @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_gpt.h> +#include <asm/arch/spr_misc.h> + +#define GPT_RESOLUTION (CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ) +#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING) + +static struct gpt_regs *const gpt_regs_p = + (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE; + +static struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + +static ulong timestamp; +static ulong lastdec; + +int timer_init(void) +{ + u32 synth; + + /* Prescaler setting */ +#if defined(CONFIG_SPEAR3XX) + writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg); + synth = MISC_GPT4SYNTH; +#elif defined(CONFIG_SPEAR600) + writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg); + synth = MISC_GPT3SYNTH; +#else +# error Incorrect config. Can only be spear{600|300|310|320} +#endif + + writel(readl(&misc_regs_p->periph_clk_cfg) | synth, + &misc_regs_p->periph_clk_cfg); + + /* disable timers */ + writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control); + + /* load value for free running */ + writel(GPT_FREE_RUNNING, &gpt_regs_p->compare); + + /* auto reload, start timer */ + writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control); + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return (get_timer_masked() / GPT_RESOLUTION) - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void __udelay(unsigned long usec) +{ + ulong tmo; + ulong start = get_timer_masked(); + ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100); + ulong rndoff; + + rndoff = (usec % 10) ? 1 : 0; + + /* tenudelcnt timer tick gives 10 microsecconds delay */ + tmo = ((usec / 10) + rndoff) * tenudelcnt; + + while ((ulong) (get_timer_masked() - start) < tmo) + ; +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER(); + + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + /* we have an overflow ... */ + timestamp += now + GPT_FREE_RUNNING - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked(unsigned long usec) +{ + return udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SPEAR_HZ; +} diff --git a/include/asm-arm/arch-spear/hardware.h b/include/asm-arm/arch-spear/hardware.h new file mode 100644 index 0000000..818f36c --- /dev/null +++ b/include/asm-arm/arch-spear/hardware.h @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define CONFIG_SYS_USBD_BASE (0xE1100000) +#define CONFIG_SYS_PLUG_BASE (0xE1200000) +#define CONFIG_SYS_FIFO_BASE (0xE1000800) +#define CONFIG_SYS_SMI_BASE (0xFC000000) +#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) +#define CONFIG_SPEAR_TIMERBASE (0xFC800000) +#define CONFIG_SPEAR_MISCBASE (0xFCA80000) + +#define CONFIG_SYS_NAND_CLE (1 << 16) +#define CONFIG_SYS_NAND_ALE (1 << 17) + +#if defined(CONFIG_SPEAR600) +#define CONFIG_SYS_I2C_BASE (0xD0200000) +#define CONFIG_SPEAR_FSMCBASE (0xD1800000) + +#elif defined(CONFIG_SPEAR300) +#define CONFIG_SYS_I2C_BASE (0xD0180000) +#define CONFIG_SPEAR_FSMCBASE (0x94000000) + +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SYS_I2C_BASE (0xD0180000) +#define CONFIG_SPEAR_FSMCBASE (0x44000000) + +#undef CONFIG_SYS_NAND_CLE +#undef CONFIG_SYS_NAND_ALE +#define CONFIG_SYS_NAND_CLE (1 << 17) +#define CONFIG_SYS_NAND_ALE (1 << 16) + +#define CONFIG_SPEAR_EMIBASE (0x4F000000) +#define CONFIG_SPEAR_RASBASE (0xB4000000) + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_I2C_BASE (0xD0180000) +#define CONFIG_SPEAR_FSMCBASE (0x4C000000) + +#define CONFIG_SPEAR_EMIBASE (0x40000000) +#define CONFIG_SPEAR_RASBASE (0xB3000000) + +#endif +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-spear/spr_gpt.h b/include/asm-arm/arch-spear/spr_gpt.h new file mode 100755 index 0000000..965b5ab --- /dev/null +++ b/include/asm-arm/arch-spear/spr_gpt.h @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_GPT_H +#define _SPR_GPT_H + +struct gpt_regs { + u8 reserved[0x80]; + u32 control; + u32 status; + u32 compare; + u32 count; + u32 capture_re; + u32 capture_fe; +}; + +/* + * TIMER_CONTROL register settings + */ + +#define GPT_PRESCALER_MASK 0x000F +#define GPT_PRESCALER_1 0x0000 +#define GPT_PRESCALER_2 0x0001 +#define GPT_PRESCALER_4 0x0002 +#define GPT_PRESCALER_8 0x0003 +#define GPT_PRESCALER_16 0x0004 +#define GPT_PRESCALER_32 0x0005 +#define GPT_PRESCALER_64 0x0006 +#define GPT_PRESCALER_128 0x0007 +#define GPT_PRESCALER_256 0x0008 + +#define GPT_MODE_SINGLE_SHOT 0x0010 +#define GPT_MODE_AUTO_RELOAD 0x0000 + +#define GPT_ENABLE 0x0020 + +#define GPT_CAPT_MODE_MASK 0x00C0 +#define GPT_CAPT_MODE_NONE 0x0000 +#define GPT_CAPT_MODE_RE 0x0040 +#define GPT_CAPT_MODE_FE 0x0080 +#define GPT_CAPT_MODE_BOTH 0x00C0 + +#define GPT_INT_MATCH 0x0100 +#define GPT_INT_FE 0x0200 +#define GPT_INT_RE 0x0400 + +/* + * TIMER_STATUS register settings + */ + +#define GPT_STS_MATCH 0x0001 +#define GPT_STS_FE 0x0002 +#define GPT_STS_RE 0x0004 + +/* + * TIMER_COMPARE register settings + */ + +#define GPT_FREE_RUNNING 0xFFFF + +/* Timer, HZ specific defines */ +#define CONFIG_SPEAR_HZ (1000) +#define CONFIG_SPEAR_HZ_CLOCK (8300000) + +#endif diff --git a/include/asm-arm/arch-spear/spr_misc.h b/include/asm-arm/arch-spear/spr_misc.h new file mode 100644 index 0000000..8b96d9b --- /dev/null +++ b/include/asm-arm/arch-spear/spr_misc.h @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_MISC_H +#define _SPR_MISC_H + +struct misc_regs { + u32 auto_cfg_reg; /* 0x0 */ + u32 armdbg_ctr_reg; /* 0x4 */ + u32 pll1_cntl; /* 0x8 */ + u32 pll1_frq; /* 0xc */ + u32 pll1_mod; /* 0x10 */ + u32 pll2_cntl; /* 0x14 */ + u32 pll2_frq; /* 0x18 */ + u32 pll2_mod; /* 0x1C */ + u32 pll_ctr_reg; /* 0x20 */ + u32 amba_clk_cfg; /* 0x24 */ + u32 periph_clk_cfg; /* 0x28 */ + u32 periph1_clken; /* 0x2C */ + u32 periph2_clken; /* 0x30 */ + u32 ras_clken; /* 0x34 */ + u32 periph1_rst; /* 0x38 */ + u32 periph2_rst; /* 0x3C */ + u32 ras_rst; /* 0x40 */ + u32 prsc1_clk_cfg; /* 0x44 */ + u32 prsc2_clk_cfg; /* 0x48 */ + u32 prsc3_clk_cfg; /* 0x4C */ + u32 amem_cfg_ctrl; /* 0x50 */ + u32 port_cfg_ctrl; /* 0x54 */ + u32 reserved_1; /* 0x58 */ + u32 clcd_synth_clk; /* 0x5C */ + u32 irda_synth_clk; /* 0x60 */ + u32 uart_synth_clk; /* 0x64 */ + u32 gmac_synth_clk; /* 0x68 */ + u32 ras_synth1_clk; /* 0x6C */ + u32 ras_synth2_clk; /* 0x70 */ + u32 ras_synth3_clk; /* 0x74 */ + u32 ras_synth4_clk; /* 0x78 */ + u32 arb_icm_ml1; /* 0x7C */ + u32 arb_icm_ml2; /* 0x80 */ + u32 arb_icm_ml3; /* 0x84 */ + u32 arb_icm_ml4; /* 0x88 */ + u32 arb_icm_ml5; /* 0x8C */ + u32 arb_icm_ml6; /* 0x90 */ + u32 arb_icm_ml7; /* 0x94 */ + u32 arb_icm_ml8; /* 0x98 */ + u32 arb_icm_ml9; /* 0x9C */ + u32 dma_src_sel; /* 0xA0 */ + u32 uphy_ctr_reg; /* 0xA4 */ + u32 gmac_ctr_reg; /* 0xA8 */ + u32 port_bridge_ctrl; /* 0xAC */ + u32 reserved_2[4]; /* 0xB0--0xBC */ + u32 prc1_ilck_ctrl_reg; /* 0xC0 */ + u32 prc2_ilck_ctrl_reg; /* 0xC4 */ + u32 prc3_ilck_ctrl_reg; /* 0xC8 */ + u32 prc4_ilck_ctrl_reg; /* 0xCC */ + u32 prc1_intr_ctrl_reg; /* 0xD0 */ + u32 prc2_intr_ctrl_reg; /* 0xD4 */ + u32 prc3_intr_ctrl_reg; /* 0xD8 */ + u32 prc4_intr_ctrl_reg; /* 0xDC */ + u32 powerdown_cfg_reg; /* 0xE0 */ + u32 ddr_1v8_compensation; /* 0xE4 */ + u32 ddr_2v5_compensation; /* 0xE8 */ + u32 core_3v3_compensation; /* 0xEC */ + u32 ddr_pad; /* 0xF0 */ + u32 bist1_ctr_reg; /* 0xF4 */ + u32 bist2_ctr_reg; /* 0xF8 */ + u32 bist3_ctr_reg; /* 0xFC */ + u32 bist4_ctr_reg; /* 0x100 */ + u32 bist5_ctr_reg; /* 0x104 */ + u32 bist1_rslt_reg; /* 0x108 */ + u32 bist2_rslt_reg; /* 0x10C */ + u32 bist3_rslt_reg; /* 0x110 */ + u32 bist4_rslt_reg; /* 0x114 */ + u32 bist5_rslt_reg; /* 0x118 */ + u32 syst_error_reg; /* 0x11C */ + u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */ + u32 ras_gpp1_in; /* 0x8000 */ + u32 ras_gpp2_in; /* 0x8004 */ + u32 ras_gpp1_out; /* 0x8008 */ + u32 ras_gpp2_out; /* 0x800C */ +}; + +/* AUTO_CFG_REG value */ +#define MISC_SOCCFGMSK 0x0000003F +#define MISC_SOCCFG30 0x0000000C +#define MISC_SOCCFG31 0x0000000D +#define MISC_NANDDIS 0x00020000 + +/* PERIPH_CLK_CFG value */ +#define MISC_GPT3SYNTH 0x00000400 +#define MISC_GPT4SYNTH 0x00000800 + +/* PRSC_CLK_CFG value */ +/* + * Fout = Fin / (2^(N+1) * (M + 1)) + */ +#define MISC_PRSC_N_1 0x00001000 +#define MISC_PRSC_M_9 0x00000009 +#define MISC_PRSC_N_4 0x00004000 +#define MISC_PRSC_M_399 0x0000018F +#define MISC_PRSC_N_6 0x00006000 +#define MISC_PRSC_M_2593 0x00000A21 +#define MISC_PRSC_M_124 0x0000007C +#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9) + +/* PERIPH1_CLKEN, PERIPH1_RST value */ +#define MISC_USBDENB 0x01000000 + +#endif diff --git a/include/asm-arm/arch-spear/spr_syscntl.h b/include/asm-arm/arch-spear/spr_syscntl.h new file mode 100644 index 0000000..3c92f09 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_syscntl.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2009 + * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +struct syscntl_regs { + u32 scctrl; + u32 scsysstat; + u32 scimctrl; + u32 scimsysstat; + u32 scxtalctrl; + u32 scpllctrl; + u32 scpllfctrl; + u32 scperctrl0; + u32 scperctrl1; + u32 scperen; + u32 scperdis; + const u32 scperclken; + const u32 scperstat; +};

SPEAr SoCs contain a serial memory interface controller. This controller is used to interface with spi based memories. This patch adds the driver for this IP.

Signed-off-by: Vipin vipin.kumar@st.com --- drivers/mtd/Makefile | 1 + drivers/mtd/spr_smi.c | 523 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_smi.h | 115 ++++++++ 3 files changed, 639 insertions(+), 0 deletions(-) mode change 100644 => 100755 drivers/mtd/Makefile create mode 100755 drivers/mtd/spr_smi.c create mode 100755 include/asm-arm/arch-spear/spr_smi.h

diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile old mode 100644 new mode 100755 index 754d648..cbf6f15 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o +COBJS-$(CONFIG_SPEARSMI) += spr_smi.o

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/spr_smi.c new file mode 100755 index 0000000..9a70a19 --- /dev/null +++ b/drivers/mtd/spr_smi.c @@ -0,0 +1,523 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <flash.h> +#include <linux/err.h> + +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_smi.h> + +#if !defined(CONFIG_SYS_NO_FLASH) + +static struct smi_regs *const smicntl = + (struct smi_regs * const)CONFIG_SYS_SMI_BASE; +static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = + CONFIG_SYS_FLASH_ADDR_BASE; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +#define ST_M25Pxx_ID 0x00002020 + +static struct flash_dev flash_ids[] = { + {0x10, 0x10000, 2}, /* 64K Byte */ + {0x11, 0x20000, 4}, /* 128K Byte */ + {0x12, 0x40000, 4}, /* 256K Byte */ + {0x13, 0x80000, 8}, /* 512K Byte */ + {0x14, 0x100000, 16}, /* 1M Byte */ + {0x15, 0x200000, 32}, /* 2M Byte */ + {0x16, 0x400000, 64}, /* 4M Byte */ + {0x17, 0x800000, 128}, /* 8M Byte */ + {0x18, 0x1000000, 64}, /* 16M Byte */ + {0x00,} +}; + +/* + * smi_wait_xfer_finish - Wait until TFF is set in status register + * @timeout: timeout in milliseconds + * + * Wait until TFF is set in status register + */ +static void smi_wait_xfer_finish(int timeout) +{ + while (timeout--) { + if (readl(&smicntl->smi_sr) & TFF) + break; + udelay(1000); + } +} + +/* + * smi_read_id - Read flash id + * @info: flash_info structure pointer + * @banknum: bank number + * + * Read the flash id present at bank #banknum + */ +static unsigned int smi_read_id(flash_info_t *info, int banknum) +{ + unsigned int value; + + writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); + writel(READ_ID, &smicntl->smi_tr); + writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, + &smicntl->smi_cr2); + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); + + writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr); + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); + + return value; +} + +/* + * flash_get_size - Detect the SMI flash by reading the ID. + * @base: Base address of the flash area bank #banknum + * @banknum: Bank number + * + * Detect the SMI flash by reading the ID. Initializes the flash_info structure + * with size, sector count etc. + */ +static ulong flash_get_size(ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + struct flash_dev *dev; + unsigned int value; + unsigned int density; + int i; + + value = smi_read_id(info, banknum); + density = (value >> 16) & 0xff; + + for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; + i++, dev = &flash_ids[i]) { + if (dev->density == density) { + info->size = dev->size; + info->sector_count = dev->sector_count; + break; + } + } + + if (dev->density == 0x0) + return 0; + + info->flash_id = value & 0xffff; + info->start[0] = base; + + return info->size; +} + +/* + * smi_read_sr - Read status register of SMI + * @bank: bank number + * + * This routine will get the status register of the flash chip present at the + * given bank + */ +static unsigned int smi_read_sr(int bank) +{ + u32 ctrlreg1; + + /* store the CTRL REG1 state */ + ctrlreg1 = readl(&smicntl->smi_cr1); + + /* Program SMI in HW Mode */ + writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE), + &smicntl->smi_cr1); + + /* Performing a RSR instruction in HW mode */ + writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); + + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + /* Restore the CTRL REG1 state */ + writel(ctrlreg1, &smicntl->smi_cr1); + + return readl(&smicntl->smi_sr); +} + +/* + * smi_wait_till_ready - Wait till last operation is over. + * @bank: bank number shifted. + * @timeout: timeout in milliseconds. + * + * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0) + * The routine checks for #timeout loops, each at interval of 1 milli-second. + * If successful the routine returns 0. + */ +static int smi_wait_till_ready(int bank, int timeout) +{ + int count; + unsigned int sr; + + /* One chip guarantees max 5 msec wait here after page writes, + but potentially three seconds (!) after page erase. */ + for (count = 0; count < timeout; count++) { + + sr = smi_read_sr(bank); + if (sr < 0) + break; + else if (!(sr & WIP_BIT)) + return 0; + + /* Try again after 1m-sec */ + udelay(1000); + } + printf("SMI controller is still in wait, timeout=%d\n", timeout); + return -EIO; +} + +/* + * smi_write_enable - Enable the flash to do write operation + * @bank: bank number + * + * Set write enable latch with Write Enable command. + * Returns negative if error occurred. + */ +static int smi_write_enable(int bank) +{ + u32 ctrlreg1; + int timeout = WMODE_TOUT; + + /* Store the CTRL REG1 state */ + ctrlreg1 = readl(&smicntl->smi_cr1); + + /* Program SMI in H/W Mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); + + /* Give the Flash, Write Enable command */ + writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); + + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + /* Restore the CTRL REG1 state */ + writel(ctrlreg1, &smicntl->smi_cr1); + + while (timeout--) { + if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) + break; + udelay(1000); + } + + if (timeout) + return 0; + + return -1; +} + +/* + * smi_init - SMI initialization routine + * + * SMI initialization routine. Sets SMI control register1. + */ +static void smi_init(void) +{ + /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ + writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, + &smicntl->smi_cr1); +} + +/* + * smi_sector_erase - Erase flash sector + * @info: flash_info structure pointer + * @sector: sector number + * + * Set write enable latch with Write Enable command. + * Returns negative if error occurred. + */ +static int smi_sector_erase(flash_info_t *info, unsigned int sector) +{ + int bank; + unsigned int sect_add; + unsigned int instruction; + + switch (info->start[0]) { + case SMIBANK0_BASE: + bank = BANK0; + break; + case SMIBANK1_BASE: + bank = BANK1; + break; + case SMIBANK2_BASE: + bank = BANK2; + break; + case SMIBANK3_BASE: + bank = BANK3; + break; + default: + return -1; + } + + sect_add = sector * (info->size / info->sector_count); + instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE; + + writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr); + + if (info->flash_id == ST_M25Pxx_ID) { + /* Wait until finished previous write command. */ + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; + + /* Send write enable, before erase commands. */ + if (smi_write_enable(bank)) + return -EIO; + + /* Put SMI in SW mode */ + writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); + + /* Send Sector Erase command in SW Mode */ + writel(instruction, &smicntl->smi_tr); + writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, + &smicntl->smi_cr2); + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; + + /* Put SMI in HW mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, + &smicntl->smi_cr1); + + return 0; + } else { + /* Put SMI in HW mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, + &smicntl->smi_cr1); + return -EINVAL; + } +} + +/* + * smi_write - Write to SMI flash + * @src_addr: source buffer + * @dst_addr: destination buffer + * @length: length to write in words + * @bank: bank base address + * + * Write to SMI flash + */ +static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, + unsigned int length, ulong bank_addr) +{ + int banknum; + unsigned int WM; + + switch (bank_addr) { + case SMIBANK0_BASE: + banknum = BANK0; + WM = WM0; + break; + case SMIBANK1_BASE: + banknum = BANK1; + WM = WM1; + break; + case SMIBANK2_BASE: + banknum = BANK2; + WM = WM2; + break; + case SMIBANK3_BASE: + banknum = BANK3; + WM = WM3; + break; + default: + return -1; + } + + if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + /* Set SMI in Hardware Mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); + + if (smi_write_enable(banknum)) + return -EIO; + + /* Perform the write command */ + while (length--) { + if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { + if (smi_wait_till_ready(banknum, + CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + if (smi_write_enable(banknum)) + return -EIO; + } + + *dst_addr++ = *src_addr++; + + if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) + return -EIO; + } + + if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr); + + return 0; +} + +/* + * write_buff - Write to SMI flash + * @info: flash info structure + * @src: source buffer + * @dest_addr: destination buffer + * @length: length to write in words + * + * Write to SMI flash + */ +int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) +{ + return smi_write((unsigned int *)src, (unsigned int *)dest_addr, + (length + 3) / 4, info->start[0]); +} + +/* + * flash_init - SMI flash initialization + * + * SMI flash initialization + */ +unsigned long flash_init(void) +{ + unsigned long size = 0; + int i, j; + + smi_init(); + + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + size += flash_info[i].size = flash_get_size(bank_base[i], i); + } + + for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { + for (i = 1; i < flash_info[j].sector_count; i++) + flash_info[j].start[i] = + flash_info[j].start[i - 1] + + flash_info->size / flash_info->sector_count; + + } + + return size; +} + +/* + * flash_print_info - Print SMI flash information + * + * Print SMI flash information + */ +void flash_print_info(flash_info_t *info) +{ + int i; + if (info->flash_id == FLASH_UNKNOWN) { + puts("missing or unknown FLASH type\n"); + return; + } + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + puts(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO + int size; + int erased; + u32 *flash; + + /* + * Check if whole sector is erased + */ + size = (info->size) / (info->sector_count); + flash = (u32 *) info->start[i]; + size = size / sizeof(int); + + while ((size--) && (*flash++ == ~0)) + ; + + size++; + if (size) + erased = 0; + else + erased = 1; + + if ((i % 5) == 0) + printf("\n"); + + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO) " : " "); +#endif + } + putc('\n'); + return; +} + +/* + * flash_erase - Erase SMI flash + * + * Erase SMI flash + */ +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot = 0; + flash_sect_t sect; + + if (info->flash_id != ST_M25Pxx_ID) { + puts("Can't erase unknown flash type - aborted\n"); + return 1; + } + + if ((s_first < 0) || (s_first > s_last)) { + puts("- no sectors to erase\n"); + return 1; + } + + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + putc('\n'); + } + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { + if (smi_sector_erase(info, sect)) + rcode = 1; + else + putc('.'); + } + } + puts(" done\n"); + return rcode; +} +#endif diff --git a/include/asm-arm/arch-spear/spr_smi.h b/include/asm-arm/arch-spear/spr_smi.h new file mode 100755 index 0000000..06df745 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_smi.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef SPR_SMI_H +#define SPR_SMI_H + +/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ +/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ + +#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE +#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE + +#define SMIBANK0_BASE (FLASH_START_ADDRESS) +#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) +#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) +#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) + +#define BANK0 0 +#define BANK1 1 +#define BANK2 2 +#define BANK3 3 + +struct smi_regs { + u32 smi_cr1; + u32 smi_cr2; + u32 smi_sr; + u32 smi_tr; + u32 smi_rr; +}; + +/* CONTROL REG 1 */ +#define BANK_EN 0x0000000F /* enables all banks */ +#define DSEL_TIME 0x00000060 /* Deselect time */ +#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ +#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ +#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ +#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ +#define SW_MODE 0x10000000 /* enables SW Mode */ +#define WB_MODE 0x20000000 /* Write Burst Mode */ +#define FAST_MODE 0x00008000 /* Fast Mode */ +#define HOLD1 0x00010000 + +/* CONTROL REG 2 */ +#define RD_STATUS_REG 0x00000400 /* reads status reg */ +#define WE 0x00000800 /* Write Enable */ +#define BANK0_SEL 0x00000000 /* Select Banck0 */ +#define BANK1_SEL 0x00001000 /* Select Banck1 */ +#define BANK2_SEL 0x00002000 /* Select Banck2 */ +#define BANK3_SEL 0x00003000 /* Select Banck3 */ +#define BANKSEL_SHIFT 12 +#define SEND 0x00000080 /* Send data */ +#define TX_LEN_1 0x00000001 /* data length = 1 byte */ +#define TX_LEN_2 0x00000002 /* data length = 2 byte */ +#define TX_LEN_3 0x00000003 /* data length = 3 byte */ +#define TX_LEN_4 0x00000004 /* data length = 4 byte */ +#define RX_LEN_1 0x00000010 /* data length = 1 byte */ +#define RX_LEN_2 0x00000020 /* data length = 2 byte */ +#define RX_LEN_3 0x00000030 /* data length = 3 byte */ +#define RX_LEN_4 0x00000040 /* data length = 4 byte */ +#define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ +#define WCIE 0x00000200 /* WCF Interrupt Enable */ + +/* STATUS_REG */ +#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ +#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ +#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ +#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ +#define RSR 0x00000005 /* Read Status regiser */ +#define TFF 0x00000100 /* Transfer Finished FLag */ +#define WCF 0x00000200 /* Transfer Finished FLag */ +#define ERF1 0x00000400 /* Error Flag 1 */ +#define ERF2 0x00000800 /* Error Flag 2 */ +#define WM0 0x00001000 /* WM Bank 0 */ +#define WM1 0x00002000 /* WM Bank 1 */ +#define WM2 0x00004000 /* WM Bank 2 */ +#define WM3 0x00008000 /* WM Bank 3 */ +#define WM_SHIFT 12 + +/* TR REG */ +#define READ_ID 0x0000009F /* Read Identification */ +#define BULK_ERASE 0x000000C7 /* BULK erase */ +#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ +#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ + +struct flash_dev { + u32 density; + ulong size; + ushort sector_count; +}; + +#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ +#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ +#define WMODE_TOUT 2 /* write enable timeout */ + +#endif

SPEAr SoCs contain a synopsys usb device controller. USB Device IP can work in 2 modes - DMA mode - Slave mode

The driver adds support only for slave mode operation of usb device IP. This driver is used along with standard USBTTY driver to obtain a tty interface over USB on the host

Signed-off-by: Vipin vipin.kumar@st.com --- drivers/serial/usbtty.h | 2 + drivers/usb/gadget/Makefile | 1 + drivers/usb/gadget/spr_udc.c | 998 ++++++++++++++++++++++++++++++++++++++++++ include/usb/spr_udc.h | 230 ++++++++++ 4 files changed, 1231 insertions(+), 0 deletions(-) mode change 100644 => 100755 drivers/serial/usbtty.h mode change 100644 => 100755 drivers/usb/gadget/Makefile create mode 100755 drivers/usb/gadget/spr_udc.c create mode 100755 include/usb/spr_udc.h

diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h old mode 100644 new mode 100755 index 6b6c4a1..a23169a --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -33,6 +33,8 @@ #include <usb/musb_udc.h> #elif defined(CONFIG_PXA27X) #include <usb/pxa27x_udc.h> +#elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600) +#include <usb/spr_udc.h> #endif

#include <version_autogenerated.h> diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile old mode 100644 new mode 100755 index 2a19b1e..1d7362d --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o COBJS-$(CONFIG_PXA27X) += pxa27x_udc.o +COBJS-$(CONFIG_SPEARUDC) += spr_udc.o endif

COBJS := $(COBJS-y) diff --git a/drivers/usb/gadget/spr_udc.c b/drivers/usb/gadget/spr_udc.c new file mode 100755 index 0000000..f2b06d6 --- /dev/null +++ b/drivers/usb/gadget/spr_udc.c @@ -0,0 +1,998 @@ +/* + * Based on drivers/usb/gadget/omap1510_udc.c + * TI OMAP1510 USB bus interface driver + * + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +#include <usbdevice.h> +#include "ep0.h" +#include <usb/spr_udc.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> + +#define UDC_INIT_MDELAY 80 /* Device settle delay */ + +/* Some kind of debugging output... */ +#ifndef DEBUG_SPRUSBTTY +#define UDCDBG(str) +#define UDCDBGA(fmt, args...) +#else +#define UDCDBG(str) serial_printf(str "\n") +#define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args) +#endif + +static struct urb *ep0_urb; +static struct usb_device_instance *udc_device; + +static struct plug_regs *const plug_regs_p = + (struct plug_regs * const)CONFIG_SYS_PLUG_BASE; +static struct udc_regs *const udc_regs_p = + (struct udc_regs * const)CONFIG_SYS_USBD_BASE; +static struct udc_endp_regs *const outep_regs_p = + &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0]; +static struct udc_endp_regs *const inep_regs_p = + &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0]; + +/* + * udc_state_transition - Write the next packet to TxFIFO. + * @initial: Initial state. + * @final: Final state. + * + * Helper function to implement device state changes. The device states and + * the events that transition between them are: + * + * STATE_ATTACHED + * || /\ + * / || + * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET + * || /\ + * / || + * STATE_POWERED + * || /\ + * / || + * DEVICE_RESET DEVICE_POWER_INTERRUPTION + * || /\ + * / || + * STATE_DEFAULT + * || /\ + * / || + * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET + * || /\ + * / || + * STATE_ADDRESSED + * || /\ + * / || + * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED + * || /\ + * / || + * STATE_CONFIGURED + * + * udc_state_transition transitions up (in the direction from STATE_ATTACHED + * to STATE_CONFIGURED) from the specified initial state to the specified final + * state, passing through each intermediate state on the way. If the initial + * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then + * no state transitions will take place. + * + * udc_state_transition also transitions down (in the direction from + * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the + * specified final state, passing through each intermediate state on the way. + * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final + * state, then no state transitions will take place. + * + * This function must only be called with interrupts disabled. + */ +static void udc_state_transition(usb_device_state_t initial, + usb_device_state_t final) +{ + if (initial < final) { + switch (initial) { + case STATE_ATTACHED: + usbd_device_event_irq(udc_device, + DEVICE_HUB_CONFIGURED, 0); + if (final == STATE_POWERED) + break; + case STATE_POWERED: + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + if (final == STATE_DEFAULT) + break; + case STATE_DEFAULT: + usbd_device_event_irq(udc_device, + DEVICE_ADDRESS_ASSIGNED, 0); + if (final == STATE_ADDRESSED) + break; + case STATE_ADDRESSED: + usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0); + case STATE_CONFIGURED: + break; + default: + break; + } + } else if (initial > final) { + switch (initial) { + case STATE_CONFIGURED: + usbd_device_event_irq(udc_device, + DEVICE_DE_CONFIGURED, 0); + if (final == STATE_ADDRESSED) + break; + case STATE_ADDRESSED: + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + if (final == STATE_DEFAULT) + break; + case STATE_DEFAULT: + usbd_device_event_irq(udc_device, + DEVICE_POWER_INTERRUPTION, 0); + if (final == STATE_POWERED) + break; + case STATE_POWERED: + usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0); + case STATE_ATTACHED: + break; + default: + break; + } + } +} + +/* Stall endpoint */ +static void udc_stall_ep(u32 ep_num) +{ + writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, + &inep_regs_p[ep_num].endp_cntl); + + writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, + &outep_regs_p[ep_num].endp_cntl); +} + +static void *get_fifo(int ep_num, int in) +{ + u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE; + + switch (ep_num) { + case UDC_EP3: + fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn); + /* break intentionally left out */ + + case UDC_EP1: + fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn); + /* break intentionally left out */ + + case UDC_EP0: + default: + if (in) { + fifo_ptr += + readl(&outep_regs_p[2].endp_maxpacksize) >> 16; + /* break intentionally left out */ + } else { + break; + } + + case UDC_EP2: + fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16; + /* break intentionally left out */ + } + + return (void *)fifo_ptr; +} + +static int usbgetpckfromfifo(int epNum, u8 *bufp, u32 len) +{ + u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0); + u32 i, nw, nb; + u32 *wrdp; + u8 *bytp; + + if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY) + return -1; + + nw = len / sizeof(u32); + nb = len % sizeof(u32); + + wrdp = (u32 *)bufp; + for (i = 0; i < nw; i++) { + writel(readl(fifo_ptr), wrdp); + wrdp++; + } + + bytp = (u8 *)wrdp; + for (i = 0; i < nb; i++) { + writeb(readb(fifo_ptr), bytp); + fifo_ptr++; + bytp++; + } + readl(&outep_regs_p[epNum].write_done); + + return 0; +} + +static void usbputpcktofifo(int epNum, u8 *bufp, u32 len) +{ + u32 i, nw, nb; + u32 *wrdp; + u8 *bytp; + u8 *fifo_ptr = get_fifo(epNum, 1); + + nw = len / sizeof(int); + nb = len % sizeof(int); + wrdp = (u32 *)bufp; + for (i = 0; i < nw; i++) { + writel(*wrdp, fifo_ptr); + wrdp++; + } + + bytp = (u8 *)wrdp; + for (i = 0; i < nb; i++) { + writeb(*bytp, fifo_ptr); + fifo_ptr++; + bytp++; + } +} + +/* + * spear_write_noniso_tx_fifo - Write the next packet to TxFIFO. + * @endpoint: Endpoint pointer. + * + * If the endpoint has an active tx_urb, then the next packet of data from the + * URB is written to the tx FIFO. The total amount of data in the urb is given + * by urb->actual_length. The maximum amount of data that can be sent in any + * one packet is given by endpoint->tx_packetSize. The number of data bytes + * from this URB that have already been transmitted is given by endpoint->sent. + * endpoint->last is updated by this routine with the number of data bytes + * transmitted in this packet. + * + */ +static void spear_write_noniso_tx_fifo(struct usb_endpoint_instance + *endpoint) +{ + struct urb *urb = endpoint->tx_urb; + int align; + + if (urb) { + u32 last; + + UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d", + urb->buffer, urb->buffer_length, urb->actual_length); + + last = MIN(urb->actual_length - endpoint->sent, + endpoint->tx_packetSize); + + if (last) { + u8 *cp = urb->buffer + endpoint->sent; + + /* + * This ensures that USBD packet fifo is accessed + * - through word aligned pointer or + * - through non word aligned pointer but only + * with a max length to make the next packet + * word aligned + */ + + align = ((ulong)cp % sizeof(int)); + if (align) + last = MIN(last, sizeof(int) - align); + + UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d", + endpoint->sent, endpoint->tx_packetSize, last); + + usbputpcktofifo(endpoint->endpoint_address & + USB_ENDPOINT_NUMBER_MASK, cp, last); + } + endpoint->last = last; + } +} + +/* + * Handle SETUP USB interrupt. + * This function implements TRM Figure 14-14. + */ +static void spear_udc_setup(struct usb_endpoint_instance *endpoint) +{ + u8 *datap = (u8 *)&ep0_urb->device_request; + int ep_addr = endpoint->endpoint_address; + + UDCDBG("-> Entering device setup"); + usbgetpckfromfifo(ep_addr, datap, 8); + + /* Try to process setup packet */ + if (ep0_recv_setup(ep0_urb)) { + /* Not a setup packet, stall next EP0 transaction */ + udc_stall_ep(0); + UDCDBG("can't parse setup packet, still waiting for setup"); + return; + } + + /* Check direction */ + if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) + == USB_REQ_HOST2DEVICE) { + UDCDBG("control write on EP0"); + if (le16_to_cpu(ep0_urb->device_request.wLength)) { + /* Stall this request */ + UDCDBG("Stalling unsupported EP0 control write data " + "stage."); + udc_stall_ep(0); + } + } else { + + UDCDBG("control read on EP0"); + /* + * The ep0_recv_setup function has already placed our response + * packet data in ep0_urb->buffer and the packet length in + * ep0_urb->actual_length. + */ + endpoint->tx_urb = ep0_urb; + endpoint->sent = 0; + /* + * Write packet data to the FIFO. spear_write_noniso_tx_fifo + * will update endpoint->last with the number of bytes written + * to the FIFO. + */ + spear_write_noniso_tx_fifo(endpoint); + + writel(0x0, &inep_regs_p[ep_addr].write_done); + } + + udc_unset_nak(endpoint->endpoint_address); + + UDCDBG("<- Leaving device setup"); +} + +/* + * Handle endpoint 0 RX interrupt + */ +static void spear_udc_ep0_rx(struct usb_endpoint_instance *endpoint) +{ + u8 dummy[64]; + + UDCDBG("RX on EP0"); + + /* Check direction */ + if ((ep0_urb->device_request.bmRequestType + & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { + /* + * This rx interrupt must be for a control write data + * stage packet. + * + * We don't support control write data stages. + * We should never end up here. + */ + + UDCDBG("Stalling unexpected EP0 control write " + "data stage packet"); + udc_stall_ep(0); + } else { + /* + * This rx interrupt must be for a control read status + * stage packet. + */ + UDCDBG("ACK on EP0 control read status stage packet"); + u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff; + usbgetpckfromfifo(0, dummy, len); + } +} + +/* + * Handle endpoint 0 TX interrupt + */ +static void spear_udc_ep0_tx(struct usb_endpoint_instance *endpoint) +{ + struct usb_device_request *request = &ep0_urb->device_request; + int ep_addr; + + UDCDBG("TX on EP0"); + + /* Check direction */ + if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == + USB_REQ_HOST2DEVICE) { + /* + * This tx interrupt must be for a control write status + * stage packet. + */ + UDCDBG("ACK on EP0 control write status stage packet"); + } else { + /* + * This tx interrupt must be for a control read data + * stage packet. + */ + int wLength = le16_to_cpu(request->wLength); + + /* + * Update our count of bytes sent so far in this + * transfer. + */ + endpoint->sent += endpoint->last; + + /* + * We are finished with this transfer if we have sent + * all of the bytes in our tx urb (urb->actual_length) + * unless we need a zero-length terminating packet. We + * need a zero-length terminating packet if we returned + * fewer bytes than were requested (wLength) by the host, + * and the number of bytes we returned is an exact + * multiple of the packet size endpoint->tx_packetSize. + */ + if ((endpoint->sent == ep0_urb->actual_length) && + ((ep0_urb->actual_length == wLength) || + (endpoint->last != endpoint->tx_packetSize))) { + /* Done with control read data stage. */ + UDCDBG("control read data stage complete"); + } else { + /* + * We still have another packet of data to send + * in this control read data stage or else we + * need a zero-length terminating packet. + */ + UDCDBG("ACK control read data stage packet"); + spear_write_noniso_tx_fifo(endpoint); + + ep_addr = endpoint->endpoint_address; + writel(0x0, &inep_regs_p[ep_addr].write_done); + } + } +} + +static struct usb_endpoint_instance *spear_find_ep(int ep) +{ + int i; + + for (i = 0; i < udc_device->bus->max_endpoints; i++) { + if ((udc_device->bus->endpoint_array[i].endpoint_address & + USB_ENDPOINT_NUMBER_MASK) == ep) + return &udc_device->bus->endpoint_array[i]; + } + return NULL; +} + +/* + * Handle RX transaction on non-ISO endpoint. + * The ep argument is a physical endpoint number for a non-ISO IN endpoint + * in the range 1 to 15. + */ +static void spear_udc_epn_rx(int ep) +{ + int nbytes = 0; + struct urb *urb; + struct usb_endpoint_instance *endpoint = spear_find_ep(ep); + + if (endpoint) { + urb = endpoint->rcv_urb; + + if (urb) { + u8 *cp = urb->buffer + urb->actual_length; + + nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) & + 0xfff; + usbgetpckfromfifo(ep, cp, nbytes); + usbd_rcv_complete(endpoint, nbytes, 0); + } + } +} + +/* + * Handle TX transaction on non-ISO endpoint. + * The ep argument is a physical endpoint number for a non-ISO IN endpoint + * in the range 16 to 30. + */ +static void spear_udc_epn_tx(int ep) +{ + struct usb_endpoint_instance *endpoint = spear_find_ep(ep); + + /* + * We need to transmit a terminating zero-length packet now if + * we have sent all of the data in this URB and the transfer + * size was an exact multiple of the packet size. + */ + if (endpoint && endpoint->tx_urb && endpoint->tx_urb->actual_length) { + if (endpoint->last == endpoint->tx_packetSize) { + /* handle zero length packet here */ + writel(0x0, &inep_regs_p[ep].write_done); + } + /* retire the data that was just sent */ + usbd_tx_complete(endpoint); + /* + * Check to see if we have more data ready to transmit + * now. + */ + if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { + /* write data to FIFO */ + spear_write_noniso_tx_fifo(endpoint); + writel(0x0, &inep_regs_p[ep].write_done); + + } else if (endpoint->tx_urb + && (endpoint->tx_urb->actual_length == 0)) { + /* udc_set_nak(ep); */ + } + } +} + +/* + * Start of public functions. + */ + +/* Called to start packet transmission. */ +int udc_endpoint_write(struct usb_endpoint_instance *endpoint) +{ + udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK); + return 0; +} + +/* Start to initialize h/w stuff */ +int udc_init(void) +{ + int i; + u32 plug_st; + + udc_device = NULL; + + UDCDBG("starting"); + + readl(&plug_regs_p->plug_pending); + + udc_disconnect(); + + for (i = 0; i < UDC_INIT_MDELAY; i++) + udelay(1000); + + plug_st = readl(&plug_regs_p->plug_state); + writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state); + + writel(~0x0, &udc_regs_p->endp_int); + writel(~0x0, &udc_regs_p->dev_int_mask); + writel(~0x0, &udc_regs_p->endp_int_mask); + + writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW | + /* Dev_Conf_SYNCFRAME | */ + DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf); + + writel(0x0, &udc_regs_p->dev_cntl); + + /* Clear all interrupts pending */ + writel(DEV_INT_MSK, &udc_regs_p->dev_int); + + return 0; +} + +/* + * udc_setup_ep - setup endpoint + * Associate a physical endpoint with endpoint_instance + */ +void udc_setup_ep(struct usb_device_instance *device, + u32 ep, struct usb_endpoint_instance *endpoint) +{ + UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address); + int ep_addr; + int ep_num, ep_type; + int packet_size; + int buffer_size; + int attributes; + char *tt; + u32 endp_intmask; + + tt = getenv("usbtty"); + if (!tt) + tt = "generic"; + + ep_addr = endpoint->endpoint_address; + ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + + if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* IN endpoint */ + packet_size = endpoint->tx_packetSize; + buffer_size = packet_size * 2; + attributes = endpoint->tx_attributes; + } else { + /* OUT endpoint */ + packet_size = endpoint->rcv_packetSize; + buffer_size = packet_size * 2; + attributes = endpoint->rcv_attributes; + } + + switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { + case USB_ENDPOINT_XFER_CONTROL: + ep_type = ENDP_EPTYPE_CNTL; + break; + case USB_ENDPOINT_XFER_BULK: + default: + ep_type = ENDP_EPTYPE_BULK; + break; + case USB_ENDPOINT_XFER_INT: + ep_type = ENDP_EPTYPE_INT; + break; + case USB_ENDPOINT_XFER_ISOC: + ep_type = ENDP_EPTYPE_ISO; + break; + } + + struct udc_endp_regs *out_p = &outep_regs_p[ep_num]; + struct udc_endp_regs *in_p = &inep_regs_p[ep_num]; + + if (!ep_addr) { + /* Setup endpoint 0 */ + buffer_size = packet_size; + + writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK, + &in_p->endp_cntl); + + writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK, + &out_p->endp_cntl); + + writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl); + + writel(buffer_size / sizeof(int), &in_p->endp_bsorfn); + + writel(packet_size, &in_p->endp_maxpacksize); + + writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl); + + writel(packet_size | ((buffer_size / sizeof(int)) << 16), + &out_p->endp_maxpacksize); + + writel((packet_size << 19) | ENDP_EPTYPE_CNTL, + &udc_regs_p->udc_endp_reg[ep_num]); + + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* Setup the IN endpoint */ + writel(0x0, &in_p->endp_status); + writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl); + writel(buffer_size / sizeof(int), &in_p->endp_bsorfn); + writel(packet_size, &in_p->endp_maxpacksize); + + if (!strcmp(tt, "cdc_acm")) { + if (ep_type == ENDP_EPTYPE_INT) { + /* Conf no. 1 Interface no. 0 */ + writel((packet_size << 19) | + ENDP_EPDIR_IN | (1 << 7) | + (0 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } else { + /* Conf no. 1 Interface no. 1 */ + writel((packet_size << 19) | + ENDP_EPDIR_IN | (1 << 7) | + (1 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } + } else { + /* Conf no. 1 Interface no. 0 */ + writel((packet_size << 19) | + ENDP_EPDIR_IN | (1 << 7) | + (0 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } + + } else { + /* Setup the OUT endpoint */ + writel(0x0, &out_p->endp_status); + writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl); + writel(packet_size | ((buffer_size / sizeof(int)) << 16), + &out_p->endp_maxpacksize); + + if (!strcmp(tt, "cdc_acm")) { + writel((packet_size << 19) | + ENDP_EPDIR_OUT | (1 << 7) | + (1 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } else { + writel((packet_size << 19) | + ENDP_EPDIR_OUT | (1 << 7) | + (0 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } + + } + + endp_intmask = readl(&udc_regs_p->endp_int_mask); + endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num); + writel(endp_intmask, &udc_regs_p->endp_int_mask); +} + +/* Turn on the USB connection by enabling the pullup resistor */ +void udc_connect(void) +{ + u32 plug_st; + + plug_st = readl(&plug_regs_p->plug_state); + plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); + writel(plug_st, &plug_regs_p->plug_state); +} + +/* Turn off the USB connection by disabling the pullup resistor */ +void udc_disconnect(void) +{ + u32 plug_st; + + plug_st = readl(&plug_regs_p->plug_state); + plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); + writel(plug_st, &plug_regs_p->plug_state); +} + +/* Switch on the UDC */ +void udc_enable(struct usb_device_instance *device) +{ + UDCDBGA("enable device %p, status %d", device, device->status); + + /* Save the device structure pointer */ + udc_device = device; + + /* Setup ep0 urb */ + if (!ep0_urb) { + ep0_urb = + usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array); + } else { + serial_printf("udc_enable: ep0_urb already allocated %p\n", + ep0_urb); + } + + writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask); +} + +/** + * udc_startup - allow udc code to do any additional startup + */ +void udc_startup_events(struct usb_device_instance *device) +{ + /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ + usbd_device_event_irq(device, DEVICE_INIT, 0); + + /* + * The DEVICE_CREATE event puts the USB device in the state + * STATE_ATTACHED. + */ + usbd_device_event_irq(device, DEVICE_CREATE, 0); + + /* + * Some USB controller driver implementations signal + * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. + * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, + * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. + * The SPEAr USB client controller has the capability to detect when the + * USB cable is connected to a powered USB bus, so we will defer the + * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later. + */ + + udc_enable(device); +} + +/* + * Plug detection interrupt handling + */ +void spear_udc_plug_irq(void) +{ + if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) { + /* + * USB cable attached + * Turn off PHY reset bit (PLUG detect). + * Switch PHY opmode to normal operation (PLUG detect). + */ + udc_connect(); + writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask); + + UDCDBG("device attached and powered"); + udc_state_transition(udc_device->device_state, STATE_POWERED); + } else { + /* + * USB cable detached + * Reset the PHY and switch the mode. + */ + udc_disconnect(); + writel(~0x0, &udc_regs_p->dev_int_mask); + + UDCDBG("device detached or unpowered"); + udc_state_transition(udc_device->device_state, STATE_ATTACHED); + } +} + +/* + * Device interrupt handling + */ +void spear_udc_dev_irq(void) +{ + if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) { + writel(~0x0, &udc_regs_p->endp_int_mask); + + udc_connect(); + + writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH, + &inep_regs_p[0].endp_cntl); + + writel(DEV_INT_USBRESET, &udc_regs_p->dev_int); + + UDCDBG("device reset in progess"); + udc_state_transition(udc_device->device_state, STATE_DEFAULT); + } + + /* Device Enumeration completed */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) { + writel(DEV_INT_ENUM, &udc_regs_p->dev_int); + + /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */ + writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001, + &udc_regs_p->endp_int_mask); + + UDCDBG("default -> addressed"); + udc_state_transition(udc_device->device_state, STATE_ADDRESSED); + } + + /* The USB will be in SUSPEND in 3 ms */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) { + writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int); + + UDCDBG("entering inactive state"); + /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */ + } + + /* SetConfiguration command received */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) { + writel(DEV_INT_SETCFG, &udc_regs_p->dev_int); + + UDCDBG("entering configured state"); + udc_state_transition(udc_device->device_state, + STATE_CONFIGURED); + } + + /* SetInterface command received */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF) + writel(DEV_INT_SETINTF, &udc_regs_p->dev_int); + + /* USB Suspend detected on cable */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) { + writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int); + + UDCDBG("entering suspended state"); + usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); + } + + /* USB Start-Of-Frame detected on cable */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF) + writel(DEV_INT_SOF, &udc_regs_p->dev_int); +} + +/* + * Endpoint interrupt handling + */ +void spear_udc_endpoint_irq(void) +{ + while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) { + + writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int); + + if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK) + == ENDP_STATUS_OUT_SETUP) { + spear_udc_setup(udc_device->bus->endpoint_array + 0); + writel(ENDP_STATUS_OUT_SETUP, + &outep_regs_p[0].endp_status); + + } else if ((readl(&outep_regs_p[0].endp_status) & + ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { + spear_udc_ep0_rx(udc_device->bus->endpoint_array + 0); + writel(ENDP_STATUS_OUT_DATA, + &outep_regs_p[0].endp_status); + + } else if ((readl(&outep_regs_p[0].endp_status) & + ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) { + /* NONE received */ + } + + writel(0x0, &outep_regs_p[0].endp_status); + } + + if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) { + spear_udc_ep0_tx(udc_device->bus->endpoint_array + 0); + + writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status); + writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int); + } + + while (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) { + u32 epnum = 0; + u32 ep_int = readl(&udc_regs_p->endp_int) & + ENDP_INT_NONISOOUT_MSK; + + ep_int >>= 16; + while (0x0 == (ep_int & 0x1)) { + ep_int >>= 1; + epnum++; + } + + writel((1 << 16) << epnum, &udc_regs_p->endp_int); + + if ((readl(&outep_regs_p[epnum].endp_status) & + ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { + + spear_udc_epn_rx(epnum); + writel(ENDP_STATUS_OUT_DATA, + &outep_regs_p[epnum].endp_status); + } else if ((readl(&outep_regs_p[epnum].endp_status) & + ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) { + writel(0x0, &outep_regs_p[epnum].endp_status); + } + } + + if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) { + u32 epnum = 0; + u32 ep_int = readl(&udc_regs_p->endp_int) & + ENDP_INT_NONISOIN_MSK; + + while (0x0 == (ep_int & 0x1)) { + ep_int >>= 1; + epnum++; + } + + if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) { + writel(ENDP_STATUS_IN, + &outep_regs_p[epnum].endp_status); + spear_udc_epn_tx(epnum); + + writel(ENDP_STATUS_IN, + &outep_regs_p[epnum].endp_status); + } + + writel((1 << epnum), &udc_regs_p->endp_int); + } +} + +/* + * UDC interrupts + */ +void udc_irq(void) +{ + /* + * Loop while we have interrupts. + * If we don't do this, the input chain + * polling delay is likely to miss + * host requests. + */ + while (readl(&plug_regs_p->plug_pending)) + spear_udc_plug_irq(); + + while (readl(&udc_regs_p->dev_int)) + spear_udc_dev_irq(); + + if (readl(&udc_regs_p->endp_int)) + spear_udc_endpoint_irq(); +} + +/* Flow control */ +void udc_set_nak(int epid) +{ + writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK, + &inep_regs_p[epid].endp_cntl); + + writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK, + &outep_regs_p[epid].endp_cntl); +} + +void udc_unset_nak(int epid) +{ + u32 val; + + val = readl(&inep_regs_p[epid].endp_cntl); + val &= ~ENDP_CNTL_SNAK; + val |= ENDP_CNTL_CNAK; + writel(val, &inep_regs_p[epid].endp_cntl); + + val = readl(&outep_regs_p[epid].endp_cntl); + val &= ~ENDP_CNTL_SNAK; + val |= ENDP_CNTL_CNAK; + writel(val, &outep_regs_p[epid].endp_cntl); +} diff --git a/include/usb/spr_udc.h b/include/usb/spr_udc.h new file mode 100755 index 0000000..2c332d5 --- /dev/null +++ b/include/usb/spr_udc.h @@ -0,0 +1,230 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPR_UDC_H +#define __SPR_UDC_H + +/* + * Defines for USBD + * + * The udc_ahb controller has three AHB slaves: + * + * 1. THe UDC registers + * 2. The plug detect + * 3. The RX/TX FIFO + */ + +#define MAX_ENDPOINTS 16 + +struct udc_endp_regs { + u32 endp_cntl; + u32 endp_status; + u32 endp_bsorfn; + u32 endp_maxpacksize; + u32 reserved_1; + u32 endp_desc_point; + u32 reserved_2; + u32 write_done; +}; + +/* Endpoint Control Register definitions */ + +#define ENDP_CNTL_STALL 0x00000001 +#define ENDP_CNTL_FLUSH 0x00000002 +#define ENDP_CNTL_SNOOP 0x00000004 +#define ENDP_CNTL_POLL 0x00000008 +#define ENDP_CNTL_CONTROL 0x00000000 +#define ENDP_CNTL_ISO 0x00000010 +#define ENDP_CNTL_BULK 0x00000020 +#define ENDP_CNTL_INT 0x00000030 +#define ENDP_CNTL_NAK 0x00000040 +#define ENDP_CNTL_SNAK 0x00000080 +#define ENDP_CNTL_CNAK 0x00000100 +#define ENDP_CNTL_RRDY 0x00000200 + +/* Endpoint Satus Register definitions */ + +#define ENDP_STATUS_PIDMSK 0x0000000f +#define ENDP_STATUS_OUTMSK 0x00000030 +#define ENDP_STATUS_OUT_NONE 0x00000000 +#define ENDP_STATUS_OUT_DATA 0x00000010 +#define ENDP_STATUS_OUT_SETUP 0x00000020 +#define ENDP_STATUS_IN 0x00000040 +#define ENDP_STATUS_BUFFNAV 0x00000080 +#define ENDP_STATUS_FATERR 0x00000100 +#define ENDP_STATUS_HOSTBUSERR 0x00000200 +#define ENDP_STATUS_TDC 0x00000400 +#define ENDP_STATUS_RXPKTMSK 0x003ff800 + +struct udc_regs { + struct udc_endp_regs in_regs[MAX_ENDPOINTS]; + struct udc_endp_regs out_regs[MAX_ENDPOINTS]; + u32 dev_conf; + u32 dev_cntl; + u32 dev_stat; + u32 dev_int; + u32 dev_int_mask; + u32 endp_int; + u32 endp_int_mask; + u32 reserved_3[0x39]; + u32 reserved_4; /* offset 0x500 */ + u32 udc_endp_reg[MAX_ENDPOINTS]; +}; + +/* Device Configuration Register definitions */ + +#define DEV_CONF_HS_SPEED 0x00000000 +#define DEV_CONF_LS_SPEED 0x00000002 +#define DEV_CONF_FS_SPEED 0x00000003 +#define DEV_CONF_REMWAKEUP 0x00000004 +#define DEV_CONF_SELFPOW 0x00000008 +#define DEV_CONF_SYNCFRAME 0x00000010 +#define DEV_CONF_PHYINT_8 0x00000020 +#define DEV_CONF_PHYINT_16 0x00000000 +#define DEV_CONF_UTMI_BIDIR 0x00000040 +#define DEV_CONF_STATUS_STALL 0x00000080 + +/* Device Control Register definitions */ + +#define DEV_CNTL_RESUME 0x00000001 +#define DEV_CNTL_TFFLUSH 0x00000002 +#define DEV_CNTL_RXDMAEN 0x00000004 +#define DEV_CNTL_TXDMAEN 0x00000008 +#define DEV_CNTL_DESCRUPD 0x00000010 +#define DEV_CNTL_BIGEND 0x00000020 +#define DEV_CNTL_BUFFILL 0x00000040 +#define DEV_CNTL_TSHLDEN 0x00000080 +#define DEV_CNTL_BURSTEN 0x00000100 +#define DEV_CNTL_DMAMODE 0x00000200 +#define DEV_CNTL_SOFTDISCONNECT 0x00000400 +#define DEV_CNTL_SCALEDOWN 0x00000800 +#define DEV_CNTL_BURSTLENU 0x00010000 +#define DEV_CNTL_BURSTLENMSK 0x00ff0000 +#define DEV_CNTL_TSHLDLENU 0x01000000 +#define DEV_CNTL_TSHLDLENMSK 0xff000000 + +/* Device Status Register definitions */ + +#define DEV_STAT_CFG 0x0000000f +#define DEV_STAT_INTF 0x000000f0 +#define DEV_STAT_ALT 0x00000f00 +#define DEV_STAT_SUSP 0x00001000 +#define DEV_STAT_ENUM 0x00006000 +#define DEV_STAT_ENUM_SPEED_HS 0x00000000 +#define DEV_STAT_ENUM_SPEED_FS 0x00002000 +#define DEV_STAT_ENUM_SPEED_LS 0x00004000 +#define DEV_STAT_RXFIFO_EMPTY 0x00008000 +#define DEV_STAT_PHY_ERR 0x00010000 +#define DEV_STAT_TS 0xf0000000 + +/* Device Interrupt Register definitions */ + +#define DEV_INT_MSK 0x0000007f +#define DEV_INT_SETCFG 0x00000001 +#define DEV_INT_SETINTF 0x00000002 +#define DEV_INT_INACTIVE 0x00000004 +#define DEV_INT_USBRESET 0x00000008 +#define DEV_INT_SUSPUSB 0x00000010 +#define DEV_INT_SOF 0x00000020 +#define DEV_INT_ENUM 0x00000040 + +/* Endpoint Interrupt Register definitions */ + +#define ENDP0_INT_CTRLIN 0x00000001 +#define ENDP1_INT_BULKIN 0x00000002 +#define ENDP_INT_NONISOIN_MSK 0x0000AAAA +#define ENDP2_INT_BULKIN 0x00000004 +#define ENDP0_INT_CTRLOUT 0x00010000 +#define ENDP1_INT_BULKOUT 0x00020000 +#define ENDP2_INT_BULKOUT 0x00040000 +#define ENDP_INT_NONISOOUT_MSK 0x55540000 + +/* Endpoint Register definitions */ +#define ENDP_EPDIR_OUT 0x00000000 +#define ENDP_EPDIR_IN 0x00000010 +#define ENDP_EPTYPE_CNTL 0x0 +#define ENDP_EPTYPE_ISO 0x1 +#define ENDP_EPTYPE_BULK 0x2 +#define ENDP_EPTYPE_INT 0x3 + +/* + * Defines for Plug Detect + */ + +struct plug_regs { + u32 plug_state; + u32 plug_pending; +}; + +/* Plug State Register definitions */ +#define PLUG_STATUS_EN 0x1 +#define PLUG_STATUS_ATTACHED 0x2 +#define PLUG_STATUS_PHY_RESET 0x4 +#define PLUG_STATUS_PHY_MODE 0x8 + +/* + * Defines for UDC FIFO (Slave Mode) + */ +struct udcfifo_regs { + u32 *fifo_p; +}; + +/* + * USBTTY definitions + */ +#define EP0_MAX_PACKET_SIZE 64 +#define UDC_INT_ENDPOINT 1 +#define UDC_INT_PACKET_SIZE 64 +#define UDC_OUT_ENDPOINT 2 +#define UDC_BULK_PACKET_SIZE 64 +#define UDC_IN_ENDPOINT 3 +#define UDC_OUT_PACKET_SIZE 64 +#define UDC_IN_PACKET_SIZE 64 + +/* + * UDC endpoint definitions + */ +#define UDC_EP0 0 +#define UDC_EP1 1 +#define UDC_EP2 2 +#define UDC_EP3 3 + +/* + * Function declarations + */ + +void udc_irq(void); + +void udc_set_nak(int epid); +void udc_unset_nak(int epid); +int udc_endpoint_write(struct usb_endpoint_instance *endpoint); +int udc_init(void); +void udc_enable(struct usb_device_instance *device); +void udc_disable(void); +void udc_connect(void); +void udc_disconnect(void); +void udc_startup_events(struct usb_device_instance *device); +void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, + struct usb_endpoint_instance *endpoint); + +#endif /* __SPR_UDC_H */

This patch adds the support to read and write mac id from i2c memory. For reading: if (env contains ethaddr) pick env ethaddr else pick ethaddr from i2c memory For writing: chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id in i2c memory

Signed-off-by: Vipin vipin.kumar@st.com --- board/spear/common/spr_misc.c | 68 ++++++++++++++++++++++++++++++++- include/asm-arm/arch-spear/spr_defs.h | 8 ++++ 2 files changed, 75 insertions(+), 1 deletions(-)

diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index dfa3ece..204ccf2 100755 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -67,6 +67,12 @@ int dram_init(void)

int misc_init_r(void) { +#if defined(CONFIG_CMD_NET) + uchar mac_id[6]; + + if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id)) + eth_setenv_enetaddr("ethaddr", mac_id); +#endif setenv("verify", "n");

#if defined(CONFIG_SPEAR_USBTTY) @@ -101,12 +107,54 @@ int spear_board_init(ulong mach_type) return 0; }

+static int i2c_read_mac(uchar *buffer) +{ + u8 buf[2]; + + i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); + + /* Check if mac in i2c memory is valid */ + if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { + /* Valid mac address is saved in i2c eeprom */ + i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN); + return 0; + } + + return -1; +} + +static int write_mac(uchar *mac) +{ + u8 buf[2]; + + buf[0] = (u8)MAGIC_BYTE0; + buf[1] = (u8)MAGIC_BYTE1; + i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); + + buf[0] = (u8)~MAGIC_BYTE0; + buf[1] = (u8)~MAGIC_BYTE1; + + i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); + + /* check if valid MAC address is saved in I2C EEPROM or not? */ + if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { + i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN); + puts("I2C EEPROM written with mac address \n"); + return 0; + } + + puts("I2C EEPROM writing failed \n"); + return -1; +} + int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { void (*sram_setfreq) (unsigned int, unsigned int); struct chip_data *chip = &chip_data; unsigned char mac[6]; - unsigned int frequency; + unsigned int reg, frequency; + char *s, *e; + char i2c_mac[20];

if ((argc > 3) || (argc < 2)) { cmd_usage(cmdtp); @@ -137,6 +185,17 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) }

return 0; + } else if (!strcmp(argv[1], "ethaddr")) { + + s = argv[2]; + for (reg = 0; reg < 6; ++reg) { + mac[reg] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + write_mac(mac); + + return 0; } else if (!strcmp(argv[1], "print")) {

if (chip->cpufreq == -1) @@ -156,6 +215,13 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else printf("DDR Type = Not Known\n");

+ if (!i2c_read_mac(mac)) { + sprintf(i2c_mac, "%pM", mac); + printf("Ethaddr (from i2c mem) = %s\n", i2c_mac); + } else { + printf("Ethaddr (from i2c mem) = Not set\n"); + } + printf("Xloader Rev = %s\n", chip->version);

return 0; diff --git a/include/asm-arm/arch-spear/spr_defs.h b/include/asm-arm/arch-spear/spr_defs.h index 9dde54a..fa8412c 100644 --- a/include/asm-arm/arch-spear/spr_defs.h +++ b/include/asm-arm/arch-spear/spr_defs.h @@ -35,4 +35,12 @@ struct chip_data { uchar version[32]; };

+/* HW mac id in i2c memory definitions */ +#define MAGIC_OFF 0x0 +#define MAGIC_LEN 0x2 +#define MAGIC_BYTE0 0x55 +#define MAGIC_BYTE1 0xAA +#define MAC_OFF 0x2 +#define MAC_LEN 0x6 + #endif

SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface Paraller NOR flashes. This patch adds the support for this IP

The standard CFI driver is used to interface with NOR flashes

Signed-off-by: Vipin vipin.kumar@st.com --- board/spear/common/spr_misc.c | 59 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_emi.h | 54 +++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+), 0 deletions(-) create mode 100644 include/asm-arm/arch-spear/spr_emi.h

diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 204ccf2..e356912 100755 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -27,6 +27,7 @@ #include <net.h> #include <asm/io.h> #include <asm/arch/hardware.h> +#include <asm/arch/spr_emi.h> #include <asm/arch/spr_xloader_table.h> #include <asm/arch/spr_defs.h>

@@ -83,6 +84,61 @@ int misc_init_r(void) return 0; }

+#ifdef CONFIG_SPEAR_EMI +struct cust_emi_para { + unsigned int tap; + unsigned int tsdp; + unsigned int tdpw; + unsigned int tdpr; + unsigned int tdcs; +}; + +/* EMI timing setting of m28w640hc of linux kernel */ +const struct cust_emi_para emi_timing_m28w640hc = { + .tap = 0x10, + .tsdp = 0x05, + .tdpw = 0x0a, + .tdpr = 0x0a, + .tdcs = 0x05, +}; + +/* EMI timing setting of bootrom */ +const struct cust_emi_para emi_timing_bootrom = { + .tap = 0xf, + .tsdp = 0x0, + .tdpw = 0xff, + .tdpr = 0x111, + .tdcs = 0x02, +}; + +void spear_emi_init(void) +{ + const struct cust_emi_para *p = &emi_timing_m28w640hc; + struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE; + unsigned int cs; + unsigned int val, tmp; + + val = readl(CONFIG_SPEAR_RASBASE); + + if (val & EMI_ACKMSK) + tmp = 0x3f; + else + tmp = 0x0; + + writel(tmp, &emi_regs_p->ack); + + for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) { + writel(p->tap, &emi_regs_p->bank_regs[cs].tap); + writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp); + writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw); + writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr); + writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs); + writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3), + &emi_regs_p->bank_regs[cs].control); + } +} +#endif + int spear_board_init(ulong mach_type) { struct xloader_table *xloader_tb = @@ -104,6 +160,9 @@ int spear_board_init(ulong mach_type) sizeof(chip->version)); }

+#ifdef CONFIG_SPEAR_EMI + spear_emi_init(); +#endif return 0; }

diff --git a/include/asm-arm/arch-spear/spr_emi.h b/include/asm-arm/arch-spear/spr_emi.h new file mode 100644 index 0000000..c1f1c2a --- /dev/null +++ b/include/asm-arm/arch-spear/spr_emi.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2009 + * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPEAR_EMI_H__ +#define __SPEAR_EMI_H__ + +#ifdef CONFIG_SPEAR_EMI + +struct emi_bank_regs { + u32 tap; + u32 tsdp; + u32 tdpw; + u32 tdpr; + u32 tdcs; + u32 control; +}; + +struct emi_regs { + struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS]; + u32 tout; + u32 ack; + u32 irq; +}; + +#define EMI_ACKMSK 0x40 + +/* control register definitions */ +#define EMI_CNTL_ENBBYTEW (1 << 2) +#define EMI_CNTL_ENBBYTER (1 << 3) +#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW) + +#endif + +#endif

SPEAr320 SoC support contains basic spear320 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver - emi driver(cfi support)

Signed-off-by: Vipin vipin.kumar@st.com --- MAKEALL | 1 + Makefile | 3 +- board/spear/spear320/Makefile | 51 +++++++++++++++++++++++++++++++++ board/spear/spear320/config.mk | 44 +++++++++++++++++++++++++++++ board/spear/spear320/spear320.c | 59 +++++++++++++++++++++++++++++++++++++++ include/configs/spear3xx.h | 29 +++++++++++++++++++ 6 files changed, 186 insertions(+), 1 deletions(-) create mode 100755 board/spear/spear320/Makefile create mode 100755 board/spear/spear320/config.mk create mode 100755 board/spear/spear320/spear320.c

diff --git a/MAKEALL b/MAKEALL index c605f71..270861b 100755 --- a/MAKEALL +++ b/MAKEALL @@ -576,6 +576,7 @@ LIST_ARM9=" \ smdk2410 \ spear300 \ spear310 \ + spear320 \ spear600 \ trab \ VCMA9 \ diff --git a/Makefile b/Makefile index 14b0b82..3b4386b 100644 --- a/Makefile +++ b/Makefile @@ -3029,7 +3029,8 @@ smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0

spear300_config \ -spear310_config : unconfig +spear310_config \ +spear320_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx arm arm926ejs $(@:_config=) spear spear

spear600_config : unconfig diff --git a/board/spear/spear320/Makefile b/board/spear/spear320/Makefile new file mode 100755 index 0000000..1b80586 --- /dev/null +++ b/board/spear/spear320/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := spear320.o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk new file mode 100755 index 0000000..cba8436 --- /dev/null +++ b/board/spear/spear320/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2009 +# Vipin Kumar, ST Microelectronics vipin.kumar@st.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +TEXT_BASE = 0x00700000 + +ALL += $(obj)u-boot.img + +# Environment variables in NAND +ifeq ($(ENV),NAND) +PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND +else +PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH +endif + +# Support parallel flash +ifeq ($(FLASH),PNOR) +PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR +endif + +ifeq ($(CONSOLE),USB) +PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY +endif diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c new file mode 100755 index 0000000..756aa56 --- /dev/null +++ b/board/spear/spear320/spear320.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2009 + * Ryan Chen, ST Micoelectronics, ryan.chen@st.com. + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_nand.h> + +int board_init(void) +{ + return spear_board_init(MACH_TYPE_SPEAR300); +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +int board_nand_init(struct nand_chip *nand) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG30) || + ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG31)) { + + return spear_nand_init(nand); + } + + return -1; +} diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index d25f12a..0248aba 100755 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -34,6 +34,9 @@ #elif defined(CONFIG_MK_spear310) #define CONFIG_SPEAR3XX 1 #define CONFIG_SPEAR310 1 +#elif defined(CONFIG_MK_spear320) +#define CONFIG_SPEAR3XX 1 +#define CONFIG_SPEAR320 1 #endif

#include <configs/spear-common.h> @@ -62,6 +65,18 @@ (void *)CONFIG_SYS_SERIAL3, \ (void *)CONFIG_SYS_SERIAL4, \ (void *)CONFIG_SYS_SERIAL5 } +#elif defined(CONFIG_SPEAR320) + +#if (CONFIG_CONS_INDEX) +#undef CONFIG_PL011_CLOCK +#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) +#endif + +#define CONFIG_SYS_SERIAL1 0xA3000000 +#define CONFIG_SYS_SERIAL2 0xA4000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2 } #endif

#if defined(CONFIG_SPEAR_EMI) @@ -84,6 +99,17 @@ CONFIG_SYS_CS5_FLASH_BASE } #define CONFIG_SYS_MAX_FLASH_BANKS 6

+#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_FLASH_BASE 0x44000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000 +#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000 +#define CONFIG_SYS_CS3_FLASH_BASE 0x47000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE, \ + CONFIG_SYS_CS2_FLASH_BASE, \ + CONFIG_SYS_CS3_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 4 + #endif

#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) @@ -97,6 +123,9 @@ #elif defined(CONFIG_SPEAR310) #define CONFIG_SYS_NAND_BASE (0x40000000)

+#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_NAND_BASE (0x50000000) + #endif

#endif /* __CONFIG_H */

On 1/18/2010 11:45 AM, Ben Warren wrote:

...

int misc_init_r(void) { +#if defined(CONFIG_CMD_NET)

• uchar mac_id[6];
• if (!eth_getenv_enetaddr("ethaddr", mac_id) &&

!i2c_read_mac(mac_id))

•    eth_setenv_enetaddr("ethaddr", mac_id);
  
  

It's really not a good idea to programatically set an environment variable like this. Also, there's already a well-defined and documented protocol for how MAC addresses should be read and the precedence between EEPROM storage and environment storage. Please find a way to fit into that model. Since you don't have network support yet, I have no idea which network controller you're using, and recommend waiting until this is really needed.

I am referring to doc/README.enetaddr in the uboot source. This document says "If the hardware design mandates that the MAC address is stored in some special place (like EEPROM etc...), then the board specific init code (such as the board-specific misc_init_r() function) is responsible for locating the MAC address(es) and initializing the respective environment variable(s) from it. Note that this shall be done if, and only if, the environment does not already contain these environment variables, i.e. existing variable definitions must not be overwritten."

Coming back to the code if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id)) eth_setenv_enetaddr("ethaddr", mac_id);

first I read the env variable "ethaddr" and skip setting it if it already exists then I read mac id from i2c memory and store the same in env variable

Please let me know if I am missing anything.

Although the patch is not really needed right now, it will be needed soon. I am planning to send the net support patch during the next merging window. Since the current patch does not have any side effects, it can be included as of now.

...

     if (chip->cpufreq == -1)

@@ -156,6 +215,13 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else printf("DDR Type = Not Known\n");

•    if (!i2c_read_mac(mac)) {
  

•        sprintf(i2c_mac, "%pM", mac);
  

•        printf("Ethaddr (from i2c mem) = %s\n", i2c_mac);
  
  

Maybe I'm missing some context, but why's the sprintf needed?

Yes, sprintf is not needed here Thanks for pointing out

Regards Vipin

On 1/18/2010 12:49 PM, Ben Warren wrote:

...

...

...

     if (chip->cpufreq == -1)

@@ -156,6 +215,13 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else printf("DDR Type = Not Known\n");

•    if (!i2c_read_mac(mac)) {
  

•        sprintf(i2c_mac, "%pM", mac);
  

•        printf("Ethaddr (from i2c mem) = %s\n", i2c_mac);
  
  

Maybe I'm missing some context, but why's the sprintf needed?

Yes, sprintf is not needed here Thanks for pointing out

Hello Tom, Should I send the whole patch set again or only the subpatch after removing the sprintf

Regards Vipin

On Monday 18 January 2010 01:15:43 Ben Warren wrote:

Vipin KUMAR wrote:

...

This patch adds the support to read and write mac id from i2c memory. For reading: if (env contains ethaddr) pick env ethaddr else pick ethaddr from i2c memory For writing: chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id in i2c memory

--- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -67,6 +67,12 @@ int dram_init(void)

int misc_init_r(void) { +#if defined(CONFIG_CMD_NET)

• uchar mac_id[6];
• if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))

• eth_setenv_enetaddr("ethaddr", mac_id);
  

It's really not a good idea to programatically set an environment variable like this. Also, there's already a well-defined and documented protocol for how MAC addresses should be read and the precedence between EEPROM storage and environment storage. Please find a way to fit into that model. Since you don't have network support yet, I have no idea which network controller you're using, and recommend waiting until this is really needed.

he's doing it the way doc/README.enetaddr suggests ... -mike