[PATCH 1/2] clk: imx8mp: Update clocks based on kernel 6.4-RC4
There are some newer clocks added to the kernel recently, so to fix prepare for resycing the device trees, update the clock list. Since there are some minor changes to the USB clocks, update which USB clocks are enabled to match with the upstream kernel as well.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 09bef596f2..a21a3ce34b 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,7 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); - clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "usb_core_ref", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde..3f28ce685f 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319 - -#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
Several changes have been made to the device tree in the kernel, so update that as well as the corresponding imx8mp-u-boot.dtsi files to prevent breaking the booting.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 18d1728e1d..dfb747bb02 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -44,6 +44,9 @@
&aips3 { bootph-pre-ram; + spba-bus@30800000 { + bootph-pre-ram; + }; };
&iomuxc { diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948..428c60462e 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@
A53_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>; @@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; };
@@ -406,12 +409,36 @@ status = "disabled"; };
+ gpt1: timer@302d0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; + clock-names = "ipg", "per"; + }; + + gpt2: timer@302e0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; + clock-names = "ipg", "per"; + }; + + gpt3: timer@302f0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; + clock-names = "ipg", "per"; + }; + iomuxc: pinctrl@30330000 { compatible = "fsl,imx8mp-iomuxc"; reg = <0x30330000 0x10000>; };
- gpr: iomuxc-gpr@30340000 { + gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -424,27 +451,44 @@ #address-cells = <1>; #size-cells = <1>;
- imx8mp_uid: unique-id@420 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x8 0x8> describes fuses 0x420 and + * 0x430). + */ + imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; };
- cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
- eth_mac1: mac-address@90 { + eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; };
- eth_mac2: mac-address@96 { + eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; }; + + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ + reg = <0x264 0x10>; + }; };
- anatop: anatop@30360000 { - compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; };
snvs: snvs@30370000 { @@ -523,6 +567,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;
@@ -589,7 +634,7 @@ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; };
- pgc_hsiomix: power-domains@17 { + pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; clocks = <&clk IMX8MP_CLK_HSIO_AXI>, @@ -631,6 +676,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; + + pgc_mlmix: power-domain@24 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_MLMIX>; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + }; }; }; }; @@ -693,6 +746,30 @@ clocks = <&osc_24m>; clock-names = "per"; }; + + gpt6: timer@306e0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x306e0000 0x10000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; + clock-names = "ipg", "per"; + }; + + gpt5: timer@306f0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x306f0000 0x10000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; + clock-names = "ipg", "per"; + }; + + gpt4: timer@30700000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x30700000 0x10000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; + clock-names = "ipg", "per"; + }; };
aips3: bus@30800000 { @@ -702,112 +779,129 @@ #size-cells = <1>; ranges;
- ecspi1: spi@30820000 { + spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30800000 0x100000>; #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, - <&clk IMX8MP_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + #size-cells = <1>; + ranges;
- ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, - <&clk IMX8MP_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, + <&clk IMX8MP_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, - <&clk IMX8MP_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, + <&clk IMX8MP_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- uart1: serial@30860000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_UART1_ROOT>, - <&clk IMX8MP_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, + <&clk IMX8MP_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- uart3: serial@30880000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_UART3_ROOT>, - <&clk IMX8MP_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART1_ROOT>, + <&clk IMX8MP_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- uart2: serial@30890000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_UART2_ROOT>, - <&clk IMX8MP_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart3: serial@30880000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART3_ROOT>, + <&clk IMX8MP_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- flexcan1: can@308c0000 { - compatible = "fsl,imx8mp-flexcan"; - reg = <0x308c0000 0x10000>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_IPG_ROOT>, - <&clk IMX8MP_CLK_CAN1_ROOT>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8MP_CLK_CAN1>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&gpr 0x10 4>; - status = "disabled"; - }; + uart2: serial@30890000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_UART2_ROOT>, + <&clk IMX8MP_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + };
- flexcan2: can@308d0000 { - compatible = "fsl,imx8mp-flexcan"; - reg = <0x308d0000 0x10000>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_IPG_ROOT>, - <&clk IMX8MP_CLK_CAN2_ROOT>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8MP_CLK_CAN2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&gpr 0x10 5>; - status = "disabled"; + flexcan1: can@308c0000 { + compatible = "fsl,imx8mp-flexcan"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 4>; + status = "disabled"; + }; + + flexcan2: can@308d0000 { + compatible = "fsl,imx8mp-flexcan"; + reg = <0x308d0000 0x10000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 5>; + status = "disabled"; + }; };
crypto: crypto@30900000 { @@ -1063,11 +1157,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2";
- opp-200M { + opp-200000000 { opp-hz = /bits/ 64 <200000000>; };
- opp-1000M { + opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; }; @@ -1080,10 +1174,78 @@ #size-cells = <1>; ranges;
+ mipi_dsi: dsi@32e60000 { + compatible = "fsl,imx8mp-mipi-dsim"; + reg = <0x32e60000 0x400>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <200000000>, <24000000>; + samsung,pll-clock-frequency = <24000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif1: endpoint { + remote-endpoint = <&lcdif1_to_dsim>; + }; + }; + }; + }; + + lcdif1: display-controller@32e80000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32e80000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; + status = "disabled"; + + port { + lcdif1_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif1>; + }; + }; + }; + + lcdif2: display-controller@32e90000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32e90000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; + status = "disabled"; + + port { + lcdif2_to_ldb: endpoint { + remote-endpoint = <&ldb_from_lcdif2>; + }; + }; + }; + media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; reg = <0x32ec0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>, @@ -1122,12 +1284,55 @@ "disp1", "disp2", "isp", "phy";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, - <&clk IMX8MP_CLK_MEDIA_APB>; + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <500000000>, <200000000>; - + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_VIDEO_PLL1_OUT>; + assigned-clock-rates = <500000000>, <200000000>, + <0>, <0>, <1039500000>; #power-domain-cells = <1>; + + lvds_bridge: bridge@5c { + compatible = "fsl,imx8mp-ldb"; + reg = <0x5c 0x4>, <0x128 0x4>; + reg-names = "ldb", "lvds"; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ldb_from_lcdif2: endpoint { + remote-endpoint = <&lcdif2_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + }; + }; + + port@2 { + reg = <2>; + + ldb_lvds_ch1: endpoint { + }; + }; + }; + }; };
pcie_phy: pcie-phy@32f00000 { @@ -1158,6 +1363,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>; + #clock-cells = <0>; }; };
@@ -1165,6 +1371,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -1192,6 +1405,32 @@ status = "disabled"; };
+ pcie_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; + reg-names = "dbi", "addr_space"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + num-lanes = <1>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gpu3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; @@ -1223,6 +1462,28 @@ power-domains = <&pgc_gpu2d>; };
+ vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mm-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>; + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; + }; + vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>; @@ -1234,6 +1495,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; + assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; @@ -1279,7 +1543,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; @@ -1292,9 +1556,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>; - clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>; @@ -1321,7 +1585,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; @@ -1334,9 +1598,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>; - clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>, - <&clk IMX8MP_CLK_USB_ROOT>; + <&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>;
On Tue, May 30, 2023 at 7:46 PM Adam Ford aford173@gmail.com wrote:
Several changes have been made to the device tree in the kernel, so update that as well as the corresponding imx8mp-u-boot.dtsi files to prevent breaking the booting.
Signed-off-by: Adam Ford aford173@gmail.com
Reviewed-by: Fabio Estevam festevam@denx.de
Several changes have been made to the device tree in the kernel, so update that as well as the corresponding imx8mp-u-boot.dtsi files to prevent breaking the booting. Signed-off-by: Adam Ford aford173@gmail.com Reviewed-by: Fabio Estevam festevam@denx.de diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 18d1728e1d..dfb747bb02 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -44,6 +44,9 @@
&aips3 { bootph-pre-ram;
- spba-bus@30800000 {
bootph-pre-ram;- };
};
&iomuxc { diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index bb916a0948..428c60462e 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -123,6 +123,7 @@
A53_L2: l2-cache0 { compatible = "cache";
cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>;@@ -379,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; };@@ -406,12 +409,36 @@ status = "disabled"; };
gpt1: timer@302d0000 {compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";reg = <0x302d0000 0x10000>;interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;clock-names = "ipg", "per";};gpt2: timer@302e0000 {compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";reg = <0x302e0000 0x10000>;interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;clock-names = "ipg", "per";};gpt3: timer@302f0000 {compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";reg = <0x302f0000 0x10000>;interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;clock-names = "ipg", "per";};iomuxc: pinctrl@30330000 { compatible = "fsl,imx8mp-iomuxc"; reg = <0x30330000 0x10000>; };
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 { compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; };@@ -424,27 +451,44 @@ #address-cells = <1>; #size-cells = <1>;
imx8mp_uid: unique-id@420 {
/** The register address below maps to the MX8M* Fusemap Description Table entries this way.* Assuming* reg = <ADDR SIZE>;* then* Fuse Address = (ADDR * 4) + 0x400* Note that if SIZE is greater than 4, then* each subsequent fuse is located at offset* +0x10 in Fusemap Description Table (e.g.* reg = <0x8 0x8> describes fuses 0x420 and* 0x430).*/imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; };
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; };
eth_mac1: mac-address@90 {
eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; };
eth_mac2: mac-address@96 {
eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; };tmu_calib: calib@264 { /* 0xd90-0xdc0 */reg = <0x264 0x10>;}; };
anatop: anatop@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop","syscon";
anatop: clock-controller@30360000 {compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>;#clock-cells = <1>; }; snvs: snvs@30370000 {@@ -523,6 +567,7 @@ compatible = "fsl,imx8mp-gpc"; reg = <0x303a0000 0x1000>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>;@@ -589,7 +634,7 @@ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; };
pgc_hsiomix: power-domains@17 {
pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; clocks = <&clk IMX8MP_CLK_HSIO_AXI>,@@ -631,6 +676,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; };
pgc_mlmix: power-domain@24 {#power-domain-cells = <0>;reg = <IMX8MP_POWER_DOMAIN_MLMIX>;clocks = <&clk IMX8MP_CLK_ML_AXI>,<&clk IMX8MP_CLK_ML_AHB>,<&clk IMX8MP_CLK_NPU_ROOT>;}; }; };@@ -693,6 +746,30 @@ clocks = <&osc_24m>; clock-names = "per"; };
gpt6: timer@306e0000 {compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";reg = <0x306e0000 0x10000>;interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;clock-names = "ipg", "per";};gpt5: timer@306f0000 {compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";reg = <0x306f0000 0x10000>;interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;clock-names = "ipg", "per";};gpt4: timer@30700000 {compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";reg = <0x30700000 0x10000>;interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;clock-names = "ipg", "per";};};
aips3: bus@30800000 {
@@ -702,112 +779,129 @@ #size-cells = <1>; ranges;
ecspi1: spi@30820000 {
spba-bus@30800000 {compatible = "fsl,spba-bus", "simple-bus";reg = <0x30800000 0x100000>; #address-cells = <1>;
#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
#size-cells = <1>;ranges;
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi1: spi@30820000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30820000 0x10000>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,<&clk IMX8MP_CLK_ECSPI1_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
ecspi2: spi@30830000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30830000 0x10000>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,<&clk IMX8MP_CLK_ECSPI2_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
ecspi3: spi@30840000 {#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";reg = <0x30840000 0x10000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,<&clk IMX8MP_CLK_ECSPI3_ROOT>;clock-names = "ipg", "per";assigned-clock-rates = <80000000>;assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart1: serial@30860000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30860000 0x10000>;interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART1_ROOT>,<&clk IMX8MP_CLK_UART1_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
uart3: serial@30880000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30880000 0x10000>;interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART3_ROOT>,<&clk IMX8MP_CLK_UART3_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};
uart2: serial@30890000 {compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";reg = <0x30890000 0x10000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_UART2_ROOT>,<&clk IMX8MP_CLK_UART2_ROOT>;clock-names = "ipg", "per";dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;dma-names = "rx", "tx";status = "disabled";};
flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";
flexcan1: can@308c0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308c0000 0x10000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN1_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN1>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 4>;status = "disabled";};flexcan2: can@308d0000 {compatible = "fsl,imx8mp-flexcan";reg = <0x308d0000 0x10000>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_IPG_ROOT>,<&clk IMX8MP_CLK_CAN2_ROOT>;clock-names = "ipg", "per";assigned-clocks = <&clk IMX8MP_CLK_CAN2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;assigned-clock-rates = <40000000>;fsl,clk-source = /bits/ 8 <0>;fsl,stop-mode = <&gpr 0x10 5>;status = "disabled";}; }; crypto: crypto@30900000 {@@ -1063,11 +1157,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2";
opp-200M {
opp-200000000 { opp-hz = /bits/ 64 <200000000>; };
opp-1000M {
opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; };@@ -1080,10 +1174,78 @@ #size-cells = <1>; ranges;
mipi_dsi: dsi@32e60000 {compatible = "fsl,imx8mp-mipi-dsim";reg = <0x32e60000 0x400>;clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;clock-names = "bus_clk", "sclk_mipi";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,<&clk IMX8MP_CLK_24M>;assigned-clock-rates = <200000000>, <24000000>;samsung,pll-clock-frequency = <24000000>;interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;dsim_from_lcdif1: endpoint {remote-endpoint = <&lcdif1_to_dsim>;};};};};lcdif1: display-controller@32e80000 {compatible = "fsl,imx8mp-lcdif";reg = <0x32e80000 0x10000>;clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;clock-names = "pix", "axi", "disp_axi";interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;status = "disabled";port {lcdif1_to_dsim: endpoint {remote-endpoint = <&dsim_from_lcdif1>;};};};lcdif2: display-controller@32e90000 {compatible = "fsl,imx8mp-lcdif";reg = <0x32e90000 0x10000>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;clock-names = "pix", "axi", "disp_axi";power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;status = "disabled";port {lcdif2_to_ldb: endpoint {remote-endpoint = <&ldb_from_lcdif2>;};};};media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; reg = <0x32ec0000 0x10000>;#address-cells = <1>;#size-cells = <1>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, <&pgc_mipi_phy1>,@@ -1122,12 +1284,55 @@ "disp1", "disp2", "isp", "phy";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
<&clk IMX8MP_CLK_MEDIA_APB>,<&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,<&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,<&clk IMX8MP_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>;assigned-clock-rates = <500000000>, <200000000>;
<&clk IMX8MP_SYS_PLL1_800M>,<&clk IMX8MP_VIDEO_PLL1_OUT>,<&clk IMX8MP_VIDEO_PLL1_OUT>;assigned-clock-rates = <500000000>, <200000000>,<0>, <0>, <1039500000>; #power-domain-cells = <1>;lvds_bridge: bridge@5c {compatible = "fsl,imx8mp-ldb";reg = <0x5c 0x4>, <0x128 0x4>;reg-names = "ldb", "lvds";clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;clock-names = "ldb";assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;ldb_from_lcdif2: endpoint {remote-endpoint = <&lcdif2_to_ldb>;};};port@1 {reg = <1>;ldb_lvds_ch0: endpoint {};};port@2 {reg = <2>;ldb_lvds_ch1: endpoint {};};};}; }; pcie_phy: pcie-phy@32f00000 {@@ -1158,6 +1363,7 @@ <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>;
#clock-cells = <0>; };@@ -1165,6 +1371,13 @@ compatible = "fsl,imx8mp-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,<&clk IMX8MP_CLK_HSIO_AXI>,<&clk IMX8MP_CLK_PCIE_ROOT>;clock-names = "pcie", "pcie_bus", "pcie_aux";assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;assigned-clock-rates = <10000000>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; #address-cells = <3>; #size-cells = <2>; device_type = "pci";@@ -1192,6 +1405,32 @@ status = "disabled"; };
pcie_ep: pcie-ep@33800000 {compatible = "fsl,imx8mp-pcie-ep";reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;reg-names = "dbi", "addr_space";clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,<&clk IMX8MP_CLK_HSIO_AXI>,<&clk IMX8MP_CLK_PCIE_ROOT>;clock-names = "pcie", "pcie_bus", "pcie_aux";assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;assigned-clock-rates = <10000000>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;num-lanes = <1>;interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */interrupt-names = "dma";fsl,max-link-speed = <3>;power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,<&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;reset-names = "apps", "turnoff";phys = <&pcie_phy>;phy-names = "pcie-phy";num-ib-windows = <4>;num-ob-windows = <4>;status = "disabled";};- gpu3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>;
@@ -1223,6 +1462,28 @@ power-domains = <&pgc_gpu2d>; };
vpu_g1: video-codec@38300000 {compatible = "nxp,imx8mm-vpu-g1";reg = <0x38300000 0x10000>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;};vpu_g2: video-codec@38310000 {compatible = "nxp,imx8mq-vpu-g2";reg = <0x38310000 0x10000>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;assigned-clock-rates = <500000000>;power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;};- vpumix_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>;
@@ -1234,6 +1495,9 @@ <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clock-names = "g1", "g2", "vc8000e";
assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;assigned-clock-rates = <600000000>, <600000000>; interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;@@ -1279,7 +1543,7 @@ reg = <0x32f10100 0x8>, <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1292,9 +1556,9 @@ usb_dwc3_0: usb@38100000 { compatible = "snps,dwc3"; reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>;@@ -1321,7 +1585,7 @@ reg = <0x32f10108 0x8>, <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;@@ -1334,9 +1598,9 @@ usb_dwc3_1: usb@38200000 { compatible = "snps,dwc3"; reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>, <&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>; clock-names = "bus_early", "ref", "suspend"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>;
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
On Tue, May 30, 2023 at 7:46 PM Adam Ford aford173@gmail.com wrote:
There are some newer clocks added to the kernel recently, so to fix prepare for resycing the device trees, update the clock list. Since there are some minor changes to the USB clocks, update which USB clocks are enabled to match with the upstream kernel as well.
Signed-off-by: Adam Ford aford173@gmail.com
Reviewed-by: Fabio Estevam festevam@denx.de
On Tue, May 30, 2023 at 3:46 PM Adam Ford aford173@gmail.com wrote:
There are some newer clocks added to the kernel recently, so to fix prepare for resycing the device trees, update the clock list. Since there are some minor changes to the USB clocks, update which USB clocks are enabled to match with the upstream kernel as well.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 09bef596f2..a21a3ce34b 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,7 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "usb_core_ref", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0));clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde..3f28ce685f 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
2.39.2
Adam,
This series does update the imx8mp.dtsi as well as provide functioning USB for me on imx8mp-venice-gw74xx.
For both: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx
I do still see a clk already disabled message on usb stop (which was there before also but I believe the sync of the imx8mm.dtsi resolved the one on imx8mm). I'm curious if you see this as well: u-boot=> usb start && usb tree starting USB... Bus usb@38200000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus usb@38200000 for devices... 4 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found USB device tree: 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Hub (480 Mb/s, 0mA) | | Microchip Tech USB2744 | | | +-4 Vendor specific (480 Mb/s, 0mA) | Microchip Tech Hub Controller | +-3 Hub (5 Gb/s, 0mA) Microchip Tech USB5744
u-boot=> usb stop stopping USB.. clk usb_phy_root_clk already disabled
Also, I assume your Type-C ports on the imx8mp-beacon-kit do not work yet due to no U-Boot driver for usb-c-connector, nxp,ptn5110, ti,hd3ss3220?
Best Regards,
Tim
On Wed, May 31, 2023 at 10:44 AM Tim Harvey tharvey@gateworks.com wrote:
On Tue, May 30, 2023 at 3:46 PM Adam Ford aford173@gmail.com wrote:
There are some newer clocks added to the kernel recently, so to fix prepare for resycing the device trees, update the clock list. Since there are some minor changes to the USB clocks, update which USB clocks are enabled to match with the upstream kernel as well.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 09bef596f2..a21a3ce34b 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,7 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "usb_core_ref", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0));clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde..3f28ce685f 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
2.39.2
Adam,
This series does update the imx8mp.dtsi as well as provide functioning USB for me on imx8mp-venice-gw74xx.
Thanks for testing!
For both: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx
I do still see a clk already disabled message on usb stop (which was there before also but I believe the sync of the imx8mm.dtsi resolved the one on imx8mm). I'm curious if you see this as well: u-boot=> usb start && usb tree starting USB... Bus usb@38200000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus usb@38200000 for devices... 4 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found USB device tree: 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Hub (480 Mb/s, 0mA) | | Microchip Tech USB2744 | | | +-4 Vendor specific (480 Mb/s, 0mA) | Microchip Tech Hub Controller | +-3 Hub (5 Gb/s, 0mA) Microchip Tech USB5744
u-boot=> usb stop stopping USB.. clk usb_phy_root_clk already disabled
I didn't try the usb stop, but I can do that later today.
Also, I assume your Type-C ports on the imx8mp-beacon-kit do not work yet due to no U-Boot driver for usb-c-connector, nxp,ptn5110,
I only tried the USB host-only port which is connected to a hub, but I can try the others as well.
ti,hd3ss3220?
The HD3ss3220 does the muxing automatically without really needing a driver, and I haven't tried that either, but I can try that as a peripheral and as a host to see if/what happens.
adam
Best Regards,
Tim
On Wed, May 31, 2023 at 8:50 AM Adam Ford aford173@gmail.com wrote:
On Wed, May 31, 2023 at 10:44 AM Tim Harvey tharvey@gateworks.com wrote:
On Tue, May 30, 2023 at 3:46 PM Adam Ford aford173@gmail.com wrote:
There are some newer clocks added to the kernel recently, so to fix prepare for resycing the device trees, update the clock list. Since there are some minor changes to the USB clocks, update which USB clocks are enabled to match with the upstream kernel as well.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 09bef596f2..a21a3ce34b 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,7 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "usb_core_ref", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0));clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde..3f28ce685f 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
2.39.2
Adam,
This series does update the imx8mp.dtsi as well as provide functioning USB for me on imx8mp-venice-gw74xx.
Thanks for testing!
For both: Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx
I do still see a clk already disabled message on usb stop (which was there before also but I believe the sync of the imx8mm.dtsi resolved the one on imx8mm). I'm curious if you see this as well: u-boot=> usb start && usb tree starting USB... Bus usb@38200000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus usb@38200000 for devices... 4 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found USB device tree: 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Hub (480 Mb/s, 0mA) | | Microchip Tech USB2744 | | | +-4 Vendor specific (480 Mb/s, 0mA) | Microchip Tech Hub Controller | +-3 Hub (5 Gb/s, 0mA) Microchip Tech USB5744
u-boot=> usb stop stopping USB.. clk usb_phy_root_clk already disabled
I didn't try the usb stop, but I can do that later today.
Also, I assume your Type-C ports on the imx8mp-beacon-kit do not work yet due to no U-Boot driver for usb-c-connector, nxp,ptn5110,
I only tried the USB host-only port which is connected to a hub, but I can try the others as well.
ti,hd3ss3220?
The HD3ss3220 does the muxing automatically without really needing a driver, and I haven't tried that either, but I can try that as a peripheral and as a host to see if/what happens.
adam
For imx8mp-venice-gw74xx the above shows the same... the USB host-only port connected to a hub.
The Type-C connector on the imx8mp-venice-gw74xx is connected to a TPS25821 which handles CC and outputs a POL# to drive the SS mux and a SINK# to specify host or device mode which is routed to an imx8mp GPIO so I'm using the gpio-usb-b-connector compatible with id-gpios. As there is no driver for that yet one easy workaround if you want it to default to host-only mode is to just add something like this to the u-boot.dtsi:
/* gpio-usb-con not supported yet in U-Boot so make this a host for now */ &usb_dwc3_0 { dr_mode = "host"; };
The USB hub the other port of the imx8mp-venice-gw74xx attaches to has a HUB_RST# pin which I treat as a VBUS regulator which is not yet supported by the dwc host controller in U-Boot but I get passed that currently by ensuring it has a pull-up. I have a couple of patches I need to clean up and submit that add regulator enable support to dwc3-generic but I haven't figured out what that drivers 'remove' hook doesn't get called on 'usb stop' which is where the regulator disable should go.
Best Regards,
Tim
There are some newer clocks added to the kernel recently, so to fix prepare for resycing the device trees, update the clock list. Since there are some minor changes to the USB clocks, update which USB clocks are enabled to match with the upstream kernel as well. Signed-off-by: Adam Ford aford173@gmail.com Reviewed-by: Fabio Estevam festevam@denx.de Tested-by: Tim Harvey tharvey@gateworks.com #imx8mp-venice-gw74xx diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 09bef596f2..a21a3ce34b 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -337,7 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
- clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "usb_core_ref", base + 0x44d0, 0));
- clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0));
- clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde..3f28ce685f 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,18 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319
-#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_USB_SUSP 320 +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 +#define IMX8MP_CLK_END 330
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
participants (4)
-
Adam Ford -
Fabio Estevam -
sbabic＠denx.de -
Tim Harvey