[U-Boot] [PATCH 1/7] powerpc/i2c: introduce CONFIG_I2C_TWR for setting tWR value
From: york yorksun@freescale.com
EEPROM requires tWR for write cycle time. Since there is no other way to poll if the internal programming ends, wait for 5ms which is the max timing for AT24C01/02/04/08/16 by default. It can be overridden by defining CONFIG_I2C_TWR in configuration file if the slowest device has different write cycle time.
Signed-off-by: York Sun yorksun@freescale.com --- README | 7 +++++++ drivers/i2c/fsl_i2c.c | 9 +++++++++ 2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/README b/README index 8bb9c8d..83a316c 100644 --- a/README +++ b/README @@ -1717,6 +1717,13 @@ The following options need to be configured: devices can use either method, but some require one or the other.
+ CONFIG_I2C_TWR + + defining this will override the default write cycle time + 5ms which is the default for AT24C01/02/4/08/16. If the + slowest I2C device has different write cycle time, this + option should be defined. The unit is microsecond. + - SPI Support: CONFIG_SPI
Enables SPI driver (so far only tested with diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index cb13dee..d192b2a 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -42,6 +42,14 @@ #define CONFIG_I2C_TIMEOUT 10000 #endif
+/* + * tWR is the write cycle time for EEPROM device + * in microseconds + */ +#ifndef CONFIG_I2C_TWR +#define CONFIG_I2C_TWR 5000 +#endif + #define I2C_READ_BIT 1 #define I2C_WRITE_BIT 0
@@ -416,6 +424,7 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) if (i2c_wait4bus()) /* Wait until STOP */ debug("i2c_write: wait4bus timed out\n");
+ udelay(CONFIG_I2C_TWR); if (i == length) return 0;
From: york yorksun@freescale.com
If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width.
Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 24 ++++++++++++++++++++---- 1 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 6ccc3b0..80c7046 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -418,8 +418,19 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, /* Choose dynamic power management mode. */ popts->dynamic_power = 0;
- /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ - popts->data_bus_width = 0; + /* + * check first dimm for primary sdram width + * presuming all dimms are similar + * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit + */ + if (pdimm[0].primary_sdram_width == 64) + popts->data_bus_width = 0; + else if (pdimm[0].primary_sdram_width == 32) + popts->data_bus_width = 1; + else if (pdimm[0].primary_sdram_width == 16) + popts->data_bus_width = 2; + else + panic("Error: invalid primary sdram width!\n");
/* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) @@ -427,8 +438,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ #else - popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ - popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ + if (popts->data_bus_width == 1) { /* 32-bit bus */ + popts->OTF_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + } else { + popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ + popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ + } #endif #else popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
On May 26, 2011, at 6:25 PM, York Sun wrote:
From: york yorksun@freescale.com
If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width.
Signed-off-by: York Sun yorksun@freescale.com
arch/powerpc/cpu/mpc8xxx/ddr/options.c | 24 ++++++++++++++++++++---- 1 files changed, 20 insertions(+), 4 deletions(-)
applied to 85xx next
- k
From: york yorksun@freescale.com
We used to have fixed parameters for soldered DDR chips. This patch enables calculation based on raw timing data, implemneted in board-specific file.
Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu.c | 4 +++- arch/powerpc/cpu/mpc8xxx/ddr/Makefile | 13 +++++++++++-- arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 5 +++++ arch/powerpc/cpu/mpc8xxx/ddr/main.c | 12 ++++++++++++ 4 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f863f4a..8c2272a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -336,7 +336,9 @@ phys_size_t initdram(int board_type) } #endif
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) +#if defined(CONFIG_SPD_EEPROM) || \ + defined(CONFIG_DDR_SPD) || \ + defined(CONFIG_DDR_RAW_TIMING) dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile index 4a5a785..d1b4c4b 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile @@ -12,15 +12,24 @@ LIB = $(obj)libddr.o
COBJS-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ lc_common_dimm_params.o -COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
COBJS-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ lc_common_dimm_params.o -COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
COBJS-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ lc_common_dimm_params.o +ifdef CONFIG_DDR_SPD +SPD := y +endif +ifdef CONFIG_SPD_EEPROM +SPD := y +endif +ifdef SPD +COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o +COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o COBJS-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o +endif +
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index 1e866fe..eb2180e 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -14,6 +14,7 @@
#include "common_timing_params.h"
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* * Bind the main DDR setup driver's generic names * to this specific DDR technology. @@ -25,6 +26,7 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spd, { return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); } +#endif
/* * Data Structures @@ -80,4 +82,7 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos); + +/* board specific function */ +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int dimm_number); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index c8fa123..2b43e73 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -313,6 +313,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
switch (start_step) { case STEP_GET_SPD: +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* STEP 1: Gather all DIMM SPD data */ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); @@ -344,6 +345,17 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, } }
+#else + case STEP_COMPUTE_DIMM_PARMS: + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + dimm_params_t *pdimm = + &(pinfo->dimm_params[i][j]); + fsl_ddr_get_dimm_params(pdimm, i); + } + } + debug("Filling dimm parameters from board specific file\n"); +#endif case STEP_COMPUTE_COMMON_PARMS: /* * STEP 3: Compute a common set of timing parameters
On May 26, 2011, at 6:25 PM, York Sun wrote:
From: york yorksun@freescale.com
We used to have fixed parameters for soldered DDR chips. This patch enables calculation based on raw timing data, implemneted in board-specific file.
Signed-off-by: York Sun yorksun@freescale.com
arch/powerpc/cpu/mpc85xx/cpu.c | 4 +++- arch/powerpc/cpu/mpc8xxx/ddr/Makefile | 13 +++++++++++-- arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 5 +++++ arch/powerpc/cpu/mpc8xxx/ddr/main.c | 12 ++++++++++++ 4 files changed, 31 insertions(+), 3 deletions(-)
applied to 85xx next
- k
On Jun 3, 2011, at 2:42 AM, Kumar Gala wrote:
On May 26, 2011, at 6:25 PM, York Sun wrote:
From: york yorksun@freescale.com
We used to have fixed parameters for soldered DDR chips. This patch enables calculation based on raw timing data, implemneted in board-specific file.
Signed-off-by: York Sun yorksun@freescale.com
arch/powerpc/cpu/mpc85xx/cpu.c | 4 +++- arch/powerpc/cpu/mpc8xxx/ddr/Makefile | 13 +++++++++++-- arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 5 +++++ arch/powerpc/cpu/mpc8xxx/ddr/main.c | 12 ++++++++++++ 4 files changed, 31 insertions(+), 3 deletions(-)
applied to 85xx next
After further review, I'm dropping this one for now. We need to add some docs about 'RAW TIMING'
- k
From: york yorksun@freescale.com
Only use DDR DIMM part number if SPD has valid length, to prevent from display garbage in case SPD doesn't cover these fields.
Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 756b15f..838cebe 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -114,7 +114,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * and copying the part name in ASCII from the SPD onto it */ memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); + if ((spd->info_size_crc & 0xF) > 1) + memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
/* DIMM organization parameters */ pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
On May 26, 2011, at 6:25 PM, York Sun wrote:
From: york yorksun@freescale.com
Only use DDR DIMM part number if SPD has valid length, to prevent from display garbage in case SPD doesn't cover these fields.
Signed-off-by: York Sun yorksun@freescale.com
arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
applied to 85xx next
- k
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices.
Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 14 +++++++++++++- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 3 ++- arch/powerpc/include/asm/fsl_ddr_sdram.h | 3 +++ 3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 2b43e73..db7cf11 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -174,7 +174,19 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, switch (pinfo->memctl_opts[i].data_bus_width) { case 2: /* 16-bit */ - printf("can't handle 16-bit mode yet\n"); + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned int dw; + if (!pinfo->dimm_params[i][j].n_ranks) + continue; + dw = pinfo->dimm_params[i][j].primary_sdram_width; + if ((dw == 72 || dw == 64)) { + dbw_cap_adj[i] = 2; + break; + } else if ((dw == 40 || dw == 32)) { + dbw_cap_adj[i] = 1; + break; + } + } break;
case 1: diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 80c7046..02efe58 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -438,7 +438,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ #else - if (popts->data_bus_width == 1) { /* 32-bit bus */ + if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { + /* 32-bit or 16-bit bus */ popts->OTF_burst_chop_en = 0; popts->burst_length = DDR_BL8; } else { diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 127a840..1778cc5 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -181,6 +181,9 @@ typedef struct memctl_options_partial_s { unsigned int all_DIMMs_minimum_tRCD_ps; } memctl_options_partial_t;
+#define DDR_DATA_BUS_WIDTH_64 0 +#define DDR_DATA_BUS_WIDTH_32 1 +#define DDR_DATA_BUS_WIDTH_16 2 /* * Generalized parameters for memory controller configuration, * might be a little specific to the FSL memory controller
On May 26, 2011, at 6:25 PM, York Sun wrote:
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices.
Signed-off-by: York Sun yorksun@freescale.com
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 14 +++++++++++++- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 3 ++- arch/powerpc/include/asm/fsl_ddr_sdram.h | 3 +++ 3 files changed, 18 insertions(+), 2 deletions(-)
applied to 85xx next
- k
In case of empty SPD or checksum error, fallback to raw timing on supported boards.
Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index db7cf11..2e43da6 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -343,12 +343,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, &(pinfo->dimm_params[i][j]);
retval = compute_dimm_parameters(spd, pdimm, i); +#ifdef CONFIG_DDR_RAW_TIMING + if (retval != 0) { + printf("SPD error! Trying fallback to " + "raw timing calculation\n"); + fsl_ddr_get_dimm_params(pdimm, i, j); + } +#else if (retval == 2) { printf("Error: compute_dimm_parameters" " non-zero returned FATAL value " "for memctl=%u dimm=%u\n", i, j); return 0; } +#endif if (retval) { debug("Warning: compute_dimm_parameters" " non-zero return value for memctl=%u "
On May 26, 2011, at 6:25 PM, York Sun wrote:
In case of empty SPD or checksum error, fallback to raw timing on supported boards.
Signed-off-by: York Sun yorksun@freescale.com
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index db7cf11..2e43da6 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -343,12 +343,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, &(pinfo->dimm_params[i][j]);
retval = compute_dimm_parameters(spd, pdimm, i);+#ifdef CONFIG_DDR_RAW_TIMING
Should this be CONFIG_SYS_DDR_RAW_TIMING??
We need this added to README at a minimum for what DDR_RAW_TIMING means.
if (retval != 0) {printf("SPD error! Trying fallback to ""raw timing calculation\n");fsl_ddr_get_dimm_params(pdimm, i, j);}+#else if (retval == 2) { printf("Error: compute_dimm_parameters" " non-zero returned FATAL value " "for memctl=%u dimm=%u\n", i, j); return 0; } +#endif if (retval) { debug("Warning: compute_dimm_parameters" " non-zero return value for memctl=%u " -- 1.7.0.4
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Fri, 2011-06-03 at 02:46 -0500, Kumar Gala wrote:
On May 26, 2011, at 6:25 PM, York Sun wrote:
In case of empty SPD or checksum error, fallback to raw timing on supported boards.
Signed-off-by: York Sun yorksun@freescale.com
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index db7cf11..2e43da6 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -343,12 +343,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, &(pinfo->dimm_params[i][j]);
retval = compute_dimm_parameters(spd, pdimm, i);+#ifdef CONFIG_DDR_RAW_TIMING
Should this be CONFIG_SYS_DDR_RAW_TIMING??
We need this added to README at a minimum for what DDR_RAW_TIMING means.
Will do.
York
On Jun 3, 2011, at 3:10 AM, York Sun wrote:
On Fri, 2011-06-03 at 02:46 -0500, Kumar Gala wrote:
On May 26, 2011, at 6:25 PM, York Sun wrote:
In case of empty SPD or checksum error, fallback to raw timing on supported boards.
Signed-off-by: York Sun yorksun@freescale.com
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index db7cf11..2e43da6 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -343,12 +343,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, &(pinfo->dimm_params[i][j]);
retval = compute_dimm_parameters(spd, pdimm, i);+#ifdef CONFIG_DDR_RAW_TIMING
Should this be CONFIG_SYS_DDR_RAW_TIMING??
We need this added to README at a minimum for what DDR_RAW_TIMING means.
Will do.
York
thanks. Might be good to do it in patch 3/7.
Just repost 3/7, 6/7, 7/7 against 'next' branch of git://git.denx.de/u-boot-mpc85xx.git
- k
Adding controller number so board implementation can distinguish.
Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 4 +++- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index eb2180e..f59aa33 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -84,5 +84,7 @@ extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos);
/* board specific function */ -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int dimm_number); +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 2e43da6..b559787 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -371,7 +371,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { dimm_params_t *pdimm = &(pinfo->dimm_params[i][j]); - fsl_ddr_get_dimm_params(pdimm, i); + fsl_ddr_get_dimm_params(pdimm, i, j); } } debug("Filling dimm parameters from board specific file\n");
York Sun wrote:
From: york yorksun@freescale.com
You should fix this so that it includes your full name.
On Thu, 2011-05-26 at 17:20 -0700, Tabi Timur-B04825 wrote:
York Sun wrote:
From: york yorksun@freescale.com
You should fix this so that it includes your full name.
--
Sure. I can fix it along with other feedback.
York
Hello York,
York Sun wrote:
From: york yorksun@freescale.com
EEPROM requires tWR for write cycle time. Since there is no other way to poll if the internal programming ends, wait for 5ms which is the max timing for AT24C01/02/04/08/16 by default. It can be overridden by defining CONFIG_I2C_TWR in configuration file if the slowest device has different write cycle time.
Signed-off-by: York Sun yorksun@freescale.com
README | 7 +++++++ drivers/i2c/fsl_i2c.c | 9 +++++++++ 2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/README b/README index 8bb9c8d..83a316c 100644 --- a/README +++ b/README @@ -1717,6 +1717,13 @@ The following options need to be configured: devices can use either method, but some require one or the other.
CONFIG_I2C_TWR
Maybe CONFIG_SYS_I2C_EEPROM_TWR is better?
defining this will override the default write cycle time
the default eeprom write cycle time ...
5ms which is the default for AT24C01/02/4/08/16. If theslowest I2C device has different write cycle time, thisoption should be defined. The unit is microsecond.
SPI Support: CONFIG_SPI
Enables SPI driver (so far only tested with
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index cb13dee..d192b2a 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -42,6 +42,14 @@ #define CONFIG_I2C_TIMEOUT 10000 #endif
+/*
- tWR is the write cycle time for EEPROM device
- in microseconds
- */
+#ifndef CONFIG_I2C_TWR +#define CONFIG_I2C_TWR 5000 +#endif
#define I2C_READ_BIT 1 #define I2C_WRITE_BIT 0
@@ -416,6 +424,7 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) if (i2c_wait4bus()) /* Wait until STOP */ debug("i2c_write: wait4bus timed out\n");
- udelay(CONFIG_I2C_TWR); if (i == length) return 0;
Hmm.. you add this timeout in the i2c driver, which will result in adding this default 5 ms delay for *all* i2c writes, not only for eeprom devices ... why you didn;t add this timeout in cmd_eeprom, where it seems to me is the better place for it? Looking in this common/cmd_eeprom.c there is a CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS define ... is this not adequate?
bye, Heiko
On Fri, 2011-05-27 at 08:04 +0200, Heiko Schocher wrote:
Hmm.. you add this timeout in the i2c driver, which will result in adding this default 5 ms delay for *all* i2c writes, not only for eeprom devices ... why you didn;t add this timeout in cmd_eeprom, where it seems to me is the better place for it? Looking in this common/cmd_eeprom.c there is a CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS define ... is this not adequate?
You are right. I overlooked CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS and should use this instead.
Drop this patch, please.
York
participants (4)
-
Heiko Schocher -
Kumar Gala -
Tabi Timur-B04825 -
York Sun