Add device data for main_uart1 in dev-data.c for J7200. Now, main_uart1 will be powered on while booting the J7200 SoC.

Signed-off-by: Bhavya Kapoor b-kapoor@ti.com --- arch/arm/mach-k3/j7200/dev-data.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c index d3194ae51a..c1a4dab694 100644 --- a/arch/arm/mach-k3/j7200/dev-data.c +++ b/arch/arm/mach-k3/j7200/dev-data.c @@ -53,6 +53,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(92, &soc_lpsc_list[5]), PSC_DEV(91, &soc_lpsc_list[6]), PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(278, &soc_lpsc_list[7]), PSC_DEV(4, &soc_lpsc_list[8]), PSC_DEV(4, &soc_lpsc_list[9]), PSC_DEV(202, &soc_lpsc_list[10]), @@ -77,5 +78,5 @@ const struct ti_k3_pd_platdata j7200_pd_platdata = { .num_psc = 2, .num_pd = 6, .num_lpsc = 17, - .num_devs = 22, + .num_devs = 23, };

Add main_uart1 clocks in clk-data.c for J7200. Now, main_uart1 clocks will be set up while booting the J7200 SoC.

Signed-off-by: Bhavya Kapoor b-kapoor@ti.com --- arch/arm/mach-k3/j7200/clk-data.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c index 0437e30abb..9b45786a2d 100644 --- a/arch/arm/mach-k3/j7200/clk-data.c +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -379,6 +379,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c4, 0, 2, 0, 0, 48000000), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), @@ -534,6 +535,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"), + DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"), DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -546,7 +549,7 @@ static const struct dev_clk soc_dev_clk_data[] = {

const struct ti_k3_clk_platdata j7200_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 108, + .clk_list_cnt = 109, .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 127, + .soc_dev_clk_data_cnt = 129, };