From: Aswath Govindraju a-govindraju@ti.com

Add definitions for additional phy types that's used specifically for Torrent SERDES.

Signed-off-by: Aswath Govindraju a-govindraju@ti.com Signed-off-by: Kishon Vijay Abraham I kishon@ti.com --- include/dt-bindings/phy/phy.h | 1 + 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index 7e657da454..d3714edd4b 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -19,5 +19,6 @@ #define PHY_TYPE_DP 6 #define PHY_TYPE_XPCS 7 #define PHY_TYPE_SGMII 8 +#define PHY_TYPE_QSGMII 9

#endif /* _DT_BINDINGS_PHY */

Add defines for refclk driver used to route the refclk out of torrent SERDES.

Signed-off-by: Kishon Vijay Abraham I kishon@ti.com --- include/dt-bindings/phy/phy-cadence.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 include/dt-bindings/phy/phy-cadence.h

diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h new file mode 100644 index 0000000000..4652bcb862 --- /dev/null +++ b/include/dt-bindings/phy/phy-cadence.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for Cadence SERDES. + */ + +#ifndef _DT_BINDINGS_CADENCE_SERDES_H +#define _DT_BINDINGS_CADENCE_SERDES_H + +/* Torrent */ +#define TORRENT_SERDES_NO_SSC 0 +#define TORRENT_SERDES_EXTERNAL_SSC 1 +#define TORRENT_SERDES_INTERNAL_SSC 2 + +#define CDNS_TORRENT_REFCLK_DRIVER 0 + +/* Sierra */ +#define CDNS_SIERRA_PLL_CMNLC 0 +#define CDNS_SIERRA_PLL_CMNLC1 1 + +#endif /* _DT_BINDINGS_CADENCE_SERDES_H */

From: Alan Douglas adouglas@cadence.com

Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver.

The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane.

The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY

One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset.

Signed-off-by: Jean-Jacques Hiblot jjhiblot@ti.com Signed-off-by: Alan Douglas adouglas@cadence.com Signed-off-by: Kishon Vijay Abraham I kishon@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/phy/Kconfig | 2 + drivers/phy/Makefile | 1 + drivers/phy/cadence/Kconfig | 5 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-sierra.c | 751 +++++++++++++++++++++++ 5 files changed, 760 insertions(+) create mode 100644 drivers/phy/cadence/Kconfig create mode 100644 drivers/phy/cadence/Makefile create mode 100644 drivers/phy/cadence/phy-cadence-sierra.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 008186a10d..9208e430a6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -269,4 +269,6 @@ config PHY_MTK_TPHY so you can easily distinguish them by banks layout.

source "drivers/phy/rockchip/Kconfig" +source "drivers/phy/cadence/Kconfig" + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3c4a673a83..4736c5eadb 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o +obj-y += cadence/ diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig new file mode 100644 index 0000000000..18a04819f5 --- /dev/null +++ b/drivers/phy/cadence/Kconfig @@ -0,0 +1,5 @@ +config PHY_CADENCE_SIERRA + tristate "Cadence Sierra PHY Driver" + depends on DM_RESET + help + Enable this to support the Cadence Sierra PHY driver diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile new file mode 100644 index 0000000000..d57856152a --- /dev/null +++ b/drivers/phy/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_$(SPL_)PHY_CADENCE_SIERRA) += phy-cadence-sierra.o diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c new file mode 100644 index 0000000000..715def6f17 --- /dev/null +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cadence Sierra PHY Driver + * + * Based on the linux driver provided by Cadence + * + * Copyright (c) 2018 Cadence Design Systems + * Author: Alan Douglas adouglas@cadence.com + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Jean-Jacques Hiblot jjhiblot@ti.com + * + */ +#include <common.h> +#include <clk.h> +#include <generic-phy.h> +#include <reset.h> +#include <dm/device.h> +#include <dm/device-internal.h> +#include <dm/device_compat.h> +#include <dm/lists.h> +#include <dm/read.h> +#include <dm/uclass.h> +#include <dm/devres.h> +#include <linux/io.h> +#include <dt-bindings/phy/phy.h> +#include <regmap.h> + +/* PHY register offsets */ +#define SIERRA_COMMON_CDB_OFFSET 0x0 +#define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_CMN_PLLLC_MODE_PREG 0x48 +#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 +#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A +#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B +#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F +#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 +#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 + +#define SIERRA_LANE_CDB_OFFSET(ln, offset) \ + (0x4000 + ((ln) * (0x800 >> (2 - (offset))))) + +#define SIERRA_DET_STANDEC_A_PREG 0x000 +#define SIERRA_DET_STANDEC_B_PREG 0x001 +#define SIERRA_DET_STANDEC_C_PREG 0x002 +#define SIERRA_DET_STANDEC_D_PREG 0x003 +#define SIERRA_DET_STANDEC_E_PREG 0x004 +#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 +#define SIERRA_PSM_A0IN_TMR_PREG 0x009 +#define SIERRA_PSM_DIAG_PREG 0x015 +#define SIERRA_PSC_TX_A0_PREG 0x028 +#define SIERRA_PSC_TX_A1_PREG 0x029 +#define SIERRA_PSC_TX_A2_PREG 0x02A +#define SIERRA_PSC_TX_A3_PREG 0x02B +#define SIERRA_PSC_RX_A0_PREG 0x030 +#define SIERRA_PSC_RX_A1_PREG 0x031 +#define SIERRA_PSC_RX_A2_PREG 0x032 +#define SIERRA_PSC_RX_A3_PREG 0x033 +#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A +#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E +#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F +#define SIERRA_PLLCTRL_STATUS_PREG 0x044 +#define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B +#define SIERRA_DFE_BIASTRIM_PREG 0x04C +#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A +#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 +#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 +#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 +#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 +#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 +#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E +#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 +#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 +#define SIERRA_CREQ_EQ_CTRL_PREG 0x093 +#define SIERRA_CREQ_SPARE_PREG 0x096 +#define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 +#define SIERRA_CTLELUT_CTRL_PREG 0x098 +#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 +#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 +#define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 +#define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 +#define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 +#define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD +#define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE +#define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 +#define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 +#define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 +#define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 +#define SIERRA_DEQ_GLUT0 0x0E8 +#define SIERRA_DEQ_GLUT1 0x0E9 +#define SIERRA_DEQ_GLUT2 0x0EA +#define SIERRA_DEQ_GLUT3 0x0EB +#define SIERRA_DEQ_GLUT4 0x0EC +#define SIERRA_DEQ_GLUT5 0x0ED +#define SIERRA_DEQ_GLUT6 0x0EE +#define SIERRA_DEQ_GLUT7 0x0EF +#define SIERRA_DEQ_GLUT8 0x0F0 +#define SIERRA_DEQ_GLUT9 0x0F1 +#define SIERRA_DEQ_GLUT10 0x0F2 +#define SIERRA_DEQ_GLUT11 0x0F3 +#define SIERRA_DEQ_GLUT12 0x0F4 +#define SIERRA_DEQ_GLUT13 0x0F5 +#define SIERRA_DEQ_GLUT14 0x0F6 +#define SIERRA_DEQ_GLUT15 0x0F7 +#define SIERRA_DEQ_GLUT16 0x0F8 +#define SIERRA_DEQ_ALUT0 0x108 +#define SIERRA_DEQ_ALUT1 0x109 +#define SIERRA_DEQ_ALUT2 0x10A +#define SIERRA_DEQ_ALUT3 0x10B +#define SIERRA_DEQ_ALUT4 0x10C +#define SIERRA_DEQ_ALUT5 0x10D +#define SIERRA_DEQ_ALUT6 0x10E +#define SIERRA_DEQ_ALUT7 0x10F +#define SIERRA_DEQ_ALUT8 0x110 +#define SIERRA_DEQ_ALUT9 0x111 +#define SIERRA_DEQ_ALUT10 0x112 +#define SIERRA_DEQ_ALUT11 0x113 +#define SIERRA_DEQ_ALUT12 0x114 +#define SIERRA_DEQ_ALUT13 0x115 +#define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 +#define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 +#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 +#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 +#define SIERRA_DEQ_PICTRL_PREG 0x161 +#define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 +#define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 +#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 +#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C +#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 +#define SIERRA_LFPSDET_SUPPORT_PREG 0x188 +#define SIERRA_LFPSFILT_NS_PREG 0x18A +#define SIERRA_LFPSFILT_RD_PREG 0x18B +#define SIERRA_LFPSFILT_MP_PREG 0x18C +#define SIERRA_SIGDET_SUPPORT_PREG 0x190 +#define SIERRA_SDFILT_H2L_A_PREG 0x191 +#define SIERRA_SDFILT_L2H_PREG 0x193 +#define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E +#define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F +#define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 +#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F +#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 + +#define SIERRA_PHY_CONFIG_CTRL_OFFSET 0xc000 +#define SIERRA_PHY_PLL_CFG 0xe + +#define SIERRA_MACRO_ID 0x00007364 +#define SIERRA_MAX_LANES 16 +#define PLL_LOCK_TIME 100 + +static const struct reg_field macro_id_type = + REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); +static const struct reg_field phy_pll_cfg_1 = + REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); +static const struct reg_field pllctrl_lock = + REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); + +#define reset_control_assert(rst) cdns_reset_assert(rst) +#define reset_control_deassert(rst) cdns_reset_deassert(rst) +#define reset_control reset_ctl + +struct cdns_sierra_inst { + u32 phy_type; + u32 num_lanes; + u32 mlane; + struct reset_ctl_bulk *lnk_rst; +}; + +struct cdns_reg_pairs { + u16 val; + u32 off; +}; + +struct cdns_sierra_data { + u32 id_value; + u8 block_offset_shift; + u8 reg_offset_shift; + u32 pcie_cmn_regs; + u32 pcie_ln_regs; + u32 usb_cmn_regs; + u32 usb_ln_regs; + struct cdns_reg_pairs *pcie_cmn_vals; + struct cdns_reg_pairs *pcie_ln_vals; + struct cdns_reg_pairs *usb_cmn_vals; + struct cdns_reg_pairs *usb_ln_vals; +}; + +struct cdns_regmap_cdb_context { + struct udevice *dev; + void __iomem *base; + u8 reg_offset_shift; +}; + +struct cdns_sierra_phy { + struct udevice *dev; + void *base; + size_t size; + struct regmap *regmap; + struct cdns_sierra_data *init_data; + struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; + struct reset_control *phy_rst; + struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; + struct regmap *regmap_phy_config_ctrl; + struct regmap *regmap_common_cdb; + struct regmap_field *macro_id_type; + struct regmap_field *phy_pll_cfg_1; + struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; + struct clk *clk; + struct clk *cmn_refclk; + struct clk *cmn_refclk1; + int nsubnodes; + u32 num_lanes; + bool autoconf; +}; + +static inline int cdns_reset_assert(struct reset_control *rst) +{ + if (rst) + return reset_assert(rst); + else + return 0; +} + +static inline int cdns_reset_deassert(struct reset_control *rst) +{ + if (rst) + return reset_deassert(rst); + else + return 0; +} + +static inline struct cdns_sierra_inst *phy_get_drvdata(struct phy *phy) +{ + struct cdns_sierra_phy *sp = dev_get_priv(phy->dev); + int index; + + if (phy->id >= SIERRA_MAX_LANES) + return NULL; + + for (index = 0; index < sp->nsubnodes; index++) { + if (phy->id == sp->phys[index].mlane) + return &sp->phys[index]; + } + + return NULL; +} + +static int cdns_sierra_phy_init(struct phy *gphy) +{ + struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); + struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev); + struct regmap *regmap = phy->regmap; + int i, j; + struct cdns_reg_pairs *cmn_vals, *ln_vals; + u32 num_cmn_regs, num_ln_regs; + + /* Initialise the PHY registers, unless auto configured */ + if (phy->autoconf) + return 0; + + clk_set_rate(phy->cmn_refclk, 25000000); + clk_set_rate(phy->cmn_refclk1, 25000000); + + if (ins->phy_type == PHY_TYPE_PCIE) { + num_cmn_regs = phy->init_data->pcie_cmn_regs; + num_ln_regs = phy->init_data->pcie_ln_regs; + cmn_vals = phy->init_data->pcie_cmn_vals; + ln_vals = phy->init_data->pcie_ln_vals; + } else if (ins->phy_type == PHY_TYPE_USB3) { + num_cmn_regs = phy->init_data->usb_cmn_regs; + num_ln_regs = phy->init_data->usb_ln_regs; + cmn_vals = phy->init_data->usb_cmn_vals; + ln_vals = phy->init_data->usb_ln_vals; + } else { + return -EINVAL; + } + + regmap = phy->regmap_common_cdb; + for (j = 0; j < num_cmn_regs ; j++) + regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val); + + for (i = 0; i < ins->num_lanes; i++) { + for (j = 0; j < num_ln_regs ; j++) { + regmap = phy->regmap_lane_cdb[i + ins->mlane]; + regmap_write(regmap, ln_vals[j].off, ln_vals[j].val); + } + } + + return 0; +} + +static int cdns_sierra_phy_on(struct phy *gphy) +{ + struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); + struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev); + struct udevice *dev = gphy->dev; + u32 val; + int ret; + + /* Take the PHY lane group out of reset */ + ret = reset_deassert_bulk(ins->lnk_rst); + if (ret) { + dev_err(dev, "Failed to take the PHY lane out of reset\n"); + return ret; + } + + ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], + val, val, 1000, PLL_LOCK_TIME); + if (ret < 0) + dev_err(dev, "PLL lock of lane failed\n"); + + reset_control_assert(sp->phy_rst); + reset_control_deassert(sp->phy_rst); + + return ret; +} + +static int cdns_sierra_phy_off(struct phy *gphy) +{ + struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); + + return reset_assert_bulk(ins->lnk_rst); +} + +static int cdns_sierra_phy_reset(struct phy *gphy) +{ + struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev); + + reset_control_assert(sp->phy_rst); + reset_control_deassert(sp->phy_rst); + return 0; +}; + +static const struct phy_ops ops = { + .init = cdns_sierra_phy_init, + .power_on = cdns_sierra_phy_on, + .power_off = cdns_sierra_phy_off, + .reset = cdns_sierra_phy_reset, +}; + +static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, + ofnode child) +{ + if (ofnode_read_u32(child, "reg", &inst->mlane)) + return -EINVAL; + + if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) + return -EINVAL; + + if (ofnode_read_u32(child, "cdns,phy-type", &inst->phy_type)) + return -EINVAL; + + return 0; +} + +static struct regmap *cdns_regmap_init(struct udevice *dev, void __iomem *base, + u32 block_offset, u8 block_offset_shift, + u8 reg_offset_shift) +{ + struct cdns_sierra_phy *sp = dev_get_priv(dev); + struct regmap_config config; + + config.r_start = (ulong)(base + (block_offset << block_offset_shift)); + config.r_size = sp->size - (block_offset << block_offset_shift); + config.reg_offset_shift = reg_offset_shift; + config.width = REGMAP_SIZE_16; + + return devm_regmap_init(dev, NULL, NULL, &config); +} + +static int cdns_regfield_init(struct cdns_sierra_phy *sp) +{ + struct udevice *dev = sp->dev; + struct regmap_field *field; + struct regmap *regmap; + int i; + + regmap = sp->regmap_common_cdb; + field = devm_regmap_field_alloc(dev, regmap, macro_id_type); + if (IS_ERR(field)) { + dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); + return PTR_ERR(field); + } + sp->macro_id_type = field; + + regmap = sp->regmap_phy_config_ctrl; + field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); + if (IS_ERR(field)) { + dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); + return PTR_ERR(field); + } + sp->phy_pll_cfg_1 = field; + + for (i = 0; i < SIERRA_MAX_LANES; i++) { + regmap = sp->regmap_lane_cdb[i]; + field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock); + if (IS_ERR(field)) { + dev_err(dev, "P%d_ENABLE reg field init failed\n", i); + return PTR_ERR(field); + } + sp->pllctrl_lock[i] = field; + } + + return 0; +} + +static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, + void __iomem *base, u8 block_offset_shift, + u8 reg_offset_shift) +{ + struct udevice *dev = sp->dev; + struct regmap *regmap; + u32 block_offset; + int i; + + for (i = 0; i < SIERRA_MAX_LANES; i++) { + block_offset = SIERRA_LANE_CDB_OFFSET(i, reg_offset_shift); + regmap = cdns_regmap_init(dev, base, block_offset, + block_offset_shift, reg_offset_shift); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init lane CDB regmap\n"); + return PTR_ERR(regmap); + } + sp->regmap_lane_cdb[i] = regmap; + } + + regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, + block_offset_shift, reg_offset_shift); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init common CDB regmap\n"); + return PTR_ERR(regmap); + } + sp->regmap_common_cdb = regmap; + + regmap = cdns_regmap_init(dev, base, SIERRA_PHY_CONFIG_CTRL_OFFSET, + block_offset_shift, reg_offset_shift); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init PHY config and control regmap\n"); + return PTR_ERR(regmap); + } + sp->regmap_phy_config_ctrl = regmap; + + return 0; +} + +static int cdns_sierra_phy_probe(struct udevice *dev) +{ + struct cdns_sierra_phy *sp = dev_get_priv(dev); + struct cdns_sierra_data *data; + unsigned int id_value; + int ret, node = 0; + struct clk *clk; + ofnode child; + + sp->dev = dev; + + sp->base = devfdt_remap_addr_index(dev, 0); + if (!sp->base) { + dev_err(dev, "unable to map regs\n"); + return -ENOMEM; + } + devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&sp->size); + + /* Get init data for this PHY */ + data = (struct cdns_sierra_data *)dev_get_driver_data(dev); + sp->init_data = data; + + ret = cdns_regmap_init_blocks(sp, sp->base, data->block_offset_shift, + data->reg_offset_shift); + if (ret) + return ret; + + ret = cdns_regfield_init(sp); + if (ret) + return ret; + + sp->clk = devm_clk_get_optional(dev, "phy_clk"); + if (IS_ERR(sp->clk)) { + dev_err(dev, "failed to get clock phy_clk\n"); + return PTR_ERR(sp->clk); + } + + sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); + if (IS_ERR(sp->phy_rst)) { + dev_err(dev, "failed to get reset\n"); + return PTR_ERR(sp->phy_rst); + } + + clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk1 clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk1 = clk; + + ret = clk_prepare_enable(sp->clk); + if (ret) + return ret; + + /* Check that PHY is present */ + regmap_field_read(sp->macro_id_type, &id_value); + if (sp->init_data->id_value != id_value) { + dev_err(dev, "PHY not found 0x%x vs 0x%x\n", + sp->init_data->id_value, id_value); + ret = -EINVAL; + goto clk_disable; + } + + sp->autoconf = dev_read_bool(dev, "cdns,autoconf"); + + ofnode_for_each_subnode(child, dev_ofnode(dev)) { + sp->phys[node].lnk_rst = devm_reset_bulk_get_by_node(dev, + child); + if (IS_ERR(sp->phys[node].lnk_rst)) { + ret = PTR_ERR(sp->phys[node].lnk_rst); + dev_err(dev, "failed to get reset %s\n", + ofnode_get_name(child)); + goto put_child2; + } + + if (!sp->autoconf) { + ret = cdns_sierra_get_optional(&sp->phys[node], child); + if (ret) { + dev_err(dev, "missing property in node %s\n", + ofnode_get_name(child)); + goto put_child; + } + } + sp->num_lanes += sp->phys[node].num_lanes; + + node++; + } + sp->nsubnodes = node; + + /* If more than one subnode, configure the PHY as multilink */ + if (!sp->autoconf && sp->nsubnodes > 1) + regmap_field_write(sp->phy_pll_cfg_1, 0x1); + + reset_control_deassert(sp->phy_rst); + dev_info(dev, "sierra probed\n"); + return 0; + +put_child: + node++; +put_child2: + +clk_disable: + clk_disable_unprepare(sp->clk); + return ret; +} + +static int cdns_sierra_phy_remove(struct udevice *dev) +{ + struct cdns_sierra_phy *phy = dev_get_priv(dev); + int i; + + reset_control_assert(phy->phy_rst); + + /* + * The device level resets will be put automatically. + * Need to put the subnode resets here though. + */ + for (i = 0; i < phy->nsubnodes; i++) + reset_assert_bulk(phy->phys[i].lnk_rst); + + return 0; +} + +/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ +static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { + {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, + {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, + {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, + {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, + {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} +}; + +/* refclk100MHz_32b_PCIe_ln_ext_ssc */ +static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { + {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, + {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, + {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, + {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, + {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, + {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, + {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG} +}; + +/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ +static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { + {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, + {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, + {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, + {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} +}; + +/* refclk100MHz_20b_USB_ln_ext_ssc */ +static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { + {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, + {0x000F, SIERRA_DET_STANDEC_B_PREG}, + {0x00A5, SIERRA_DET_STANDEC_C_PREG}, + {0x69ad, SIERRA_DET_STANDEC_D_PREG}, + {0x0241, SIERRA_DET_STANDEC_E_PREG}, + {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, + {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, + {0xCF00, SIERRA_PSM_DIAG_PREG}, + {0x001F, SIERRA_PSC_TX_A0_PREG}, + {0x0007, SIERRA_PSC_TX_A1_PREG}, + {0x0003, SIERRA_PSC_TX_A2_PREG}, + {0x0003, SIERRA_PSC_TX_A3_PREG}, + {0x0FFF, SIERRA_PSC_RX_A0_PREG}, + {0x0619, SIERRA_PSC_RX_A1_PREG}, + {0x0003, SIERRA_PSC_RX_A2_PREG}, + {0x0001, SIERRA_PSC_RX_A3_PREG}, + {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, + {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, + {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, + {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, + {0x2512, SIERRA_DFE_BIASTRIM_PREG}, + {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, + {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG}, + {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, + {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, + {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, + {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG}, + {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, + {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, + {0x8000, SIERRA_CREQ_SPARE_PREG}, + {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, + {0x8453, SIERRA_CTLELUT_CTRL_PREG}, + {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG}, + {0x4110, SIERRA_DFE_SMP_RATESEL_PREG}, + {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, + {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, + {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, + {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, + {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, + {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, + {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, + {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, + {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG}, + {0x0014, SIERRA_DEQ_GLUT0}, + {0x0014, SIERRA_DEQ_GLUT1}, + {0x0014, SIERRA_DEQ_GLUT2}, + {0x0014, SIERRA_DEQ_GLUT3}, + {0x0014, SIERRA_DEQ_GLUT4}, + {0x0014, SIERRA_DEQ_GLUT5}, + {0x0014, SIERRA_DEQ_GLUT6}, + {0x0014, SIERRA_DEQ_GLUT7}, + {0x0014, SIERRA_DEQ_GLUT8}, + {0x0014, SIERRA_DEQ_GLUT9}, + {0x0014, SIERRA_DEQ_GLUT10}, + {0x0014, SIERRA_DEQ_GLUT11}, + {0x0014, SIERRA_DEQ_GLUT12}, + {0x0014, SIERRA_DEQ_GLUT13}, + {0x0014, SIERRA_DEQ_GLUT14}, + {0x0014, SIERRA_DEQ_GLUT15}, + {0x0014, SIERRA_DEQ_GLUT16}, + {0x0BAE, SIERRA_DEQ_ALUT0}, + {0x0AEB, SIERRA_DEQ_ALUT1}, + {0x0A28, SIERRA_DEQ_ALUT2}, + {0x0965, SIERRA_DEQ_ALUT3}, + {0x08A2, SIERRA_DEQ_ALUT4}, + {0x07DF, SIERRA_DEQ_ALUT5}, + {0x071C, SIERRA_DEQ_ALUT6}, + {0x0659, SIERRA_DEQ_ALUT7}, + {0x0596, SIERRA_DEQ_ALUT8}, + {0x0514, SIERRA_DEQ_ALUT9}, + {0x0492, SIERRA_DEQ_ALUT10}, + {0x0410, SIERRA_DEQ_ALUT11}, + {0x038E, SIERRA_DEQ_ALUT12}, + {0x030C, SIERRA_DEQ_ALUT13}, + {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, + {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, + {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, + {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, + {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, + {0x0033, SIERRA_DEQ_PICTRL_PREG}, + {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, + {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, + {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, + {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, + {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, + {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, + {0x000F, SIERRA_LFPSFILT_NS_PREG}, + {0x0009, SIERRA_LFPSFILT_RD_PREG}, + {0x0001, SIERRA_LFPSFILT_MP_PREG}, + {0x8013, SIERRA_SDFILT_H2L_A_PREG}, + {0x8009, SIERRA_SDFILT_L2H_PREG}, + {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, + {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, + {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} +}; + +static const struct cdns_sierra_data cdns_map_sierra = { + SIERRA_MACRO_ID, + 0x2, + 0x2, + ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), + cdns_pcie_cmn_regs_ext_ssc, + cdns_pcie_ln_regs_ext_ssc, + cdns_usb_cmn_regs_ext_ssc, + cdns_usb_ln_regs_ext_ssc, +}; + +static const struct cdns_sierra_data cdns_ti_map_sierra = { + SIERRA_MACRO_ID, + 0x0, + 0x1, + ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), + ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), + cdns_pcie_cmn_regs_ext_ssc, + cdns_pcie_ln_regs_ext_ssc, + cdns_usb_cmn_regs_ext_ssc, + cdns_usb_ln_regs_ext_ssc, +}; + +static const struct udevice_id cdns_sierra_id_table[] = { + { + .compatible = "cdns,sierra-phy-t0", + .data = (ulong)&cdns_map_sierra, + }, + { + .compatible = "ti,sierra-phy-t0", + .data = (ulong)&cdns_ti_map_sierra, + }, + {} +}; + +U_BOOT_DRIVER(sierra_phy_provider) = { + .name = "cdns,sierra", + .id = UCLASS_PHY, + .of_match = cdns_sierra_id_table, + .probe = cdns_sierra_phy_probe, + .remove = cdns_sierra_phy_remove, + .ops = &ops, + .priv_auto = sizeof(struct cdns_sierra_phy), +};

From: Jean-Jacques Hiblot jjhiblot@ti.com

Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes.

This is an adaptation of the linux driver.

Signed-off-by: Jean-Jacques Hiblot jjhiblot@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Signed-off-by: Kishon Vijay Abraham I kishon@ti.com --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/ti/Kconfig | 9 + drivers/phy/ti/Makefile | 1 + drivers/phy/ti/phy-j721e-wiz.c | 1156 ++++++++++++++++++++++++++++++++ 5 files changed, 1168 insertions(+) create mode 100644 drivers/phy/ti/Kconfig create mode 100644 drivers/phy/ti/Makefile create mode 100644 drivers/phy/ti/phy-j721e-wiz.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 9208e430a6..7821161e3c 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -270,5 +270,6 @@ config PHY_MTK_TPHY

source "drivers/phy/rockchip/Kconfig" source "drivers/phy/cadence/Kconfig" +source "drivers/phy/ti/Kconfig"

endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 4736c5eadb..2efaa8827b 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-y += cadence/ +obj-y += ti/ diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig new file mode 100644 index 0000000000..111085f235 --- /dev/null +++ b/drivers/phy/ti/Kconfig @@ -0,0 +1,9 @@ +config PHY_J721E_WIZ + tristate "TI J721E WIZ (SERDES Wrapper) support" + depends on ARCH_K3 + help + This option enables support for WIZ module present in TI's J721E + SoC. WIZ is a serdes wrapper used to configure some of the input + signals to the SERDES (Sierra/Torrent). This driver configures + three clock selects (pll0, pll1, dig) and resets for each of the + lanes. diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile new file mode 100644 index 0000000000..873ddbf036 --- /dev/null +++ b/drivers/phy/ti/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_$(SPL_)PHY_J721E_WIZ) += phy-j721e-wiz.o diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c new file mode 100644 index 0000000000..d74efcd212 --- /dev/null +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -0,0 +1,1156 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Jean-Jacques Hiblot jjhiblot@ti.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <asm/gpio.h> +#include <dm/lists.h> +#include <dm/device-internal.h> +#include <regmap.h> +#include <reset-uclass.h> +#include <dt-bindings/phy/phy.h> + +#include <dt-bindings/phy/phy-ti.h> + +#define WIZ_MAX_INPUT_CLOCKS 4 +/* To include mux clocks, divider clocks and gate clocks */ +#define WIZ_MAX_OUTPUT_CLOCKS 32 + +#define WIZ_MAX_LANES 4 +#define WIZ_MUX_NUM_CLOCKS 3 +#define WIZ_DIV_NUM_CLOCKS_16G 2 +#define WIZ_DIV_NUM_CLOCKS_10G 1 + +#define WIZ_SERDES_CTRL 0x404 +#define WIZ_SERDES_TOP_CTRL 0x408 +#define WIZ_SERDES_RST 0x40c +#define WIZ_SERDES_TYPEC 0x410 +#define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) +#define WIZ_LANEDIV(n) (0x484 + (0x40 * (n))) + +#define WIZ_MAX_LANES 4 +#define WIZ_MUX_NUM_CLOCKS 3 +#define WIZ_DIV_NUM_CLOCKS_16G 2 +#define WIZ_DIV_NUM_CLOCKS_10G 1 + +#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) + +enum wiz_lane_standard_mode { + LANE_MODE_GEN1, + LANE_MODE_GEN2, + LANE_MODE_GEN3, + LANE_MODE_GEN4, +}; + +enum wiz_refclk_mux_sel { + PLL0_REFCLK, + PLL1_REFCLK, + REFCLK_DIG, +}; + +enum wiz_refclk_div_sel { + CMN_REFCLK, + CMN_REFCLK1, +}; + +enum wiz_clock_input { + WIZ_CORE_REFCLK, + WIZ_EXT_REFCLK, + WIZ_CORE_REFCLK1, + WIZ_EXT_REFCLK1, +}; + +static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); +static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); +static const struct reg_field pll1_refclk_mux_sel = + REG_FIELD(WIZ_SERDES_RST, 29, 29); +static const struct reg_field pll0_refclk_mux_sel = + REG_FIELD(WIZ_SERDES_RST, 28, 28); +static const struct reg_field refclk_dig_sel_16g = + REG_FIELD(WIZ_SERDES_RST, 24, 25); +static const struct reg_field refclk_dig_sel_10g = + REG_FIELD(WIZ_SERDES_RST, 24, 24); +static const struct reg_field pma_cmn_refclk_int_mode = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); +static const struct reg_field pma_cmn_refclk_mode = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); +static const struct reg_field pma_cmn_refclk_dig_div = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); +static const struct reg_field pma_cmn_refclk1_dig_div = + REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); + +static const struct reg_field p_enable[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 30, 31), + REG_FIELD(WIZ_LANECTL(1), 30, 31), + REG_FIELD(WIZ_LANECTL(2), 30, 31), + REG_FIELD(WIZ_LANECTL(3), 30, 31), +}; + +enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; + +static const struct reg_field p_align[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 29, 29), + REG_FIELD(WIZ_LANECTL(1), 29, 29), + REG_FIELD(WIZ_LANECTL(2), 29, 29), + REG_FIELD(WIZ_LANECTL(3), 29, 29), +}; + +static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 28, 28), + REG_FIELD(WIZ_LANECTL(1), 28, 28), + REG_FIELD(WIZ_LANECTL(2), 28, 28), + REG_FIELD(WIZ_LANECTL(3), 28, 28), +}; + +static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 24, 25), + REG_FIELD(WIZ_LANECTL(1), 24, 25), + REG_FIELD(WIZ_LANECTL(2), 24, 25), + REG_FIELD(WIZ_LANECTL(3), 24, 25), +}; + +static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 22, 23), + REG_FIELD(WIZ_LANECTL(1), 22, 23), + REG_FIELD(WIZ_LANECTL(2), 22, 23), + REG_FIELD(WIZ_LANECTL(3), 22, 23), +}; + +static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANEDIV(0), 16, 22), + REG_FIELD(WIZ_LANEDIV(1), 16, 22), + REG_FIELD(WIZ_LANEDIV(2), 16, 22), + REG_FIELD(WIZ_LANEDIV(3), 16, 22), +}; + +static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANEDIV(0), 0, 8), + REG_FIELD(WIZ_LANEDIV(1), 0, 8), + REG_FIELD(WIZ_LANEDIV(2), 0, 8), + REG_FIELD(WIZ_LANEDIV(3), 0, 8), +}; + +struct wiz_clk_mux_sel { + enum wiz_refclk_mux_sel mux_sel; + u32 table[WIZ_MAX_INPUT_CLOCKS]; + const char *node_name; + u32 num_parents; + u32 parents[WIZ_MAX_INPUT_CLOCKS]; +}; + +struct wiz_clk_div_sel { + enum wiz_refclk_div_sel div_sel; + const char *node_name; +}; + +static struct wiz_clk_mux_sel clk_mux_sel_16g[] = { + { + /* + * Mux value to be configured for each of the input clocks + * in the order populated in device tree + */ + .num_parents = 2, + .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, + .mux_sel = PLL0_REFCLK, + .table = { 1, 0 }, + .node_name = "pll0-refclk", + }, + { + .num_parents = 2, + .parents = { WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK1 }, + .mux_sel = PLL1_REFCLK, + .table = { 1, 0 }, + .node_name = "pll1-refclk", + }, + { + .num_parents = 4, + .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK, WIZ_EXT_REFCLK1 }, + .mux_sel = REFCLK_DIG, + .table = { 1, 3, 0, 2 }, + .node_name = "refclk-dig", + }, +}; + +static struct wiz_clk_mux_sel clk_mux_sel_10g[] = { + { + /* + * Mux value to be configured for each of the input clocks + * in the order populated in device tree + */ + .num_parents = 2, + .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, + .mux_sel = PLL0_REFCLK, + .table = { 1, 0 }, + .node_name = "pll0-refclk", + }, + { + .num_parents = 2, + .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, + .mux_sel = PLL1_REFCLK, + .table = { 1, 0 }, + .node_name = "pll1-refclk", + }, + { + .num_parents = 2, + .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, + .mux_sel = REFCLK_DIG, + .table = { 1, 0 }, + .node_name = "refclk-dig", + }, +}; + +static struct wiz_clk_div_sel clk_div_sel[] = { + { + .div_sel = CMN_REFCLK, + .node_name = "cmn-refclk-dig-div", + }, + { + .div_sel = CMN_REFCLK1, + .node_name = "cmn-refclk1-dig-div", + }, +}; + +enum wiz_type { + J721E_WIZ_16G, + J721E_WIZ_10G, + AM64_WIZ_10G, +}; + +#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ +#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 + +struct wiz { + struct regmap *regmap; + enum wiz_type type; + struct wiz_clk_mux_sel *clk_mux_sel; + struct wiz_clk_div_sel *clk_div_sel; + unsigned int clk_div_sel_num; + struct regmap_field *por_en; + struct regmap_field *phy_reset_n; + struct regmap_field *phy_en_refclk; + struct regmap_field *p_enable[WIZ_MAX_LANES]; + struct regmap_field *p_align[WIZ_MAX_LANES]; + struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; + struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; + struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; + struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; + struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; + struct regmap_field *pma_cmn_refclk_int_mode; + struct regmap_field *pma_cmn_refclk_mode; + struct regmap_field *pma_cmn_refclk_dig_div; + struct regmap_field *pma_cmn_refclk1_dig_div; + struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; + struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; + + struct udevice *dev; + u32 num_lanes; + struct gpio_desc *gpio_typec_dir; + u32 lane_phy_type[WIZ_MAX_LANES]; + struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; + unsigned int id; +}; + +struct wiz_div_clk { + struct clk parent_clk; + struct wiz *wiz; +}; + +struct wiz_mux_clk { + struct clk parent_clks[4]; + struct wiz *wiz; +}; + +struct wiz_clk { + struct wiz *wiz; +}; + +struct wiz_reset { + struct wiz *wiz; +}; + +static ulong wiz_div_clk_get_rate(struct clk *clk) +{ + struct udevice *dev = clk->dev; + struct wiz_div_clk *priv = dev_get_priv(dev); + struct wiz_clk_div_sel *data = dev_get_plat(dev); + struct wiz *wiz = priv->wiz; + ulong parent_rate = clk_get_rate(&priv->parent_clk); + u32 val; + + regmap_field_read(wiz->div_sel_field[data->div_sel], &val); + + return parent_rate >> val; +} + +static ulong wiz_div_clk_set_rate(struct clk *clk, ulong rate) +{ + struct udevice *dev = clk->dev; + struct wiz_div_clk *priv = dev_get_priv(dev); + struct wiz_clk_div_sel *data = dev_get_plat(dev); + struct wiz *wiz = priv->wiz; + ulong parent_rate = clk_get_rate(&priv->parent_clk); + u32 div = parent_rate / rate; + + div = __ffs(div); + regmap_field_write(wiz->div_sel_field[data->div_sel], div); + + return parent_rate >> div; +} + +const struct clk_ops wiz_div_clk_ops = { + .get_rate = wiz_div_clk_get_rate, + .set_rate = wiz_div_clk_set_rate, +}; + +int wiz_div_clk_probe(struct udevice *dev) +{ + struct wiz_div_clk *priv = dev_get_priv(dev); + struct clk parent_clk; + int rc; + + rc = clk_get_by_index(dev, 0, &parent_clk); + if (rc) { + dev_err(dev, "unable to get parent clock. ret %d\n", rc); + return rc; + } + priv->parent_clk = parent_clk; + priv->wiz = dev_get_priv(dev->parent); + return 0; +} + +U_BOOT_DRIVER(wiz_div_clk) = { + .name = "wiz_div_clk", + .id = UCLASS_CLK, + .priv_auto = sizeof(struct wiz_div_clk), + .ops = &wiz_div_clk_ops, + .probe = wiz_div_clk_probe, +}; + +static int wiz_clk_mux_set_parent(struct clk *clk, struct clk *parent) +{ + struct udevice *dev = clk->dev; + struct wiz_mux_clk *priv = dev_get_priv(dev); + struct wiz_clk_mux_sel *data = dev_get_plat(dev); + struct wiz *wiz = priv->wiz; + int i; + + for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) + if (parent->dev == priv->parent_clks[i].dev) + break; + + if (i == ARRAY_SIZE(priv->parent_clks)) + return -EINVAL; + + regmap_field_write(wiz->mux_sel_field[data->mux_sel], data->table[i]); + return 0; +} + +static int wiz_clk_xlate(struct clk *clk, struct ofnode_phandle_args *args) +{ + struct udevice *dev = clk->dev; + struct wiz_mux_clk *priv = dev_get_priv(dev); + struct wiz *wiz = priv->wiz; + + clk->id = wiz->id; + + return 0; +} + +static const struct clk_ops wiz_clk_mux_ops = { + .set_parent = wiz_clk_mux_set_parent, + .of_xlate = wiz_clk_xlate, +}; + +int wiz_mux_clk_probe(struct udevice *dev) +{ + struct wiz_mux_clk *priv = dev_get_priv(dev); + int rc; + int i; + + for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) { + rc = clk_get_by_index(dev, i, &priv->parent_clks[i]); + if (rc) + priv->parent_clks[i].dev = NULL; + } + priv->wiz = dev_get_priv(dev->parent); + return 0; +} + +U_BOOT_DRIVER(wiz_mux_clk) = { + .name = "wiz_mux_clk", + .id = UCLASS_CLK, + .priv_auto = sizeof(struct wiz_mux_clk), + .ops = &wiz_clk_mux_ops, + .probe = wiz_mux_clk_probe, +}; + +static int wiz_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct udevice *dev = clk->dev; + struct wiz_clk *priv = dev_get_priv(dev); + const struct wiz_clk_mux_sel *mux_sel; + struct wiz *wiz = priv->wiz; + int num_parents; + int i, j, id; + + id = clk->id >> 10; + + /* set_parent is applicable only for MUX clocks */ + if (id > TI_WIZ_REFCLK_DIG) + return 0; + + for (i = 0; i < WIZ_MAX_INPUT_CLOCKS; i++) + if (wiz->input_clks[i]->dev == parent->dev) + break; + + if (i == WIZ_MAX_INPUT_CLOCKS) + return -EINVAL; + + mux_sel = &wiz->clk_mux_sel[id]; + num_parents = mux_sel->num_parents; + for (j = 0; j < num_parents; j++) + if (mux_sel->parents[j] == i) + break; + + if (j == num_parents) + return -EINVAL; + + regmap_field_write(wiz->mux_sel_field[id], mux_sel->table[j]); + + return 0; +} + +static int wiz_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) +{ + struct udevice *dev = clk->dev; + struct wiz_clk *priv = dev_get_priv(dev); + struct wiz *wiz = priv->wiz; + + clk->id = args->args[0] << 10 | wiz->id; + + return 0; +} + +static const struct clk_ops wiz_clk_ops = { + .set_parent = wiz_clk_set_parent, + .of_xlate = wiz_clk_of_xlate, +}; + +int wiz_clk_probe(struct udevice *dev) +{ + struct wiz_clk *priv = dev_get_priv(dev); + + priv->wiz = dev_get_priv(dev->parent); + + return 0; +} + +U_BOOT_DRIVER(wiz_clk) = { + .name = "wiz_clk", + .id = UCLASS_CLK, + .priv_auto = sizeof(struct wiz_clk), + .ops = &wiz_clk_ops, + .probe = wiz_clk_probe, +}; + +static int wiz_reset_request(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int wiz_reset_free(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int wiz_reset_assert(struct reset_ctl *reset_ctl) +{ + struct wiz_reset *priv = dev_get_priv(reset_ctl->dev); + struct wiz *wiz = priv->wiz; + int ret; + int id = reset_ctl->id; + + if (id == 0) { + ret = regmap_field_write(wiz->phy_reset_n, false); + return ret; + } + + ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); + return ret; +} + +static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) +{ + if (wiz->type != AM64_WIZ_10G) + return 0; + + if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) + return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); + + return 0; +} + +static int wiz_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct wiz_reset *priv = dev_get_priv(reset_ctl->dev); + struct wiz *wiz = priv->wiz; + int ret; + int id = reset_ctl->id; + + ret = wiz_phy_fullrt_div(wiz, id - 1); + if (ret) + return ret; + + /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ + if (id == 0 && wiz->gpio_typec_dir) { + if (dm_gpio_get_value(wiz->gpio_typec_dir)) { + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN10_SWAP, + WIZ_SERDES_TYPEC_LN10_SWAP); + } else { + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN10_SWAP, 0); + } + } + + if (id == 0) { + ret = regmap_field_write(wiz->phy_reset_n, true); + return ret; + } + + if (wiz->lane_phy_type[id - 1] == PHY_TYPE_PCIE) + ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); + else + ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); + + return ret; +} + +static struct reset_ops wiz_reset_ops = { + .request = wiz_reset_request, + .rfree = wiz_reset_free, + .rst_assert = wiz_reset_assert, + .rst_deassert = wiz_reset_deassert, +}; + +int wiz_reset_probe(struct udevice *dev) +{ + struct wiz_reset *priv = dev_get_priv(dev); + + priv->wiz = dev_get_priv(dev->parent); + + return 0; +} + +U_BOOT_DRIVER(wiz_reset) = { + .name = "wiz-reset", + .id = UCLASS_RESET, + .probe = wiz_reset_probe, + .ops = &wiz_reset_ops, + .flags = DM_FLAG_LEAVE_PD_ON, +}; + +static int wiz_reset(struct wiz *wiz) +{ + int ret; + + ret = regmap_field_write(wiz->por_en, 0x1); + if (ret) + return ret; + + mdelay(1); + + ret = regmap_field_write(wiz->por_en, 0x0); + if (ret) + return ret; + + return 0; +} + +static int wiz_p_mac_div_sel(struct wiz *wiz) +{ + u32 num_lanes = wiz->num_lanes; + int ret; + int i; + + for (i = 0; i < num_lanes; i++) { + if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { + ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); + if (ret) + return ret; + + ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); + if (ret) + return ret; + } + } + + return 0; +} + +static int wiz_mode_select(struct wiz *wiz) +{ + u32 num_lanes = wiz->num_lanes; + int ret; + int i; + + for (i = 0; i < num_lanes; i++) { + if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { + ret = regmap_field_write(wiz->p_standard_mode[i], + LANE_MODE_GEN2); + if (ret) + return ret; + } + } + + return 0; +} + +static int wiz_init_raw_interface(struct wiz *wiz, bool enable) +{ + u32 num_lanes = wiz->num_lanes; + int i; + int ret; + + for (i = 0; i < num_lanes; i++) { + ret = regmap_field_write(wiz->p_align[i], enable); + if (ret) + return ret; + + ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); + if (ret) + return ret; + } + + return 0; +} + +static int wiz_init(struct wiz *wiz) +{ + struct udevice *dev = wiz->dev; + int ret; + + ret = wiz_reset(wiz); + if (ret) { + dev_err(dev, "WIZ reset failed\n"); + return ret; + } + + ret = wiz_mode_select(wiz); + if (ret) { + dev_err(dev, "WIZ mode select failed\n"); + return ret; + } + + ret = wiz_p_mac_div_sel(wiz); + if (ret) { + dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); + return ret; + } + + ret = wiz_init_raw_interface(wiz, true); + if (ret) { + dev_err(dev, "WIZ interface initialization failed\n"); + return ret; + } + + return 0; +} + +static int wiz_regfield_init(struct wiz *wiz) +{ + struct regmap *regmap = wiz->regmap; + int num_lanes = wiz->num_lanes; + struct udevice *dev = wiz->dev; + enum wiz_type type; + int i; + + wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); + if (IS_ERR(wiz->por_en)) { + dev_err(dev, "POR_EN reg field init failed\n"); + return PTR_ERR(wiz->por_en); + } + + wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, + phy_reset_n); + if (IS_ERR(wiz->phy_reset_n)) { + dev_err(dev, "PHY_RESET_N reg field init failed\n"); + return PTR_ERR(wiz->phy_reset_n); + } + + wiz->pma_cmn_refclk_int_mode = + devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); + if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { + dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); + return PTR_ERR(wiz->pma_cmn_refclk_int_mode); + } + + wiz->pma_cmn_refclk_mode = + devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); + if (IS_ERR(wiz->pma_cmn_refclk_mode)) { + dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); + return PTR_ERR(wiz->pma_cmn_refclk_mode); + } + + wiz->div_sel_field[CMN_REFCLK] = + devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div); + if (IS_ERR(wiz->div_sel_field[CMN_REFCLK])) { + dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); + return PTR_ERR(wiz->div_sel_field[CMN_REFCLK]); + } + + wiz->div_sel_field[CMN_REFCLK1] = + devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk1_dig_div); + if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) { + dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); + return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]); + } + + wiz->mux_sel_field[PLL0_REFCLK] = + devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel); + if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { + dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); + return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); + } + + wiz->mux_sel_field[PLL1_REFCLK] = + devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel); + if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { + dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); + return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); + } + + type = dev_get_driver_data(dev); + if (type == J721E_WIZ_10G || type == AM64_WIZ_10G) + wiz->mux_sel_field[REFCLK_DIG] = + devm_regmap_field_alloc(dev, regmap, + refclk_dig_sel_10g); + else + wiz->mux_sel_field[REFCLK_DIG] = + devm_regmap_field_alloc(dev, regmap, + refclk_dig_sel_16g); + if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { + dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); + return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); + } + + for (i = 0; i < num_lanes; i++) { + wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, + p_enable[i]); + if (IS_ERR(wiz->p_enable[i])) { + dev_err(dev, "P%d_ENABLE reg field init failed\n", i); + return PTR_ERR(wiz->p_enable[i]); + } + + wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, + p_align[i]); + if (IS_ERR(wiz->p_align[i])) { + dev_err(dev, "P%d_ALIGN reg field init failed\n", i); + return PTR_ERR(wiz->p_align[i]); + } + + wiz->p_raw_auto_start[i] = + devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); + if (IS_ERR(wiz->p_raw_auto_start[i])) { + dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", + i); + return PTR_ERR(wiz->p_raw_auto_start[i]); + } + + wiz->p_standard_mode[i] = + devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); + if (IS_ERR(wiz->p_standard_mode[i])) { + dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", + i); + return PTR_ERR(wiz->p_standard_mode[i]); + } + + wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); + if (IS_ERR(wiz->p0_fullrt_div[i])) { + dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i); + return PTR_ERR(wiz->p0_fullrt_div[i]); + } + + wiz->p_mac_div_sel0[i] = + devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); + if (IS_ERR(wiz->p_mac_div_sel0[i])) { + dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n", + i); + return PTR_ERR(wiz->p_mac_div_sel0[i]); + } + + wiz->p_mac_div_sel1[i] = + devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]); + if (IS_ERR(wiz->p_mac_div_sel1[i])) { + dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n", + i); + return PTR_ERR(wiz->p_mac_div_sel1[i]); + } + } + + return 0; +} + +static int wiz_clock_init(struct wiz *wiz) +{ + struct udevice *dev = wiz->dev; + unsigned long rate; + struct clk *clk; + int ret; + + clk = devm_clk_get(dev, "core_ref_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "core_ref_clk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + wiz->input_clks[WIZ_CORE_REFCLK] = clk; + /* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */ + wiz->input_clks[WIZ_CORE_REFCLK1] = clk; + + rate = clk_get_rate(clk); + if (rate >= 100000000) + regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); + else + regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); + + clk = devm_clk_get(dev, "ext_ref_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "ext_ref_clk clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + + wiz->input_clks[WIZ_EXT_REFCLK] = clk; + /* Initialize EXT_REFCLK1 to the same clock reference to maintain old DT compatibility */ + wiz->input_clks[WIZ_EXT_REFCLK1] = clk; + + rate = clk_get_rate(clk); + if (rate >= 100000000) + regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); + else + regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); + + return 0; +} + +static ofnode get_child_by_name(struct udevice *dev, const char *name) +{ + int l = strlen(name); + ofnode node = dev_read_first_subnode(dev); + + while (ofnode_valid(node)) { + const char *child_name = ofnode_get_name(node); + + if (!strncmp(child_name, name, l)) { + if (child_name[l] == '\0' || child_name[l] == '@') + return node; + } + node = dev_read_next_subnode(node); + } + return node; +} + +static int j721e_wiz_bind_clocks(struct wiz *wiz) +{ + struct udevice *dev = wiz->dev; + struct driver *wiz_clk_drv; + int i, rc; + + wiz_clk_drv = lists_driver_lookup_name("wiz_clk"); + if (!wiz_clk_drv) { + dev_err(dev, "Cannot find driver 'wiz_clk'\n"); + return -ENOENT; + } + + for (i = 0; i < WIZ_DIV_NUM_CLOCKS_10G; i++) { + rc = device_bind(dev, wiz_clk_drv, clk_div_sel[i].node_name, + &clk_div_sel[i], dev_ofnode(dev), NULL); + if (rc) { + dev_err(dev, "cannot bind driver for clock %s\n", + clk_div_sel[i].node_name); + } + } + + for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { + rc = device_bind(dev, wiz_clk_drv, clk_mux_sel_10g[i].node_name, + &clk_mux_sel_10g[i], dev_ofnode(dev), NULL); + if (rc) { + dev_err(dev, "cannot bind driver for clock %s\n", + clk_mux_sel_10g[i].node_name); + } + } + + return 0; +} + +static int j721e_wiz_bind_of_clocks(struct wiz *wiz) +{ + struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; + struct udevice *dev = wiz->dev; + enum wiz_type type = wiz->type; + struct driver *div_clk_drv; + struct driver *mux_clk_drv; + ofnode node; + int i, rc; + + if (type == AM64_WIZ_10G) + return j721e_wiz_bind_clocks(wiz); + + div_clk_drv = lists_driver_lookup_name("wiz_div_clk"); + if (!div_clk_drv) { + dev_err(dev, "Cannot find driver 'wiz_div_clk'\n"); + return -ENOENT; + } + + mux_clk_drv = lists_driver_lookup_name("wiz_mux_clk"); + if (!mux_clk_drv) { + dev_err(dev, "Cannot find driver 'wiz_mux_clk'\n"); + return -ENOENT; + } + + for (i = 0; i < wiz->clk_div_sel_num; i++) { + node = get_child_by_name(dev, clk_div_sel[i].node_name); + if (!ofnode_valid(node)) { + dev_err(dev, "cannot find node for clock %s\n", + clk_div_sel[i].node_name); + continue; + } + rc = device_bind(dev, div_clk_drv, clk_div_sel[i].node_name, + &clk_div_sel[i], node, NULL); + if (rc) { + dev_err(dev, "cannot bind driver for clock %s\n", + clk_div_sel[i].node_name); + } + } + + for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { + node = get_child_by_name(dev, clk_mux_sel[i].node_name); + if (!ofnode_valid(node)) { + dev_err(dev, "cannot find node for clock %s\n", + clk_mux_sel[i].node_name); + continue; + } + rc = device_bind(dev, mux_clk_drv, clk_mux_sel[i].node_name, + &clk_mux_sel[i], node, NULL); + if (rc) { + dev_err(dev, "cannot bind driver for clock %s\n", + clk_mux_sel[i].node_name); + } + } + + return 0; +} + +static int j721e_wiz_bind_reset(struct udevice *dev) +{ + int rc; + struct driver *drv; + + drv = lists_driver_lookup_name("wiz-reset"); + if (!drv) { + dev_err(dev, "Cannot find driver 'wiz-reset'\n"); + return -ENOENT; + } + + rc = device_bind(dev, drv, "wiz-reset", NULL, dev_ofnode(dev), NULL); + if (rc) { + dev_err(dev, "cannot bind driver for wiz-reset\n"); + return rc; + } + + return 0; +} + +static int j721e_wiz_bind(struct udevice *dev) +{ + dm_scan_fdt_dev(dev); + + return 0; +} + +static int wiz_get_lane_phy_types(struct udevice *dev, struct wiz *wiz) +{ + ofnode child, serdes; + + serdes = get_child_by_name(dev, "serdes"); + if (!ofnode_valid(serdes)) { + dev_err(dev, "%s: Getting "serdes"-node failed\n", __func__); + return -EINVAL; + } + + ofnode_for_each_subnode(child, serdes) { + u32 reg, num_lanes = 1, phy_type = PHY_NONE; + int ret, i; + + ret = ofnode_read_u32(child, "reg", &reg); + if (ret) { + dev_err(dev, "%s: Reading "reg" from failed: %d\n", + __func__, ret); + return ret; + } + ofnode_read_u32(child, "cdns,num-lanes", &num_lanes); + ofnode_read_u32(child, "cdns,phy-type", &phy_type); + + dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, + reg, reg + num_lanes - 1, phy_type); + + for (i = reg; i < reg + num_lanes; i++) + wiz->lane_phy_type[i] = phy_type; + } + + return 0; +} + +static int j721e_wiz_probe(struct udevice *dev) +{ + struct wiz *wiz = dev_get_priv(dev); + struct ofnode_phandle_args args; + unsigned int val; + int rc, i; + ofnode node; + struct regmap *regmap; + u32 num_lanes; + + node = get_child_by_name(dev, "serdes"); + + if (!ofnode_valid(node)) { + dev_err(dev, "Failed to get SERDES child DT node\n"); + return -ENODEV; + } + + rc = regmap_init_mem(node, &regmap); + if (rc) { + dev_err(dev, "Failed to get memory resource\n"); + return rc; + } + rc = dev_read_u32(dev, "num-lanes", &num_lanes); + if (rc) { + dev_err(dev, "Failed to read num-lanes property\n"); + goto err_addr_to_resource; + } + + if (num_lanes > WIZ_MAX_LANES) { + dev_err(dev, "Cannot support %d lanes\n", num_lanes); + goto err_addr_to_resource; + } + + wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", + GPIOD_IS_IN); + if (IS_ERR(wiz->gpio_typec_dir)) { + rc = PTR_ERR(wiz->gpio_typec_dir); + dev_err(dev, "Failed to request typec-dir gpio: %d\n", rc); + goto err_addr_to_resource; + } + + rc = dev_read_phandle_with_args(dev, "power-domains", "#power-domain-cells", 0, 0, &args); + if (rc) { + dev_err(dev, "Failed to get power domain: %d\n", rc); + goto err_addr_to_resource; + } + + wiz->id = args.args[0]; + wiz->regmap = regmap; + wiz->num_lanes = num_lanes; + wiz->dev = dev; + wiz->clk_div_sel = clk_div_sel; + wiz->type = dev_get_driver_data(dev); + if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) { + wiz->clk_mux_sel = clk_mux_sel_10g; + wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G; + } else { + wiz->clk_mux_sel = clk_mux_sel_16g; + wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G; + } + + rc = wiz_get_lane_phy_types(dev, wiz); + if (rc) { + dev_err(dev, "Failed to get lane PHY types\n"); + goto err_addr_to_resource; + } + + rc = wiz_regfield_init(wiz); + if (rc) { + dev_err(dev, "Failed to initialize regfields\n"); + goto err_addr_to_resource; + } + + for (i = 0; i < wiz->num_lanes; i++) { + regmap_field_read(wiz->p_enable[i], &val); + if (val & (P_ENABLE | P_ENABLE_FORCE)) { + dev_err(dev, "SERDES already configured\n"); + rc = -EBUSY; + goto err_addr_to_resource; + } + } + + rc = j721e_wiz_bind_of_clocks(wiz); + if (rc) { + dev_err(dev, "Failed to bind clocks\n"); + goto err_addr_to_resource; + } + + rc = j721e_wiz_bind_reset(dev); + if (rc) { + dev_err(dev, "Failed to bind reset\n"); + goto err_addr_to_resource; + } + + rc = wiz_clock_init(wiz); + if (rc) { + dev_warn(dev, "Failed to initialize clocks\n"); + goto err_addr_to_resource; + } + + rc = wiz_init(wiz); + if (rc) { + dev_err(dev, "WIZ initialization failed\n"); + goto err_addr_to_resource; + } + + return 0; + +err_addr_to_resource: + free(regmap); + + return rc; +} + +static int j721e_wiz_remove(struct udevice *dev) +{ + struct wiz *wiz = dev_get_priv(dev); + + if (wiz->regmap) + free(wiz->regmap); + + return 0; +} + +static const struct udevice_id j721e_wiz_ids[] = { + { + .compatible = "ti,j721e-wiz-16g", .data = J721E_WIZ_16G, + }, + { + .compatible = "ti,j721e-wiz-10g", .data = J721E_WIZ_10G, + }, + { + .compatible = "ti,am64-wiz-10g", .data = AM64_WIZ_10G, + }, + {} +}; + +U_BOOT_DRIVER(phy_j721e_wiz) = { + .name = "phy-j721e-wiz", + .id = UCLASS_NOP, + .of_match = j721e_wiz_ids, + .bind = j721e_wiz_bind, + .probe = j721e_wiz_probe, + .remove = j721e_wiz_remove, + .priv_auto = sizeof(struct wiz), + .flags = DM_FLAG_LEAVE_PD_ON, +};

Configure the parent clock of wiz3_pll0_refclk to the internal clock required for USB3 to be functional and also remove "ti,usb2-only" property as it now supports USB3 mode. This has properties specific to u-boot on top of DT present in v5.13 of Linux Kernel.

Signed-off-by: Jean-Jacques Hiblot jjhiblot@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Signed-off-by: Kishon Vijay Abraham I kishon@ti.com --- .../k3-j721e-common-proc-board-u-boot.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 974dae8416..85dbf8d2ac 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -129,13 +129,17 @@ u-boot,dm-spl; };

+&wiz3_pll1_refclk { + assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>; + assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>; +}; + &main_usbss0_pins_default { u-boot,dm-spl; };

&usbss0 { u-boot,dm-spl; - ti,usb2-only; };

&usb0 { @@ -215,3 +219,16 @@ &main_r5fss1 { ti,cluster-mode = <0>; }; + +&wiz3_pll1_refclk { + assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>; + assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>; +}; + +&serdes_ln_ctrl { + u-boot,mux-autoprobe; +}; + +&usb_serdes_mux { + u-boot,mux-autoprobe; +};

From: Aswath Govindraju a-govindraju@ti.com

Add default lane function for torrent serdes. This is in sync with v5.13 Linux Kernel.

Signed-off-by: Aswath Govindraju a-govindraju@ti.com Signed-off-by: Kishon Vijay Abraham I kishon@ti.com --- arch/arm/dts/k3-j7200-common-proc-board.dts | 23 +++++++++++++++++++++ 1 file changed, 23 insertions(+)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts index 5120711d4f..f0440cda1a 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-common-proc-board.dts @@ -9,6 +9,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/net/ti-dp83867.h> #include <dt-bindings/mux/ti-serdes.h> +#include <dt-bindings/phy/phy.h>

/ { chosen { @@ -281,3 +282,25 @@ ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + serdes0_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_qsgmii_link: link@1 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_QSGMII>; + resets = <&serdes_wiz0 3>; + }; +};

From: Jean-Jacques Hiblot jjhiblot@ti.com

Enable the mmio mux driver, the J721E-wiz PHy driver and the cadence sierra phy driver. All of them are required for USB3 support

Signed-off-by: Jean-Jacques Hiblot jjhiblot@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Signed-off-by: Kishon Vijay Abraham I kishon@ti.com --- configs/j721e_evm_a72_defconfig | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 365d662690..e2b0270ef9 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -135,9 +135,15 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_TI_DP83867=y +CONFIG_MULTIPLEXER=y +CONFIG_MUX_MMIO=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_PHY_CADENCE_SIERRA=y +CONFIG_PHY_J721E_WIZ=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y

MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1" on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 18.

Signed-off-by: Kishon Vijay Abraham I kishon@ti.com Reviewed-by: Suman Anna s-anna@ti.com --- include/configs/j721e_evm.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index b707fc4e89..00d0a18a68 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -139,11 +139,24 @@ #endif /* CONFIG_TARGET_J721E_A72_EVM */

#ifdef CONFIG_TARGET_J7200_A72_EVM +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \ + "do_main_cpsw0_qsgmii_phyinit=1\0" \ + "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \ + "gpio clear gpio@22_16\0" \ + "main_cpsw0_qsgmii_phyinit=" \ + "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \ + "test ${boot} = mmc; then " \ + "run init_main_cpsw0_qsgmii_phy;" \ + "fi;\0" #define DEFAULT_RPROCS "" \ "2 /lib/firmware/j7200-main-r5f0_0-fw " \ "3 /lib/firmware/j7200-main-r5f0_1-fw " #endif /* CONFIG_TARGET_J7200_A72_EVM */

+#ifndef EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY +#endif + /* set default dfu_bufsiz to 128KB (sector size of OSPI) */ #define EXTRA_ENV_DFUARGS \ "dfu_bufsiz=0x20000\0" \ @@ -170,7 +183,8 @@ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ DEFAULT_UFS_TI_ARGS \ - EXTRA_ENV_J721E_BOARD_SETTINGS_MTD + EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \ + EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY

/* Now for the remaining common defines */ #include <configs/ti_armv7_common.h>

Move j721e document from board/ti/j721e/README to doc/board/ti/j721e_evm.rst after converting it to RST format.

Signed-off-by: Kishon Vijay Abraham I kishon@ti.com --- board/ti/j721e/README | 277 -------------------------------- doc/board/index.rst | 1 + doc/board/ti/j721e_evm.rst | 316 +++++++++++++++++++++++++++++++++++++ 3 files changed, 317 insertions(+), 277 deletions(-) delete mode 100644 board/ti/j721e/README create mode 100644 doc/board/ti/j721e_evm.rst

diff --git a/board/ti/j721e/README b/board/ti/j721e/README deleted file mode 100644 index b1c9145c92..0000000000 --- a/board/ti/j721e/README +++ /dev/null @@ -1,277 +0,0 @@ -Introduction: -------------- -The J721e family of SoCs are part of K3 Multicore SoC architecture platform -targeting automotive applications. They are designed as a low power, high -performance and highly integrated device architecture, adding significant -enhancement on processing power, graphics capability, video and imaging -processing, virtualization and coherent memory support. - -The device is partitioned into three functional domains, each containing -specific processing cores and peripherals: -1. Wake-up (WKUP) domain: - - Device Management and Security Controller (DMSC) -2. Microcontroller (MCU) domain: - - Dual Core ARM Cortex-R5F processor -3. MAIN domain: - - Dual core 64-bit ARM Cortex-A72 - - 2 x Dual cortex ARM Cortex-R5 subsystem - - 2 x C66x Digital signal processor sub system - - C71x Digital signal processor sub-system with MMA. - -More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1 - -Boot Flow: ----------- -Boot flow is similar to that of AM65x SoC and extending it with remoteproc -support. Below is the pictorial representation of boot flow: - -+------------------------------------------------------------------------+-----------------------+ -| DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | -+------------------------------------------------------------------------+-----------------------+ -| +--------+ | | | | -| | Reset | | | | | -| +--------+ | | | | -| : | | | | -| +--------+ | +-----------+ | | | -| | *ROM* |----------|-->| Reset rls | | | | -| +--------+ | +-----------+ | | | -| | | | : | | | -| | ROM | | : | | | -| |services| | : | | | -| | | | +-------------+ | | | -| | | | | *R5 ROM* | | | | -| | | | +-------------+ | | | -| | |<---------|---|Load and auth| | | | -| | | | | tiboot3.bin | | | | -| | | | +-------------+ | | | -| | | | : | | | -| | | | : | | | -| | | | : | | | -| | | | +-------------+ | | | -| | | | | *R5 SPL* | | | | -| | | | +-------------+ | | | -| | | | | Load | | | | -| | | | | sysfw.itb | | | | -| | Start | | +-------------+ | | | -| | System |<---------|---| Start | | | | -| |Firmware| | | SYSFW | | | | -| +--------+ | +-------------+ | | | -| : | | | | | | -| +---------+ | | Load | | | | -| | *SYSFW* | | | system | | | | -| +---------+ | | Config data | | | | -| | |<--------|---| | | | | -| | | | +-------------+ | | | -| | | | | DDR | | | | -| | | | | config | | | | -| | | | +-------------+ | | | -| | | | | Load | | | | -| | | | | tispl.bin | | | | -| | | | +-------------+ | | | -| | | | | Load R5 | | | | -| | | | | firmware | | | | -| | | | +-------------+ | | | -| | |<--------|---| Start A72 | | | | -| | | | | and jump to | | | | -| | | | | DM fw image | | | | -| | | | +-------------+ | | | -| | | | | +-----------+ | | -| | |---------|-----------------------|---->| Reset rls | | | -| | | | | +-----------+ | | -| | TIFS | | | : | | -| |Services | | | +-----------+ | | -| | |<--------|-----------------------|---->|*ATF/OPTEE*| | | -| | | | | +-----------+ | | -| | | | | : | | -| | | | | +-----------+ | | -| | |<--------|-----------------------|---->| *A72 SPL* | | | -| | | | | +-----------+ | | -| | | | | | Load | | | -| | | | | | u-boot.img| | | -| | | | | +-----------+ | | -| | | | | : | | -| | | | | +-----------+ | | -| | |<--------|-----------------------|---->| *U-Boot* | | | -| | | | | +-----------+ | | -| | | | | | prompt | | | -| | | | | +-----------+ | | -| | | | | | Load R5 | | | -| | | | | | Firmware | | | -| | | | | +-----------+ | | -| | |<--------|-----------------------|-----| Start R5 | | +-----------+ | -| | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | -| | | | | | Load C6 | | +-----------+ | -| | | | | | Firmware | | | -| | | | | +-----------+ | | -| | |<--------|-----------------------|-----| Start C6 | | +-----------+ | -| | |---------|-----------------------|-----+-----------+-----|----->| C6 starts | | -| | | | | | Load C7 | | +-----------+ | -| | | | | | Firmware | | | -| | | | | +-----------+ | | -| | |<--------|-----------------------|-----| Start C7 | | +-----------+ | -| | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | -| +---------+ | | | +-----------+ | -| | | | | -+------------------------------------------------------------------------+-----------------------+ - -- Here DMSC acts as master and provides all the critical services. R5/A72 -requests DMSC to get these services done as shown in the above diagram. - -Sources: --------- -1. SYSFW: - Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git - Branch: master - -2. ATF: - Tree: https://github.com/ARM-software/arm-trusted-firmware.git - Branch: master - -3. OPTEE: - Tree: https://github.com/OP-TEE/optee_os.git - Branch: master - -4. U-Boot: - Tree: https://source.denx.de/u-boot/u-boot - Branch: master - -Build procedure: ----------------- -1. SYSFW: -$ make CROSS_COMPILE=arm-linux-gnueabihf- - -2. ATF: -$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed - -3. OPTEE: -$ make PLATFORM=k3-j721e CFG_ARM64_core=y - -4. U-Boot: - -4.1. R5: -$ make CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=/tmp/r5 -$ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5 - -4.2. A72: -$ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72 -$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<path to DM firmware image> O=/tmp/a72 - -Target Images --------------- -Copy the below images to an SD card and boot: -- sysfw.itb from step 1 -- tiboot3.bin from step 4.1 -- tispl.bin, u-boot.img from 4.2 - -Image formats: --------------- - -- tiboot3.bin: - +-----------------------+ - | X.509 | - | Certificate | - | +-------------------+ | - | | | | - | | R5 | | - | | u-boot-spl.bin | | - | | | | - | +-------------------+ | - | | | | - | | FIT header | | - | | +---------------+ | | - | | | | | | - | | | DTB 1...N | | | - | | +---------------+ | | - | +-------------------+ | - +-----------------------+ - -- tispl.bin - +-----------------------+ - | | - | FIT HEADER | - | +-------------------+ | - | | | | - | | A72 ATF | | - | +-------------------+ | - | | | | - | | A72 OPTEE | | - | +-------------------+ | - | | | | - | | R5 DM FW | | - | +-------------------+ | - | | | | - | | A72 SPL | | - | +-------------------+ | - | | | | - | | SPL DTB 1...N | | - | +-------------------+ | - +-----------------------+ - -- sysfw.itb - +-----------------------+ - | | - | FIT HEADER | - | +-------------------+ | - | | | | - | | sysfw.bin | | - | +-------------------+ | - | | | | - | | board config | | - | +-------------------+ | - | | | | - | | PM config | | - | +-------------------+ | - | | | | - | | RM config | | - | +-------------------+ | - | | | | - | | Secure config | | - | +-------------------+ | - +-----------------------+ - -OSPI: ------ -ROM supports booting from OSPI from offset 0x0. - -Flashing images to OSPI: - -Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img, -and sysfw.itb over tftp and then flash those to OSPI at their respective -addresses. - -=> sf probe -=> tftp ${loadaddr} tiboot3.bin -=> sf update $loadaddr 0x0 $filesize -=> tftp ${loadaddr} tispl.bin -=> sf update $loadaddr 0x80000 $filesize -=> tftp ${loadaddr} u-boot.img -=> sf update $loadaddr 0x280000 $filesize -=> tftp ${loadaddr} sysfw.itb -=> sf update $loadaddr 0x6C0000 $filesize - -Flash layout for OSPI: - - 0x0 +----------------------------+ - | ospi.tiboot3(512K) | - | | - 0x80000 +----------------------------+ - | ospi.tispl(2M) | - | | - 0x280000 +----------------------------+ - | ospi.u-boot(4M) | - | | - 0x680000 +----------------------------+ - | ospi.env(128K) | - | | - 0x6A0000 +----------------------------+ - | ospi.env.backup (128K) | - | | - 0x6C0000 +----------------------------+ - | ospi.sysfw(1M) | - | | - 0x7C0000 +----------------------------+ - | padding (256k) | - 0x800000 +----------------------------+ - | ospi.rootfs(UBIFS) | - | | - +----------------------------+ diff --git a/doc/board/index.rst b/doc/board/index.rst index 196b597609..69f2385ce3 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -26,6 +26,7 @@ Board-specific doc socionext/index st/index tbs/index + ti/index toradex/index xen/index xilinx/index diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst new file mode 100644 index 0000000000..8b460709d1 --- /dev/null +++ b/doc/board/ti/j721e_evm.rst @@ -0,0 +1,316 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Lokesh Vutla lokeshvutla@ti.com + +Texas Instruments K3 Platforms +============================== + +Introduction: +------------- +The J721e family of SoCs are part of K3 Multicore SoC architecture platform +targeting automotive applications. They are designed as a low power, high +performance and highly integrated device architecture, adding significant +enhancement on processing power, graphics capability, video and imaging +processing, virtualization and coherent memory support. + +The device is partitioned into three functional domains, each containing +specific processing cores and peripherals: + +1. Wake-up (WKUP) domain: + * Device Management and Security Controller (DMSC) + +2. Microcontroller (MCU) domain: + * Dual Core ARM Cortex-R5F processor + +3. MAIN domain: + * Dual core 64-bit ARM Cortex-A72 + * 2 x Dual cortex ARM Cortex-R5 subsystem + * 2 x C66x Digital signal processor sub system + * C71x Digital signal processor sub-system with MMA. + +More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1 + +Boot Flow: +---------- +Boot flow is similar to that of AM65x SoC and extending it with remoteproc +support. Below is the pictorial representation of boot flow: + +.. code-block:: text + + +------------------------------------------------------------------------+-----------------------+ + | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | + +------------------------------------------------------------------------+-----------------------+ + | +--------+ | | | | + | | Reset | | | | | + | +--------+ | | | | + | : | | | | + | +--------+ | +-----------+ | | | + | | *ROM* |----------|-->| Reset rls | | | | + | +--------+ | +-----------+ | | | + | | | | : | | | + | | ROM | | : | | | + | |services| | : | | | + | | | | +-------------+ | | | + | | | | | *R5 ROM* | | | | + | | | | +-------------+ | | | + | | |<---------|---|Load and auth| | | | + | | | | | tiboot3.bin | | | | + | | | | +-------------+ | | | + | | | | : | | | + | | | | : | | | + | | | | : | | | + | | | | +-------------+ | | | + | | | | | *R5 SPL* | | | | + | | | | +-------------+ | | | + | | | | | Load | | | | + | | | | | sysfw.itb | | | | + | | Start | | +-------------+ | | | + | | System |<---------|---| Start | | | | + | |Firmware| | | SYSFW | | | | + | +--------+ | +-------------+ | | | + | : | | | | | | + | +---------+ | | Load | | | | + | | *SYSFW* | | | system | | | | + | +---------+ | | Config data | | | | + | | |<--------|---| | | | | + | | | | +-------------+ | | | + | | | | | DDR | | | | + | | | | | config | | | | + | | | | +-------------+ | | | + | | | | | Load | | | | + | | | | | tispl.bin | | | | + | | | | +-------------+ | | | + | | | | | Load R5 | | | | + | | | | | firmware | | | | + | | | | +-------------+ | | | + | | |<--------|---| Start A72 | | | | + | | | | | and jump to | | | | + | | | | | DM fw image | | | | + | | | | +-------------+ | | | + | | | | | +-----------+ | | + | | |---------|-----------------------|---->| Reset rls | | | + | | | | | +-----------+ | | + | | TIFS | | | : | | + | |Services | | | +-----------+ | | + | | |<--------|-----------------------|---->|*ATF/OPTEE*| | | + | | | | | +-----------+ | | + | | | | | : | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|---->| *A72 SPL* | | | + | | | | | +-----------+ | | + | | | | | | Load | | | + | | | | | | u-boot.img| | | + | | | | | +-----------+ | | + | | | | | : | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|---->| *U-Boot* | | | + | | | | | +-----------+ | | + | | | | | | prompt | | | + | | | | | +-----------+ | | + | | | | | | Load R5 | | | + | | | | | | Firmware | | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | + | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | + | | | | | | Load C6 | | +-----------+ | + | | | | | | Firmware | | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|-----| Start C6 | | +-----------+ | + | | |---------|-----------------------|-----+-----------+-----|----->| C6 starts | | + | | | | | | Load C7 | | +-----------+ | + | | | | | | Firmware | | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | + | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | + | +---------+ | | | +-----------+ | + | | | | | + +------------------------------------------------------------------------+-----------------------+ + +- Here DMSC acts as master and provides all the critical services. R5/A72 + requests DMSC to get these services done as shown in the above diagram. + +Sources: +-------- +1. SYSFW: + Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git + Branch: master + +2. ATF: + Tree: https://github.com/ARM-software/arm-trusted-firmware.git + Branch: master + +3. OPTEE: + Tree: https://github.com/OP-TEE/optee_os.git + Branch: master + +4. U-Boot: + Tree: https://source.denx.de/u-boot/u-boot + Branch: master + +Build procedure: +---------------- +1. SYSFW: + +.. code-block:: text + + $ make CROSS_COMPILE=arm-linux-gnueabihf- + +2. ATF: + +.. code-block:: text + + $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed + +3. OPTEE: + +.. code-block:: text + + $ make PLATFORM=k3-j721e CFG_ARM64_core=y + +4. U-Boot: + +* 4.1 R5: + +.. code-block:: text + + $ make CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=/tmp/r5 + $ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5 + +* 4.2 A72: + +.. code-block:: text + + $ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72 + $ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<path to DM firmware image> O=/tmp/a72 + +Target Images +-------------- +Copy the below images to an SD card and boot: + - sysfw.itb from step 1 + - tiboot3.bin from step 4.1 + - tispl.bin, u-boot.img from 4.2 + +Image formats: +-------------- + +- tiboot3.bin: + +.. code-block:: text + + +-----------------------+ + | X.509 | + | Certificate | + | +-------------------+ | + | | | | + | | R5 | | + | | u-boot-spl.bin | | + | | | | + | +-------------------+ | + | | | | + | | FIT header | | + | | +---------------+ | | + | | | | | | + | | | DTB 1...N | | | + | | +---------------+ | | + | +-------------------+ | + +-----------------------+ + +- tispl.bin + +.. code-block:: text + + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | A72 ATF | | + | +-------------------+ | + | | | | + | | A72 OPTEE | | + | +-------------------+ | + | | | | + | | R5 DM FW | | + | +-------------------+ | + | | | | + | | A72 SPL | | + | +-------------------+ | + | | | | + | | SPL DTB 1...N | | + | +-------------------+ | + +-----------------------+ + +- sysfw.itb + +.. code-block:: text + + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | sysfw.bin | | + | +-------------------+ | + | | | | + | | board config | | + | +-------------------+ | + | | | | + | | PM config | | + | +-------------------+ | + | | | | + | | RM config | | + | +-------------------+ | + | | | | + | | Secure config | | + | +-------------------+ | + +-----------------------+ + +OSPI: +----- +ROM supports booting from OSPI from offset 0x0. + +Flashing images to OSPI: + +Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img, +and sysfw.itb over tftp and then flash those to OSPI at their respective +addresses. + +.. code-block:: text + + => sf probe + => tftp ${loadaddr} tiboot3.bin + => sf update $loadaddr 0x0 $filesize + => tftp ${loadaddr} tispl.bin + => sf update $loadaddr 0x80000 $filesize + => tftp ${loadaddr} u-boot.img + => sf update $loadaddr 0x280000 $filesize + => tftp ${loadaddr} sysfw.itb + => sf update $loadaddr 0x6C0000 $filesize + +Flash layout for OSPI: + +.. code-block:: text + + 0x0 +----------------------------+ + | ospi.tiboot3(512K) | + | | + 0x80000 +----------------------------+ + | ospi.tispl(2M) | + | | + 0x280000 +----------------------------+ + | ospi.u-boot(4M) | + | | + 0x680000 +----------------------------+ + | ospi.env(128K) | + | | + 0x6A0000 +----------------------------+ + | ospi.env.backup (128K) | + | | + 0x6C0000 +----------------------------+ + | ospi.sysfw(1M) | + | | + 0x7C0000 +----------------------------+ + | padding (256k) | + 0x800000 +----------------------------+ + | ospi.rootfs(UBIFS) | + | | + +----------------------------+