[PATCH V2 1/2] net: fec_mxc: Fix clk_ref rate on iMX93
From: Peng Fan peng.fan@nxp.com
i.MX93 FEC ENET port supports two mode: RGMII and RMII. For RGMII, there is an internal /2 divider, so the freq needs to set with (*2), otherwise the speed will not reach 1G and cause communication error in some network environments. For RMII, the clk path is ccm -> enet tx_clk pin -> pad loop back to enet, no /2 divider.
So fix for RGMII mode with freq multiplied by 2.
Fixes: 09de565f76b ("net: fec_mxc: support i.MX93") Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com ---
V2: only update freq to RGMII mode
drivers/net/fec_mxc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 0a0d92bc2cd..d0590fd137b 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1210,10 +1210,13 @@ static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface) else if (interface == PHY_INTERFACE_MODE_RGMII || interface == PHY_INTERFACE_MODE_RGMII_ID || interface == PHY_INTERFACE_MODE_RGMII_RXID || - interface == PHY_INTERFACE_MODE_RGMII_TXID) + interface == PHY_INTERFACE_MODE_RGMII_TXID) { freq = 125000000; - else + if (is_imx93()) + freq = freq << 1; + } else { return -EINVAL; + }
ret = clk_set_rate(clk_ref, freq); if (ret < 0)
From: Ye Li ye.li@nxp.com
After FEC is halted by calling fec_halt callback, we should not continue receiving packet. Otherwise it will process previous pending interrupts on EIR register and uses wrong rbd index as this has been reset to 0.
The GRA interrupt which is triggered by issuing graceful stop command to FEC transmitter in fec_halt is processed in this case. It causes wrong receive buffer descriptors be used by FEC in next time.
Signed-off-by: Ye Li ye.li@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com ---
V2: None
drivers/net/fec_mxc.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index d0590fd137b..50edeb4b5b6 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -818,6 +818,9 @@ static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) return -ENOMEM; }
+ if (!(readl(&fec->eth->ecntrl) & FEC_ECNTRL_ETHER_EN)) + return 0; + /* Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); writel(ievent, &fec->eth->ievent);
On Tue, Sep 24, 2024 at 3:28 AM Peng Fan (OSS) peng.fan@oss.nxp.com wrote:
From: Peng Fan peng.fan@nxp.com
i.MX93 FEC ENET port supports two mode: RGMII and RMII. For RGMII, there is an internal /2 divider, so the freq needs to set with (*2), otherwise the speed will not reach 1G and cause communication error in some network environments. For RMII, the clk path is ccm -> enet tx_clk pin -> pad loop back to enet, no /2 divider.
So fix for RGMII mode with freq multiplied by 2.
Fixes: 09de565f76b ("net: fec_mxc: support i.MX93") Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com
V2: only update freq to RGMII mode
Applied both to u-boot-imx/next, thanks.
participants (2)
-
Fabio Estevam -
Peng Fan (OSS)