Fix some style violations in the fsl_i2c I2C driver.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

drivers/i2c/fsl_i2c.c | 109 +++++++++++++++++++++++++------------------------- 1 file changed, 55 insertions(+), 54 deletions(-)

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index ff3dc25927..3d6808d04e 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -116,10 +116,10 @@ static const struct { * * The return value is the actual bus speed that is set. */ -static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, - unsigned int i2c_clk, unsigned int speed) +static uint set_i2c_bus_speed(const struct fsl_i2c_base *base, + uint i2c_clk, uint speed) { - unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX); + ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);

/* * We want to choose an FDR/DFSR that generates an I2C bus speed that @@ -130,8 +130,8 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, #ifdef __PPC__ u8 dfsr, fdr = 0x31; /* Default if no FDR found */ /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */ - unsigned short a, b, ga, gb; - unsigned long c_div, est_div; + ushort a, b, ga, gb; + ulong c_div, est_div;

#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; @@ -151,18 +151,21 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) { for (gb = 0; gb < 8; gb++) { b = 16 << gb; - c_div = b * (a + ((3*dfsr)/b)*2); + c_div = b * (a + ((3 * dfsr) / b) * 2); if ((c_div > divider) && (c_div < est_div)) { - unsigned short bin_gb, bin_ga; + ushort bin_gb, bin_ga;

est_div = c_div; bin_gb = gb << 2; bin_ga = (ga & 0x3) | ((ga & 0x4) << 3); fdr = bin_gb | bin_ga; speed = i2c_clk / est_div; - debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, " - "a:%d, b:%d, speed:%d\n", - fdr, est_div, ga, gb, a, b, speed); + + debug("FDR: 0x%.2x, ", fdr); + debug("div: %ld, ", est_div); + debug("ga: 0x%x, gb: 0x%x, ", ga, gb); + debug("a: %d, b: %d, speed: %d\n", a, b, speed); + /* Condition 2 not accounted for */ debug("Tr <= %d ns\n", (b - 3 * dfsr) * 1000000 / @@ -174,13 +177,13 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, if (a == 24) a += 4; } - debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr); - debug("FDR:0x%.2x, speed:%d\n", fdr, speed); + debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr); + debug("FDR: 0x%.2x, speed: %d\n", fdr, speed); #endif writeb(dfsr, &base->dfsrr); /* set default filter */ writeb(fdr, &base->fdr); /* set bus speed */ #else - unsigned int i; + uint i;

for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) if (fsl_i2c_speed_map[i].divider >= divider) { @@ -197,7 +200,7 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, }

#ifndef CONFIG_DM_I2C -static unsigned int get_i2c_clock(int bus) +static uint get_i2c_clock(int bus) { if (bus) return gd->arch.i2c2_clk; /* I2C2 clock */ @@ -211,10 +214,11 @@ static int fsl_i2c_fixup(const struct fsl_i2c_base *base) const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); unsigned long long timeval = 0; int ret = -1; - unsigned int flags = 0; + uint flags = 0;

#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 - unsigned int svr = get_svr(); + uint svr = get_svr(); + if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) flags = I2C_CR_BIT6; @@ -263,7 +267,7 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int /* Call board specific i2c bus reset routine before accessing the * environment, which might be in a chip on that bus. For details * about this problem see doc/I2C_Edge_Conditions. - */ + */ i2c_init_board(); #endif writeb(0, &base->cr); /* stop I2C controller */ @@ -286,8 +290,7 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int } }

-static int -i2c_wait4bus(const struct fsl_i2c_base *base) +static int i2c_wait4bus(const struct fsl_i2c_base *base) { unsigned long long timeval = get_ticks(); const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); @@ -300,8 +303,7 @@ i2c_wait4bus(const struct fsl_i2c_base *base) return 0; }

-static inline int -i2c_wait(const struct fsl_i2c_base *base, int write) +static inline int i2c_wait(const struct fsl_i2c_base *base, int write) { u32 csr; unsigned long long timeval = get_ticks(); @@ -317,29 +319,29 @@ i2c_wait(const struct fsl_i2c_base *base, int write) writeb(0x0, &base->sr);

if (csr & I2C_SR_MAL) { - debug("i2c_wait: MAL\n"); + debug("%s: MAL\n", __func__); return -1; }

if (!(csr & I2C_SR_MCF)) { - debug("i2c_wait: unfinished\n"); + debug("%s: unfinished\n", __func__); return -1; }

if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { - debug("i2c_wait: No RXACK\n"); + debug("%s: No RXACK\n", __func__); return -1; }

return 0; } while ((get_ticks() - timeval) < timeout);

- debug("i2c_wait: timed out\n"); + debug("%s: timed out\n", __func__); return -1; }

-static inline int -i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta) +static inline int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, + u8 dir, int rsta) { writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | (rsta ? I2C_CR_RSTA : 0), @@ -353,8 +355,8 @@ i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta) return 1; }

-static inline int -__i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length) +static inline int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, + int length) { int i;

@@ -368,8 +370,8 @@ __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length) return i; }

-static inline int -__i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length) +static inline int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, + int length) { int i;

@@ -399,9 +401,8 @@ __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length) return i; }

-static int -__i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, - u8 *data, int dlen) +static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, + int olen, u8 *data, int dlen) { int ret = -1; /* signal error */

@@ -447,9 +448,8 @@ __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, return -1; }

-static int -__i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, - u8 *data, int dlen) +static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, + u8 *offset, int olen, u8 *data, int dlen) { int ret = -1; /* signal error */

@@ -471,10 +471,9 @@ __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, return -1; }

-static int -__i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) +static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) { - /* For unknow reason the controller will ACK when + /* For unknown reason the controller will ACK when * probing for a slave with the same address, so skip * it. */ @@ -484,8 +483,8 @@ __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) return __i2c_read(base, chip, 0, 0, NULL, 0); }

-static unsigned int __i2c_set_bus_speed(const struct fsl_i2c_base *base, - unsigned int speed, int i2c_clk) +static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base, + uint speed, int i2c_clk) { writeb(0, &base->cr); /* stop controller */ set_i2c_bus_speed(base, i2c_clk, speed); @@ -501,32 +500,30 @@ static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) get_i2c_clock(adap->hwadapnr), adap->hwadapnr); }

-static int -fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip) +static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip) { return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip); }

-static int -fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen, - u8 *data, int dlen) +static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, + int olen, u8 *data, int dlen) { u8 *o = (u8 *)&offset; + return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], olen, data, dlen); }

-static int -fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen, - u8 *data, int dlen) +static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, + int olen, u8 *data, int dlen) { u8 *o = (u8 *)&offset; + return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], olen, data, dlen); }

-static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) +static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) { return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed, get_i2c_clock(adap->hwadapnr)); @@ -562,12 +559,14 @@ static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr, u32 chip_flags) { struct fsl_i2c_dev *dev = dev_get_priv(bus); + return __i2c_probe_chip(dev->base, chip_addr); }

-static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed) { struct fsl_i2c_dev *dev = dev_get_priv(bus); + return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk); }

@@ -600,6 +599,7 @@ static int fsl_i2c_ofdata_to_platdata(struct udevice *bus) static int fsl_i2c_probe(struct udevice *bus) { struct fsl_i2c_dev *dev = dev_get_priv(bus); + __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk, dev->index); return 0; @@ -613,7 +613,8 @@ static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) memset(&dummy, 0, sizeof(struct i2c_msg));

/* We expect either two messages (one with an offset and one with the - * actucal data) or one message (just data) */ + * actual data) or one message (just data) + */ if (nmsgs > 2 || nmsgs == 0) { debug("%s: Only one or two messages are supported.", __func__); return -1;

Some functions in the fsl_i2c driver are declared as inline, even though they are quite large, which needlessly increases the size of the resulting binary.

This patch removes the inline declarations.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

drivers/i2c/fsl_i2c.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 3d6808d04e..6d8ebe7478 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -303,7 +303,7 @@ static int i2c_wait4bus(const struct fsl_i2c_base *base) return 0; }

-static inline int i2c_wait(const struct fsl_i2c_base *base, int write) +static int i2c_wait(const struct fsl_i2c_base *base, int write) { u32 csr; unsigned long long timeval = get_ticks(); @@ -340,8 +340,8 @@ static inline int i2c_wait(const struct fsl_i2c_base *base, int write) return -1; }

-static inline int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, - u8 dir, int rsta) +static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, + u8 dir, int rsta) { writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | (rsta ? I2C_CR_RSTA : 0), @@ -355,8 +355,8 @@ static inline int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, return 1; }

-static inline int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, - int length) +static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, + int length) { int i;

@@ -370,8 +370,8 @@ static inline int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, return i; }

-static inline int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, - int length) +static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, + int length) { int i;

The ppc4xx architecture was recently removed, and with it several old gdsys 44x boards, but some "debris" from these purged boards was left over.

This patch removes these remnants (mostly entries in Makefiles, some now superfluous data structures and some now obsolete config variables from the whitelist).

Signed-off-by: Mario Six mario.six@gdsys.cc ---

board/gdsys/common/Makefile | 4 -- board/gdsys/common/miiphybb.c | 128 ------------------------------------------ include/gdsys_fpga.h | 96 ------------------------------- scripts/config_whitelist.txt | 10 ---- 4 files changed, 238 deletions(-) delete mode 100644 board/gdsys/common/miiphybb.c

diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index d4f0e70573..6f2fea207f 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -7,10 +7,6 @@

obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o -obj-$(CONFIG_IO) += miiphybb.o -obj-$(CONFIG_IO64) += miiphybb.o -obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o -obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c deleted file mode 100644 index 310562902b..0000000000 --- a/board/gdsys/common/miiphybb.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <miiphy.h> - -#include <asm/io.h> - -struct io_bb_pinset { - int mdio; - int mdc; -}; - -static int io_bb_mii_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int io_bb_mdio_active(struct bb_miiphy_bus *bus) -{ - struct io_bb_pinset *pins = bus->priv; - - out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) | pins->mdio); - - return 0; -} - -static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct io_bb_pinset *pins = bus->priv; - - out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) & ~pins->mdio); - - return 0; -} - -static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct io_bb_pinset *pins = bus->priv; - - if (v) - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | pins->mdio); - else - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~pins->mdio); - - return 0; -} - -static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - struct io_bb_pinset *pins = bus->priv; - - *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0); - - return 0; -} - -static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct io_bb_pinset *pins = bus->priv; - - if (v) - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | pins->mdc); - else - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~pins->mdc); - - return 0; -} - -static int io_bb_delay(struct bb_miiphy_bus *bus) -{ - udelay(1); - - return 0; -} - -struct io_bb_pinset io_bb_pinsets[] = { - { - .mdio = CONFIG_SYS_MDIO_PIN, - .mdc = CONFIG_SYS_MDC_PIN, - }, -#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME - { - .mdio = CONFIG_SYS_MDIO1_PIN, - .mdc = CONFIG_SYS_MDC1_PIN, - }, -#endif -}; - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = CONFIG_SYS_GBIT_MII_BUSNAME, - .init = io_bb_mii_init, - .mdio_active = io_bb_mdio_active, - .mdio_tristate = io_bb_mdio_tristate, - .set_mdio = io_bb_set_mdio, - .get_mdio = io_bb_get_mdio, - .set_mdc = io_bb_set_mdc, - .delay = io_bb_delay, - .priv = &io_bb_pinsets[0], - }, -#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME - { - .name = CONFIG_SYS_GBIT_MII1_BUSNAME, - .init = io_bb_mii_init, - .mdio_active = io_bb_mdio_active, - .mdio_tristate = io_bb_mdio_tristate, - .set_mdio = io_bb_set_mdio, - .get_mdio = io_bb_get_mdio, - .set_mdc = io_bb_set_mdc, - .delay = io_bb_delay, - .priv = &io_bb_pinsets[1], - }, -#endif -}; - -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index bb8e144e04..34d6eeb253 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -87,81 +87,6 @@ struct ihs_fpga { }; #endif

-#ifdef CONFIG_IO -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_features; /* 0x0004 */ - u16 fpga_version; /* 0x0006 */ - u16 reserved_0[5]; /* 0x0008 */ - u16 quad_serdes_reset; /* 0x0012 */ - u16 reserved_1[8181]; /* 0x0014 */ - u16 reflection_high; /* 0x3ffe */ -}; -#endif - -#ifdef CONFIG_IO64 -struct ihs_fpga_channel { - u16 status_int; - u16 config_int; - u16 switch_connect_config; - u16 tx_destination; -}; - -struct ihs_fpga_hicb { - u16 status_int; - u16 config_int; -}; - -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_features; /* 0x0004 */ - u16 fpga_version; /* 0x0006 */ - u16 reserved_0[5]; /* 0x0008 */ - u16 quad_serdes_reset; /* 0x0012 */ - u16 reserved_1[502]; /* 0x0014 */ - struct ihs_fpga_channel ch[32]; /* 0x0400 */ - struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */ - u16 reserved_2[7487]; /* 0x0580 */ - u16 reflection_high; /* 0x3ffe */ -}; -#endif - -#ifdef CONFIG_IOCON -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_version; /* 0x0004 */ - u16 fpga_features; /* 0x0006 */ - u16 reserved_0[1]; /* 0x0008 */ - u16 top_interrupt; /* 0x000a */ - u16 reserved_1[4]; /* 0x000c */ - struct ihs_gpio gpio; /* 0x0014 */ - u16 mpc3w_control; /* 0x001a */ - u16 reserved_2[2]; /* 0x001c */ - struct ihs_io_ep ep; /* 0x0020 */ - u16 reserved_3[9]; /* 0x002e */ - struct ihs_i2c i2c0; /* 0x0040 */ - u16 reserved_4[10]; /* 0x004c */ - u16 mc_int; /* 0x0060 */ - u16 mc_int_en; /* 0x0062 */ - u16 mc_status; /* 0x0064 */ - u16 mc_control; /* 0x0066 */ - u16 mc_tx_data; /* 0x0068 */ - u16 mc_tx_address; /* 0x006a */ - u16 mc_tx_cmd; /* 0x006c */ - u16 mc_res; /* 0x006e */ - u16 mc_rx_cmd_status; /* 0x0070 */ - u16 mc_rx_data; /* 0x0072 */ - u16 reserved_5[69]; /* 0x0074 */ - u16 reflection_high; /* 0x00fe */ - struct ihs_osd osd0; /* 0x0100 */ - u16 reserved_6[889]; /* 0x010e */ - u16 videomem0[2048]; /* 0x0800 */ -}; -#endif - #if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP) struct ihs_fpga { u16 reflection_low; /* 0x0000 */ @@ -271,25 +196,4 @@ struct ihs_fpga { }; #endif

-#ifdef CONFIG_DLVISION_10G -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_version; /* 0x0004 */ - u16 fpga_features; /* 0x0006 */ - u16 reserved_0[10]; /* 0x0008 */ - u16 extended_interrupt; /* 0x001c */ - u16 reserved_1[29]; /* 0x001e */ - u16 mpc3w_control; /* 0x0058 */ - u16 reserved_2[3]; /* 0x005a */ - struct ihs_i2c i2c0; /* 0x0060 */ - u16 reserved_3[2]; /* 0x006c */ - struct ihs_i2c i2c1; /* 0x0070 */ - u16 reserved_4[194]; /* 0x007c */ - struct ihs_osd osd0; /* 0x0200 */ - u16 reserved_5[761]; /* 0x020e */ - u16 videomem0[2048]; /* 0x0800 */ -}; -#endif - #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e261d02455..4c136a6502 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -499,7 +499,6 @@ CONFIG_DISCONTIGMEM CONFIG_DISCOVER_PHY CONFIG_DISPLAY_AER_xxxx CONFIG_DISPLAY_BOARDINFO_LATE -CONFIG_DLVISION_10G CONFIG_DM9000_BASE CONFIG_DM9000_BYTE_SWAPPED CONFIG_DM9000_DEBUG @@ -1167,9 +1166,6 @@ CONFIG_INI_MAX_SECTION CONFIG_INTEGRITY CONFIG_INTEL_ICH6_GPIO CONFIG_INTERRUPTS -CONFIG_IO -CONFIG_IO64 -CONFIG_IOCON CONFIG_IODELAY_RECALIBRATION CONFIG_IOMUX_LPSR CONFIG_IOMUX_SHARE_CONF_REG @@ -3410,8 +3406,6 @@ CONFIG_SYS_GAFR2_L_VAL CONFIG_SYS_GAFR2_U_VAL CONFIG_SYS_GAFR3_L_VAL CONFIG_SYS_GAFR3_U_VAL -CONFIG_SYS_GBIT_MII1_BUSNAME -CONFIG_SYS_GBIT_MII_BUSNAME CONFIG_SYS_GBL_DATA_OFFSET CONFIG_SYS_GBL_DATA_SIZE CONFIG_SYS_GENERIC_BOARD @@ -3857,13 +3851,9 @@ CONFIG_SYS_MCKR_VAL CONFIG_SYS_MCLINK_MAX CONFIG_SYS_MCMEM0_VAL CONFIG_SYS_MCMEM1_VAL -CONFIG_SYS_MDC1_PIN CONFIG_SYS_MDCNFG_VAL -CONFIG_SYS_MDC_PIN CONFIG_SYS_MDIO1_OFFSET -CONFIG_SYS_MDIO1_PIN CONFIG_SYS_MDIO_BASE_ADDR -CONFIG_SYS_MDIO_PIN CONFIG_SYS_MDMRS_VAL CONFIG_SYS_MDREFR_VAL CONFIG_SYS_MECR_VAL

Fix some style violations in the Marvell PHY driver.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

drivers/net/phy/marvell.c | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index b7f300e40f..5d9f50a436 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -134,7 +134,7 @@ static int m88e1xxx_parse_status(struct phy_device *phydev) mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);

if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) && - !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { + !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { int i = 0;

puts("Waiting for PHY realtime link"); @@ -150,10 +150,10 @@ static int m88e1xxx_parse_status(struct phy_device *phydev) putc('.'); udelay(1000); mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, - MIIM_88E1xxx_PHY_STATUS); + MIIM_88E1xxx_PHY_STATUS); } puts(" done\n"); - udelay(500000); /* another 500 ms (results in faster booting) */ + mdelay(500); /* another 500 ms (results in faster booting) */ } else { if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) phydev->link = 1; @@ -201,9 +201,9 @@ static int m88e1111s_config(struct phy_device *phydev)

if (phy_interface_is_rgmii(phydev)) { reg = phy_read(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { + (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { reg &= ~MIIM_88E1111_TX_DELAY; @@ -214,10 +214,10 @@ static int m88e1111s_config(struct phy_device *phydev) }

phy_write(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);

reg = phy_read(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);

reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);

@@ -227,47 +227,47 @@ static int m88e1111s_config(struct phy_device *phydev) reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;

phy_write(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); }

if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { reg = phy_read(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);

reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;

phy_write(phydev, MDIO_DEVAD_NONE, - MIIM_88E1111_PHY_EXT_SR, reg); + MIIM_88E1111_PHY_EXT_SR, reg); }

if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { reg = phy_read(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); phy_write(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);

reg = phy_read(phydev, MDIO_DEVAD_NONE, - MIIM_88E1111_PHY_EXT_SR); + MIIM_88E1111_PHY_EXT_SR); reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | MIIM_88E1111_HWCFG_FIBER_COPPER_RES); reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; phy_write(phydev, MDIO_DEVAD_NONE, - MIIM_88E1111_PHY_EXT_SR, reg); + MIIM_88E1111_PHY_EXT_SR, reg);

/* soft reset */ phy_reset(phydev);

reg = phy_read(phydev, MDIO_DEVAD_NONE, - MIIM_88E1111_PHY_EXT_SR); + MIIM_88E1111_PHY_EXT_SR); reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | - MIIM_88E1111_HWCFG_FIBER_COPPER_RES); + MIIM_88E1111_HWCFG_FIBER_COPPER_RES); reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; phy_write(phydev, MDIO_DEVAD_NONE, - MIIM_88E1111_PHY_EXT_SR, reg); + MIIM_88E1111_PHY_EXT_SR, reg); }

/* soft reset */ @@ -283,7 +283,7 @@ static int m88e1111s_config(struct phy_device *phydev) * m88e1518_phy_writebits - write bits to a register */ void m88e1518_phy_writebits(struct phy_device *phydev, - u8 reg_num, u16 offset, u16 len, u16 data) + u8 reg_num, u16 offset, u16 len, u16 data) { u16 reg, mask;

@@ -446,10 +446,10 @@ static int m88e1121_config(struct phy_device *phydev) /* Switch the page to access the led register */ pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, - MIIM_88E1121_PHY_LED_PAGE); + MIIM_88E1121_PHY_LED_PAGE); /* Configure leds */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, - MIIM_88E1121_PHY_LED_DEF); + MIIM_88E1121_PHY_LED_DEF); /* Restore the page pointer */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);

@@ -472,7 +472,7 @@ static int m88e1145_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);

phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, - MIIM_88E1xxx_PHY_MDI_X_AUTO); + MIIM_88E1xxx_PHY_MDI_X_AUTO);

reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) @@ -499,7 +499,7 @@ static int m88e1145_startup(struct phy_device *phydev) return ret;

phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, - MIIM_88E1145_PHY_LED_DIRECT); + MIIM_88E1145_PHY_LED_DIRECT); return m88e1xxx_parse_status(phydev); }

This patch adds a command that enables the calculation of bit operations (AND, OR, XOR) on binary data from the command line. Memory locations as well as the contents of environment variables are eligible as sources and destination of the binary data used in the operations.

The possible applications are manifold: Setting specific bits in registers using the regular read-OR-write pattern, masking out bits in bit values, implementation of simple OTP encryption using the XOR operation, etc.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

cmd/Kconfig | 6 ++ cmd/Makefile | 1 + cmd/binop.c | 176 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 183 insertions(+) create mode 100644 cmd/binop.c

diff --git a/cmd/Kconfig b/cmd/Kconfig index c80ac364ea..322e466313 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -350,6 +350,12 @@ config CMD_MEMORY base - print or set address offset loop - initialize loop on address range

+config CMD_BINOP + bool "binop" + help + Compute binary operations (xor, or, and) of data from memory and + store the result in memory or the environment. + config CMD_CRC32 bool "crc32" select HASH diff --git a/cmd/Makefile b/cmd/Makefile index bd231f24d8..243f9f45d4 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_SOURCE) += source.o obj-$(CONFIG_CMD_SOURCE) += source.o obj-$(CONFIG_CMD_BDI) += bdinfo.o obj-$(CONFIG_CMD_BEDBUG) += bedbug.o +obj-$(CONFIG_CMD_BINOP) += binop.o obj-$(CONFIG_CMD_BLOCK_CACHE) += blkcache.o obj-$(CONFIG_CMD_BMP) += bmp.o obj-$(CONFIG_CMD_BOOTEFI) += bootefi.o diff --git a/cmd/binop.c b/cmd/binop.c new file mode 100644 index 0000000000..0002c66609 --- /dev/null +++ b/cmd/binop.c @@ -0,0 +1,176 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <mapmem.h> +#include <linux/ctype.h> + +enum { + OP_ID_XOR, + OP_ID_AND, + OP_ID_OR, +}; + +void write_to_env_var(char *varname, u8 *result, ulong len) +{ + char *str_output; + char *str_ptr; + int i; + + str_output = malloc(len * 2 + 1); + str_ptr = str_output; + + for (i = 0; i < len; i++) { + sprintf(str_ptr, "%02x", result[i]); + str_ptr += 2; + } + *str_ptr = '\0'; + setenv(varname, str_output); + + free(str_output); +} + +void decode_hexstring(char *hexstr, u8 *result) +{ + int i; + int acc = 0; + + for (i = 0; i < strlen(hexstr); ++i) { + char d = hexstr[i]; + int value; + + if (isdigit(d)) + value = (d - '0'); + else + value = (islower(d) ? toupper(d) : d) - 'A' + 10; + + if (i % 2 == 0) { + acc = value * 16; + } else { + result[i / 2] = acc + value; + acc = 0; + } + } +} + +void read_from_env_var(char *varname, u8 *result) +{ + char *str_value; + + str_value = getenv(varname); + if (str_value) + decode_hexstring(str_value, result); + else + decode_hexstring(varname, result); +} + +void read_from_mem(ulong addr, u8 *result, ulong len) +{ + u8 *src; + + src = map_sysmem(addr, len); + memcpy(result, src, len); + unmap_sysmem(src); +} + +void write_to_mem(char *varname, u8 *result, ulong len) +{ + ulong addr; + u8 *buf; + + addr = simple_strtoul(varname, NULL, 16); + buf = map_sysmem(addr, len); + memcpy(buf, result, len); + unmap_sysmem(buf); +} + +static int do_binop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong len; + u8 *result, *src1, *src2; + char *oparg, *lenarg, *src1arg, *src2arg, *destarg; + int i, op; + + if (argc < 5) + return CMD_RET_USAGE; + + oparg = argv[1]; + lenarg = argv[2]; + src1arg = argv[3]; + src2arg = argv[4]; + + if (!strcmp(oparg, "xor")) + op = OP_ID_XOR; + else if (!strcmp(oparg, "or")) + op = OP_ID_OR; + else if (!strcmp(oparg, "and")) + op = OP_ID_AND; + else + return CMD_RET_USAGE; + + len = simple_strtoul(lenarg, NULL, 10); + + src1 = malloc(len); + src2 = malloc(len); + + if (*src1arg == '*') + read_from_mem(simple_strtoul(src1arg + 1, NULL, 16), src1, len); + else + read_from_env_var(src1arg, src1); + + if (*src2arg == '*') + read_from_mem(simple_strtoul(src2arg + 1, NULL, 16), src2, len); + else + read_from_env_var(src2arg, src2); + + result = malloc(len); + + switch (op) { + case OP_ID_XOR: + for (i = 0; i < len; i++) + result[i] = src1[i] ^ src2[i]; + break; + case OP_ID_OR: + for (i = 0; i < len; i++) + result[i] = src1[i] | src2[i]; + break; + case OP_ID_AND: + for (i = 0; i < len; i++) + result[i] = src1[i] & src2[i]; + break; + } + + if (argc == 5) { + for (i = 0; i < len; i++) { + printf("%02x ", result[i]); + if (i % 16 == 15) + puts("\n"); + } + puts("\n"); + + goto exit; + } + + destarg = argv[5]; + + if (*destarg == '*') + write_to_mem(destarg + 1, result, len); /* Skip asterisk */ + else + write_to_env_var(destarg, result, len); +exit: + free(result); + free(src2); + free(src1); + + return 0; +} + +U_BOOT_CMD( + binop, 6, 1, do_binop, + "compute binary operation", + "op count [*]src1 [*]src2 [[*]dest]\n" + " - compute binary operation of data at/in src1 and\n src2 (either *memaddr, env var name or hex string)\n and store result in/at dest, where op is one of\n xor, or, and." +);

Fix some style violations in the generic PHY management code.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

drivers/net/phy/phy.c | 83 +++++++++++++++++++++++++++++++-------------------- 1 file changed, 50 insertions(+), 33 deletions(-)

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 08ec2f2ad6..a16bb6ca89 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Generic PHY support and helper functions */

/** - * genphy_config_advert - sanitize and advertise auto-negotation parameters + * genphy_config_advert - sanitize and advertise auto-negotiation parameters * @phydev: target phy_device struct * * Description: Writes MII_ADVERTISE with the appropriate values, @@ -117,7 +117,6 @@ static int genphy_config_advert(struct phy_device *phydev) return changed; }

- /** * genphy_setup_forced - configures/forces speed/duplex from @phydev * @phydev: target phy_device struct @@ -130,14 +129,15 @@ static int genphy_setup_forced(struct phy_device *phydev) int err; int ctl = BMCR_ANRESTART;

- phydev->pause = phydev->asym_pause = 0; + phydev->pause = 0; + phydev->asym_pause = 0;

- if (SPEED_1000 == phydev->speed) + if (phydev->speed == SPEED_1000) ctl |= BMCR_SPEED1000; - else if (SPEED_100 == phydev->speed) + else if (phydev->speed == SPEED_100) ctl |= BMCR_SPEED100;

- if (DUPLEX_FULL == phydev->duplex) + if (phydev->duplex == DUPLEX_FULL) ctl |= BMCR_FULLDPLX;

err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); @@ -145,7 +145,6 @@ static int genphy_setup_forced(struct phy_device *phydev) return err; }

- /** * genphy_restart_aneg - Enable and Restart Autonegotiation * @phydev: target phy_device struct @@ -169,7 +168,6 @@ int genphy_restart_aneg(struct phy_device *phydev) return ctl; }

- /** * genphy_config_aneg - restart auto-negotiation or write BMCR * @phydev: target phy_device struct @@ -182,7 +180,7 @@ int genphy_config_aneg(struct phy_device *phydev) { int result;

- if (AUTONEG_ENABLE != phydev->autoneg) + if (phydev->autoneg != AUTONEG_ENABLE) return genphy_setup_forced(phydev);

result = genphy_config_advert(phydev); @@ -192,7 +190,8 @@ int genphy_config_aneg(struct phy_device *phydev)

if (result == 0) { /* Advertisment hasn't changed, but maybe aneg was never on to - * begin with? Or maybe phy was isolated? */ + * begin with? Or maybe phy was isolated? + */ int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);

if (ctl < 0) @@ -203,7 +202,8 @@ int genphy_config_aneg(struct phy_device *phydev) }

/* Only restart aneg if we are advertising something different - * than we were before. */ + * than we were before. + */ if (result > 0) result = genphy_restart_aneg(phydev);

@@ -240,7 +240,7 @@ int genphy_update_link(struct phy_device *phydev) int i = 0;

printf("%s Waiting for PHY auto negotiation to complete", - phydev->dev->name); + phydev->dev->name); while (!(mii_reg & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? @@ -305,7 +305,8 @@ int genphy_parse_link(struct phy_device *phydev) */ gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000); if (gblpa < 0) { - debug("Could not read MII_STAT1000. Ignoring gigabit capability\n"); + debug("Could not read MII_STAT1000. "); + debug("Ignoring gigabit capability\n"); gblpa = 0; } gblpa &= phy_read(phydev, @@ -338,8 +339,9 @@ int genphy_parse_link(struct phy_device *phydev) if (lpa & LPA_100FULL) phydev->duplex = DUPLEX_FULL;

- } else if (lpa & LPA_10FULL) + } else if (lpa & LPA_10FULL) { phydev->duplex = DUPLEX_FULL; + }

/* * Extended status may indicate that the PHY supports @@ -571,7 +573,9 @@ static int phy_probe(struct phy_device *phydev) { int err = 0;

- phydev->advertising = phydev->supported = phydev->drv->features; + phydev->advertising = phydev->drv->features; + phydev->supported = phydev->drv->features; + phydev->mmds = phydev->drv->mmds;

if (phydev->drv->probe) @@ -591,7 +595,7 @@ static struct phy_driver *generic_for_interface(phy_interface_t interface) }

static struct phy_driver *get_phy_driver(struct phy_device *phydev, - phy_interface_t interface) + phy_interface_t interface) { struct list_head *entry; int phy_id = phydev->phy_id; @@ -614,11 +618,12 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, struct phy_device *dev;

/* We allocate the device, and initialize the - * default values */ + * default values + */ dev = malloc(sizeof(*dev)); if (!dev) { printf("Failed to allocate PHY device for %s:%d\n", - bus->name, addr); + bus->name, addr); return NULL; }

@@ -657,7 +662,8 @@ int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) int phy_reg;

/* Grab the bits from PHYIR1, and put them - * in the upper half */ + * in the upper half + */ phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);

if (phy_reg < 0) @@ -677,9 +683,11 @@ int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) }

static struct phy_device *create_phy_by_mask(struct mii_dev *bus, - unsigned phy_mask, int devad, phy_interface_t interface) + uint phy_mask, int devad, + phy_interface_t interface) { u32 phy_id = 0xffffffff; + while (phy_mask) { int addr = ffs(phy_mask) - 1; int r = get_phy_id(bus, addr, devad, &phy_id); @@ -692,11 +700,13 @@ static struct phy_device *create_phy_by_mask(struct mii_dev *bus, }

static struct phy_device *search_for_existing_phy(struct mii_dev *bus, - unsigned phy_mask, phy_interface_t interface) + uint phy_mask, + phy_interface_t interface) { /* If we have one, return the existing device, with new interface */ while (phy_mask) { int addr = ffs(phy_mask) - 1; + if (bus->phymap[addr]) { bus->phymap[addr]->interface = interface; return bus->phymap[addr]; @@ -707,7 +717,9 @@ static struct phy_device *search_for_existing_phy(struct mii_dev *bus, }

static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus, - unsigned phy_mask, phy_interface_t interface, bool force_c45) + uint phy_mask, + phy_interface_t interface, + bool force_c45) { int i; struct phy_device *phydev; @@ -721,7 +733,7 @@ static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus, if (!i && force_c45) continue; phydev = create_phy_by_mask(bus, phy_mask, - i ? i : MDIO_DEVAD_NONE, interface); + i ? i : MDIO_DEVAD_NONE, interface); if (IS_ERR(phydev)) return NULL; if (phydev) @@ -731,6 +743,7 @@ static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus, debug("\n%s PHY: ", bus->name); while (phy_mask) { int addr = ffs(phy_mask) - 1; + debug("%d ", addr); phy_mask &= ~(1 << addr); } @@ -740,7 +753,8 @@ static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus, }

/** - * get_phy_device - reads the specified PHY device and returns its @phy_device struct + * get_phy_device - reads the specified PHY device and returns its + * @phy_device struct * @bus: the target MII bus * @addr: PHY address on the MII bus * @@ -819,15 +833,15 @@ int miiphy_reset(const char *devname, unsigned char addr) return phy_reset(phydev); }

-struct phy_device *__phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, - phy_interface_t interface, bool force_c45) +struct phy_device *__phy_find_by_mask(struct mii_dev *bus, uint phy_mask, + phy_interface_t interface, bool force_c45) { /* Reset the bus */ if (bus->reset) { bus->reset(bus);

/* Wait 15ms to make sure the PHY has come out of hard reset */ - udelay(15000); + mdelay(15); }

return get_phy_device_by_mask(bus, phy_mask, interface, force_c45); @@ -843,8 +857,8 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev) phy_reset(phydev); if (phydev->dev && phydev->dev != dev) { printf("%s:%d is connected to %s. Reconnecting to %s\n", - phydev->bus->name, phydev->addr, - phydev->dev->name, dev->name); + phydev->bus->name, phydev->addr, + phydev->dev->name, dev->name); } phydev->dev = dev; debug("%s connected to %s\n", dev->name, phydev->drv->name); @@ -852,20 +866,23 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)

#ifdef CONFIG_DM_ETH struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct udevice *dev, phy_interface_t interface) + struct udevice *dev, + phy_interface_t interface) #else struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct eth_device *dev, phy_interface_t interface) + struct eth_device *dev, + phy_interface_t interface) #endif { struct phy_device *phydev = NULL; #ifdef CONFIG_PHY_FIXED int sn; const char *name; + sn = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev)); while (sn > 0) { name = fdt_get_name(gd->fdt_blob, sn, NULL); - if (name != NULL && strcmp(name, "fixed-link") == 0) { + if (name && strcmp(name, "fixed-link") == 0) { phydev = phy_device_create(bus, sn, PHY_FIXED_ID, interface); break; @@ -873,7 +890,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, sn = fdt_next_subnode(gd->fdt_blob, sn); } #endif - if (phydev == NULL) + if (!phydev) phydev = phy_find_by_mask(bus, 1 << addr, interface);

if (phydev)

From: Dirk Eibach dirk.eibach@gdsys.cc

Implement support for the Marvell Alaska X 88X2242P Integrated Dual-port and Quad-port Multi-speed Ethernet Transceivers.

Signed-off-by: Dirk Eibach dirk.eibach@gdsys.cc Signed-off-by: Mario Six mario.six@gdsys.cc ---

drivers/net/phy/Kconfig | 67 ++++ drivers/net/phy/Makefile | 1 + drivers/net/phy/marvell.c | 1 - drivers/net/phy/mv88x2.c | 846 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/mv88x2.h | 12 + drivers/net/phy/phy.c | 3 + include/phy.h | 1 + 7 files changed, 930 insertions(+), 1 deletion(-) create mode 100644 drivers/net/phy/mv88x2.c create mode 100644 drivers/net/phy/mv88x2.h

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 0230852244..bb21be197f 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -55,6 +55,73 @@ config PHY_LXT config PHY_MARVELL bool "Marvell Ethernet PHYs support"

+ +if PHY_MARVELL + +config BOARD_M88E1510_CONFIG + bool "M88E1510 board-specific callback" + +endif + +config PHY_MV88X2 + depends on PHYLIB_10G + bool "Marvell 88X2 PHYs support" + +if PHY_MV88X2 + +config BOARD_MV88X2_CONFIG + bool "MV88X2 board-specific callback" + +config MV88X2_DEBUG_REGS + bool "Debug register printing" + +config MV88X2_LINE_10GBASE_R + bool "Enable Line 10GBASE-R support" + +config MV88X2_HOST_10GBASE_X2 + bool "Enable Host 10GBASE-X2 support" + +config MV88X2_X2_DISPARITY + bool "Enable 10GBASE-X2 disparity" + +config MV88X2_LED0_BLINK + int "LED0 blink behavior" + range 0 11 + default 0 + +config MV88X2_LED0_SOLID + int "LED0 solid behavior" + range 0 7 + default 0 + +config MV88X2_LED1_BLINK + int "LED1 blink behavior" + range 0 11 + default 0 + +config MV88X2_LED1_SOLID + int "LED1 solid behavior" + range 0 7 + default 0 + +config MV88X2_HOST_LANE_MUX_2_PORT + hex "Host side lane muxing (2 ports)" + default 0x0 + +config MV88X2_HOST_LANE_MUX_4_PORT + hex "Host side lane muxing (4 ports)" + default 0x0 + +config MV88X2_SFI_POL + hex "SFI polarity" + default 0x0 + +config MV88X2_XFI_POL + hex "XFI polarity" + default 0x0 + +endif + config PHY_MICREL bool "Micrel Ethernet PHYs support" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 88c00a5cd3..631797a1f0 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_PHY_ET1011C) += et1011c.o obj-$(CONFIG_PHY_LXT) += lxt.o obj-$(CONFIG_PHY_MARVELL) += marvell.o obj-$(CONFIG_PHY_MICREL) += micrel.o +obj-$(CONFIG_PHY_MV88X2) += mv88x2.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 8eddf70c68..66107a8af3 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -720,6 +720,5 @@ int phy_marvell_init(void) phy_register(&M88E1510_driver); phy_register(&M88E1518_driver); phy_register(&M88E1680_driver); - return 0; } diff --git a/drivers/net/phy/mv88x2.c b/drivers/net/phy/mv88x2.c new file mode 100644 index 0000000000..9d04197e47 --- /dev/null +++ b/drivers/net/phy/mv88x2.c @@ -0,0 +1,846 @@ +/* + * Driver for Marvell 88X2 PHYs + * Support for Revision A devices is not included. + * + * (C) Copyright 2016 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <miiphy.h> +#include <phy.h> +#include <console.h> + +#include "mv88x2.h" + +enum { + MGD_2140M_A1 = 0x1b, /* 88X2140M_A1 */ + + MGD_22x2M = 0x31, /* 88X22x2M */ + MGD_2242_B0 = 0x311, /* 88X2242_B0 */ + MGD_2242M_A0 = 0x312, /* 88X2242M_A0 (MGD_22x2M + rev=2) */ + MGD_2242M_B0 = 0x313, /* 88X2242M_B0 (MGD_22x2M + rev=3) */ + MGD_2222_B0 = 0x315, /* 88X2222_B0 (MGD_22x2M + rev=5) */ + MGD_2222M_B0 = 0x317, /* 88X2222M_B0 (MGD_22x2M + rev=7) */ + + MGD_22x2P = 0x19, /* 88X22x2P */ + MGD_2242P_A0 = 0x191, /* 88X2242P_A0 (MGD_22x2P + rev=1) */ + MGD_2222P_A0 = 0x199, /* 88X2222P_A0 (MGD_22x2P + rev=9) */ +}; + +enum { + MGD_PCS_SPEED_40GBASE_R4 = 0x70, + MGD_PCS_SPEED_10GBASE_R = 0x71, + MGD_PCS_SPEED_10GBASE_X2 = 0x72, + MGD_PCS_SPEED_10GBASE_X4 = 0x73, + MGD_PCS_SPEED_10GBASE_W = 0x74, /* line side only */ + MGD_PCS_SPEED_20GBASE_R2 = 0x75, + MGD_PCS_SPEED_20GBASE_X4 = 0x76, + MGD_PCS_SPEED_2500BASE_X = 0X76, + MGD_PCS_SPEED_20GBASE_R8 = 0x77, /* host side only */ + MGD_PCS_SPEED_40GBASE_R8 = 0x77, /* host side only */ + MGD_PCS_SPEED_1000BASE_AN_OFF = 0x7A, + MGD_PCS_SPEED_1000BASE_AN_ON = 0x7B, + MGD_PCS_SPEED_SGMII_MAC_AN_OFF = 0x7C, + MGD_PCS_SPEED_SGMII_MAC_AN_ON = 0x7D, + MGD_PCS_SPEED_SGMII_LINE_AN_OFF = 0x7E, + MGD_PCS_SPEED_SGMII_LINE_AN_ON = 0x7F, + MGD_PCS_SPEED_UNKNOWN = 0x78, /* temp set reserved */ +}; + +struct debug_register { + int port; + int devad; + int regnum; +} debug_registers[] = { + /* PCS Registers */ + { 0, 31, 0xf002 }, + /* line side */ + { 0, 3, 0xf074 }, /* pwr mgmt TX state control*/ + { 0, 3, 0x0001 }, /* PCS status*/ + { 0, 3, 0xf002 }, /* PCS port configuration*/ + { 0, 3, 0xf010 }, /* Packet generator/CRC checker*/ + { 0, 3, 0x3021 }, /* PCS status2 (block lock/High BER)*/ + /* host side */ + { 0, 4, 0xf074 }, /* Power management control*/ + { 0, 4, 0x1018 }, /* XAUI/RXAUI alignment and sync*/ + { 0, 4, 0x3032 }, /* XAUI/RXAUI block lock per lane*/ + { 0, 4, 0x3034 }, /* XAUI/RXAUI alignment*/ + { 0, 4, 0x0001 }, /* PCS status*/ + { 0, 4, 0xf002 }, /* PCS port configuration*/ + { 0, 4, 0xf010 }, /* Packet generator/CRC checker*/ + { 0, 4, 0x3021 }, /* PCS status2 (block lock/High BER)*/ + /* DSP Registers */ + /* line side */ + { 0, 30, 0xb841 }, + /* port 0 */ + { 0, 30, 0xb111 }, + { 0, 30, 0xb116 }, /* sfi tx settings*/ + { 0, 30, 0xb117 }, /* sfi tx settings*/ + { 0, 30, 0xb042 }, /* dsp status*/ + { 0, 30, 0xb132 }, /* pga*/ + { 0, 30, 0xb000 }, + { 0, 30, 0xb001 }, + { 0, 30, 0xb1be }, /* snr*/ + { 0, 30, 0xb1f1 }, + { 0, 30, 0xb1d3 }, + { 0, 30, 0xb065 }, + { 0, 30, 0xb1bb }, + { 0, 30, 0xb1bc }, + { 0, 30, 0xb1bf }, + { 0, 30, 0xb1b3 }, + /* port 1 */ + { 0, 30, 0xb311 }, + { 0, 30, 0xb316 }, + { 0, 30, 0xb317 }, + { 0, 30, 0xb242 }, + { 0, 30, 0xb332 }, + { 0, 30, 0xb200 }, + { 0, 30, 0xb201 }, + { 0, 30, 0xb3be }, + { 0, 30, 0xb3f1 }, + { 0, 30, 0xb3d3 }, + { 0, 30, 0xb265 }, + { 0, 30, 0xb3bb }, + { 0, 30, 0xb3bc }, + { 0, 30, 0xb3bf }, + { 0, 30, 0xb3b3 }, + /* port 2 */ + { 0, 30, 0xb511 }, + { 0, 30, 0xb516 }, + { 0, 30, 0xb517 }, + { 0, 30, 0xb442 }, + { 0, 30, 0xb532 }, + { 0, 30, 0xb400 }, + { 0, 30, 0xb401 }, + { 0, 30, 0xb5be }, + { 0, 30, 0xb5f1 }, + { 0, 30, 0xb5d3 }, + { 0, 30, 0xb465 }, + { 0, 30, 0xb5bb }, + { 0, 30, 0xb5bc }, + { 0, 30, 0xb5bf }, + { 0, 30, 0xb5b3 }, + /* port 3 */ + { 0, 30, 0xb711 }, + { 0, 30, 0xb716 }, + { 0, 30, 0xb717 }, + { 0, 30, 0xb642 }, + { 0, 30, 0xb732 }, + { 0, 30, 0xb600 }, + { 0, 30, 0xb601 }, + { 0, 30, 0xb7be }, + { 0, 30, 0xb7f1 }, + { 0, 30, 0xb7d3 }, + { 0, 30, 0xb665 }, + { 0, 30, 0xb7bb }, + { 0, 30, 0xb7bc }, + { 0, 30, 0xb7bf }, + { 0, 30, 0xb7b3 }, + { 0, 30, 0xb753 }, + { 0, 30, 0xb780 }, + { 0, 30, 0xb7d4 }, + { 0, 30, 0xb7d6 }, + { 0, 30, 0xb7ea }, + /* host side */ + { 0, 30, 0x9041 }, + /* port 0 */ + { 0, 30, 0x8111 }, + { 0, 30, 0x8116 }, + { 0, 30, 0x8117 }, + { 0, 30, 0x8042 }, + { 0, 30, 0x8132 }, + { 0, 30, 0x81d1 }, + /* port 1 */ + { 0, 30, 0x8311 }, + { 0, 30, 0x8316 }, + { 0, 30, 0x8317 }, + { 0, 30, 0x8242 }, + { 0, 30, 0x8332 }, + { 0, 30, 0x83d1 }, + /* port 2 */ + { 0, 30, 0x8511 }, + { 0, 30, 0x8516 }, + { 0, 30, 0x8517 }, + { 0, 30, 0x8442 }, + { 0, 30, 0x8532 }, + { 0, 30, 0x85d1 }, + /* port 3 */ + { 0, 30, 0x8711 }, + { 0, 30, 0x8716 }, + { 0, 30, 0x8717 }, + { 0, 30, 0x8642 }, + { 0, 30, 0x8732 }, + { 0, 30, 0x87d1 }, +}; + +static const char *get_name(u16 device_id) +{ + switch (device_id) { + case MGD_2140M_A1: + return "MV88X2140M_A1"; + case MGD_2242_B0: + return "MV88X2242_B0"; + case MGD_2242M_A0: + return "MV88X2242M_A0"; + case MGD_2242M_B0: + return "MV88X2242M_B0"; + case MGD_2222_B0: + return "MV88X2222_B0"; + case MGD_2222M_B0: + return "MV88X2222M_B0"; + case MGD_2242P_A0: + return "MV88X2242P_A0"; + case MGD_2222P_A0: + return "MV88X2222P_A0"; + } + + return ""; +} + +static int get_num_ports(u16 device_id) +{ + int res = -1; + + switch (device_id) { + case MGD_2140M_A1: + case MGD_2242M_A0: + case MGD_2242M_B0: + case MGD_2242_B0: + case MGD_2242P_A0: + res = 4; + break; + + case MGD_2222P_A0: + case MGD_2222_B0: + case MGD_2222M_B0: + res = 2; + break; + }; + + return res; +} + +/* + * 88X2 takes 4 consecutive addresses on the mdio bus + * this provides access to these port instances + */ +static int m88x2_read(struct phy_device *phydev, int port, int devad, + int regnum) +{ + struct mii_dev *bus = phydev->bus; + + return bus->read(bus, phydev->addr + port, devad, regnum); +} + +static int m88x2_write(struct phy_device *phydev, int port, int devad, + int regnum, u16 val) +{ + struct mii_dev *bus = phydev->bus; + + return bus->write(bus, phydev->addr + port, devad, regnum, val); +} + +static int m88x2_write_mask(struct phy_device *phydev, int port, int devad, + int regnum, u16 mask, u16 val) +{ + u16 reg; + struct mii_dev *bus = phydev->bus; + + reg = bus->read(bus, phydev->addr + port, devad, regnum); + reg &= ~mask; + reg |= val; + + return bus->write(bus, phydev->addr + port, devad, regnum, reg); +} + +static int m88x2_write_all(struct phy_device *phydev, int devad, int regnum, + u16 val) +{ + unsigned int k; + + for (k = 0; k < 4; ++k) { + int res = m88x2_write(phydev, k, devad, regnum, val); + + if (res < 0) + return res; + } + + return 0; +} + +#ifdef CONFIG_MV88X2_DEBUG_REGS +static void m88x2_dump_debug(struct phy_device *phydev) +{ + unsigned int k; + + for (k = 0; k < ARRAY_SIZE(debug_registers); ++k) { + int val; + struct debug_register *reg = &debug_registers[k]; + + val = m88x2_read(phydev, reg->port, reg->devad, reg->regnum); + printf("%2x.%04x %04x\n", reg->devad, reg->regnum, val); + } +} +#endif + +/* 88X2 has a weird way of mixing revision and device id encoding */ +static int get_device_id(struct phy_device *phydev) +{ + u16 id2 = phy_read(phydev, 1, 3); + u16 device_id_raw = id2 & 0x3FF; + u16 device_id_base = device_id_raw >> 4; + u16 revision = device_id_raw & 0xF; + int res = -1; + + switch (device_id_base) { + case MGD_22x2M: + switch (revision) { + case 1: + res = MGD_2242_B0; + break; + case 2: + res = MGD_2242M_A0; + break; + case 3: + res = MGD_2242M_B0; + break; + case 5: + res = MGD_2222_B0; + break; + case 7: + res = MGD_2222M_B0; + break; + } + break; + case MGD_22x2P: + switch (revision) { + case 1: + res = MGD_2242P_A0; + break; + case 9: + res = MGD_2222P_A0; + break; + } + break; + } + + return res; +} + +static int configure_host_lanes(struct phy_device *phydev, int num_ports) +{ + printf(" setup host lane mux for %d ports\n", num_ports); + +#ifdef CONFIG_MV88X2_HOST_LANE_MUX_4_PORT + if (num_ports == 4) { + m88x2_write(phydev, 0, 31, 0xf402, + CONFIG_MV88X2_HOST_LANE_MUX_4_PORT); + } +#endif + +#ifdef CONFIG_MV88X2_HOST_LANE_MUX_2_PORT + if (num_ports == 2) + m88x2_write(phydev, 0, 31, 0xf402, + CONFIG_MV88X2_HOST_LANE_MUX_2_PORT); +#endif + + m88x2_write_mask(phydev, 0, 31, 0xf404, 0x8000, 0x8000); + + m88x2_write_all(phydev, 31, 0xf003, 0x0080); + + return 0; +} + +static int configure_options(struct phy_device *phydev) +{ + struct mv88x2_config_data data; + + printf(" setup board specific options\n"); + + memset(&data, 0, sizeof(struct mv88x2_config_data)); + + data.led0_blink = CONFIG_MV88X2_LED0_BLINK; + data.led0_solid = CONFIG_MV88X2_LED0_SOLID; + data.led1_blink = CONFIG_MV88X2_LED1_BLINK; + data.led1_solid = CONFIG_MV88X2_LED1_SOLID; + data.sfi_pol = CONFIG_MV88X2_SFI_POL; + data.xfi_pol = CONFIG_MV88X2_XFI_POL; + +#ifdef CONFIG_BOARD_MV88X2_CONFIG + board_mv88x2_config(&data); +#endif + + if (data.sfi_pol) + m88x2_write(phydev, 0, 31, 0xf407, data.sfi_pol); + + m88x2_write(phydev, 0, 31, 0xf406, data.xfi_pol); + +#ifdef CONFIG_MV88X2_X2_DISPARITY + m88x2_write_all(phydev, 4, 0x9000, 0x0002); +#endif + + m88x2_write_all(phydev, 31, 0xf020, data.led0_blink << 8 | + data.led0_solid << 4); + + m88x2_write_all(phydev, 31, 0xf021, data.led1_blink << 8 | + data.led1_solid << 4); + return 0; +} + +static int port_power_up(struct phy_device *phydev, unsigned int device_id, + unsigned int port) +{ + printf(" power up port %u\n", port); + + /* power up all ports in config reg */ + m88x2_write(phydev, 0, 31, 0xf403, 0x0000); + + if (device_id == MGD_2242M_B0 || + device_id == MGD_2222_B0 || + device_id == MGD_2222M_B0 || + device_id == MGD_2242_B0) { + m88x2_write(phydev, 0, 31, 0xf400, 0xba98); + m88x2_write(phydev, 0, 31, 0xf401, 0xba98); + } + + /* power up primary ports */ + m88x2_write(phydev, port, 3, 0, 0x2040); + m88x2_write(phydev, port, 4, 0, 0x2040); + + /* port reset */ + m88x2_write(phydev, port, 31, 0xf003, 0x8080); + + /* power up line side */ + m88x2_write_mask(phydev, port, 31, 0xf003, BIT(14), 0); + /* power up host side */ + m88x2_write_mask(phydev, port, 31, 0xf003, BIT(6), 0); + + /* SFI */ + m88x2_write_mask(phydev, port, 1, 0, BIT(11), 0); +#ifdef CONFIG_MV88X2_LINE_10GBASE_R + m88x2_write_mask(phydev, port, 3, 0, BIT(11), 0); +#endif + + /* XFI */ +#if defined(CONFIG_MV88X2_HOST_10GBASE_R) + m88x2_write_mask(phydev, port, 4, 0, BIT(11), 0); +#elif defined(CONFIG_MV88X2_HOST_10GBASE_X2) || \ + defined(CONFIG_MV88X2_HOST_10GBASE_X4) + m88x2_write_mask(phydev, port, 4, 0x1000, BIT(11), 0); +#endif + + return 0; +} + +#if defined(CONFIG_MV88X2_LINE_10GBASE_R) && \ + defined(CONFIG_MV88X2_HOST_10GBASE_X2) +/* initialization sequence from Marvell MGD driver Release 2.4 */ +static int init_port_mode_2242m_b0_10gr_10gx2(struct phy_device *phydev, + unsigned int port) +{ + printf(" init_port_mode_2242m_b0_10gr_10gx2 port %u\n", port); + + m88x2_write(phydev, 0, 30, 0xb841, 0x0000); + m88x2_write(phydev, 0, 30, 0x9041, 0x03aa); + udelay(100); + + m88x2_write_mask(phydev, 0, 30, 0xb040 + port * 0x200, 0x4000, 0x4000); + + m88x2_write_mask(phydev, 0, 30, 0x8040 + port * 0x400, 0x4000, 0x4000); + udelay(100); + + /* 10GR-10GX2 */ + m88x2_write(phydev, port, 3, 0xf002, + (0x80 << 8) | MGD_PCS_SPEED_10GBASE_R); + m88x2_write(phydev, port, 4, 0xf002, + (0x80 << 8) | MGD_PCS_SPEED_10GBASE_X2); + + m88x2_write(phydev, 0, 30, 0xb108 + port * 0x200, 0xf8d0); + + m88x2_write_mask(phydev, 0, 30, 0xb1e7 + port * 0x200, 0xc000, 0x0000); + + m88x2_write_mask(phydev, 0, 30, 0xb1e8 + port * 0x200, 0x7f00, 0x2000); + + m88x2_write_mask(phydev, 0, 30, 0xb042 + port * 0x200, 0x00f0, 0x00b0); + + m88x2_write(phydev, 0, 30, 0xb1a2 + port * 0x200, 0x00b0); + m88x2_write(phydev, 0, 30, 0xb19c + port * 0x200, 0x00a0); + + m88x2_write_mask(phydev, 0, 30, 0xb1b5 + port * 0x200, 0x1000, 0x0000); + + m88x2_write_mask(phydev, 0, 30, 0xb1b4 + port * 0x200, 0x1000, 0x1000); + + m88x2_write_mask(phydev, 0, 30, 0xb181 + port * 0x200, 0xff00, 0x3300); + + m88x2_write(phydev, 0, 30, 0x8141 + port * 0x400, 0x8f1a); + m88x2_write(phydev, 0, 30, 0x8131 + port * 0x400, 0x8f1a); + m88x2_write(phydev, 0, 30, 0x8077 + port * 0x400, 0x820a); + + m88x2_write_mask(phydev, 0, 30, 0x80a0 + port * 0x400, 0x01ff, 0x0100); + + m88x2_write_mask(phydev, 0, 30, 0x8085 + port * 0x400, 0x3f00, 0x0700); + + m88x2_write_mask(phydev, 0, 30, 0x807b + port * 0x400, 0x0fff, 0x02b2); + + m88x2_write_mask(phydev, 0, 30, 0x80b0 + port * 0x400, 0x0770, 0x0220); + + m88x2_write_mask(phydev, 0, 30, 0x80b1 + port * 0x400, 0x0c30, 0x0820); + + m88x2_write_mask(phydev, 0, 30, 0x8093 + port * 0x400, 0x7f00, 0x4600); + + m88x2_write_mask(phydev, 0, 30, 0x809f + port * 0x400, 0x007f, 0x0079); + + m88x2_write(phydev, 0, 30, 0x805c + port * 0x400, 0x4759); + m88x2_write(phydev, 0, 30, 0x805d + port * 0x400, 0x5900); + m88x2_write(phydev, port, 31, 0xf016, 0x0010); + /* CQ: 00006634 03/21/2016 */ + m88x2_write_mask(phydev, 0, 30, 0xb153 + port * 0x200, 0x0070, 0x0070); + m88x2_write(phydev, port, 31, 0xf003, 0x8080); + + return 0; +} + +/* initialization sequence from Marvell MGD driver Release 2.4 */ +static int init_mode_2242m_b0_10gr_10gx2(struct phy_device *phydev, + int num_ports) +{ + ulong mv88x2cfg = getenv_hex("mv88x2cfg", 0xe7); + + printf(" init_mode_2242m_b0_10gr_10gx2\n"); + + /* Chip Hardware Reset */ + m88x2_write(phydev, 0, 31, 0xf404, 0x4000); + udelay(100); + + configure_host_lanes(phydev, num_ports); + if (mv88x2cfg & BIT(7)) + configure_options(phydev); + + /* set pcs speed mode */ + m88x2_write_all(phydev, 31, 0xf002, 0x7172); + + /* Couple Lane Writing Line Side */ + m88x2_write(phydev, 0, 30, 0xb841, 0xe000); + /* Couple Lane Writing Host Side */ + m88x2_write(phydev, 0, 30, 0x9041, 0x03fe); + + /* LINE: Analog BW and ETA TxPLL */ + m88x2_write(phydev, 0, 30, 0xb108, 0xf8d0); + + m88x2_write_mask(phydev, 0, 30, 0xb1e7, 0xc000, 0x0000); + + /* Hack pga table index for testing boost adjustment */ + m88x2_write_mask(phydev, 0, 30, 0xb1e8, 0x7f00, 0x2000); + + /* Enable ramping detection */ + m88x2_write_mask(phydev, 0, 30, 0xb042, 0x00f0, 0x00b0); + + /* Initial gain */ + m88x2_write(phydev, 0, 30, 0xb1a2, 0x00b0); + /* Initial FFE */ + m88x2_write(phydev, 0, 30, 0xb19c, 0x00a0); + + /* freeze FFE main tap adaptation */ + m88x2_write_mask(phydev, 0, 30, 0xb1b5, 0x1000, 0x0000); + m88x2_write_mask(phydev, 0, 30, 0xb1b4, 0x1000, 0x1000); + + /* lower FFE mu */ + m88x2_write_mask(phydev, 0, 30, 0xb181, 0xff00, 0x3300); + + /* Host: Analog BW and ETA TxPLL */ + m88x2_write(phydev, 0, 30, 0x8141, 0x8f1a); + /* Host: Analog BW and ETA RxPll */ + m88x2_write(phydev, 0, 30, 0x8131, 0x8f1a); + /* Change DFE threshold */ + m88x2_write(phydev, 0, 30, 0x8077, 0x820a); + + /* 3/24/2015 updates */ + /* Force BLW gain to zero */ + m88x2_write_mask(phydev, 0, 30, 0x80a0, 0x01ff, 0x0100); + + /* Constrain C0 min */ + m88x2_write_mask(phydev, 0, 30, 0x8085, 0x3f00, 0x0700); + + /* change C0 min for best veo search */ + m88x2_write_mask(phydev, 0, 30, 0x807b, 0x0fff, 0x02b2); + + /* Force EQR/EQC value */ + m88x2_write_mask(phydev, 0, 30, 0x80b0, 0x0770, 0x0220); + m88x2_write_mask(phydev, 0, 30, 0x80b1, 0x0c30, 0x0820); + + /* peakdet threshold change before and after startup */ + m88x2_write_mask(phydev, 0, 30, 0x8093, 0x7f00, 0x4600); + m88x2_write_mask(phydev, 0, 30, 0x809f, 0x007f, 0x0079); + + /* kpkf for 6G */ + m88x2_write(phydev, 0, 30, 0x805c, 0x4759); + m88x2_write(phydev, 0, 30, 0x805d, 0x5900); + + /* enable sfp tx_fault, rx_los and mod_abs functions */ + m88x2_write_all(phydev, 31, 0xf014, 0x0777); + + /* enable sfp tx_disable function */ + m88x2_write_all(phydev, 31, 0xf016, 0x0010); + + /* enable sfp tx_fault, rx_los and mod_abs interrupts*/ + m88x2_write_all(phydev, 31, 0xf010, 0x0007); + + /* CQ: 00006634 03/21/2016 */ + m88x2_write_mask(phydev, 0, 30, 0xb153, 0x0070, 0x0070); + m88x2_write_mask(phydev, 0, 30, 0xb353, 0x0070, 0x0070); + m88x2_write_mask(phydev, 0, 30, 0xb553, 0x0070, 0x0070); + m88x2_write_mask(phydev, 0, 30, 0xb753, 0x0070, 0x0070); + + /* PCS Reset */ + m88x2_write_all(phydev, 31, 0xf003, 0x8080); + + udelay(2000); + + /* release FFE main tap adaptation */ + m88x2_write_mask(phydev, 0, 30, 0xb1b5, 0x1000, 0x1000); + m88x2_write_mask(phydev, 0, 30, 0xb1b4, 0x1000, 0x1000); + + return 0; +} +#endif + +static int disable_tx_rx_reset(struct phy_device *phydev, unsigned int port) +{ + printf(" %s port %u\n", __func__, port); + + m88x2_write_mask(phydev, port, 3, 0xf074, 0x2000, 0); + + return 0; +} + +static int m88x2_config(struct phy_device *phydev) +{ + unsigned int k; + int device_id; + int num_ports; + int sfi_pol; + + /* + * mv88x2cfg environment variable encoding, default: 0xe7 + * bit 0: execute init_mode() + * bit 1: execute init_port_mode() + * bit 2: execute port_power_up() + * bit 3: initialize sfi_pol, xfi_pol and disparity before + * port_power_up() + * bit 4: initialize sfi_pol, xfi_pol and disparity after + * port_power_up() + * bit 5: initialize lane_mux + * bit 6: disable tx/rx reset mechanism + * bit 7: initialize sfi_pol, xfi_pol and disparity ASAP() + */ + ulong mv88x2cfg = getenv_hex("mv88x2cfg", 0xe7); + + device_id = get_device_id(phydev); + if (device_id < 0) + return -1; + + num_ports = get_num_ports(device_id); + if (num_ports < 0) + return -1; + + printf("%s (%d ports, %02x on %s):\n", get_name(device_id), num_ports, + phydev->addr, phydev->bus->name); + +#ifdef CONFIG_MV88X2_LINE_10GBASE_R +#ifdef CONFIG_MV88X2_HOST_10GBASE_X2 + if (mv88x2cfg & BIT(0)) + init_mode_2242m_b0_10gr_10gx2(phydev, num_ports); +#endif +#endif + + if (mv88x2cfg & BIT(3)) + configure_options(phydev); + + for (k = 0; k < 4; ++k) { + /* on devices with 2 ports, ports 0 and 2 are active */ + if ((k % 2) && (num_ports == 2)) + continue; + +#ifdef CONFIG_MV88X2_LINE_10GBASE_R +#ifdef CONFIG_MV88X2_HOST_10GBASE_X2 + if (mv88x2cfg & BIT(1)) + init_port_mode_2242m_b0_10gr_10gx2(phydev, k); +#endif +#endif + + if (mv88x2cfg & BIT(6)) + disable_tx_rx_reset(phydev, k); + + if (mv88x2cfg & BIT(2)) + port_power_up(phydev, device_id, k); + } + + if (mv88x2cfg & BIT(4)) + configure_options(phydev); + + sfi_pol = m88x2_read(phydev, 0, 31, 0xf407); + + /* Marvells magic SFI input polarity inversion fix */ + if (sfi_pol & 0x0f00) { + puts(" "); + puts("apply Marvells magic SFI input polarity inversion fix\n"); + m88x2_write(phydev, 0, 30, 0xb800, 0); + m88x2_write_mask(phydev, 0, 30, 0xb133, 0x0020, 0x0020); + m88x2_write_mask(phydev, 0, 30, 0xb333, 0x0020, 0x0020); + m88x2_write_mask(phydev, 0, 30, 0xb533, 0x0020, 0x0020); + m88x2_write_mask(phydev, 0, 30, 0xb733, 0x0020, 0x0020); + } + + return 0; +}; + +static int m88x2_startup(struct phy_device *phydev) +{ +#ifdef CONFIG_MV88X2_DEBUG_REGS + m88x2_dump_debug(phydev); +#endif + + return gen10g_startup(phydev); +} + +static struct phy_driver M88X2_driver = { + .name = "Marvell 88X2", + .uid = 0x01410f10, + .mask = 0xffffff0, + .features = PHY_10G_FEATURES, + .config = &m88x2_config, + .startup = &m88x2_startup, + .shutdown = &gen10g_shutdown, +}; + +int phy_m88x2_init(void) +{ + phy_register(&M88X2_driver); + + return 0; +} + +static int sfi_test(struct phy_device *phydev, int portmask) +{ + int port; + + /* PCS Reset */ + m88x2_write_all(phydev, 31, 0xf003, 0x8080); + + mdelay(2000); + + for (port = 0; port < 4; ++port) { + if (!(portmask & BIT(port))) + continue; + /* pseudo random byte with crc */ + m88x2_write(phydev, port, 3, 0xf011, 0x00a0); + /* continuously generate packets */ + m88x2_write(phydev, port, 3, 0xf017, 0xffff); + /* enable generator and checker */ + m88x2_write(phydev, port, 3, 0xf010, 0x0003); + udelay(200); + /* clear counters */ + m88x2_write(phydev, port, 3, 0xf010, 0x0043); + } + + mdelay(4000); + + for (port = 0; port < 4; ++port) { + unsigned long long rxcnt, errcnt; + + if (!(portmask & BIT(port))) + continue; + + rxcnt = m88x2_read(phydev, port, 3, 0xf021); + rxcnt |= (unsigned long long)m88x2_read(phydev, port, 3, + 0xf022) << 16; + rxcnt |= (unsigned long long)m88x2_read(phydev, port, 3, + 0xf023) << 32; + + errcnt = m88x2_read(phydev, port, 3, 0xf027); + errcnt |= (unsigned long long)m88x2_read(phydev, port, 3, + 0xf028) << 16; + errcnt |= (unsigned long long)m88x2_read(phydev, port, 3, + 0xf029) << 32; + + if (errcnt > 1) + printf("\033[49;1;31m"); + + printf("%d: %llu\033[0m/%llu ", port, errcnt, rxcnt); + } + + printf("\n"); + + for (port = 0; port < 4; ++port) { + if (!(portmask & BIT(port))) + continue; + + /* disable generator */ + m88x2_write(phydev, port, 3, 0xf010, 0x0001); + } + + return 0; +} + +static int do_mv88x2(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char op[2]; + int portmask = 0xf; + int pos = argc - 1; + struct mii_dev *bus; + struct phy_device *phydev = NULL; + + if (argc < 2) + return CMD_RET_USAGE; + + /* + * We use the last specified parameters, unless new ones are + * entered. + */ + op[0] = argv[1][0]; + + bus = mdio_get_current_dev(); + + switch (op[0]) { + case 's': + if (pos > 3) + portmask = simple_strtoul(argv[pos--], NULL, 16); + break; + } + + if (pos > 2) + bus = miiphy_get_dev_by_name(argv[pos - 1]); + if (!bus) + return -1; + + if (pos > 1) { + unsigned int addr = simple_strtoul(argv[pos], NULL, 16); + + if (addr > 31) + return -1; + phydev = phy_find_by_mask_c45(bus, BIT(addr), + PHY_INTERFACE_MODE_XGMII); + } + if (!phydev) + return -1; + + switch (op[0]) { + case 's': + sfi_test(phydev, portmask); + break; + } + + return 0; +} + +/***************************************************/ + +U_BOOT_CMD( + mv88x2, 6, 0, do_mv88x2, + "MV88X2 utility commands", + "sfitest <busname> <addr> [<portmask>] - use PHY packet generator/checker to test SFI ports at <portmask>\n" +); diff --git a/drivers/net/phy/mv88x2.h b/drivers/net/phy/mv88x2.h new file mode 100644 index 0000000000..6cd2073cae --- /dev/null +++ b/drivers/net/phy/mv88x2.h @@ -0,0 +1,12 @@ +struct mv88x2_config_data { + ulong sfi_pol; + ulong xfi_pol; + u16 led0_blink; + u16 led0_solid; + u16 led1_blink; + u16 led1_solid; +}; + +#ifdef CONFIG_BOARD_MV88X2_CONFIG +int board_mv88x2_config(struct mv88x2_config_data *data); +#endif diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index a16bb6ca89..f39ab39061 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -493,6 +493,9 @@ int phy_init(void) #ifdef CONFIG_PHY_MICREL phy_micrel_init(); #endif +#ifdef CONFIG_PHY_MV88X2 + phy_m88x2_init(); +#endif #ifdef CONFIG_PHY_NATSEMI phy_natsemi_init(); #endif diff --git a/include/phy.h b/include/phy.h index 75a9ae3314..1c94f511a7 100644 --- a/include/phy.h +++ b/include/phy.h @@ -275,6 +275,7 @@ int phy_et1011c_init(void); int phy_lxt_init(void); int phy_marvell_init(void); int phy_micrel_init(void); +int phy_m88x2_init(void); int phy_natsemi_init(void); int phy_realtek_init(void); int phy_smsc_init(void);

DM serial drivers on PowerPC determine their clock frequency via the get_serial_clock function. This function is not Implemented yet for MPC83xx.

This patch Implements the function so that DM serial drivers work on MPC83xx.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

arch/powerpc/cpu/mpc83xx/speed.c | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 5498c19e25..5864a4fb57 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -515,6 +515,13 @@ ulong get_ddr_freq(ulong dummy) return gd->mem_clk; }

+#ifdef CONFIG_DM_SERIAL +int get_serial_clock(void) +{ + return get_bus_freq(0); +} +#endif + static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char buf[32];

The variable cfi_flash_num_flash_banks is defined iff CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, but it is used unconditionally in the function cfi_flash_init_dm. This leads to a undefined variable compile error when CONFIG_SYS_MAX_FLASH_BANKS_DETECT is not defined, but DM is enabled.

Fix this by always defining the cfi_flash_num_flash_banks variable.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

drivers/mtd/cfi_flash.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 2445632580..4f9a88e2a3 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -91,6 +91,8 @@ static u16 cfi_flash_config_reg(int i)

#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; +#else +int cfi_flash_num_flash_banks; #endif

#ifdef CONFIG_CFI_FLASH /* for driver model */

Fix some style violations in the MPC85XX GPIO driver.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

drivers/gpio/mpc85xx_gpio.c | 42 ++++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 20 deletions(-)

diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c index cfeb6e7632..4566c091b7 100644 --- a/drivers/gpio/mpc85xx_gpio.c +++ b/drivers/gpio/mpc85xx_gpio.c @@ -34,11 +34,13 @@ struct mpc85xx_gpio_data { uint gpio_count; /* The GPDAT register cannot be used to determine the value of output * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value - * for output pins */ + * for output pins + */ u32 dat_shadow; };

-inline u32 gpio_mask(unsigned gpio) { +inline u32 gpio_mask(uint gpio) +{ return (1U << (31 - (gpio))); }

@@ -92,7 +94,7 @@ static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base, clrbits_be32(&base->gpodr, gpios); }

-static int mpc85xx_gpio_direction_input(struct udevice *dev, unsigned gpio) +static int mpc85xx_gpio_direction_input(struct udevice *dev, uint gpio) { struct mpc85xx_gpio_data *data = dev_get_priv(dev);

@@ -100,8 +102,7 @@ static int mpc85xx_gpio_direction_input(struct udevice *dev, unsigned gpio) return 0; }

-static int mpc85xx_gpio_set_value(struct udevice *dev, unsigned gpio, - int value) +static int mpc85xx_gpio_set_value(struct udevice *dev, uint gpio, int value) { struct mpc85xx_gpio_data *data = dev_get_priv(dev);

@@ -115,46 +116,46 @@ static int mpc85xx_gpio_set_value(struct udevice *dev, unsigned gpio, return 0; }

-static int mpc85xx_gpio_direction_output(struct udevice *dev, unsigned gpio, +static int mpc85xx_gpio_direction_output(struct udevice *dev, uint gpio, int value) { return mpc85xx_gpio_set_value(dev, gpio, value); }

-static int mpc85xx_gpio_get_value(struct udevice *dev, unsigned gpio) +static int mpc85xx_gpio_get_value(struct udevice *dev, uint gpio) { struct mpc85xx_gpio_data *data = dev_get_priv(dev);

if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) { /* Output -> use shadowed value */ return !!(data->dat_shadow & gpio_mask(gpio)); - } else { - /* Input -> read value from GPDAT register */ - return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio)); } + + /* Input -> read value from GPDAT register */ + return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio)); }

-static int mpc85xx_gpio_get_open_drain(struct udevice *dev, unsigned gpio) +static int mpc85xx_gpio_get_open_drain(struct udevice *dev, uint gpio) { struct mpc85xx_gpio_data *data = dev_get_priv(dev);

return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio)); }

-static int mpc85xx_gpio_set_open_drain(struct udevice *dev, unsigned gpio, +static int mpc85xx_gpio_set_open_drain(struct udevice *dev, uint gpio, int value) { struct mpc85xx_gpio_data *data = dev_get_priv(dev);

- if (value) { + if (value) mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio)); - } else { + else mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio)); - } + return 0; }

-static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio) +static int mpc85xx_gpio_get_function(struct udevice *dev, uint gpio) { struct mpc85xx_gpio_data *data = dev_get_priv(dev); int dir; @@ -164,14 +165,15 @@ static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio) }

#if CONFIG_IS_ENABLED(OF_CONTROL) -static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) { +static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) +{ struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev); fdt_addr_t addr; fdt_size_t size;

addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, - dev_of_offset(dev), "reg", 0, &size, false); - + dev_of_offset(dev), + "reg", 0, &size, false); plat->addr = addr; plat->size = size; plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), @@ -229,7 +231,7 @@ static const struct dm_gpio_ops gpio_mpc85xx_ops = { .set_value = mpc85xx_gpio_set_value, .get_open_drain = mpc85xx_gpio_get_open_drain, .set_open_drain = mpc85xx_gpio_set_open_drain, - .get_function = mpc85xx_gpio_get_function, + .get_function = mpc85xx_gpio_get_function, };

static const struct udevice_id mpc85xx_gpio_ids[] = {

Since the GPIO controllers on MPC8XXX just vary in the number of pins offered, the DM driver for the MPC85XX SoC can be used for the whole family.

To reflect this, we rename the mpc85xx_gpio driver to the more generic mpc8xxx_gpio, and add the needed mpc8xxx_gpio_plat structure to the mpc83xx gpio.h.

Hence, this driver now also serves as a GPIO DM-driver for the MPC83XX platform.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 8 + arch/powerpc/include/asm/arch-mpc85xx/gpio.h | 2 +- drivers/gpio/Kconfig | 9 +- drivers/gpio/Makefile | 2 +- drivers/gpio/mpc85xx_gpio.c | 253 ------------------------- drivers/gpio/mpc8xxx_gpio.c | 274 +++++++++++++++++++++++++++ 6 files changed, 287 insertions(+), 261 deletions(-) delete mode 100644 drivers/gpio/mpc85xx_gpio.c create mode 100644 drivers/gpio/mpc8xxx_gpio.c

diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 40ef2151b8..6ec4f00022 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -19,7 +19,15 @@

#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS)

+struct mpc8xxx_gpio_plat { + ulong addr; + unsigned long size; + uint ngpios; +}; + +#ifndef DM_GPIO void mpc83xx_gpio_init_f(void); void mpc83xx_gpio_init_r(void); +#endif /* DM_GPIO */

#endif /* MPC83XX_GPIO_H_ */ diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h index 76faa22c8b..b2ba31e623 100644 --- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h @@ -18,7 +18,7 @@ #include <asm/mpc85xx_gpio.h> #endif

-struct mpc85xx_gpio_plat { +struct mpc8xxx_gpio_plat { ulong addr; unsigned long size; uint ngpios; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 15135e538d..4e37e2179e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -239,11 +239,11 @@ config DM_PCA953X Now, max 24 bits chips and PCA953X compatible chips are supported

-config MPC85XX_GPIO - bool "Freescale MPC85XX GPIO driver" +config MPC8XXX_GPIO + bool "Freescale MPC8XXX GPIO driver" depends on DM_GPIO help - This driver supports the built-in GPIO controller of MPC85XX CPUs. + This driver supports the built-in GPIO controller of MPC8XXX CPUs. Each GPIO bank is identified by its own entry in the device tree, i.e.

@@ -261,7 +261,4 @@ config MPC85XX_GPIO Aside from the standard functions of input/output mode, and output value setting, the open-drain feature, which can configure individual GPIOs to work as open-drain outputs, is supported. - - The driver has been tested on MPC85XX, but it is likely that other - PowerQUICC III devices will work as well. endmenu diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 8937e99b47..3f38555ab0 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -37,7 +37,7 @@ obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o obj-$(CONFIG_ALTERA_PIO) += altera_pio.o obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o -obj-$(CONFIG_MPC85XX_GPIO) += mpc85xx_gpio.o +obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c deleted file mode 100644 index 4566c091b7..0000000000 --- a/drivers/gpio/mpc85xx_gpio.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * (C) Copyright 2016 - * Mario Six, Guntermann & Drunck GmbH, six@gdsys.de - * - * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is - * - * Copyright 2010 eXMeritus, A Boeing Company - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <asm/gpio.h> -#include <mapmem.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct ccsr_gpio { - u32 gpdir; - u32 gpodr; - u32 gpdat; - u32 gpier; - u32 gpimr; - u32 gpicr; -}; - -struct mpc85xx_gpio_data { - /* The bank's register base in memory */ - struct ccsr_gpio __iomem *base; - /* The address of the registers; used to identify the bank */ - ulong addr; - /* The GPIO count of the bank */ - uint gpio_count; - /* The GPDAT register cannot be used to determine the value of output - * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value - * for output pins - */ - u32 dat_shadow; -}; - -inline u32 gpio_mask(uint gpio) -{ - return (1U << (31 - (gpio))); -} - -static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask) -{ - return in_be32(&base->gpdat) & mask; -} - -static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask) -{ - return in_be32(&base->gpdir) & mask; -} - -static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios) -{ - clrbits_be32(&base->gpdat, gpios); - /* GPDIR register 0 -> input */ - clrbits_be32(&base->gpdir, gpios); -} - -static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios) -{ - clrbits_be32(&base->gpdat, gpios); - /* GPDIR register 1 -> output */ - setbits_be32(&base->gpdir, gpios); -} - -static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios) -{ - setbits_be32(&base->gpdat, gpios); - /* GPDIR register 1 -> output */ - setbits_be32(&base->gpdir, gpios); -} - -static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask) -{ - return in_be32(&base->gpodr) & mask; -} - -static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32 - gpios) -{ - /* GPODR register 1 -> open drain on */ - setbits_be32(&base->gpodr, gpios); -} - -static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base, - u32 gpios) -{ - /* GPODR register 0 -> open drain off (actively driven) */ - clrbits_be32(&base->gpodr, gpios); -} - -static int mpc85xx_gpio_direction_input(struct udevice *dev, uint gpio) -{ - struct mpc85xx_gpio_data *data = dev_get_priv(dev); - - mpc85xx_gpio_set_in(data->base, gpio_mask(gpio)); - return 0; -} - -static int mpc85xx_gpio_set_value(struct udevice *dev, uint gpio, int value) -{ - struct mpc85xx_gpio_data *data = dev_get_priv(dev); - - if (value) { - data->dat_shadow |= gpio_mask(gpio); - mpc85xx_gpio_set_high(data->base, gpio_mask(gpio)); - } else { - data->dat_shadow &= ~gpio_mask(gpio); - mpc85xx_gpio_set_low(data->base, gpio_mask(gpio)); - } - return 0; -} - -static int mpc85xx_gpio_direction_output(struct udevice *dev, uint gpio, - int value) -{ - return mpc85xx_gpio_set_value(dev, gpio, value); -} - -static int mpc85xx_gpio_get_value(struct udevice *dev, uint gpio) -{ - struct mpc85xx_gpio_data *data = dev_get_priv(dev); - - if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) { - /* Output -> use shadowed value */ - return !!(data->dat_shadow & gpio_mask(gpio)); - } - - /* Input -> read value from GPDAT register */ - return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio)); -} - -static int mpc85xx_gpio_get_open_drain(struct udevice *dev, uint gpio) -{ - struct mpc85xx_gpio_data *data = dev_get_priv(dev); - - return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio)); -} - -static int mpc85xx_gpio_set_open_drain(struct udevice *dev, uint gpio, - int value) -{ - struct mpc85xx_gpio_data *data = dev_get_priv(dev); - - if (value) - mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio)); - else - mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio)); - - return 0; -} - -static int mpc85xx_gpio_get_function(struct udevice *dev, uint gpio) -{ - struct mpc85xx_gpio_data *data = dev_get_priv(dev); - int dir; - - dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio)); - return dir ? GPIOF_OUTPUT : GPIOF_INPUT; -} - -#if CONFIG_IS_ENABLED(OF_CONTROL) -static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) -{ - struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev); - fdt_addr_t addr; - fdt_size_t size; - - addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, - dev_of_offset(dev), - "reg", 0, &size, false); - plat->addr = addr; - plat->size = size; - plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "ngpios", 32); - - return 0; -} -#endif - -static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev) -{ - struct mpc85xx_gpio_data *priv = dev_get_priv(dev); - struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev); - unsigned long size = plat->size; - - if (size == 0) - size = 0x100; - - priv->addr = plat->addr; - priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size); - - if (!priv->base) - return -ENOMEM; - - priv->gpio_count = plat->ngpios; - priv->dat_shadow = 0; - - return 0; -} - -static int mpc85xx_gpio_probe(struct udevice *dev) -{ - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - struct mpc85xx_gpio_data *data = dev_get_priv(dev); - char name[32], *str; - - mpc85xx_gpio_platdata_to_priv(dev); - - snprintf(name, sizeof(name), "MPC@%lx_", data->addr); - str = strdup(name); - - if (!str) - return -ENOMEM; - - uc_priv->bank_name = str; - uc_priv->gpio_count = data->gpio_count; - - return 0; -} - -static const struct dm_gpio_ops gpio_mpc85xx_ops = { - .direction_input = mpc85xx_gpio_direction_input, - .direction_output = mpc85xx_gpio_direction_output, - .get_value = mpc85xx_gpio_get_value, - .set_value = mpc85xx_gpio_set_value, - .get_open_drain = mpc85xx_gpio_get_open_drain, - .set_open_drain = mpc85xx_gpio_set_open_drain, - .get_function = mpc85xx_gpio_get_function, -}; - -static const struct udevice_id mpc85xx_gpio_ids[] = { - { .compatible = "fsl,pq3-gpio" }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(gpio_mpc85xx) = { - .name = "gpio_mpc85xx", - .id = UCLASS_GPIO, - .ops = &gpio_mpc85xx_ops, -#if CONFIG_IS_ENABLED(OF_CONTROL) - .ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct mpc85xx_gpio_plat), - .of_match = mpc85xx_gpio_ids, -#endif - .probe = mpc85xx_gpio_probe, - .priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data), -}; diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c new file mode 100644 index 0000000000..0aa72ecd9f --- /dev/null +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2016 + * Mario Six, Guntermann & Drunck GmbH, six@gdsys.de + * + * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is + * + * Copyright 2010 eXMeritus, A Boeing Company + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <mapmem.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; +}; + +struct mpc8xxx_gpio_data { + /* The bank's register base in memory */ + struct ccsr_gpio __iomem *base; + /* The address of the registers; used to identify the bank */ + ulong addr; + /* The GPIO count of the bank */ + uint gpio_count; + /* The GPDAT register cannot be used to determine the value of output + * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value + * for output pins + */ + u32 dat_shadow; + ulong type; +}; + +enum { + MPC8XXX_GPIO_TYPE, + MPC5121_GPIO_TYPE, +}; + +inline u32 gpio_mask(uint gpio) +{ + return (1U << (31 - (gpio))); +} + +static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask) +{ + return in_be32(&base->gpdat) & mask; +} + +static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask) +{ + return in_be32(&base->gpdir) & mask; +} + +static inline void mpc8xxx_gpio_set_in(struct ccsr_gpio *base, u32 gpios) +{ + clrbits_be32(&base->gpdat, gpios); + /* GPDIR register 0 -> input */ + clrbits_be32(&base->gpdir, gpios); +} + +static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios) +{ + clrbits_be32(&base->gpdat, gpios); + /* GPDIR register 1 -> output */ + setbits_be32(&base->gpdir, gpios); +} + +static inline void mpc8xxx_gpio_set_high(struct ccsr_gpio *base, u32 gpios) +{ + setbits_be32(&base->gpdat, gpios); + /* GPDIR register 1 -> output */ + setbits_be32(&base->gpdir, gpios); +} + +static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask) +{ + return in_be32(&base->gpodr) & mask; +} + +static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32 + gpios) +{ + /* GPODR register 1 -> open drain on */ + setbits_be32(&base->gpodr, gpios); +} + +static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base, + u32 gpios) +{ + /* GPODR register 0 -> open drain off (actively driven) */ + clrbits_be32(&base->gpodr, gpios); +} + +static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio) +{ + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + mpc8xxx_gpio_set_in(data->base, gpio_mask(gpio)); + return 0; +} + +static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value) +{ + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + if (value) { + data->dat_shadow |= gpio_mask(gpio); + mpc8xxx_gpio_set_high(data->base, gpio_mask(gpio)); + } else { + data->dat_shadow &= ~gpio_mask(gpio); + mpc8xxx_gpio_set_low(data->base, gpio_mask(gpio)); + } + return 0; +} + +static int mpc8xxx_gpio_direction_output(struct udevice *dev, uint gpio, + int value) +{ + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + /* GPIO 28..31 are input only on MPC5121 */ + if (data->type == MPC5121_GPIO_TYPE && gpio >= 28) + return -EINVAL; + + return mpc8xxx_gpio_set_value(dev, gpio, value); +} + +static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio) +{ + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) { + /* Output -> use shadowed value */ + return !!(data->dat_shadow & gpio_mask(gpio)); + } + + /* Input -> read value from GPDAT register */ + return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio)); +} + +static int mpc8xxx_gpio_get_open_drain(struct udevice *dev, uint gpio) +{ + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + return !!mpc8xxx_gpio_open_drain_val(data->base, gpio_mask(gpio)); +} + +static int mpc8xxx_gpio_set_open_drain(struct udevice *dev, uint gpio, + int value) +{ + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + if (value) + mpc8xxx_gpio_open_drain_on(data->base, gpio_mask(gpio)); + else + mpc8xxx_gpio_open_drain_off(data->base, gpio_mask(gpio)); + + return 0; +} + +static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio) +{ + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + int dir; + + dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio)); + return dir ? GPIOF_OUTPUT : GPIOF_INPUT; +} + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, + dev_of_offset(dev), + "reg", 0, &size, false); + plat->addr = addr; + plat->size = size; + plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "ngpios", 32); + + return 0; +} +#endif + +static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev) +{ + struct mpc8xxx_gpio_data *priv = dev_get_priv(dev); + struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev); + unsigned long size = plat->size; + ulong driver_data = dev_get_driver_data(dev); + + if (size == 0) + size = 0x100; + + priv->addr = plat->addr; + priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size); + + if (!priv->base) + return -ENOMEM; + + priv->gpio_count = plat->ngpios; + priv->dat_shadow = 0; + + priv->type = driver_data; + + return 0; +} + +static int mpc8xxx_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + char name[32], *str; + + mpc8xxx_gpio_platdata_to_priv(dev); + + snprintf(name, sizeof(name), "MPC@%lx_", data->addr); + str = strdup(name); + + if (!str) + return -ENOMEM; + + uc_priv->bank_name = str; + uc_priv->gpio_count = data->gpio_count; + + return 0; +} + +static const struct dm_gpio_ops gpio_mpc8xxx_ops = { + .direction_input = mpc8xxx_gpio_direction_input, + .direction_output = mpc8xxx_gpio_direction_output, + .get_value = mpc8xxx_gpio_get_value, + .set_value = mpc8xxx_gpio_set_value, + .get_open_drain = mpc8xxx_gpio_get_open_drain, + .set_open_drain = mpc8xxx_gpio_set_open_drain, + .get_function = mpc8xxx_gpio_get_function, +}; + +static const struct udevice_id mpc8xxx_gpio_ids[] = { + { .compatible = "fsl,pq3-gpio", .data = MPC8XXX_GPIO_TYPE }, + { .compatible = "fsl,mpc8308-gpio", .data = MPC8XXX_GPIO_TYPE }, + { .compatible = "fsl,mpc8349-gpio", .data = MPC8XXX_GPIO_TYPE }, + { .compatible = "fsl,mpc8572-gpio", .data = MPC8XXX_GPIO_TYPE}, + { .compatible = "fsl,mpc8610-gpio", .data = MPC8XXX_GPIO_TYPE}, + { .compatible = "fsl,mpc5121-gpio", .data = MPC5121_GPIO_TYPE, }, + { .compatible = "fsl,qoriq-gpio", .data = MPC8XXX_GPIO_TYPE }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(gpio_mpc8xxx) = { + .name = "gpio_mpc8xxx", + .id = UCLASS_GPIO, + .ops = &gpio_mpc8xxx_ops, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat), + .of_match = mpc8xxx_gpio_ids, +#endif + .probe = mpc8xxx_gpio_probe, + .priv_auto_alloc_size = sizeof(struct mpc8xxx_gpio_data), +};

Fix some style violations in the board_f file.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

common/board_f.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/common/board_f.c b/common/board_f.c index ffa84e3566..b258a1a73c 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -50,7 +50,7 @@ #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR #undef XTRN_DECLARE_GLOBAL_DATA_PTR #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ -DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); +DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR); #else DECLARE_GLOBAL_DATA_PTR; #endif @@ -137,7 +137,7 @@ static int display_text_info(void) #endif

debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", - text_base, bss_start, bss_end); + text_base, bss_start, bss_end); #endif

return 0; @@ -311,7 +311,7 @@ static int reserve_logbuffer(void) /* reserve kernel log buffer */ gd->relocaddr -= LOGBUFF_RESERVE; debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, - gd->relocaddr); + gd->relocaddr); #endif

return 0; @@ -436,7 +436,7 @@ static int reserve_malloc(void) { gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; debug("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); + TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); return 0; }

@@ -466,7 +466,7 @@ static int reserve_global_data(void) gd->start_addr_sp -= sizeof(gd_t); gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); debug("Reserving %zu Bytes for Global Data at: %08lx\n", - sizeof(gd_t), gd->start_addr_sp); + sizeof(gd_t), gd->start_addr_sp); return 0; }

Fix some style violations in the board_r file.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

common/board_r.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/common/board_r.c b/common/board_r.c index ecca1edb04..199cadbed1 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -161,9 +161,9 @@ static int initr_reloc_global_data(void) #endif #ifdef CONFIG_OF_EMBED /* - * The fdt_blob needs to be moved to new relocation address - * incase of FDT blob is embedded with in image - */ + * The fdt_blob needs to be moved to new relocation address + * incase of FDT blob is embedded with in image + */ gd->fdt_blob += gd->reloc_off; #endif #ifdef CONFIG_EFI_LOADER @@ -368,14 +368,16 @@ static int initr_flash(void) print_size(flash_size, ""); #ifdef CONFIG_SYS_FLASH_CHECKSUM /* - * Compute and print flash CRC if flashchecksum is set to 'y' - * - * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX - */ + * Compute and print flash CRC if flashchecksum is set to 'y' + * + * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX + */ if (getenv_yesno("flashchecksum") == 1) { + const uchar flash_base = CONFIG_SYS_FLASH_BASE; + printf(" CRC: %08X", crc32(0, - (const unsigned char *) CONFIG_SYS_FLASH_BASE, - flash_size)); + flash_base, + flash_size)); } #endif /* CONFIG_SYS_FLASH_CHECKSUM */ putc('\n'); @@ -392,7 +394,6 @@ static int initr_flash(void) update_flash_size(flash_size); #endif

- #if defined(CONFIG_OXC) || defined(CONFIG_RMU) /* flash mapped at end of memory map */ bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size; @@ -657,7 +658,7 @@ int initr_mem(void) /* Also take the logbuffer into account (pram is in kB) */ pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; # endif - sprintf(memsz, "%ldk", (long int) ((gd->ram_size / 1024) - pram)); + sprintf(memsz, "%ldk", (long int)((gd->ram_size / 1024) - pram)); setenv("mem", memsz);

return 0; @@ -710,7 +711,7 @@ static init_fnc_t init_sequence_r[] = { initr_caches, /* Note: For Freescale LS2 SoCs, new MMU table is created in DDR. * A temporary mapping of IFC high region is since removed, - * so environmental variables in NOR flash is not availble + * so environmental variables in NOR flash is not available * until board_init() is called below to remap IFC to high * region. */ @@ -775,7 +776,7 @@ static init_fnc_t init_sequence_r[] = { #if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) /* * Do early PCI configuration _before_ the flash gets initialised, - * because PCU ressources are crucial for flash access on some boards. + * because PCU resources are crucial for flash access on some boards. */ initr_pci, #endif

Commit 2a79275 ("dm: Add callback to modify the device tree") implemented a board-specific callback that can modify U-Boot's device tree before relocation to accomodate a range of hardware variations of certain boards.

However, this approach only turns out to be useful when the copy of the device tree before relocation is actually writeable. If e.g. a device boots out of a NOR flash, this scheme does not work, since the modification of the flash's contents is not possible, and the unmodified device tree is relocated and used by U-Boot.

To circumvent this problem, we split the modification process into two phases.

In phase one we only collect information about the board by querying the hardware (reading GPIO values, probing I2C chips, etc.), and store the obtained information in a special, board-specific structure that is part of the global data structure. This phase runs prior to relocation, and utilizes the pre-relocation DM to query hardware information.

In phase two, we read the information back from the structure, and do the actual manipulation of the device tree. This phase occurs *after* the relocation of the U-Boot image, but before the driver model is initialized from the device tree. Since the device tree lives in RAM alongside the U-Boot image after relocation, the tree is definitely writeable at this point.

Each phase is implemented by a board-specific callback function: phase one by board_fix_fdt_get_info, which takes no arguments, and phase two by board_fix_fdt_change, which takes the writeable device tree blob as its sole argument. Since the structure where the gathered hardware information is stored is necessarily board-dependent, we create a include file where the boards utilizing the functionality can define their individually needed structures.

This commit also adapts the controlcenterdc board's fixup function to the new scheme.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

board/gdsys/a38x/controlcenterdc.c | 20 +++++- common/board_f.c | 6 +- common/board_r.c | 10 +++ doc/driver-model/fdt-fixup.txt | 129 ++++++++++++++++++++++++------------- include/asm-generic/global_data.h | 7 ++ include/common.h | 3 +- include/fdt_fixup.h | 5 ++ 7 files changed, 130 insertions(+), 50 deletions(-) create mode 100644 include/fdt_fixup.h

diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index 32168d3576..05e18bac4c 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -236,7 +236,7 @@ int board_late_init(void) return 0; }

-int board_fix_fdt(void *rw_fdt_blob) +int board_fix_fdt_get_info(void) { struct udevice *bus = NULL; uint k; @@ -254,7 +254,23 @@ int board_fix_fdt(void *rw_fdt_blob) snprintf(name, 64, "/soc/internal-regs/i2c@11000/pca9698@%02x", k);

- if (!dm_i2c_simple_probe(bus, k)) + gd->board_fixup_data.chip_exists[k - 0x21] = dm_i2c_simple_probe(bus, k); + } + + return 0; +} + +int board_fix_fdt_change(void *rw_fdt_blob) +{ + struct of_board_fixup_data data = gd->board_fixup_data; + uint k; + char name[64]; + + for (k = 0x21; k <= 0x26; k++) { + snprintf(name, 64, + "/soc/internal-regs/i2c@11000/pca9698@%02x", k); + + if (!data.chip_exists[k - 0x21]) fdt_disable_by_ofname(rw_fdt_blob, name); }

diff --git a/common/board_f.c b/common/board_f.c index b258a1a73c..b835bd22bc 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -660,9 +660,9 @@ static int setup_reloc(void) }

#ifdef CONFIG_OF_BOARD_FIXUP -static int fix_fdt(void) +static int fix_fdt_get_info(void) { - return board_fix_fdt((void *)gd->fdt_blob); + return board_fix_fdt_get_info(); } #endif

@@ -887,7 +887,7 @@ static const init_fnc_t init_sequence_f[] = { #endif display_new_sp, #ifdef CONFIG_OF_BOARD_FIXUP - fix_fdt, + fix_fdt_get_info, #endif INIT_FUNC_WATCHDOG_RESET reloc_fdt, diff --git a/common/board_r.c b/common/board_r.c index 199cadbed1..25f27f0843 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -694,6 +694,13 @@ static int run_main_loop(void) return 0; }

+#ifdef CONFIG_OF_BOARD_FIXUP +static int fix_fdt_change(void) +{ + return board_fix_fdt_change((void *)gd->fdt_blob); +} +#endif + /* * Over time we hope to remove these functions with code fragments and * stub funtcions, and instead call the relevant function directly. @@ -731,6 +738,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_OF_LIVE initr_of_live, #endif +#ifdef CONFIG_OF_BOARD_FIXUP + fix_fdt_change, +#endif #ifdef CONFIG_DM initr_dm, #endif diff --git a/doc/driver-model/fdt-fixup.txt b/doc/driver-model/fdt-fixup.txt index 70344bd2c3..9a9467edd8 100644 --- a/doc/driver-model/fdt-fixup.txt +++ b/doc/driver-model/fdt-fixup.txt @@ -52,81 +52,122 @@ tree (at least after the relocation) would greatly simplify the solution of this problem, it is a non-negligible task to implement it, an a interim solution is needed to address the problem at least in the medium-term.

-Hence, we propose a solution to this problem by offering a board-specific -call-back function, which is passed a writeable pointer to the device tree. -This function is called before the device tree is relocated, and specifically -before the main U-Boot's driver model is instantiated, hence the main U-Boot -"sees" all modifications to the device tree made in this function. Furthermore, -we have the pre-relocation driver model at our disposal at this stage, which -means that we can query the hardware for the existence and variety of the -components easily. +Hence, we propose a solution to this problem by offering a set of two board-specific +call-back functions: + + * One function which is called prior to relocation that gathers information + about the device using the pre-relocation DM instance and stores the + collected information in a special data structure within the global data + section; using the pre-relocation driver model means that we can query the + hardware for the existence and variety of the components easily. + * A second function which is called just after relocation, but before the + post-relocation DM is instantiated; it is passed a writeable pointer to the + device tree, so that it can exectute the actual modifications of the device + tree based upon the information gathered by the first function. + +Notice that since the "modification function" is called prior to the DM +instantiation, the main U-Boot "sees" all modifications to the device tree made +by the function.

2. Implementation -----------------

To take advantage of the pre-relocation device tree manipulation mechanism, -boards have to implement the function board_fix_fdt, which has the following -signature: +boards have to implement the functions board_fix_fdt_get_info and +board_fix_fdt_change, which have the following signatures:

-int board_fix_fdt (void *rw_fdt_blob) +int board_fix_fdt_get_info (void) +int board_fix_fdt_change (void *rw_fdt_blob)

-The passed-in void pointer is a writeable pointer to the device tree, which can -be used to manipulate the device tree using e.g. functions from -include/fdt_support.h. The return value should either be 0 in case of -successful execution of the device tree manipulation or something else for a +The void pointer passed to board_fix_fdt_change is a writeable pointer to the +device tree, which can be used to manipulate the device tree using e.g. +functions from include/fdt_support.h. The return value for both functions +should either be 0 in case of successful execution of the device information +gathering and device tree manipulation respectively or something else for a failure. Note that returning a non-null value from the function will unrecoverably halt the boot process, as with any function from init_sequence_f -(in common/board_f.c). +(in common/board_f.c) or init_sequence_r (in common/board_r.c). .

-Furthermore, the Kconfig option OF_BOARD_FIXUP has to be set for the function +Furthermore, the Kconfig option OF_BOARD_FIXUP has to be set for the functions to be called:

Device Tree Control -> [*] Board-specific manipulation of Device Tree

-+----------------------------------------------------------+ -| WARNING: The actual manipulation of the device tree has | -| to be the _last_ set of operations in board_fix_fdt! | -| Since the pre-relocation driver model does not adapt to | -| changes made to the device tree either, its references | -| into the device tree will be invalid after manipulating | -| it, and unpredictable behavior might occur when | -| functions that rely on them are executed! | -+----------------------------------------------------------+ +The transfer of the collected device information is accomplished via the +board_fixup_data sub-structure in the global data structure. The layout of this +structure is board-defined, and every user of the mechanism should define a +suitable set of fields in include/fdt_fixup.h surrounded by preprocessor #ifdef +instructions. For example, a board with the target Kconfig variable +CONFIG_TARGET_SAMPLEBOARD that needs to check the existence of two I2C devices +and has to determine a board variant identified by an int, might add the +following member declarations for itself:

-Hence, the recommended layout of the board_fixup_fdt call-back function is the -following: +#ifdef CONFIG_TARGET_SAMPLEBOARD + bool chip1_present; + bool chip2_present; + int variant; +#endif

-int board_fix_fdt(void *rw_fdt_blob) +A schemetic implementation of the two functions might then look like the following: + +int board_fix_fdt_get_info(void) { /* Collect information about device's hardware and store them in e.g. - local variables */ + local variables, e.g. chip1_present, chip2_present, variant. Return a + non-zero value if the information gathering failed. */ + + /* Store the collected information in the sub-structure, so they will be + available to board_fix_fdt_change: */

- /* Do device tree manipulation using the values previously collected */ + gd->board_fixup_data.chip1_present = chip1_present; + gd->board_fixup_data.chip2_present = chip2_present; + gd->board_fixup_data.variant = variant;

- /* Return 0 on successful manipulation and non-zero otherwise */ + return 0; }

-If this convention is kept, both an "additive" approach, meaning that nodes for -detected components are added to the device tree, as well as a "subtractive" -approach, meaning that nodes for absent components are removed from the tree, -as well as a combination of both approaches should work. +int board_fix_fdt_change(void *rw_fdt_blob) +{ + /* Read back the information from the sub-structure: */ + + bool chip1_present = gd->board_fixup_data.chip1_present; + bool chip2_present = gd->board_fixup_data.chip2_present; + int variant = gd->board_fixup_data.variant; + + /* Employ device tree manipulation based on the information: */ + + if (chip1_present) { + ... + } + + if (chip2_present) { + ... + } + + switch(variant) + ... + } +} + +This convention of split functions also enables that both an "additive" +approach for DT manipulation, meaning that nodes for detected components are +added to the device tree, as well as a "subtractive" approach, meaning that +nodes for absent components are removed from the tree, as well as a combination +of both approaches should work.

3. Example ----------

-The controlcenterdc board (board/gdsys/a38x/controlcenterdc.c) features a -board_fix_fdt function, in which six GPIO expanders (which might be present or +The controlcenterdc board (board/gdsys/a38x/controlcenterdc.c) features +board_fix_fdt functions, in which six GPIO expanders (which might be present or not, since they are on daughter boards) on a I2C bus are queried for, and subsequently deactivated in the device tree if they are not present.

-Note that the dm_i2c_simple_probe function does not use the device tree, hence -it is safe to call it after the tree has already been manipulated. - 4. Work to be done ------------------

-* The application of device tree overlay should be possible in board_fixup_fdt, - but has not been tested at this stage. +* The application of device tree overlay should be possible in + board_fixup_fdt_change, but has not been tested at this stage.

-2017-01-06, Mario Six mario.six@gdsys.cc +2017-07-04, Mario Six mario.six@gdsys.cc diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index fb90be9d3e..731a4163a9 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -24,6 +24,10 @@ #include <membuff.h> #include <linux/list.h>

+#ifdef CONFIG_OF_BOARD_FIXUP +#include <fdt_fixup.h> +#endif + typedef struct global_data { bd_t *bd; unsigned long flags; @@ -75,6 +79,9 @@ typedef struct global_data { #ifdef CONFIG_OF_LIVE struct device_node *of_root; #endif +#ifdef CONFIG_OF_BOARD_FIXUP + struct of_board_fixup_data board_fixup_data; +#endif struct jt_funcs *jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ #ifdef CONFIG_TRACE diff --git a/include/common.h b/include/common.h index 751665f8a4..80a004d4b4 100644 --- a/include/common.h +++ b/include/common.h @@ -416,7 +416,8 @@ extern ssize_t spi_write (uchar *, int, uchar *, int);

/* $(BOARD)/$(BOARD).c */ int board_early_init_f (void); -int board_fix_fdt (void *rw_fdt_blob); /* manipulate the U-Boot fdt before its relocation */ +int board_fix_fdt_get_info (void); /* manipulate the U-Boot fdt before its relocation */ +int board_fix_fdt_change (void *rw_fdt_blob); /* manipulate the U-Boot fdt before its relocation */ int board_late_init (void); int board_postclk_init (void); /* after clocks/timebase, before env/serial */ int board_early_init_r (void); diff --git a/include/fdt_fixup.h b/include/fdt_fixup.h new file mode 100644 index 0000000000..9390f0a633 --- /dev/null +++ b/include/fdt_fixup.h @@ -0,0 +1,5 @@ +struct of_board_fixup_data { +#ifdef CONFIG_TARGET_CONTROLCENTERDC + bool chip_exists[6]; +#endif +};

Future gdsys boards will switch from the legacy drivers in board/gdsys/common to DM-based drivers.

Define a Kconfig option that disables the legacy drivers.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

board/gdsys/common/adv7611.c | 4 ++++ board/gdsys/common/ch7301.c | 4 ++++ board/gdsys/common/dp501.c | 4 ++++ board/gdsys/common/fanctrl.c | 4 ++++ board/gdsys/common/fpga.c | 4 ++++ board/gdsys/common/ihs_mdio.c | 4 ++++ board/gdsys/common/ioep-fpga.c | 4 ++++ board/gdsys/common/mclink.c | 4 ++++ board/gdsys/common/osd.c | 4 ++++ board/gdsys/mpc8308/Kconfig | 8 ++++++++ board/gdsys/mpc8308/mpc8308.c | 2 ++ board/gdsys/p1022/Kconfig | 6 ++++++ include/gdsys_fpga.h | 2 ++ 13 files changed, 54 insertions(+)

diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c index b728274cce..4ed9b09cd2 100644 --- a/board/gdsys/common/adv7611.c +++ b/board/gdsys/common/adv7611.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <i2c.h>

@@ -175,3 +177,5 @@ out:

return res; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c index c054e55cf7..b38b485b13 100644 --- a/board/gdsys/common/ch7301.c +++ b/board/gdsys/common/ch7301.c @@ -7,6 +7,8 @@

/* Chrontel CH7301C DVI Transmitter */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <asm/io.h> #include <errno.h> @@ -62,3 +64,5 @@ int ch7301_probe(unsigned screen, bool power)

return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 54e7f63f69..232ea13e68 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -7,6 +7,8 @@

/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <asm/io.h> #include <errno.h> @@ -156,3 +158,5 @@ int dp501_probe(unsigned screen, bool power)

return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c index 44569bb1ab..20bb187cdd 100644 --- a/board/gdsys/common/fanctrl.c +++ b/board/gdsys/common/fanctrl.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <i2c.h>

@@ -30,3 +32,5 @@ void init_fan_controller(u8 addr) val = i2c_reg_read(addr, FAN_CONFIG) | 0x04; i2c_reg_write(addr, FAN_CONFIG, val); } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/fpga.c b/board/gdsys/common/fpga.c index e10c105feb..cfb6a9d583 100644 --- a/board/gdsys/common/fpga.c +++ b/board/gdsys/common/fpga.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <gdsys_fpga.h>

@@ -23,3 +25,5 @@ int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)

return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c index 262ead5516..d67ec7d38a 100644 --- a/board/gdsys/common/ihs_mdio.c +++ b/board/gdsys/common/ihs_mdio.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h>

#include <gdsys_fpga.h> @@ -86,3 +88,5 @@ int ihs_mdio_init(struct ihs_mdio_info *info)

return mdio_register(bus); } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c index f72a01e5b2..a666b93445 100644 --- a/board/gdsys/common/ioep-fpga.c +++ b/board/gdsys/common/ioep-fpga.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h>

#include <gdsys_fpga.h> @@ -235,3 +237,5 @@ void ioep_fpga_print_info(unsigned int fpga)

printf(", %d video channel(s)\n", feature_video_channels); } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c index 9f230c9a97..6b1faf4696 100644 --- a/board/gdsys/common/mclink.c +++ b/board/gdsys/common/mclink.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <asm/io.h> #include <errno.h> @@ -135,3 +137,5 @@ int mclink_receive(u8 slave, u16 addr, u16 *data)

return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index add9574369..60e7f460a7 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <i2c.h> #include <malloc.h> @@ -498,3 +500,5 @@ U_BOOT_CMD( "size_x(max. " __stringify(MAX_X_CHARS) ") size_y(max. " __stringify(MAX_Y_CHARS) ")\n" ); + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ \ No newline at end of file diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index c0247214a9..e913e94b3a 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -1,3 +1,5 @@ +config GDSYS_LEGACY_DRIVERS + bool

config SYS_FPGA0_BASE hex @@ -32,6 +34,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "hrcon"

+config GDSYS_LEGACY_DRIVERS + default y + endif

if TARGET_STRIDER @@ -45,6 +50,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "strider"

+config GDSYS_LEGACY_DRIVERS + default y + endif

config CMD_IOLOOP diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 8d6a49f86a..3b57494493 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -25,6 +25,7 @@

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS /* as gpio output status cannot be read back, we have to buffer it locally */ u32 gpio0_out;

@@ -117,3 +118,4 @@ int board_early_init_r(void)

return 0; } +#endif diff --git a/board/gdsys/p1022/Kconfig b/board/gdsys/p1022/Kconfig index 8514d086b9..8fef636136 100644 --- a/board/gdsys/p1022/Kconfig +++ b/board/gdsys/p1022/Kconfig @@ -1,3 +1,6 @@ +config GDSYS_LEGACY_DRIVERS + bool + if TARGET_CONTROLCENTERD

config SYS_BOARD @@ -9,4 +12,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "controlcenterd"

+config GDSYS_LEGACY_DRIVERS + default y + endif diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 34d6eeb253..19a6e6ca3f 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -8,6 +8,7 @@ #ifndef __GDSYS_FPGA_H #define __GDSYS_FPGA_H

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS int init_func_fpga(void);

enum { @@ -34,6 +35,7 @@ extern struct ihs_fpga *fpga_ptr[]; &fpga_ptr[ix]->fld, \ offsetof(struct ihs_fpga, fld), \ val) +#endif

struct ihs_gpio { u16 read;

Make the ihs_i2c driver DM-compatible; for legacy boards, the old functions are retained within #ifdefs.

No board uses the new DM driver yet; this patch only lays the foundation for future support.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

drivers/i2c/Kconfig | 6 ++ drivers/i2c/ihs_i2c.c | 197 ++++++++++++++++++++++++++++++++++++++++++- scripts/config_whitelist.txt | 1 - 3 files changed, 200 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 8ac1cc6a15..12901f544e 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -201,6 +201,12 @@ config TEGRA186_BPMP_I2C by the BPMP, and can only be accessed by the main CPU via IPC requests to the BPMP. This driver covers the latter case.

+config SYS_I2C_IHS + bool "gdsys IHS I2C driver" + depends on DM_I2C + help + Support for gdsys IHS I2C driver on FPGA bus. + source "drivers/i2c/muxes/Kconfig"

endmenu diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index e066ad53db..6aeda52cfa 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -3,18 +3,38 @@ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de * * SPDX-License-Identifier: GPL-2.0+ - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. */

#include <common.h> #include <i2c.h> +#ifdef CONFIG_DM_I2C +#include <dm.h> +#include <gdsys_soc.h> +#include <ihs_fpga.h> +#else #include <gdsys_fpga.h> +#endif

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_DM_I2C +struct ihs_i2c_priv { + uint speed; + phys_addr_t addr; +}; + +enum { + REG_INTERRUPT_STATUS = 0x00, + REG_INTERRUPT_ENABLE_CONTROL = 0x02, + REG_WRITE_MAILBOX_EXT = 0x04, + REG_WRITE_MAILBOX = 0x06, + REG_READ_MAILBOX_EXT = 0x08, + REG_READ_MAILBOX = 0x0A, +}; + +#else /* !CONFIG_DM_I2C */ #ifdef CONFIG_SYS_I2C_IHS_DUAL + #define I2C_SET_REG(fld, val) \ do { \ if (I2C_ADAP_HWNR & 0x10) \ @@ -39,6 +59,7 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_GET_REG(fld, val) \ FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val) #endif +#endif /* CONFIG_DM_I2C */

enum { I2CINT_ERROR_EV = BIT(13), @@ -61,33 +82,67 @@ enum { I2COP_READ = 1, };

+#ifdef CONFIG_DM_I2C +static int wait_for_int(struct udevice *dev, int read) +#else static int wait_for_int(bool read) +#endif { u16 val; uint ctr = 0; +#ifdef CONFIG_DM_I2C + struct ihs_i2c_priv *priv = dev_get_priv(dev); + struct gdsys_soc_child_platdata *pplat = dev_get_parent_platdata(dev); +#endif

+#ifdef CONFIG_DM_I2C + val = fpga_in_le16(pplat->fpga, + priv->addr + REG_INTERRUPT_STATUS); +#else I2C_GET_REG(interrupt_status, &val); +#endif /* Wait until error or receive/transmit interrupt was raised */ while (!(val & (I2CINT_ERROR_EV | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { udelay(10); if (ctr++ > 5000) return 1; +#ifdef CONFIG_DM_I2C + val = fpga_in_le16(pplat->fpga, + priv->addr + REG_INTERRUPT_STATUS); +#else I2C_GET_REG(interrupt_status, &val); +#endif }

return (val & I2CINT_ERROR_EV) ? 1 : 0; }

+#ifdef CONFIG_DM_I2C +static int ihs_i2c_transfer(struct udevice *dev, uchar chip, + uchar *buffer, int len, int read, bool is_last) +#else static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, bool is_last) +#endif { u16 val; +#ifdef CONFIG_DM_I2C + struct ihs_i2c_priv *priv = dev_get_priv(dev); + struct gdsys_soc_child_platdata *pplat = dev_get_parent_platdata(dev); +#endif

/* Clear interrupt status */ +#ifdef CONFIG_DM_I2C + fpga_out_le16(pplat->fpga, priv->addr + REG_INTERRUPT_STATUS, + I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV); + val = fpga_in_le16(pplat->fpga, + priv->addr + REG_INTERRUPT_STATUS); +#else I2C_SET_REG(interrupt_status, I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV); I2C_GET_REG(interrupt_status, &val); +#endif

/* If we want to write and have data, write the bytes to the mailbox */ if (!read && len) { @@ -95,22 +150,45 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,

if (len > 1) val |= buffer[1] << 8; +#ifdef CONFIG_DM_I2C + fpga_out_le16(pplat->fpga, + priv->addr + REG_WRITE_MAILBOX_EXT, val); +#else I2C_SET_REG(write_mailbox_ext, val); +#endif }

+#ifdef CONFIG_DM_I2C + fpga_out_le16(pplat->fpga, priv->addr + REG_WRITE_MAILBOX, + I2CMB_NATIVE + | (read ? I2CMB_READ : I2CMB_WRITE) + | (chip << 1) + | ((len > 1) ? I2CMB_2BYTE : I2CMB_1BYTE) + | (!is_last ? I2CMB_HOLD_BUS : I2CMB_DONT_HOLD_BUS)); +#else I2C_SET_REG(write_mailbox, I2CMB_NATIVE | (read ? 0 : I2CMB_WRITE) | (chip << 1) | ((len > 1) ? I2CMB_2BYTE : 0) | (is_last ? 0 : I2CMB_HOLD_BUS)); +#endif

+#ifdef CONFIG_DM_I2C + if (wait_for_int(dev, read)) +#else if (wait_for_int(read)) +#endif return 1;

/* If we want to read, get the bytes from the mailbox */ if (read) { +#ifdef CONFIG_DM_I2C + val = fpga_in_le16(pplat->fpga, + priv->addr + REG_READ_MAILBOX_EXT); +#else I2C_GET_REG(read_mailbox_ext, &val); +#endif buffer[0] = val & 0xff; if (len > 1) buffer[1] = val >> 8; @@ -119,15 +197,25 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, return 0; }

+#ifdef CONFIG_DM_I2C +static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen, bool hold_bus) +#else static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus) +#endif { while (alen) { int transfer = min(alen, 2); bool is_last = alen <= transfer;

+#ifdef CONFIG_DM_I2C + if (ihs_i2c_transfer(dev, chip, addr, transfer, I2COP_WRITE, + hold_bus ? false : is_last)) + return 1; +#else if (ihs_i2c_transfer(chip, addr, transfer, I2COP_WRITE, hold_bus ? false : is_last)) return 1; +#endif

alen -= transfer; } @@ -135,20 +223,36 @@ static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus) return 0; }

+#ifdef CONFIG_DM_I2C +static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr, + int alen, uchar *buffer, int len, int read) +#else static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, int alen, uchar *buffer, int len, int read) +#endif { /* Don't hold the bus if length of data to send/receive is zero */ +#ifdef CONFIG_DM_I2C + if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len)) + return 1; +#else if (len <= 0 || ihs_i2c_address(chip, addr, alen, len)) return 1; +#endif

while (len) { int transfer = min(len, 2); bool is_last = len <= transfer;

+#ifdef CONFIG_DM_I2C + if (ihs_i2c_transfer(dev, chip, buffer, transfer, read, + is_last)) + return 2; +#else if (ihs_i2c_transfer(chip, buffer, transfer, read, is_last)) return 2; +#endif

buffer += transfer; len -= transfer; @@ -157,6 +261,92 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, return 0; }

+#ifdef CONFIG_DM_I2C + +int ihs_i2c_probe(struct udevice *bus) +{ + struct ihs_i2c_priv *priv = dev_get_priv(bus); + int addr; + + addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "reg", -1); + + priv->addr = addr; + + return 0; +} + +static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed) +{ + struct ihs_i2c_priv *priv = dev_get_priv(bus); + + if (speed != priv->speed && priv->speed != 0) + return 1; + + priv->speed = speed; + + return 0; +} + +static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct i2c_msg *dmsg, *omsg, dummy; + + memset(&dummy, 0, sizeof(struct i2c_msg)); + + /* We expect either two messages (one with an offset and one with the + * actucal data) or one message (just data) + */ + if (nmsgs > 2 || nmsgs == 0) { + debug("%s: Only one or two messages are supported.", __func__); + return -1; + } + + omsg = nmsgs == 1 ? &dummy : msg; + dmsg = nmsgs == 1 ? msg : msg + 1; + + if (dmsg->flags & I2C_M_RD) + return ihs_i2c_access(bus, dmsg->addr, omsg->buf, + omsg->len, dmsg->buf, dmsg->len, + I2COP_READ); + else + return ihs_i2c_access(bus, dmsg->addr, omsg->buf, + omsg->len, dmsg->buf, dmsg->len, + I2COP_WRITE); +} + +static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr, + u32 chip_flags) +{ + uchar buffer[2]; + + if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true)) + return 1; + + return 0; +} + +static const struct dm_i2c_ops ihs_i2c_ops = { + .xfer = ihs_i2c_xfer, + .probe_chip = ihs_i2c_probe_chip, + .set_bus_speed = ihs_i2c_set_bus_speed, +}; + +static const struct udevice_id ihs_i2c_ids[] = { + { .compatible = "gdsys,ihs_i2cmaster", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(i2c_ihs) = { + .name = "i2c_ihs", + .id = UCLASS_I2C, + .of_match = ihs_i2c_ids, + .probe = ihs_i2c_probe, + .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv), + .ops = &ihs_i2c_ops, +}; + +#else /* CONFIG_DM_I2C */ + static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { #ifdef CONFIG_SYS_I2C_INIT_BOARD @@ -274,3 +464,4 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe, CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19) #endif #endif +#endif /* CONFIG_DM_I2C */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 64a4b1190e..e0cb57e972 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3500,7 +3500,6 @@ CONFIG_SYS_I2C_G762_ADDR CONFIG_SYS_I2C_GENERIC_MAC CONFIG_SYS_I2C_IDT6V49205B CONFIG_SYS_I2C_IFDR_DIV -CONFIG_SYS_I2C_IHS CONFIG_SYS_I2C_IHS_CH0 CONFIG_SYS_I2C_IHS_CH0_1 CONFIG_SYS_I2C_IHS_CH1

This patch adds DM drivers for IHS FPGAs and their associated busses, as well as uclasses for both.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

drivers/misc/Kconfig | 6 + drivers/misc/Makefile | 1 + drivers/misc/gdsys_soc.c | 51 +++ drivers/misc/ihs_fpga.c | 871 +++++++++++++++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 2 + include/gdsys_soc.h | 29 ++ include/ihs_fpga.h | 111 ++++++ 7 files changed, 1071 insertions(+) create mode 100644 drivers/misc/gdsys_soc.c create mode 100644 drivers/misc/ihs_fpga.c create mode 100644 include/gdsys_soc.h create mode 100644 include/ihs_fpga.h

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index d1ddbbe157..8b59a444ce 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -196,4 +196,10 @@ config I2C_EEPROM depends on MISC help Enable a generic driver for EEPROMs attached via I2C. + +config IHS_FPGA + bool "Enable IHS FPGA driver" + depends on MISC + help + Support for IHS FPGA. endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 10265c8fb4..d2e46fc7d6 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -52,3 +52,4 @@ obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o obj-$(CONFIG_QFW) += qfw.o obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o +obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o gdsys_soc.o diff --git a/drivers/misc/gdsys_soc.c b/drivers/misc/gdsys_soc.c new file mode 100644 index 0000000000..34b06d44bd --- /dev/null +++ b/drivers/misc/gdsys_soc.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <gdsys_soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int gdsys_soc_child_post_bind(struct udevice *dev) +{ + struct gdsys_soc_child_platdata *pplat = dev_get_parent_platdata(dev); + struct udevice *fpga; + + if (uclass_get_device_by_phandle(UCLASS_IHS_FPGA, dev->parent, "fpga", + &fpga)) { + printf("%s: Could not find 'fpga' phandle.\n", + dev->parent->name); + return 1; + } + + pplat->fpga = fpga; + + return 0; +} + +UCLASS_DRIVER(gdsys_soc) = { + .id = UCLASS_GDSYS_SOC, + .name = "gdsys_soc", + .post_probe = dm_scan_fdt_dev, + .child_post_bind = gdsys_soc_child_post_bind, + .per_child_platdata_auto_alloc_size = + sizeof(struct gdsys_soc_child_platdata), +}; + +static const struct udevice_id gdsys_soc_ids[] = { + { .compatible = "gdsys,soc" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(gdsys_soc_bus) = { + .name = "gdsys_soc_bus", + .id = UCLASS_GDSYS_SOC, + .of_match = gdsys_soc_ids, +}; diff --git a/drivers/misc/ihs_fpga.c b/drivers/misc/ihs_fpga.c new file mode 100644 index 0000000000..a2b5d3f58c --- /dev/null +++ b/drivers/misc/ihs_fpga.c @@ -0,0 +1,871 @@ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * based on the ioep-fpga driver, which is + * + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> +#include <dm/lists.h> +#include <ihs_fpga.h> +#include <misc.h> +#include <mapmem.h> +#include <asm/gpio.h> +#include <linux/bitops.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct reg_spec { + uint addr; + uint shift; + ulong mask; +}; + +struct ihs_fpga_priv { + u8 *regs; + fdt_addr_t addr; + struct gpio_desc reset_gpio; + struct gpio_desc done_gpio; + struct gpio_desc startupfin_gpios[2]; + int regmap_node; + bool has_osd; +}; + +const u16 reflection_testpattern = 0xdede; + +enum pcb_video_type { + PCB_DVI_SL, + PCB_DP_165MPIX, + PCB_DP_300MPIX, + PCB_HDMI, + PCB_DP_1_2, + PCB_HDMI_2_0, +}; + +enum pcb_transmission_type { + PCB_CAT_1G, + PCB_FIBER_3G, + PCB_CAT_10G, + PCB_FIBER_10G, +}; + +enum carrier_speed { + CARRIER_SPEED_1G, + CARRIER_SPEED_3G, + CARRIER_SPEED_2_5G = CARRIER_SPEED_3G, + CARRIER_SPEED_10G, +}; + +enum ram_config { + RAM_DDR2_32BIT_295MBPS, + RAM_DDR3_32BIT_590MBPS, + RAM_DDR3_48BIT_590MBPS, + RAM_DDR3_64BIT_1800MBPS, + RAM_DDR3_48BIT_1800MBPS, +}; + +enum sysclock { + SYSCLK_147456, +}; + +struct fpga_versions { + bool video_channel; + bool con_side; + enum pcb_video_type pcb_video_type; + enum pcb_transmission_type pcb_transmission_type; + unsigned int hw_version; +}; + +struct fpga_features { + u8 video_channels; + u8 carriers; + enum carrier_speed carrier_speed; + enum ram_config ram_config; + enum sysclock sysclock; + + bool pcm_tx; + bool pcm_rx; + bool spdif_tx; + bool spdif_rx; + bool usb2; + bool rs232; + bool compression_type1; + bool compression_type2; + bool compression_type3; + bool interlace; + bool osd; + bool compression_pipes; +}; + +int fpga_set_reg(struct udevice *dev, const char *compat, + uint value) +{ + struct ihs_fpga_ops *ops = ihs_fpga_get_ops(dev); + + return ops->set_reg(dev, compat, value); +} + +int fpga_get_reg(struct udevice *dev, const char *compat, + uint *value) +{ + struct ihs_fpga_ops *ops = ihs_fpga_get_ops(dev); + + return ops->get_reg(dev, compat, value); +} + +u16 fpga_in_le16(struct udevice *dev, phys_addr_t addr) +{ + struct ihs_fpga_ops *ops = ihs_fpga_get_ops(dev); + + return ops->in_le16(dev, addr); +} + +void fpga_out_le16(struct udevice *dev, phys_addr_t addr, u16 value) +{ + struct ihs_fpga_ops *ops = ihs_fpga_get_ops(dev); + + return ops->out_le16(dev, addr, value); +} + +#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM + +static int get_versions(struct udevice *dev, struct fpga_versions *versions) +{ + enum { + VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12), + VERSIONS_FPGA_CON_SIDE = BIT(13), + VERSIONS_FPGA_SC = BIT(14), + VERSIONS_PCB_CON = BIT(9), + VERSIONS_PCB_SC = BIT(8), + VERSIONS_PCB_VIDEO_MASK = 0x3 << 6, + VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6, + VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6, + VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4, + VERSIONS_HW_VER_MASK = 0xf << 0, + }; + uint raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + fpga_get_reg(dev, "versions", &raw_versions); + + versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL; + versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE; + + switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) { + case VERSIONS_PCB_VIDEO_DP_1_2: + versions->pcb_video_type = PCB_DP_1_2; + break; + + case VERSIONS_PCB_VIDEO_HDMI_2_0: + versions->pcb_video_type = PCB_HDMI_2_0; + break; + } + + switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) { + case VERSIONS_PCB_TRANSMISSION_FIBER_10G: + versions->pcb_transmission_type = PCB_FIBER_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_10G: + versions->pcb_transmission_type = PCB_CAT_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_FIBER_3G: + versions->pcb_transmission_type = PCB_FIBER_3G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_1G: + versions->pcb_transmission_type = PCB_CAT_1G; + break; + } + + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; + + return 0; +} + +static int get_features(struct udevice *dev, struct fpga_features *features) +{ + enum { + FEATURE_SPDIF_RX = BIT(15), + FEATURE_SPDIF_TX = BIT(14), + FEATURE_PCM_RX = BIT(13), + FEATURE_PCM_TX = BIT(12), + FEATURE_RAM_MASK = GENMASK(11, 8), + FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8, + FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8, + FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8, + FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8, + FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8, + FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6), + FEATURE_CARRIER_SPEED_1G = 0x0 << 6, + FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6, + FEATURE_CARRIER_SPEED_10G = 0x2 << 6, + FEATURE_CARRIERS_MASK = GENMASK(5, 4), + FEATURE_CARRIERS_0 = 0x0 << 4, + FEATURE_CARRIERS_1 = 0x1 << 4, + FEATURE_CARRIERS_2 = 0x2 << 4, + FEATURE_CARRIERS_4 = 0x3 << 4, + FEATURE_USB2 = BIT(3), + FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0), + FEATURE_VIDEOCHANNELS_0 = 0x0 << 0, + FEATURE_VIDEOCHANNELS_1 = 0x1 << 0, + FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0, + FEATURE_VIDEOCHANNELS_2 = 0x3 << 0, + }; + + enum { + EXT_FEATURE_OSD = BIT(15), + EXT_FEATURE_ETHERNET = BIT(9), + EXT_FEATURE_INTERLACE = BIT(8), + EXT_FEATURE_RS232 = BIT(7), + EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4), + EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4, + EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4, + EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4, + EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0), + EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1), + EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2), + }; + + uint raw_features; + uint raw_extended_features; + + memset(features, 0, sizeof(struct fpga_features)); + + fpga_get_reg(dev, "fpga-features", &raw_features); + fpga_get_reg(dev, "fpga-ext-features", &raw_extended_features); + + switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) { + case FEATURE_VIDEOCHANNELS_0: + features->video_channels = 0; + break; + + case FEATURE_VIDEOCHANNELS_1: + features->video_channels = 1; + break; + + case FEATURE_VIDEOCHANNELS_1_1: + case FEATURE_VIDEOCHANNELS_2: + features->video_channels = 2; + break; + }; + + switch (raw_features & FEATURE_CARRIERS_MASK) { + case FEATURE_CARRIERS_0: + features->carriers = 0; + break; + + case FEATURE_CARRIERS_1: + features->carriers = 1; + break; + + case FEATURE_CARRIERS_2: + features->carriers = 2; + break; + + case FEATURE_CARRIERS_4: + features->carriers = 4; + break; + } + + switch (raw_features & FEATURE_CARRIER_SPEED_MASK) { + case FEATURE_CARRIER_SPEED_1G: + features->carrier_speed = CARRIER_SPEED_1G; + break; + case FEATURE_CARRIER_SPEED_2_5G: + features->carrier_speed = CARRIER_SPEED_2_5G; + break; + case FEATURE_CARRIER_SPEED_10G: + features->carrier_speed = CARRIER_SPEED_10G; + break; + } + + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT_295MBPS: + features->ram_config = RAM_DDR2_32BIT_295MBPS; + break; + + case FEATURE_RAM_DDR3_32BIT_590MBPS: + features->ram_config = RAM_DDR3_32BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT_590MBPS: + features->ram_config = RAM_DDR3_48BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_64BIT_1800MBPS: + features->ram_config = RAM_DDR3_64BIT_1800MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT_1800MBPS: + features->ram_config = RAM_DDR3_48BIT_1800MBPS; + break; + } + + features->pcm_tx = raw_features & FEATURE_PCM_TX; + features->pcm_rx = raw_features & FEATURE_PCM_RX; + features->spdif_tx = raw_features & FEATURE_SPDIF_TX; + features->spdif_rx = raw_features & FEATURE_SPDIF_RX; + features->usb2 = raw_features & FEATURE_USB2; + features->rs232 = raw_extended_features & EXT_FEATURE_RS232; + features->compression_type1 = raw_extended_features & + EXT_FEATURE_COMPRESSION_TYPE1; + features->compression_type2 = raw_extended_features & + EXT_FEATURE_COMPRESSION_TYPE2; + features->compression_type3 = raw_extended_features & + EXT_FEATURE_COMPRESSION_TYPE3; + features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE; + features->osd = raw_extended_features & EXT_FEATURE_OSD; + features->compression_pipes = raw_extended_features & + EXT_FEATURE_COMPRESSION_PERF_MASK; + + return 0; +} + +#else + +static int get_versions(unsigned int fpga, struct fpga_versions *versions) +{ + enum { + /* HW version encoding is a mess, leave it for the moment */ + VERSIONS_HW_VER_MASK = 0xf << 0, + VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4), + VERSIONS_SFP = BIT(5), + VERSIONS_VIDEO_MASK = 0x7 << 6, + VERSIONS_VIDEO_DVI = 0x0 << 6, + VERSIONS_VIDEO_DP_165 = 0x1 << 6, + VERSIONS_VIDEO_DP_300 = 0x2 << 6, + VERSIONS_VIDEO_HDMI = 0x3 << 6, + VERSIONS_UT_MASK = 0xf << 12, + VERSIONS_UT_MAIN_SERVER = 0x0 << 12, + VERSIONS_UT_MAIN_USER = 0x1 << 12, + VERSIONS_UT_VIDEO_SERVER = 0x2 << 12, + VERSIONS_UT_VIDEO_USER = 0x3 << 12, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + FPGA_GET_REG(fpga, versions, &raw_versions); + + switch (raw_versions & VERSIONS_UT_MASK) { + case VERSIONS_UT_MAIN_SERVER: + versions->video_channel = false; + versions->con_side = false; + break; + + case VERSIONS_UT_MAIN_USER: + versions->video_channel = false; + versions->con_side = true; + break; + + case VERSIONS_UT_VIDEO_SERVER: + versions->video_channel = true; + versions->con_side = false; + break; + + case VERSIONS_UT_VIDEO_USER: + versions->video_channel = true; + versions->con_side = true; + break; + } + + switch (raw_versions & VERSIONS_VIDEO_MASK) { + case VERSIONS_VIDEO_DVI: + versions->pcb_video_type = PCB_DVI_SL; + break; + + case VERSIONS_VIDEO_DP_165: + versions->pcb_video_type = PCB_DP_165MPIX; + break; + + case VERSIONS_VIDEO_DP_300: + versions->pcb_video_type = PCB_DP_300MPIX; + break; + + case VERSIONS_VIDEO_HDMI: + versions->pcb_video_type = PCB_HDMI; + break; + } + + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; + + if (raw_versions & VERSIONS_SFP) + versions->pcb_transmission_type = PCB_FIBER_3G; + else + versions->pcb_transmission_type = PCB_CAT_1G; + + return 0; +} + +static int get_features(unsigned int fpga, struct fpga_features *features) +{ + enum { + FEATURE_CARRIER_SPEED_2_5 = BIT(4), + FEATURE_RAM_MASK = 0x7 << 5, + FEATURE_RAM_DDR2_32BIT = 0x0 << 5, + FEATURE_RAM_DDR3_32BIT = 0x1 << 5, + FEATURE_RAM_DDR3_48BIT = 0x2 << 5, + FEATURE_PCM_AUDIO_TX = BIT(9), + FEATURE_PCM_AUDIO_RX = BIT(10), + FEATURE_OSD = BIT(11), + FEATURE_USB20 = BIT(12), + FEATURE_COMPRESSION_MASK = 7 << 13, + FEATURE_COMPRESSION_TYPE1 = 0x1 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13, + }; + + enum { + EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0), + EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1), + EXTENDED_FEATURE_RS232 = BIT(2), + EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3), + EXTENDED_FEATURE_INTERLACE = BIT(4), + }; + + u16 raw_features; + u16 raw_extended_features; + + memset(features, 0, sizeof(struct fpga_features)); + + FPGA_GET_REG(fpga, fpga_features, &raw_features); + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); + + features->video_channels = raw_features & 0x3; + features->carriers = (raw_features >> 2) & 0x3; + + features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5) + ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G; + + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT: + features->ram_config = RAM_DDR2_32BIT_295MBPS; + break; + + case FEATURE_RAM_DDR3_32BIT: + features->ram_config = RAM_DDR3_32BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT: + features->ram_config = RAM_DDR3_48BIT_590MBPS; + break; + } + + features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX; + features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX; + features->spdif_tx = raw_extended_features & + EXTENDED_FEATURE_SPDIF_AUDIO_TX; + features->spdif_rx = raw_extended_features & + EXTENDED_FEATURE_SPDIF_AUDIO_RX; + + features->usb2 = raw_features & FEATURE_USB20; + features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232; + + features->compression_type1 = false; + features->compression_type2 = false; + features->compression_type3 = false; + switch (raw_features & FEATURE_COMPRESSION_MASK) { + case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3: + features->compression_type3 = true; + case FEATURE_COMPRESSION_TYPE1_TYPE2: + features->compression_type2 = true; + case FEATURE_COMPRESSION_TYPE1: + features->compression_type1 = true; + break; + } + + features->interlace = raw_extended_features & + EXTENDED_FEATURE_INTERLACE; + features->osd = raw_features & FEATURE_OSD; + features->compression_pipes = raw_extended_features & + EXTENDED_FEATURE_COMPRESSION_PIPES; + + return 0; +} + +#endif + +static void fpga_print_info(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + uint fpga_version; + struct fpga_versions versions; + struct fpga_features features; + + fpga_get_reg(dev, "fpga-version", &fpga_version); + get_versions(dev, &versions); + get_features(dev, &features); + + priv->has_osd = features.osd; + + if (versions.video_channel) + printf("Videochannel"); + else + printf("Mainchannel"); + + if (versions.con_side) + printf(" User"); + else + printf(" Server"); + +// FIXME +#if 0 + if (versions & (1<<4)) + printf(" UC"); +#endif + + switch (versions.pcb_transmission_type) { + case PCB_CAT_1G: + case PCB_CAT_10G: + printf(" CAT"); + break; + case PCB_FIBER_3G: + case PCB_FIBER_10G: + printf(" Fiber"); + break; + }; + + switch (versions.pcb_video_type) { + case PCB_DVI_SL: + printf(" DVI,"); + break; + case PCB_DP_165MPIX: + printf(" DP 165MPix/s,"); + break; + case PCB_DP_300MPIX: + printf(" DP 300MPix/s,"); + break; + case PCB_HDMI: + printf(" HDMI,"); + break; + case PCB_DP_1_2: + printf(" DP 1.2,"); + break; + case PCB_HDMI_2_0: + printf(" HDMI 2.0,"); + break; + } + + printf(" FPGA V %d.%02d\n features: ", + fpga_version / 100, fpga_version % 100); + + if (!features.compression_type1 && + !features.compression_type2 && + !features.compression_type3) + printf("no compression, "); + + if (features.compression_type1) + printf("type1-deltacompression, "); + + if (features.compression_type2) + printf("type2-inlinecompression, "); + + if (features.compression_type3) + printf("type3-intempocompression, "); + + printf("%sosd", features.osd ? "" : "no "); + + if (features.pcm_rx && features.pcm_tx) + printf(", pcm rx+tx"); + else if (features.pcm_rx) + printf(", pcm rx"); + else if (features.pcm_tx) + printf(", pcm tx"); + + if (features.spdif_rx && features.spdif_tx) + printf(", spdif rx+tx"); + else if (features.spdif_rx) + printf(", spdif rx"); + else if (features.spdif_tx) + printf(", spdif tx"); + + puts(",\n "); + + switch (features.sysclock) { + case SYSCLK_147456: + printf("clock 147.456 MHz"); + break; + } + + switch (features.ram_config) { + case RAM_DDR2_32BIT_295MBPS: + printf(", RAM 32 bit DDR2"); + break; + case RAM_DDR3_32BIT_590MBPS: + printf(", RAM 32 bit DDR3"); + break; + case RAM_DDR3_48BIT_590MBPS: + case RAM_DDR3_48BIT_1800MBPS: + printf(", RAM 48 bit DDR3"); + break; + case RAM_DDR3_64BIT_1800MBPS: + printf(", RAM 64 bit DDR3"); + break; + } + + printf(", %d carrier(s)", features.carriers); + + switch (features.carrier_speed) { + case CARRIER_SPEED_1G: + printf(", 1Gbit/s"); + break; + case CARRIER_SPEED_3G: + printf(", 3Gbit/s"); + break; + case CARRIER_SPEED_10G: + printf(", 10Gbit/s"); + break; + } + + printf(", %d video channel(s)\n", features.video_channels); +} + +static void signal_startup_finished(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + + gpio_request_list_by_name(dev, "startupfin-gpios", + priv->startupfin_gpios, 2, GPIOD_IS_OUT); + if (!priv->startupfin_gpios[0].dev) { + printf("%s: Could not get startupfin-GPIOs.\n", dev->name); + return; + } + + /* Inverted */ + dm_gpio_set_value(&priv->startupfin_gpios[0], 0); + /* Non-inverted */ + dm_gpio_set_value(&priv->startupfin_gpios[1], 1); +} + +static int do_reflection_test(struct udevice *dev) +{ + int ctr = 0; + + while (1) { + uint val; + + fpga_set_reg(dev, "reflection-low", reflection_testpattern); + + fpga_get_reg(dev, "reflection-low", &val); + if (val == (~reflection_testpattern & 0xffff)) + return 1; + + mdelay(100); + if (ctr++ > 5) + return 0; + } +} + +UCLASS_DRIVER(ihs_fpga) = { + .id = UCLASS_IHS_FPGA, + .name = "ihs_fpga", + .flags = DM_UC_FLAG_SEQ_ALIAS, +}; + +static int get_reg_spec(struct udevice *dev, const char *compat, + struct reg_spec *spec) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + int childnode; + + fdt_for_each_subnode(childnode, gd->fdt_blob, priv->regmap_node) { + const struct fdt_property *compatprop; + u32 reg[3]; + uint start_bit, end_bit; + + compatprop = fdt_get_property(gd->fdt_blob, childnode, + "compatible", NULL); + + if (!strcmp(compatprop->data, compat)) { + fdtdec_get_int_array(gd->fdt_blob, childnode, "reg", + reg, 3); + start_bit = reg[1]; + end_bit = reg[1] - reg[2] + 1; + + spec->mask = GENMASK(start_bit, end_bit); + spec->addr = reg[0]; + spec->shift = end_bit; + + return 0; + } + } + + return 1; +} + +static int ihs_fpga_set_reg(struct udevice *dev, const char *compat, + uint value) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + struct reg_spec spec; + + if (get_reg_spec(dev, compat, &spec)) { + printf("%s: Could not get %s regspec for '%s'.\n", __func__, + dev->name, compat); + return -ENODEV; + } + + out_le16((void *)(priv->regs + spec.addr), value << spec.shift); + + return 0; +} + +static int ihs_fpga_get_reg(struct udevice *dev, const char *compat, + uint *value) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + struct reg_spec spec; + uint tmp; + + if (get_reg_spec(dev, compat, &spec)) { + printf("%s: Could not get %s regspec for '%s'.\n", __func__, + dev->name, compat); + return -ENODEV; + } + + tmp = in_le16((void *)(priv->regs + spec.addr)); + *value = (tmp & spec.mask) >> spec.shift; + + return 0; +} + +static u16 ihs_fpga_in_le16(struct udevice *dev, phys_addr_t addr) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + + /* TODO: MCLink transfer */ + + return in_le16((void *)(priv->regs + addr)); +} + +static void ihs_fpga_out_le16(struct udevice *dev, phys_addr_t addr, u16 value) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + + /* TODO: MCLink transfer */ + + out_le16((void *)(priv->regs + addr), value); +} + +static const struct ihs_fpga_ops ihs_fpga_ops = { + .set_reg = ihs_fpga_set_reg, + .get_reg = ihs_fpga_get_reg, + .in_le16 = ihs_fpga_in_le16, + .out_le16 = ihs_fpga_out_le16, +}; + +static int ihs_fpga_probe(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + struct fdtdec_phandle_args phandle_args; + struct fdtdec_phandle_args args; + struct udevice *busdev = NULL; + struct udevice *child = NULL; + uint mem_width; + + if (fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev), + "regmap", NULL, 0, 0, &args)) { + printf("%s: Could not get regmap.\n", dev->name); + return 1; + } + + priv->regmap_node = args.node; + + addr = devfdt_get_addr(dev); + + priv->addr = addr; + priv->regs = map_sysmem(addr, mem_width); + + gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + if (!priv->reset_gpio.dev) + printf("%s: Could not get reset-GPIO.\n", dev->name); + + gpio_request_by_name(dev, "done-gpios", 0, &priv->done_gpio, + GPIOD_IS_IN); + if (!priv->done_gpio.dev) + printf("%s: Could not get done-GPIO.\n", dev->name); + + dm_gpio_set_value(&priv->reset_gpio, 1); + + signal_startup_finished(dev); + + if (!do_reflection_test(dev)) { + int ctr = 0; + + dm_gpio_set_value(&priv->reset_gpio, 0); + + while (!dm_gpio_get_value(&priv->done_gpio)) { + mdelay(100); + if (ctr++ > 5) { + printf("Initializing FPGA failed\n"); + break; + } + } + + udelay(10); + + dm_gpio_set_value(&priv->reset_gpio, 1); + + if (!do_reflection_test(dev)) { + printf("%s: Reflection test FAILED.\n", dev->name); + return -1; + } + } + + printf("%s: Reflection test passed.\n", dev->name); + + if (fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev), "bus", + NULL, 0, 0, &phandle_args)) + return -1; + + lists_bind_fdt(dev, offset_to_ofnode(phandle_args.node), &busdev); + + fpga_print_info(dev); + + /* TODO: Check if this should be gazerbeam-specific */ + if (priv->has_osd) { + /* Disable softcore, select external pixclock */ + fpga_set_reg(dev, "control", 0x8000); + } + + device_probe(busdev); + + for (device_find_first_child(busdev, &child); + child; + device_find_next_child(&child)) + device_probe(child); + + return 0; +} + +static const struct udevice_id ihs_fpga_ids[] = { + { .compatible = "gdsys,iocon_fpga" }, + { .compatible = "gdsys,iocpu_fpga" }, + { } +}; + +U_BOOT_DRIVER(ihs_fpga_bus) = { + .name = "ihs_fpga_bus", + .id = UCLASS_IHS_FPGA, + .ops = &ihs_fpga_ops, + .of_match = ihs_fpga_ids, + .probe = ihs_fpga_probe, + .priv_auto_alloc_size = sizeof(struct ihs_fpga_priv), +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 2e6498b7dc..56fbedaa9d 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -35,12 +35,14 @@ enum uclass_id { UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */ UCLASS_DMA, /* Direct Memory Access */ UCLASS_ETH, /* Ethernet device */ + UCLASS_GDSYS_SOC, /* gdsys soc buses */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ UCLASS_FIRMWARE, /* Firmware */ UCLASS_I2C, /* I2C bus */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ UCLASS_I2C_GENERIC, /* Generic I2C device */ UCLASS_I2C_MUX, /* I2C multiplexer */ + UCLASS_IHS_FPGA, /* gdsys IHS FPGAs */ UCLASS_IRQ, /* Interrupt controller */ UCLASS_KEYBOARD, /* Keyboard input device */ UCLASS_LED, /* Light-emitting diode (LED) */ diff --git a/include/gdsys_soc.h b/include/gdsys_soc.h new file mode 100644 index 0000000000..2164651f62 --- /dev/null +++ b/include/gdsys_soc.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GDSYS_SOC_H_ +#define _GDSYS_SOC_H_ + +/** + * struct gdsys_soc_child_platdata - platform data for devices on gdsys soc + * buses + * + * To access their register maps, devices on gdsys soc buses usually have + * facilitate the accessor function of the IHS FPGA their parent bus is + * attached to. To pass the FPGA device down to the bus' children, a pointer to + * it is contained in this structure. + * + * To obtain this structure, use dev_get_parent_platdata(dev) where dev is a + * device on the gdsys soc bus. + * + * @fpga: The IHS FPGA that controls the bus the device is attached to. + */ +struct gdsys_soc_child_platdata { + struct udevice *fpga; +}; + +#endif /* _GDSYS_SOC_H_ */ diff --git a/include/ihs_fpga.h b/include/ihs_fpga.h new file mode 100644 index 0000000000..552583cbe1 --- /dev/null +++ b/include/ihs_fpga.h @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IHS_FPGA_H_ +#define _IHS_FPGA_H_ + +/** + * struct ihs_fpga_ops - driver operations for IHS FPGA uclass + * + * Drivers should support these operations unless otherwise noted. These + * operations are intended to be used by uclass code, not directly from + * other code. + */ +struct ihs_fpga_ops { + /** + * get_reg() - Get value of a named FPGA register + * + * To accommodate possible future memory layout changes, the registers + * of a IHS FPGA are described in the device tree, and each is given a + * distinct compatible string to address them with. + * + * @dev: FPGA device to read from. + * @compat: The compatible string of the register to write to. + * @value: Pointer to a variable that takes the value read from the + * register. + * @return 0 if OK, -ENODEV if no named register with the given + * compatibility string exists. + */ + int (*get_reg)(struct udevice *dev, const char *compat, uint *value); + + /** + * set_reg() - Set value of a named FPGA register + * + * To accommodate possible future memory layout changes, the registers + * of a IHS FPGA are described in the device tree, and each is given a + * distinct compatible string to address them with. + * + * @dev: FPGA device to write to. + * @compat: The compatible string of the register to write to. + * @value: Value to write to the register. + * @return 0 if OK, -ENODEV if no named register with the given + * compatibility string exists. + */ + int (*set_reg)(struct udevice *dev, const char *compat, uint value); + + /** + * in_le16() - Read 16 bit value from address in FPGA register space + * + * @dev: FPGA device to read from. + * @addr: Address in the FPGA register space to read from. + * @return 0 if OK, -ve on error. + */ + u16 (*in_le16)(struct udevice *dev, phys_addr_t addr); + + /** + * out_le16() - Write 16 bit value to address in FPGA register space + * + * @dev: FPGA device to write to. + * @addr: Address in the FPGA register space to write to. + * @return 0 if OK, -ve on error. + */ + void (*out_le16)(struct udevice *dev, phys_addr_t addr, u16 value); +}; + +#define ihs_fpga_get_ops(dev) ((struct ihs_fpga_ops *)(dev)->driver->ops) + +/** + * fpga_get_reg() - Get value of a named FPGA register + * + * @dev: FPGA device to read from. + * @compat: The compatible string of the register to write to. + * @value: Pointer to a variable that takes the value read from the register. + * @return 0 if OK, -ENODEV if no named register with the given compatibility + * string exists. + */ +int fpga_get_reg(struct udevice *dev, const char *compat, uint *value); + +/** + * fpga_set_reg() - Set value of a named FPGA register + * + * @dev: FPGA device to write to. + * @compat: The compatible string of the register to write to. + * @value: Value to write to the register. + * @return 0 if OK, -ENODEV if no named register with the given compatibility + * string exists. + */ +int fpga_set_reg(struct udevice *dev, const char *compat, uint value); + +/** + * fpga_in_le16() - Read 16 bit value from address in FPGA register space + * + * @dev: FPGA device to read from. + * @addr: Address in the FPGA register space to read from. + * @return 0 if OK, -ve on error. + */ +u16 fpga_in_le16(struct udevice *dev, phys_addr_t addr); + +/** + * fpga_out_le16() - Write 16 bit value to address in FPGA register space + * + * @dev: FPGA device to write to. + * @addr: Address in the FPGA register space to write to. + * @return 0 if OK, -ve on error. + */ +void fpga_out_le16(struct udevice *dev, phys_addr_t addr, u16 value); + +#endif /* !_IHS_FPGA_H_ */

Add a driver for the TX side of the Xilinx LogiCore DisplayPort IP core.

Signed-off-by: Mario Six mario.six@gdsys.cc ---

drivers/transmitter/Kconfig | 6 + drivers/transmitter/Makefile | 1 + drivers/transmitter/logicore_dp_dpcd.h | 342 +++++ drivers/transmitter/logicore_dp_tx.c | 1984 ++++++++++++++++++++++++++++ drivers/transmitter/logicore_dp_tx.h | 40 + drivers/transmitter/logicore_dp_tx_regif.h | 365 +++++ 6 files changed, 2738 insertions(+) create mode 100644 drivers/transmitter/logicore_dp_dpcd.h create mode 100644 drivers/transmitter/logicore_dp_tx.c create mode 100644 drivers/transmitter/logicore_dp_tx.h create mode 100644 drivers/transmitter/logicore_dp_tx_regif.h

diff --git a/drivers/transmitter/Kconfig b/drivers/transmitter/Kconfig index 64ca08f8b8..e5613586a3 100644 --- a/drivers/transmitter/Kconfig +++ b/drivers/transmitter/Kconfig @@ -13,4 +13,10 @@ config SANDBOX_TRANSMITTER help Enable the dummy transmitter for the sandbox.

+config LOGICORE_DP_TX + bool "Enable Logicore DP TX driver" + depends on DM + help + Enabled the driver for the Logicore DP TX display port transmitter. + endif diff --git a/drivers/transmitter/Makefile b/drivers/transmitter/Makefile index b873e63e28..088922d992 100644 --- a/drivers/transmitter/Makefile +++ b/drivers/transmitter/Makefile @@ -7,3 +7,4 @@

obj-y += transmitter-uclass.o obj-$(CONFIG_SANDBOX_TRANSMITTER) += sandbox_transmitter.o +obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o diff --git a/drivers/transmitter/logicore_dp_dpcd.h b/drivers/transmitter/logicore_dp_dpcd.h new file mode 100644 index 0000000000..6858294551 --- /dev/null +++ b/drivers/transmitter/logicore_dp_dpcd.h @@ -0,0 +1,342 @@ +/* + * logicore_dp_dpcd.h + * + * DPCD interface definition for XILINX LogiCore DisplayPort v6.1 + * based on Xilinx dp_v3_1 driver sources + * + * (C) Copyright 2016 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __GDSYS_LOGICORE_DP_DPCD_H__ +#define __GDSYS_LOGICORE_DP_DPCD_H__ + +/* receiver capability field */ +#define DPCD_REV 0x00000 +#define DPCD_MAX_LINK_RATE 0x00001 +#define DPCD_MAX_LANE_COUNT 0x00002 +#define DPCD_MAX_DOWNSPREAD 0x00003 +#define DPCD_NORP_PWR_V_CAP 0x00004 +#define DPCD_DOWNSP_PRESENT 0x00005 +#define DPCD_ML_CH_CODING_CAP 0x00006 +#define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007 +#define DPCD_RX_PORT0_CAP_0 0x00008 +#define DPCD_RX_PORT0_CAP_1 0x00009 +#define DPCD_RX_PORT1_CAP_0 0x0000A +#define DPCD_RX_PORT1_CAP_1 0x0000B +#define DPCD_I2C_SPEED_CTL_CAP 0x0000C +#define DPCD_EDP_CFG_CAP 0x0000D +#define DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E +#define DPCD_ADAPTER_CAP 0x0000F +#define DPCD_FAUX_CAP 0x00020 +#define DPCD_MSTM_CAP 0x00021 +#define DPCD_NUM_AUDIO_EPS 0x00022 +#define DPCD_AV_GRANULARITY 0x00023 +#define DPCD_AUD_DEC_LAT_7_0 0x00024 +#define DPCD_AUD_DEC_LAT_15_8 0x00025 +#define DPCD_AUD_PP_LAT_7_0 0x00026 +#define DPCD_AUD_PP_LAT_15_8 0x00027 +#define DPCD_VID_INTER_LAT 0x00028 +#define DPCD_VID_PROG_LAT 0x00029 +#define DPCD_REP_LAT 0x0002A +#define DPCD_AUD_DEL_INS_7_0 0x0002B +#define DPCD_AUD_DEL_INS_15_8 0x0002C +#define DPCD_AUD_DEL_INS_23_16 0x0002D +#define DPCD_GUID 0x00030 +#define DPCD_RX_GTC_VALUE_7_0 0x00054 +#define DPCD_RX_GTC_VALUE_15_8 0x00055 +#define DPCD_RX_GTC_VALUE_23_16 0x00056 +#define DPCD_RX_GTC_VALUE_31_24 0x00057 +#define DPCD_RX_GTC_MSTR_REQ 0x00058 +#define DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059 +#define DPCD_DOWNSP_0_CAP 0x00080 +#define DPCD_DOWNSP_1_CAP 0x00081 +#define DPCD_DOWNSP_2_CAP 0x00082 +#define DPCD_DOWNSP_3_CAP 0x00083 +#define DPCD_DOWNSP_0_DET_CAP 0x00080 +#define DPCD_DOWNSP_1_DET_CAP 0x00084 +#define DPCD_DOWNSP_2_DET_CAP 0x00088 +#define DPCD_DOWNSP_3_DET_CAP 0x0008C + +/* link configuration field */ +#define DPCD_LINK_BW_SET 0x00100 +#define DPCD_LANE_COUNT_SET 0x00101 +#define DPCD_TP_SET 0x00102 +#define DPCD_TRAINING_LANE0_SET 0x00103 +#define DPCD_TRAINING_LANE1_SET 0x00104 +#define DPCD_TRAINING_LANE2_SET 0x00105 +#define DPCD_TRAINING_LANE3_SET 0x00106 +#define DPCD_DOWNSPREAD_CTRL 0x00107 +#define DPCD_ML_CH_CODING_SET 0x00108 +#define DPCD_I2C_SPEED_CTL_SET 0x00109 +#define DPCD_EDP_CFG_SET 0x0010A +#define DPCD_LINK_QUAL_LANE0_SET 0x0010B +#define DPCD_LINK_QUAL_LANE1_SET 0x0010C +#define DPCD_LINK_QUAL_LANE2_SET 0x0010D +#define DPCD_LINK_QUAL_LANE3_SET 0x0010E +#define DPCD_TRAINING_LANE0_1_SET2 0x0010F +#define DPCD_TRAINING_LANE2_3_SET2 0x00110 +#define DPCD_MSTM_CTRL 0x00111 +#define DPCD_AUDIO_DELAY_7_0 0x00112 +#define DPCD_AUDIO_DELAY_15_8 0x00113 +#define DPCD_AUDIO_DELAY_23_6 0x00114 +#define DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118 +#define DPCD_FAUX_MODE_CTRL 0x00120 +#define DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121 +#define DPCD_BACK_CH_STATUS 0x00122 +#define DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123 +#define DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125 +#define DPCD_TX_GTC_VALUE_7_0 0x00154 +#define DPCD_TX_GTC_VALUE_15_8 0x00155 +#define DPCD_TX_GTC_VALUE_23_16 0x00156 +#define DPCD_TX_GTC_VALUE_31_24 0x00157 +#define DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158 +#define DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159 +#define DPCD_ADAPTER_CTRL 0x001A0 +#define DPCD_BRANCH_DEVICE_CTRL 0x001A1 +#define DPCD_PAYLOAD_ALLOCATE_SET 0x001C0 +#define DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1 +#define DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2 + +/* link/sink status field */ +#define DPCD_SINK_COUNT 0x00200 +#define DPCD_DEVICE_SERVICE_IRQ 0x00201 +#define DPCD_STATUS_LANE_0_1 0x00202 +#define DPCD_STATUS_LANE_2_3 0x00203 +#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204 +#define DPCD_SINK_STATUS 0x00205 +#define DPCD_ADJ_REQ_LANE_0_1 0x00206 +#define DPCD_ADJ_REQ_LANE_2_3 0x00207 +#define DPCD_TRAINING_SCORE_LANE_0 0x00208 +#define DPCD_TRAINING_SCORE_LANE_1 0x00209 +#define DPCD_TRAINING_SCORE_LANE_2 0x0020A +#define DPCD_TRAINING_SCORE_LANE_3 0x0020B +#define DPCD_ADJ_REQ_PC2 0x0020C +#define DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D +#define DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210 +#define DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212 +#define DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214 +#define DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216 + +/* automated testing sub-field */ +#define DPCD_FAUX_FORWARD_CH_STATUS 0x00280 +#define DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281 +#define DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282 +#define DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0 +#define DPCD_VC_PAYLOAD_ID_SLOT(SlotNum) \ + (DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum) + +/* sink control field */ +#define DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600 + +/* sideband message buffers */ +#define DPCD_DOWN_REQ 0x01000 +#define DPCD_UP_REP 0x01200 +#define DPCD_DOWN_REP 0x01400 +#define DPCD_UP_REQ 0x01600 + +/* event status indicator field */ +#define DPCD_SINK_COUNT_ESI 0x02002 +#define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003 +#define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004 +#define DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005 +#define DPCD_SINK_LANE0_1_STATUS 0x0200C +#define DPCD_SINK_LANE2_3_STATUS 0x0200D +#define DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E +#define DPCD_SINK_STATUS_ESI 0x0200F + +/* + * field addresses and sizes. + */ +#define DPCD_RECEIVER_CAP_FIELD_START DPCD_REV +#define DPCD_RECEIVER_CAP_FIELD_SIZE 0x100 +#define DPCD_LINK_CFG_FIELD_START DPCD_LINK_BW_SET +#define DPCD_LINK_CFG_FIELD_SIZE 0x100 +#define DPCD_LINK_SINK_STATUS_FIELD_START DPCD_SINK_COUNT +#define DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17 +/* 0x00000: DPCD_REV */ +#define DPCD_REV_MNR_MASK 0x0F +#define DPCD_REV_MJR_MASK 0xF0 +#define DPCD_REV_MJR_SHIFT 4 +/* 0x00001: MAX_LINK_RATE */ +#define DPCD_MAX_LINK_RATE_162GBPS 0x06 +#define DPCD_MAX_LINK_RATE_270GBPS 0x0A +#define DPCD_MAX_LINK_RATE_540GBPS 0x14 +/* 0x00002: MAX_LANE_COUNT */ +#define DPCD_MAX_LANE_COUNT_MASK 0x1F +#define DPCD_MAX_LANE_COUNT_1 0x01 +#define DPCD_MAX_LANE_COUNT_2 0x02 +#define DPCD_MAX_LANE_COUNT_4 0x04 +#define DPCD_TPS3_SUPPORT_MASK 0x40 +#define DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80 +/* 0x00003: MAX_DOWNSPREAD */ +#define DPCD_MAX_DOWNSPREAD_MASK 0x01 +#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40 +/* 0x00005: DOWNSP_PRESENT */ +#define DPCD_DOWNSP_PRESENT_MASK 0x01 +#define DPCD_DOWNSP_TYPE_MASK 0x06 +#define DPCD_DOWNSP_TYPE_SHIFT 1 +#define DPCD_DOWNSP_TYPE_DP 0x0 +#define DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1 +#define DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2 +#define DPCD_DOWNSP_TYPE_OTHERS 0x3 +#define DPCD_DOWNSP_FORMAT_CONV_MASK 0x08 +#define DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10 +/* 0x00006, 0x00108: ML_CH_CODING_SUPPORT, ML_CH_CODING_SET */ +#define DPCD_ML_CH_CODING_MASK 0x01 +/* 0x00007: DOWNSP_COUNT_MSA_OUI */ +#define DPCD_DOWNSP_COUNT_MASK 0x0F +#define DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40 +#define DPCD_OUI_SUPPORT_MASK 0x80 +/* 0x00008, 0x0000A: RX_PORT[0-1]_CAP_0 */ +#define DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02 +#define DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04 +/* 0x0000C, 0x00109: I2C_SPEED_CTL_CAP, I2C_SPEED_CTL_SET */ +#define DPCD_I2C_SPEED_CTL_NONE 0x00 +#define DPCD_I2C_SPEED_CTL_1KBIPS 0x01 +#define DPCD_I2C_SPEED_CTL_5KBIPS 0x02 +#define DPCD_I2C_SPEED_CTL_10KBIPS 0x04 +#define DPCD_I2C_SPEED_CTL_100KBIPS 0x08 +#define DPCD_I2C_SPEED_CTL_400KBIPS 0x10 +#define DPCD_I2C_SPEED_CTL_1MBIPS 0x20 +/* 0x0000E: TRAIN_AUX_RD_INTERVAL */ +#define DPCD_TRAIN_AUX_RD_INT_100_400US 0x00 +#define DPCD_TRAIN_AUX_RD_INT_4MS 0x01 +#define DPCD_TRAIN_AUX_RD_INT_8MS 0x02 +#define DPCD_TRAIN_AUX_RD_INT_12MS 0x03 +#define DPCD_TRAIN_AUX_RD_INT_16MS 0x04 +/* 0x00020: DPCD_FAUX_CAP */ +#define DPCD_FAUX_CAP_MASK 0x01 +/* 0x00021: MSTM_CAP */ +#define DPCD_MST_CAP_MASK 0x01 +/* 0x00080, 0x00081|4, 0x00082|8, 0x00083|C: DOWNSP_X_(DET_)CAP */ +#define DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07 +#define DPCD_DOWNSP_X_CAP_TYPE_DP 0x0 +#define DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1 +#define DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2 +#define DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3 +#define DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4 +#define DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5 +#define DPCD_DOWNSP_X_CAP_HPD_MASK 0x80 +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0 +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4 +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1 +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2 +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3 +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4 +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5 +#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7 +/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ +#define DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03 +#define DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0 +#define DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1 +#define DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2 +#define DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3 +/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ +#define DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01 +#define DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02 +#define DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04 + +/* link configuration field masks, shifts, and register values */ +/* 0x00100: DPCD_LINK_BW_SET */ +#define DPCD_LINK_BW_SET_162GBPS 0x06 +#define DPCD_LINK_BW_SET_270GBPS 0x0A +#define DPCD_LINK_BW_SET_540GBPS 0x14 +/* 0x00101: LANE_COUNT_SET */ +#define DPCD_LANE_COUNT_SET_MASK 0x1F +#define DPCD_LANE_COUNT_SET_1 0x01 +#define DPCD_LANE_COUNT_SET_2 0x02 +#define DPCD_LANE_COUNT_SET_4 0x04 +#define DPCD_ENHANCED_FRAME_EN_MASK 0x80 +/* 0x00102: TP_SET */ +#define DPCD_TP_SEL_MASK 0x03 +#define DPCD_TP_SEL_OFF 0x0 +#define DPCD_TP_SEL_TP1 0x1 +#define DPCD_TP_SEL_TP2 0x2 +#define DPCD_TP_SEL_TP3 0x3 +#define DPCD_TP_SET_LQP_MASK 0x06 +#define DPCD_TP_SET_LQP_SHIFT 2 +#define DPCD_TP_SET_LQP_OFF 0x0 +#define DPCD_TP_SET_LQP_D102_TEST 0x1 +#define DPCD_TP_SET_LQP_SER_MES 0x2 +#define DPCD_TP_SET_LQP_PRBS7 0x3 +#define DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10 +#define DPCD_TP_SET_SCRAMB_DIS_MASK 0x20 +#define DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0 +#define DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6 +#define DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0 +#define DPCD_TP_SET_SE_COUNT_SEL_DE 0x1 +#define DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2 +/* 0x00103-0x00106: TRAINING_LANE[0-3]_SET */ +#define DPCD_TRAINING_LANEX_SET_VS_MASK 0x03 +#define DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 +#define DPCD_TRAINING_LANEX_SET_PE_MASK 0x18 +#define DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 +#define DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 +/* 0x00107: DOWNSPREAD_CTRL */ +#define DPCD_SPREAD_AMP_MASK 0x10 +#define DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80 +/* 0x00108: ML_CH_CODING_SET - Same as 0x00006: ML_CH_CODING_SUPPORT */ +/* 0x00109: I2C_SPEED_CTL_SET - Same as 0x0000C: I2C_SPEED_CTL_CAP */ +/* 0x0010F-0x00110: TRAINING_LANE[0_1-2_3]_SET2 */ +#define DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03 +#define DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04 +#define DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30 +#define DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4 +#define DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40 +/* 0x00111: MSTM_CTRL */ +#define DPCD_MST_EN_MASK 0x01 +#define DPCD_UP_REQ_EN_MASK 0x02 +#define DPCD_UP_IS_SRC_MASK 0x03 + +/* link/sink status field masks, shifts, and register values */ +/* 0x00200: SINK_COUNT */ +#define DPCD_SINK_COUNT_LOW_MASK 0x3F +#define DPCD_SINK_CP_READY_MASK 0x40 +#define DPCD_SINK_COUNT_HIGH_MASK 0x80 +#define DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1 +/* 0x00202: STATUS_LANE_0_1 */ +#define DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01 +#define DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02 +#define DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04 +#define DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10 +#define DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20 +#define DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40 +/* 0x00202: STATUS_LANE_2_3 */ +#define DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01 +#define DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02 +#define DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04 +#define DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10 +#define DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20 +#define DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40 +/* 0x00204: LANE_ALIGN_STATUS_UPDATED */ +#define DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK \ + 0x01 +#define DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK \ + 0x40 +#define DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK \ + 0x80 +/* 0x00205: SINK_STATUS */ +#define DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01 +#define DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02 + +/* 0x00206, 0x00207: ADJ_REQ_LANE_[0,2]_[1,3] */ +#define DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03 +#define DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C +#define DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2 +#define DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30 +#define DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4 +#define DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0 +#define DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6 +/* 0x0020C: ADJ_REQ_PC2 */ +#define DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03 +#define DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C +#define DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2 +#define DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30 +#define DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4 +#define DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0 +#define DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6 + +#endif /* __GDSYS_LOGICORE_DP_DPCD_H__ */ diff --git a/drivers/transmitter/logicore_dp_tx.c b/drivers/transmitter/logicore_dp_tx.c new file mode 100644 index 0000000000..b61159cd89 --- /dev/null +++ b/drivers/transmitter/logicore_dp_tx.c @@ -0,0 +1,1984 @@ +/* + * logicore_dp_tx.c + * + * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source) + * based on Xilinx dp_v3_1 driver sources, updated to dp_v4_0 + * + * (C) Copyright 2016 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <transmitter.h> + +#include "ihs_axi.h" + +#include "logicore_dp_dpcd.h" +#include "logicore_dp_tx_regif.h" +#include "logicore_dp_tx.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define S_AXI_CLK_DEFAULT 100000000 + +#define PHY_CLOCK_SELECT_DEFAULT PHY_CLOCK_SELECT_540GBPS + +/* The maximum voltage swing level is 3. */ +#define MAXIMUM_VS_LEVEL 3 +/* The maximum pre-emphasis level is 3. */ +#define MAXIMUM_PE_LEVEL 3 + +/* Error out if an AUX request yields a defer reply more than 50 times. */ +#define AUX_MAX_DEFER_COUNT 50 +/* Error out if an AUX request times out more than 50 times awaiting a reply. */ +#define AUX_MAX_TIMEOUT_COUNT 50 +/* Error out if checking for a connected device times out more than 50 times. */ +#define IS_CONNECTED_MAX_TIMEOUT_COUNT 50 + +enum { + TS_CLOCK_RECOVERY, + TS_CHANNEL_EQUALIZATION, + TS_ADJUST_LINK_RATE, + TS_ADJUST_LANE_COUNT, + TS_FAILURE, + TS_SUCCESS +}; + +struct aux_transaction { + u16 cmd_code; + u8 num_bytes; + u32 address; + u8 *data; +}; + +/* + * all porch parameters have been removed because our videodata is hstart/vstart + * based and there is no benefit in keeping the porches + */ + +struct main_stream_attributes { + /* Pixel clock of the stream (in Hz). */ + u32 pixel_clock_hz; + /* Miscellaneous stream attributes 0 as specified by the DisplayPort + * 1.2 specification. + */ + u32 misc_0; + /* Miscellaneous stream attributes 1 as specified by the DisplayPort + * 1.2 specification. + */ + u32 misc_1; + /* N value for the video stream. */ + u32 n_vid; + /* M value used to recover the video clock from the link clock. */ + u32 m_vid; + /* Width of the user data input port. */ + u32 user_pixel_width; + /* Used to translate the number of pixels per line to the native + * internal 16-bit datapath. + */ + u32 data_per_lane; + /* Average number of bytes per transfer unit, scaled up by a factor of + * 1000. + */ + u32 avg_bytes_per_tu; + /* Size of the transfer unit in the framing logic. In MST mode, this is + * also the number of time slots that are alloted in the payload ID + * table. + */ + u32 transfer_unit_size; + /* Number of initial wait cycles at the start of a new line by the + * framing logic. + */ + u32 init_wait; + /* Bits per color component. */ + u32 bits_per_color; + /* The component format currently in use by the video stream. */ + u8 component_format; + /* The dynamic range currently in use by the video stream. */ + u8 dynamic_range; + /* The YCbCr colorimetry currently in use by the video stream. */ + u8 y_cb_cr_colorimetry; + /* Synchronous clock mode is currently in use by the video stream. */ + u8 synchronous_clock_mode; + /* If set to 1, the value stored for user_pixel_width will be used as + * the pixel width. + */ + u8 override_user_pixel_width; + /* Horiz. blank start (pixels). */ + u32 h_start; + /* Horiz. active resolution (pixels) */ + u16 h_active; + /* Horiz. sync width (pixels) */ + u16 h_sync_width; + /* Horiz. total (pixels) */ + u16 h_total; + /* Horiz. sync polarity (0=neg|1=pos) */ + bool h_sync_polarity; + /* Vert. blank start (in lines). */ + u32 v_start; + /* Vert. active resolution (lines) */ + u16 v_active; + /* Vert. sync width (lines) */ + u16 v_sync_width; + /* Vert. total (lines) */ + u16 v_total; + /* Vert. sync polarity (0=neg|1=pos) */ + bool v_sync_polarity; +}; + +struct link_config { + u8 lane_count; + u8 link_rate; + bool scrambler_en; + bool enhanced_framing_mode; + bool downspread_control; + u8 max_lane_count; + u8 max_link_rate; + bool support_enhanced_framing_mode; + bool support_downspread_control; + u8 vs_level; /* voltage swing for each lane */ + u8 pe_level; /* pre-emphasis/cursor level for each lane */ + u8 pattern; +}; + +struct dp_tx { + u32 base; + + u32 s_axi_clk; + + bool train_adaptive; + + u8 max_link_rate; + u8 max_lane_count; + + u8 dpcd_rx_caps[16]; + + /* This is a raw read of the RX device's status registers. The first 4 + * bytes correspond to the lane status associated with clock recovery, + * channel equalization, symbol lock, and interlane alignment. The + * remaining 2 bytes represent the pre-emphasis and voltage swing level + * adjustments requested by the RX device. + */ + u8 lane_status_ajd_reqs[6]; + + struct link_config link_config; + struct main_stream_attributes main_stream_attributes; +}; + +/* + * internal API + */ + +static u32 get_reg(struct udevice *dev, u32 reg) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + u32 value = 0; + int res; + + // TODO error handling + res = axi_read(dev->parent, dp_tx->base + reg, &value); + if (res < 0) + printf("%s() failed; res = %d\n", __func__, res); + + return value; +} + +static void set_reg(struct udevice *dev, u32 reg, u32 value) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + + axi_write(dev->parent, dp_tx->base + reg, value); +} + +/* + * Check if there is a connected RX device. + * The Xilinx original calls msleep_interruptible at least once, + * ignoring status. + */ +bool is_connected(struct udevice *dev) +{ + u8 retries = 0; + + do { + int status = get_reg(dev, REG_INTERRUPT_SIG_STATE) & + INTERRUPT_SIG_STATE_HPD_STATE_MASK; + if (status) + return true; + + udelay(1000); + } while (retries++ < IS_CONNECTED_MAX_TIMEOUT_COUNT); + + return false; +} + +/* + * Wait for the DisplayPort PHY to come out of reset. + */ +static int wait_phy_ready(struct udevice *dev, u32 mask) +{ + u16 timeout = 20000; + u32 phy_status; + + /* Wait until the PHY is ready. */ + do { + phy_status = get_reg(dev, REG_PHY_STATUS) & mask; + + /* Protect against an infinite loop. */ + if (!timeout--) + return -ETIMEDOUT; + + udelay(20); + } while (phy_status != mask); + + return 0; +} + +/* AUX channel access */ + +/* + * Wait until another request is no longer in progress. + */ +static int aux_wait_ready(struct udevice *dev) +{ + int status; + u32 timeout = 100; + + /* Wait until the DisplayPort TX core is ready. */ + do { + status = get_reg(dev, REG_INTERRUPT_SIG_STATE); + + /* Protect against an infinite loop. */ + if (!timeout--) + return -ETIMEDOUT; + udelay(20); + } while (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK); + + return 0; +} + +/* + * Wait for a reply indicating that the most recent AUX request + * has been received by the RX device. + */ +static int aux_wait_reply(struct udevice *dev) +{ + u32 timeout = 100; + + while (timeout > 0) { + int status = get_reg(dev, REG_REPLY_STATUS); + + /* Check for error. */ + if (status & REPLY_STATUS_REPLY_ERROR_MASK) + return -ETIMEDOUT; + + /* Check for a reply. */ + if ((status & REPLY_STATUS_REPLY_RECEIVED_MASK) && + !(status & + REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) && + !(status & + REPLY_STATUS_REPLY_IN_PROGRESS_MASK)) { + return 0; + } + + timeout--; + udelay(20); + } + + return -ETIMEDOUT; +} + +/* + * Submit the supplied AUX request to the RX device over the AUX + * channel by writing the command, the destination address, (the write buffer + * for write commands), and the data size to the DisplayPort TX core. + */ +static int aux_request_send(struct udevice *dev, + struct aux_transaction *request) +{ + u32 timeout_count; + int status; + u8 index; + + /* Ensure that any pending AUX transactions have completed. */ + timeout_count = 0; + do { + status = get_reg(dev, REG_REPLY_STATUS); + + udelay(20); + timeout_count++; + if (timeout_count >= AUX_MAX_TIMEOUT_COUNT) + return -ETIMEDOUT; + } while ((status & REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) || + (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK)); + + set_reg(dev, REG_AUX_ADDRESS, request->address); + + if ((request->cmd_code == AUX_CMD_WRITE) || + (request->cmd_code == AUX_CMD_I2C_WRITE) || + (request->cmd_code == AUX_CMD_I2C_WRITE_MOT)) { + /* Feed write data into the DisplayPort TX core's write FIFO. */ + for (index = 0; index < request->num_bytes; index++) { + set_reg(dev, + REG_AUX_WRITE_FIFO, request->data[index]); + } + } + + /* Submit the command and the data size. */ + set_reg(dev, REG_AUX_CMD, + ((request->cmd_code << AUX_CMD_SHIFT) | + ((request->num_bytes - 1) & + AUX_CMD_NBYTES_TRANSFER_MASK))); + + /* Check for a reply from the RX device to the submitted request. */ + status = aux_wait_reply(dev); + if (status) + /* Waiting for a reply timed out. */ + return -ETIMEDOUT; + + /* Analyze the reply. */ + status = get_reg(dev, REG_AUX_REPLY_CODE); + if ((status == AUX_REPLY_CODE_DEFER) || + (status == AUX_REPLY_CODE_I2C_DEFER)) { + /* The request was deferred. */ + return -EAGAIN; + } else if ((status == AUX_REPLY_CODE_NACK) || + (status == AUX_REPLY_CODE_I2C_NACK)) { + /* The request was not acknowledged. */ + return -EIO; + } + + /* The request was acknowledged. */ + + if ((request->cmd_code == AUX_CMD_READ) || + (request->cmd_code == AUX_CMD_I2C_READ) || + (request->cmd_code == AUX_CMD_I2C_READ_MOT)) { + /* Wait until all data has been received. */ + timeout_count = 0; + do { + status = get_reg(dev, REG_REPLY_DATA_COUNT); + + udelay(100); + timeout_count++; + if (timeout_count >= AUX_MAX_TIMEOUT_COUNT) + return -ETIMEDOUT; + } while (status != request->num_bytes); + + /* Obtain the read data from the reply FIFO. */ + for (index = 0; index < request->num_bytes; index++) + request->data[index] = get_reg(dev, REG_AUX_REPLY_DATA); + } + + return 0; +} + +/* + * Submit the supplied AUX request to the RX device over the AUX + * channel. If waiting for a reply times out, or if the DisplayPort TX core + * indicates that the request was deferred, the request is sent again (up to a + * maximum specified by AUX_MAX_DEFER_COUNT|AUX_MAX_TIMEOUT_COUNT). + */ +static int aux_request(struct udevice *dev, struct aux_transaction *request) +{ + u32 defer_count = 0; + u32 timeout_count = 0; + + while ((defer_count < AUX_MAX_DEFER_COUNT) && + (timeout_count < AUX_MAX_TIMEOUT_COUNT)) { + int status = aux_wait_ready(dev); + + if (status) { + /* The RX device isn't ready yet. */ + timeout_count++; + continue; + } + + status = aux_request_send(dev, request); + if (status == -EAGAIN) { + /* The request was deferred. */ + defer_count++; + } else if (status == -ETIMEDOUT) { + /* Waiting for a reply timed out. */ + timeout_count++; + } else { + /* -EIO indicates that the request was NACK'ed, + * 0 indicates that the request was ACK'ed. + */ + return status; + } + + udelay(100); + } + + /* The request was not successfully received by the RX device. */ + return -ETIMEDOUT; +} + +/* + * Common sequence of submitting an AUX command for + * AUX read, AUX write, I2C-over-AUX read, and I2C-over-AUX write transactions. + * If required, the reads and writes are split into multiple requests, each + * acting on a maximum of 16 bytes. + */ +static int aux_common(struct udevice *dev, u32 cmd_type, u32 address, + u32 num_bytes, u8 *data) +{ + struct aux_transaction request; + u32 bytes_left; + + /* + * set the start address for AUX transactions. For I2C transactions, + * this is the address of the I2C bus. + */ + request.address = address; + + bytes_left = num_bytes; + while (bytes_left) { + int status; + + request.cmd_code = cmd_type; + + if ((cmd_type == AUX_CMD_READ) || + (cmd_type == AUX_CMD_WRITE)) { + /* Increment address for normal AUX transactions. */ + request.address = address + (num_bytes - bytes_left); + } + + /* Increment the pointer to the supplied data buffer. */ + request.data = &data[num_bytes - bytes_left]; + + request.num_bytes = (bytes_left > 16) ? 16 : bytes_left; + bytes_left -= request.num_bytes; + + if ((cmd_type == AUX_CMD_I2C_READ) && bytes_left) { + /* Middle of a transaction I2C read request. Override + * the command code that was set to cmd_type. + */ + request.cmd_code = AUX_CMD_I2C_READ_MOT; + } else if ((cmd_type == AUX_CMD_I2C_WRITE) && bytes_left) { + /* Middle of a transaction I2C write request. Override + * the command code that was set to cmd_type. + */ + request.cmd_code = AUX_CMD_I2C_WRITE_MOT; + } + + status = aux_request(dev, &request); + if (status) + return status; + } + + return 0; +} + +/* + * Issue a read request over the AUX channel that will read from + * the RX device's DisplayPort Configuration data (DPCD) address space. The read + * message will be divided into multiple transactions which read a maximum of 16 + * bytes each. + */ +static int aux_read(struct udevice *dev, u32 dpcd_address, u32 bytes_to_read, + void *read_data) +{ + int status; + + if (!is_connected(dev)) + return -ENODEV; + + /* Send AUX read transaction. */ + status = aux_common(dev, AUX_CMD_READ, dpcd_address, + bytes_to_read, (u8 *)read_data); + + return status; +} + +/* + * Issue a write request over the AUX channel that will write to + * the RX device's DisplayPort Configuration data (DPCD) address space. The + * write message will be divided into multiple transactions which write a + * maximum of 16 bytes each. + */ +static int aux_write(struct udevice *dev, u32 dpcd_address, u32 bytes_to_write, + void *write_data) +{ + int status; + + if (!is_connected(dev)) + return -ENODEV; + + /* Send AUX write transaction. */ + status = aux_common(dev, AUX_CMD_WRITE, dpcd_address, + bytes_to_write, (u8 *)write_data); + + return status; +} + +/* core initialization */ + +static int initialize(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + u32 val; + u32 phy_config; + unsigned int k; + + /* place the PHY (and GTTXRESET) into reset. */ + phy_config = get_reg(dev, REG_PHY_CONFIG); + set_reg(dev, REG_PHY_CONFIG, phy_config | PHY_CONFIG_GT_ALL_RESET_MASK); + + /* reset the video streams and AUX logic. */ + set_reg(dev, REG_SOFT_RESET, + SOFT_RESET_VIDEO_STREAM_ALL_MASK | + SOFT_RESET_AUX_MASK); + + /* disable the DisplayPort TX core. */ + set_reg(dev, REG_ENABLE, 0); + + /* set the clock divider. */ + val = get_reg(dev, REG_AUX_CLK_DIVIDER); + val &= ~AUX_CLK_DIVIDER_VAL_MASK; + val |= dp_tx->s_axi_clk / 1000000; + set_reg(dev, REG_AUX_CLK_DIVIDER, val); + + /* set the DisplayPort TX core's clock speed. */ + set_reg(dev, REG_PHY_CLOCK_SELECT, PHY_CLOCK_SELECT_DEFAULT); + + /* bring the PHY (and GTTXRESET) out of reset. */ + set_reg(dev, REG_PHY_CONFIG, + phy_config & ~PHY_CONFIG_GT_ALL_RESET_MASK); + + /* enable the DisplayPort TX core. */ + set_reg(dev, REG_ENABLE, 1); + + /* Unmask Hot-Plug-Detect (HPD) interrupts. */ + set_reg(dev, REG_INTERRUPT_MASK, + ~INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK & + ~INTERRUPT_MASK_HPD_EVENT_MASK & + ~INTERRUPT_MASK_HPD_IRQ_MASK); + + for (k = 0; k < 4; k++) { + /* Disable pre-cursor levels. */ + set_reg(dev, REG_PHY_PRECURSOR_LANE_0 + 4 * k, 0); + + /* Write default voltage swing levels to the TX registers. */ + set_reg(dev, REG_PHY_VOLTAGE_DIFF_LANE_0 + 4 * k, 0); + + /* Write default pre-emphasis levels to the TX registers. */ + set_reg(dev, REG_PHY_POSTCURSOR_LANE_0 + 4 * k, 0); + } + + return 0; +} + +bool is_link_rate_valid(struct udevice *dev, u8 link_rate) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + bool valid = true; + + if ((link_rate != LINK_BW_SET_162GBPS) && + (link_rate != LINK_BW_SET_270GBPS) && + (link_rate != LINK_BW_SET_540GBPS)) + valid = false; + else if (link_rate > dp_tx->link_config.max_link_rate) + valid = false; + + return valid; +} + +bool is_lane_count_valid(struct udevice *dev, u8 lane_count) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + bool valid = true; + + if ((lane_count != LANE_COUNT_SET_1) && + (lane_count != LANE_COUNT_SET_2) && + (lane_count != LANE_COUNT_SET_4)) + valid = false; + else if (lane_count > dp_tx->link_config.max_lane_count) + valid = false; + + return valid; +} + +static int get_rx_capabilities(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + u8 rx_max_link_rate; + u8 rx_max_lane_count; + + if (!is_connected(dev)) + return -ENODEV; + + status = aux_read(dev, DPCD_RECEIVER_CAP_FIELD_START, 16, + dp_tx->dpcd_rx_caps); + if (status) + return -EIO; + + rx_max_link_rate = dp_tx->dpcd_rx_caps[DPCD_MAX_LINK_RATE]; + rx_max_lane_count = dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & + DPCD_MAX_LANE_COUNT_MASK; + + dp_tx->link_config.max_link_rate = + (rx_max_link_rate > dp_tx->max_link_rate) ? + dp_tx->max_link_rate : rx_max_link_rate; + if (!is_link_rate_valid(dev, rx_max_link_rate)) + return -EINVAL; + + dp_tx->link_config.max_lane_count = + (rx_max_lane_count > dp_tx->max_lane_count) ? + dp_tx->max_lane_count : rx_max_lane_count; + if (!is_lane_count_valid(dev, rx_max_lane_count)) + return -EINVAL; + + dp_tx->link_config.support_enhanced_framing_mode = + dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & + DPCD_ENHANCED_FRAME_SUPPORT_MASK; + dp_tx->link_config.support_downspread_control = + dp_tx->dpcd_rx_caps[DPCD_MAX_DOWNSPREAD] & + DPCD_MAX_DOWNSPREAD_MASK; + + return 0; +} + +static void enable_main_link(struct udevice *dev) +{ + /* reset the scrambler. */ + set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1); + + /* enable the main stream. */ + set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x1); +} + +static void disable_main_link(struct udevice *dev) +{ + /* reset the scrambler. */ + set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1); + + /* Disable the main stream. */ + set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x0); +} + +static void reset_dp_phy(struct udevice *dev, u32 reset) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + u32 val; + + set_reg(dev, REG_ENABLE, 0x0); + + val = get_reg(dev, REG_PHY_CONFIG); + + /* Apply reset. */ + set_reg(dev, REG_PHY_CONFIG, val | reset); + + /* Remove reset. */ + set_reg(dev, REG_PHY_CONFIG, val); + + /* Wait for the PHY to be ready. */ + wait_phy_ready(dev, PHY_STATUS_LANES_READY_MASK(dp_tx->max_lane_count)); + + set_reg(dev, REG_ENABLE, 0x1); +} + +/* + * enable or disable the enhanced framing symbol sequence for + * both the DisplayPort TX core and the RX device. + */ +static int set_enhanced_frame_mode(struct udevice *dev, u8 enable) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + u8 val; + + if (!is_connected(dev)) + return -ENODEV; + + if (dp_tx->link_config.support_enhanced_framing_mode) + dp_tx->link_config.enhanced_framing_mode = enable; + else + dp_tx->link_config.enhanced_framing_mode = false; + + /* Write enhanced frame mode enable to the DisplayPort TX core. */ + set_reg(dev, REG_ENHANCED_FRAME_EN, + dp_tx->link_config.enhanced_framing_mode); + + /* Write enhanced frame mode enable to the RX device. */ + status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val); + if (status) + return -EIO; + + if (dp_tx->link_config.enhanced_framing_mode) + val |= DPCD_ENHANCED_FRAME_EN_MASK; + else + val &= ~DPCD_ENHANCED_FRAME_EN_MASK; + + status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val); + if (status) + return -EIO; + + return 0; +} + +/* + * Set the number of lanes to be used by the main link for both + * the DisplayPort TX core and the RX device. + */ +static int set_lane_count(struct udevice *dev, u8 lane_count) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + u8 val; + + if (!is_connected(dev)) + return -ENODEV; + + printf(" set lane count to %u\n", lane_count); + + dp_tx->link_config.lane_count = lane_count; + + /* Write the new lane count to the DisplayPort TX core. */ + set_reg(dev, REG_LANE_COUNT_SET, dp_tx->link_config.lane_count); + + /* Write the new lane count to the RX device. */ + status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val); + if (status) + return -EIO; + val &= ~DPCD_LANE_COUNT_SET_MASK; + val |= dp_tx->link_config.lane_count; + + status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val); + if (status) + return -EIO; + + return 0; +} + +/* + * Set the clock frequency for the DisplayPort PHY corresponding + * to a desired data rate. + */ +static int set_clk_speed(struct udevice *dev, u32 speed) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + u32 val; + + /* Disable the DisplayPort TX core first. */ + val = get_reg(dev, REG_ENABLE); + set_reg(dev, REG_ENABLE, 0x0); + + /* Change speed of the feedback clock. */ + set_reg(dev, REG_PHY_CLOCK_SELECT, speed); + + /* Re-enable the DisplayPort TX core if it was previously enabled. */ + if (val) + set_reg(dev, REG_ENABLE, 0x1); + + /* Wait until the PHY is ready. */ + status = wait_phy_ready(dev, PHY_STATUS_LANES_READY_MASK(dp_tx->max_lane_count)); + if (status) + return -EIO; + + return 0; +} + +/* + * Set the data rate to be used by the main link for both the + * DisplayPort TX core and the RX device. + */ +static int set_link_rate(struct udevice *dev, u8 link_rate) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + + /* Write a corresponding clock frequency to the DisplayPort TX core. */ + switch (link_rate) { + case LINK_BW_SET_162GBPS: + printf(" set link rate to 1.62 Gb/s\n"); + status = set_clk_speed(dev, PHY_CLOCK_SELECT_162GBPS); + break; + case LINK_BW_SET_270GBPS: + printf(" set link rate to 2.70 Gb/s\n"); + status = set_clk_speed(dev, PHY_CLOCK_SELECT_270GBPS); + break; + case LINK_BW_SET_540GBPS: + printf(" set link rate to 5.40 Gb/s\n"); + status = set_clk_speed(dev, PHY_CLOCK_SELECT_540GBPS); + break; + default: + return -EINVAL; + } + if (status) + return -EIO; + + dp_tx->link_config.link_rate = link_rate; + + /* Write new link rate to the DisplayPort TX core. */ + set_reg(dev, REG_LINK_BW_SET, dp_tx->link_config.link_rate); + + /* Write new link rate to the RX device. */ + status = aux_write(dev, DPCD_LINK_BW_SET, 1, + &dp_tx->link_config.link_rate); + if (status) + return -EIO; + + return 0; +} + +/* link training */ + +/* + * Determine what the RX device's required training delay is for + * link training. + */ +static int get_training_delay(struct udevice *dev, int training_state) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + u16 delay; + + switch (dp_tx->dpcd_rx_caps[DPCD_TRAIN_AUX_RD_INTERVAL]) { + case DPCD_TRAIN_AUX_RD_INT_100_400US: + if (training_state == TS_CLOCK_RECOVERY) + /* delay for the clock recovery phase. */ + delay = 100; + else + /* delay for the channel equalization phase. */ + delay = 400; + break; + case DPCD_TRAIN_AUX_RD_INT_4MS: + delay = 4000; + break; + case DPCD_TRAIN_AUX_RD_INT_8MS: + delay = 8000; + break; + case DPCD_TRAIN_AUX_RD_INT_12MS: + delay = 12000; + break; + case DPCD_TRAIN_AUX_RD_INT_16MS: + delay = 16000; + break; + default: + /* Default to 20 ms. */ + delay = 20000; + break; + } + + return delay; +} + +/* + * Set current voltage swing and pre-emphasis level settings from + * the link_config structure to hardware. + */ +static void set_vswing_preemp(struct udevice *dev, u8 *aux_data) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + u8 data; + u8 vs_level_rx = dp_tx->link_config.vs_level; + u8 pe_level_rx = dp_tx->link_config.pe_level; + + /* Set up the data buffer for writing to the RX device. */ + data = (pe_level_rx << DPCD_TRAINING_LANEX_SET_PE_SHIFT) | vs_level_rx; + /* The maximum voltage swing has been reached. */ + if (vs_level_rx == MAXIMUM_VS_LEVEL) + data |= DPCD_TRAINING_LANEX_SET_MAX_VS_MASK; + + /* The maximum pre-emphasis level has been reached. */ + if (pe_level_rx == MAXIMUM_PE_LEVEL) + data |= DPCD_TRAINING_LANEX_SET_MAX_PE_MASK; + memset(aux_data, data, 4); +} + +/* + * Set new voltage swing and pre-emphasis levels using the + * adjustment requests obtained from the RX device. + */ +static int adj_vswing_preemp(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + u8 index; + u8 vs_level_adj_req[4]; + u8 pe_level_adj_req[4]; + u8 aux_data[4]; + u8 *ajd_reqs = &dp_tx->lane_status_ajd_reqs[4]; + + /* Analyze the adjustment requests for changes in voltage swing and + * pre-emphasis levels. + */ + vs_level_adj_req[0] = ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK; + vs_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >> + DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT; + vs_level_adj_req[2] = ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK; + vs_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >> + DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT; + pe_level_adj_req[0] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >> + DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT; + pe_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >> + DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT; + pe_level_adj_req[2] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >> + DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT; + pe_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >> + DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT; + + /* Change the drive settings to match the adjustment requests. Use the + * greatest level requested. + */ + dp_tx->link_config.vs_level = 0; + dp_tx->link_config.pe_level = 0; + for (index = 0; index < dp_tx->link_config.lane_count; index++) { + if (vs_level_adj_req[index] > dp_tx->link_config.vs_level) + dp_tx->link_config.vs_level = vs_level_adj_req[index]; + if (pe_level_adj_req[index] > dp_tx->link_config.pe_level) + dp_tx->link_config.pe_level = pe_level_adj_req[index]; + } + + /* Verify that the voltage swing and pre-emphasis combination is + * allowed. Some combinations will result in a differential peak-to-peak + * voltage that is outside the permissible range. See the VESA + * DisplayPort v1.2 Specification, section 3.1.5.2. + * The valid combinations are: + * PE=0 PE=1 PE=2 PE=3 + * VS=0 valid valid valid valid + * VS=1 valid valid valid + * VS=2 valid valid + * VS=3 valid + * + * NOTE: + * Xilinix dp_v3_1 driver seems to have an off by one error when + * limiting pe_level which is fixed here. + */ + if (dp_tx->link_config.pe_level > (3 - dp_tx->link_config.vs_level)) + dp_tx->link_config.pe_level = 3 - dp_tx->link_config.vs_level; + + /* Make the adjustments to both the DisplayPort TX core and the RX + * device. + */ + set_vswing_preemp(dev, aux_data); + /* Write the voltage swing and pre-emphasis levels for each lane to the + * RX device. + */ + status = aux_write(dev, DPCD_TRAINING_LANE0_SET, 4, aux_data); + if (status) + return -EIO; + + return 0; +} + +/* + * Do a burst AUX read from the RX device over the AUX + * channel. The contents of the status registers will be stored for later use by + * check_clock_recovery, check_channel_equalization, and + * adj_vswing_preemp. + */ +static int get_lane_status_adj_reqs(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + + /* Read and store 4 bytes of lane status and 2 bytes of adjustment + * requests. + */ + status = aux_read(dev, DPCD_STATUS_LANE_0_1, 6, + dp_tx->lane_status_ajd_reqs); + if (status) + return -EIO; + + return 0; +} + +/* + * Check if the RX device's DisplayPort Configuration data (DPCD) + * indicates that the clock recovery sequence during link training was + * successful - the RX device's link clock and data recovery unit has realized + * and maintained the frequency lock for all lanes currently in use. + */ +static int check_clock_recovery(struct udevice *dev, u8 lane_count) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + u8 *lane_status = dp_tx->lane_status_ajd_reqs; + + /* Check that all LANEx_CR_DONE bits are set. */ + switch (lane_count) { + case LANE_COUNT_SET_4: + if (!(lane_status[1] & DPCD_STATUS_LANE_3_CR_DONE_MASK)) + goto out_fail; + if (!(lane_status[1] & DPCD_STATUS_LANE_2_CR_DONE_MASK)) + goto out_fail; + /* Drop through and check lane 1. */ + case LANE_COUNT_SET_2: + if (!(lane_status[0] & DPCD_STATUS_LANE_1_CR_DONE_MASK)) + goto out_fail; + /* Drop through and check lane 0. */ + case LANE_COUNT_SET_1: + if (!(lane_status[0] & DPCD_STATUS_LANE_0_CR_DONE_MASK)) + goto out_fail; + default: + /* All (lane_count) lanes have achieved clock recovery. */ + break; + } + + return 0; + +out_fail: + return -EIO; +} + +/* + * Check if the RX device's DisplayPort Configuration data (DPCD) + * indicates that the channel equalization sequence during link training was + * successful - the RX device has achieved channel equalization, symbol lock, + * and interlane alignment for all lanes currently in use. + */ +static int check_channel_equalization(struct udevice *dev, u8 lane_count) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + u8 *lane_status = dp_tx->lane_status_ajd_reqs; + + /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */ + switch (lane_count) { + case LANE_COUNT_SET_4: + if (!(lane_status[1] & DPCD_STATUS_LANE_3_CE_DONE_MASK)) + goto out_fail; + if (!(lane_status[1] & DPCD_STATUS_LANE_2_CE_DONE_MASK)) + goto out_fail; + /* Drop through and check lane 1. */ + case LANE_COUNT_SET_2: + if (!(lane_status[0] & DPCD_STATUS_LANE_1_CE_DONE_MASK)) + goto out_fail; + /* Drop through and check lane 0. */ + case LANE_COUNT_SET_1: + if (!(lane_status[0] & DPCD_STATUS_LANE_0_CE_DONE_MASK)) + goto out_fail; + default: + /* All (lane_count) lanes have achieved channel equalization. */ + break; + } + + /* Check that all LANEx_SYMBOL_LOCKED bits are set. */ + switch (lane_count) { + case LANE_COUNT_SET_4: + if (!(lane_status[1] & DPCD_STATUS_LANE_3_SL_DONE_MASK)) + goto out_fail; + if (!(lane_status[1] & DPCD_STATUS_LANE_2_SL_DONE_MASK)) + goto out_fail; + /* Drop through and check lane 1. */ + case LANE_COUNT_SET_2: + if (!(lane_status[0] & DPCD_STATUS_LANE_1_SL_DONE_MASK)) + goto out_fail; + /* Drop through and check lane 0. */ + case LANE_COUNT_SET_1: + if (!(lane_status[0] & DPCD_STATUS_LANE_0_SL_DONE_MASK)) + goto out_fail; + default: + /* All (lane_count) lanes have achieved symbol lock. */ + break; + } + + /* Check that interlane alignment is done. */ + if (!(lane_status[2] & DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK)) + goto out_fail; + + return 0; + +out_fail: + return -EIO; +} + +/* + * Set the training pattern to be used during link training for + * both the DisplayPort TX core and the RX device. + */ +static int set_training_pattern(struct udevice *dev, u32 pattern) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + u8 aux_data[5]; + + /* Write to the DisplayPort TX core. */ + set_reg(dev, REG_TRAINING_PATTERN_SET, pattern); + + aux_data[0] = pattern; + + /* Write scrambler disable to the DisplayPort TX core. */ + switch (pattern) { + case TRAINING_PATTERN_SET_OFF: + set_reg(dev, REG_SCRAMBLING_DISABLE, 0); + dp_tx->link_config.scrambler_en = 1; + break; + case TRAINING_PATTERN_SET_TP1: + case TRAINING_PATTERN_SET_TP2: + case TRAINING_PATTERN_SET_TP3: + aux_data[0] |= DPCD_TP_SET_SCRAMB_DIS_MASK; + set_reg(dev, REG_SCRAMBLING_DISABLE, 1); + dp_tx->link_config.scrambler_en = 0; + break; + default: + break; + } + + /* Make the adjustments to both the DisplayPort TX core and the RX + * device. + */ + set_vswing_preemp(dev, &aux_data[1]); + /* Write the voltage swing and pre-emphasis levels for each lane to the + * RX device. + */ + if (pattern == TRAINING_PATTERN_SET_OFF) + status = aux_write(dev, DPCD_TP_SET, 1, aux_data); + else + status = aux_write(dev, DPCD_TP_SET, 5, aux_data); + if (status) + return -EIO; + + return 0; +} + +/* + * Run the clock recovery sequence as part of link training. The + * sequence is as follows: + * 0) Start signaling at the minimum voltage swing, pre-emphasis, and post- + * cursor levels. + * 1) Transmit training pattern 1 over the main link with symbol scrambling + * disabled. + * 2) The clock recovery loop. If clock recovery is unsuccessful after + * MaxIterations loop iterations, return. + * 2a) Wait for at least the period of time specified in the RX device's + * DisplayPort Configuration data (DPCD) register, + * TRAINING_AUX_RD_INTERVAL. + * 2b) Check if all lanes have achieved clock recovery lock. If so, return. + * 2c) Check if the same voltage swing level has been used 5 consecutive + * times or if the maximum level has been reached. If so, return. + * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as + * requested by the RX device. + * 2e) Loop back to 2a. + * For a more detailed description of the clock recovery sequence, see section + * 3.5.1.2.1 of the DisplayPort 1.2a specification document. + */ +static unsigned int training_state_clock_recovery(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + u32 delay_us; + u8 prev_vs_level = 0; + u8 same_vs_level_count = 0; + + /* Obtain the required delay for clock recovery as specified by the + * RX device. + */ + delay_us = get_training_delay(dev, TS_CLOCK_RECOVERY); + + /* Start CRLock. */ + + /* Transmit training pattern 1. */ + /* Disable the scrambler. */ + /* Start from minimal voltage swing and pre-emphasis levels. */ + dp_tx->link_config.vs_level = 0; + dp_tx->link_config.pe_level = 0; + status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP1); + if (status) + return TS_FAILURE; + + while (1) { + /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */ + udelay(delay_us); + + /* Get lane and adjustment requests. */ + status = get_lane_status_adj_reqs(dev); + if (status) + return TS_FAILURE; + + /* Check if all lanes have realized and maintained the frequency + * lock and get adjustment requests. + */ + status = check_clock_recovery(dev, + dp_tx->link_config.lane_count); + if (!status) + return TS_CHANNEL_EQUALIZATION; + + /* Check if the same voltage swing for each lane has been used 5 + * consecutive times. + */ + if (prev_vs_level == dp_tx->link_config.vs_level) { + same_vs_level_count++; + } else { + same_vs_level_count = 0; + prev_vs_level = dp_tx->link_config.vs_level; + } + if (same_vs_level_count >= 5) + break; + + /* Only try maximum voltage swing once. */ + if (dp_tx->link_config.vs_level == MAXIMUM_VS_LEVEL) + break; + + /* Adjust the drive settings as requested by the RX device. */ + status = adj_vswing_preemp(dev); + if (status) + /* The AUX write failed. */ + return TS_FAILURE; + } + + return TS_ADJUST_LINK_RATE; +} + +/* + * Run the channel equalization sequence as part of link + * training. The sequence is as follows: + * 0) Start signaling with the same drive settings used at the end of the + * clock recovery sequence. + * 1) Transmit training pattern 2 (or 3) over the main link with symbol + * scrambling disabled. + * 2) The channel equalization loop. If channel equalization is + * unsuccessful after 5 loop iterations, return. + * 2a) Wait for at least the period of time specified in the RX device's + * DisplayPort Configuration data (DPCD) register, + * TRAINING_AUX_RD_INTERVAL. + * 2b) Check if all lanes have achieved channel equalization, symbol lock, + * and interlane alignment. If so, return. + * 2c) Check if the same voltage swing level has been used 5 consecutive + * times or if the maximum level has been reached. If so, return. + * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as + * requested by the RX device. + * 2e) Loop back to 2a. + * For a more detailed description of the channel equalization sequence, see + * section 3.5.1.2.2 of the DisplayPort 1.2a specification document. + */ +static int training_state_channel_equalization(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + u32 delay_us; + u32 iteration_count = 0; + + /* Obtain the required delay for channel equalization as specified by + * the RX device. + */ + delay_us = get_training_delay(dev, TS_CHANNEL_EQUALIZATION); + + /* Start channel equalization. */ + + /* Write the current drive settings. */ + /* Transmit training pattern 2/3. */ + if (dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & DPCD_TPS3_SUPPORT_MASK) + status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP3); + else + status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP2); + + if (status) + return TS_FAILURE; + + while (iteration_count < 5) { + /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */ + udelay(delay_us); + + /* Get lane and adjustment requests. */ + status = get_lane_status_adj_reqs(dev); + if (status) + /* The AUX read failed. */ + return TS_FAILURE; + + /* Check that all lanes still have their clocks locked. */ + status = check_clock_recovery(dev, + dp_tx->link_config.lane_count); + if (status) + break; + + /* Check if all lanes have accomplished channel equalization, + * symbol lock, and interlane alignment. + */ + status = + check_channel_equalization(dev, + dp_tx->link_config.lane_count); + if (!status) + return TS_SUCCESS; + + /* Adjust the drive settings as requested by the RX device. */ + status = adj_vswing_preemp(dev); + if (status) + /* The AUX write failed. */ + return TS_FAILURE; + + iteration_count++; + } + + /* Tried 5 times with no success. Try a reduced bitrate first, then + * reduce the number of lanes. + */ + return TS_ADJUST_LINK_RATE; +} + +/* + * This function is reached if either the clock recovery or the channel + * equalization process failed during training. As a result, the data rate will + * be downshifted, and training will be re-attempted (starting with clock + * recovery) at the reduced data rate. If the data rate is already at 1.62 Gbps, + * a downshift in lane count will be attempted. + */ +static int training_state_adjust_link_rate(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + + switch (dp_tx->link_config.link_rate) { + case LINK_BW_SET_540GBPS: + status = set_link_rate(dev, LINK_BW_SET_270GBPS); + if (status) { + status = TS_FAILURE; + break; + } + status = TS_CLOCK_RECOVERY; + break; + case LINK_BW_SET_270GBPS: + status = set_link_rate(dev, LINK_BW_SET_162GBPS); + if (status) { + status = TS_FAILURE; + break; + } + status = TS_CLOCK_RECOVERY; + break; + default: + /* Already at the lowest link rate. Try reducing the lane + * count next. + */ + status = TS_ADJUST_LANE_COUNT; + break; + } + + return status; +} + +/* + * This function is reached if either the clock recovery or the channel + * equalization process failed during training, and a minimal data rate of 1.62 + * Gbps was being used. As a result, the number of lanes in use will be reduced, + * and training will be re-attempted (starting with clock recovery) at this + * lower lane count. + */ +static int trainig_state_adjust_lane_count(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + + switch (dp_tx->link_config.lane_count) { + case LANE_COUNT_SET_4: + status = set_lane_count(dev, LANE_COUNT_SET_2); + if (status) { + status = TS_FAILURE; + break; + } + + status = set_link_rate(dev, dp_tx->link_config.max_link_rate); + if (status) { + status = TS_FAILURE; + break; + } + status = TS_CLOCK_RECOVERY; + break; + case LANE_COUNT_SET_2: + status = set_lane_count(dev, LANE_COUNT_SET_1); + if (status) { + status = TS_FAILURE; + break; + } + + status = set_link_rate(dev, dp_tx->link_config.max_link_rate); + if (status) { + status = TS_FAILURE; + break; + } + status = TS_CLOCK_RECOVERY; + break; + default: + /* Already at the lowest lane count. Training has failed at the + * lowest lane count and link rate. + */ + status = TS_FAILURE; + break; + } + + return status; +} + +/* + * Check if the receiver's DisplayPort Configuration data (DPCD) + * indicates the receiver has achieved and maintained clock recovery, channel + * equalization, symbol lock, and interlane alignment for all lanes currently in + * use. + */ +static int check_link_status(struct udevice *dev, u8 lane_count) +{ + u8 retry_count = 0; + + if (!is_connected(dev)) + return -ENODEV; + + /* Retrieve AUX info. */ + do { + int status; + + /* Get lane and adjustment requests. */ + status = get_lane_status_adj_reqs(dev); + if (status) + return -EIO; + + /* Check if the link needs training. */ + if ((check_clock_recovery(dev, lane_count) == 0) && + (check_channel_equalization(dev, lane_count) == 0)) + return 0; + + retry_count++; + } while (retry_count < 5); /* Retry up to 5 times. */ + + return -EIO; +} + +/* + * Run the link training process. It is implemented as a state + * machine, with each state returning the next state. First, the clock recovery + * sequence will be run; if successful, the channel equalization sequence will + * run. If either the clock recovery or channel equalization sequence failed, + * the link rate or the number of lanes used will be reduced and training will + * be re-attempted. If training fails at the minimal data rate, 1.62 Gbps with + * a single lane, training will no longer re-attempt and fail. + * + * ### Here be dragons ### + * There are undocumented timeout constraints in the link training process. + * In DP v1.2a spec, Chapter 3.5.1.2.2 a 10ms limit for the complete training + * process is mentioned. Which individual timeouts are derived and implemented + * by sink manufacturers is unknown. So each step should be as short as possible + * and link training should start as soon as possible after HPD. + */ +static int run_training(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + int training_state = TS_CLOCK_RECOVERY; + + while (1) { + switch (training_state) { + case TS_CLOCK_RECOVERY: + training_state = + training_state_clock_recovery(dev); + break; + case TS_CHANNEL_EQUALIZATION: + training_state = + training_state_channel_equalization(dev); + break; + case TS_ADJUST_LINK_RATE: + training_state = + training_state_adjust_link_rate(dev); + break; + case TS_ADJUST_LANE_COUNT: + training_state = + trainig_state_adjust_lane_count(dev); + break; + default: + break; + } + + if (training_state == TS_SUCCESS) + break; + else if (training_state == TS_FAILURE) + return -EIO; + + if ((training_state == TS_ADJUST_LINK_RATE) || + (training_state == TS_ADJUST_LANE_COUNT)) { + if (!dp_tx->train_adaptive) + return -EIO; + + status = set_training_pattern(dev, + TRAINING_PATTERN_SET_OFF); + if (status) + return -EIO; + } + } + + /* Final status check. */ + status = check_link_status(dev, dp_tx->link_config.lane_count); + if (status) + return -EIO; + + return 0; +} + +/* link policy maker */ + +/** + * Determine the common capabilities between the DisplayPort TX + * core and the RX device. + */ +static int cfg_main_link_max(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + + if (!is_connected(dev)) + return -ENODEV; + + /* Configure the main link to the maximum common link rate between the + * DisplayPort TX core and the RX device. + */ + status = set_link_rate(dev, dp_tx->link_config.max_link_rate); + if (status) + return status; + + /* Configure the main link to the maximum common lane count between the + * DisplayPort TX core and the RX device. + */ + status = set_lane_count(dev, dp_tx->link_config.max_lane_count); + if (status) + return status; + + return 0; +} + +/* + * Check if the link needs training and runs the training + * sequence if training is required. + */ +static int establish_link(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int status; + int status2; + + reset_dp_phy(dev, PHY_CONFIG_PHY_RESET_MASK); + + /* Disable main link during training. */ + disable_main_link(dev); + + /* Wait for the PHY to be ready. */ + status = wait_phy_ready(dev, PHY_STATUS_LANES_READY_MASK(dp_tx->max_lane_count)); + if (status) + return -EIO; + + /* Train main link. */ + status = run_training(dev); + + /* Turn off the training pattern and enable scrambler. */ + status2 = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF); + if (status || status2) + return -EIO; + + return 0; +} + +/* + * Stream policy maker + */ + +/* + * Calculate the following Main Stream Attributes (MSA): + * - Transfer unit size + * - User pixel width + * - Horizontal total clock + * - Vertical total clock + * - misc_0 + * - misc_1 + * - Data per lane + * - Average number of bytes per transfer unit + * - Number of initial wait cycles + * These values are derived from: + * - Bits per color + * - Horizontal resolution + * - Vertical resolution + * - Horizontal blank start + * - Vertical blank start + * - Pixel clock (in KHz) + * - Horizontal sync polarity + * - Vertical sync polarity + * - Horizontal sync pulse width + * - Vertical sync pulse width + */ +static void cfg_msa_recalculate(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + u32 video_bw; + u32 link_bw; + u32 words_per_line; + u8 bits_per_pixel; + struct main_stream_attributes *msa_config; + struct link_config *link_config; + + msa_config = &dp_tx->main_stream_attributes; + link_config = &dp_tx->link_config; + + /* Set the user pixel width to handle clocks that exceed the + * capabilities of the DisplayPort TX core. + */ + if (msa_config->override_user_pixel_width == 0) { + if ((msa_config->pixel_clock_hz > 300000000) && + (link_config->lane_count == LANE_COUNT_SET_4)) { + msa_config->user_pixel_width = 4; + } /* Xilinx driver used 75 MHz as a limit here, 150 MHZ should + * be more sane + */ + else if ((msa_config->pixel_clock_hz > 150000000) && + (link_config->lane_count != LANE_COUNT_SET_1)) { + msa_config->user_pixel_width = 2; + } else { + msa_config->user_pixel_width = 1; + } + } + + /* Compute the rest of the MSA values. */ + msa_config->n_vid = 27 * 1000 * link_config->link_rate; + + /* Miscellaneous attributes. */ + if (msa_config->bits_per_color == 6) + msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_6BPC; + else if (msa_config->bits_per_color == 8) + msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_8BPC; + else if (msa_config->bits_per_color == 10) + msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_10BPC; + else if (msa_config->bits_per_color == 12) + msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_12BPC; + else if (msa_config->bits_per_color == 16) + msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_16BPC; + + msa_config->misc_0 = (msa_config->misc_0 << + MAIN_STREAMX_MISC0_BDC_SHIFT) | + (msa_config->y_cb_cr_colorimetry << + MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) | + (msa_config->dynamic_range << + MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) | + (msa_config->component_format << + MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) | + (msa_config->synchronous_clock_mode); + + msa_config->misc_1 = 0; + + /* Determine the number of bits per pixel for the specified color + * component format. + */ + if (msa_config->component_format == + MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422) + /* YCbCr422 color component format. */ + bits_per_pixel = msa_config->bits_per_color * 2; + else + /* RGB or YCbCr 4:4:4 color component format. */ + bits_per_pixel = msa_config->bits_per_color * 3; + + /* Calculate the data per lane. */ + words_per_line = (msa_config->h_active * bits_per_pixel); + if (words_per_line % 16) + words_per_line += 16; + words_per_line /= 16; + + msa_config->data_per_lane = words_per_line - link_config->lane_count; + if (words_per_line % link_config->lane_count) + msa_config->data_per_lane += (words_per_line % + link_config->lane_count); + + /* Allocate a fixed size for single-stream transport (SST) + * operation. + */ + msa_config->transfer_unit_size = 64; + + /* Calculate the average number of bytes per transfer unit. + * Note: Both the integer and the fractional part is stored in + * avg_bytes_per_tu. + */ + video_bw = ((msa_config->pixel_clock_hz / 1000) * bits_per_pixel) / 8; + link_bw = (link_config->lane_count * link_config->link_rate * 27); + msa_config->avg_bytes_per_tu = (video_bw * + msa_config->transfer_unit_size) / + link_bw; + + /* The number of initial wait cycles at the start of a new line + * by the framing logic. This allows enough data to be buffered + * in the input FIFO before video is sent. + */ + if ((msa_config->avg_bytes_per_tu / 1000) <= 4) + msa_config->init_wait = 64; + else + msa_config->init_wait = msa_config->transfer_unit_size - + (msa_config->avg_bytes_per_tu / 1000); +} + +/* + * Disable/enable the end of line reset to the internal video pipe in case of + * reduced blanking as required. + */ +static void set_line_reset(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + u32 reg_val; + u16 h_blank; + u16 h_reduced_blank; + struct main_stream_attributes *msa_config = + &dp_tx->main_stream_attributes; + + h_blank = msa_config->h_total - msa_config->h_active; + /* Reduced blanking starts at ceil(0.2 * HTotal). */ + h_reduced_blank = 2 * msa_config->h_total; + if (h_reduced_blank % 10) + h_reduced_blank += 10; + h_reduced_blank /= 10; + + /* CVT spec. states h_blank is either 80 or 160 for reduced blanking. */ + reg_val = get_reg(dev, REG_LINE_RESET_DISABLE); + if ((h_blank < h_reduced_blank) && + ((h_blank == 80) || (h_blank == 160))) { + reg_val |= LINE_RESET_DISABLE_MASK; + } else { + reg_val &= ~LINE_RESET_DISABLE_MASK; + } + set_reg(dev, REG_LINE_RESET_DISABLE, reg_val); +} + +/* + * Clear the main stream attributes registers of the DisplayPort + * TX core. + */ +static void clear_msa_values(struct udevice *dev) +{ + set_reg(dev, REG_MAIN_STREAM_HTOTAL, 0); + set_reg(dev, REG_MAIN_STREAM_VTOTAL, 0); + set_reg(dev, REG_MAIN_STREAM_POLARITY, 0); + set_reg(dev, REG_MAIN_STREAM_HSWIDTH, 0); + set_reg(dev, REG_MAIN_STREAM_VSWIDTH, 0); + set_reg(dev, REG_MAIN_STREAM_HRES, 0); + set_reg(dev, REG_MAIN_STREAM_VRES, 0); + set_reg(dev, REG_MAIN_STREAM_HSTART, 0); + set_reg(dev, REG_MAIN_STREAM_VSTART, 0); + set_reg(dev, REG_MAIN_STREAM_MISC0, 0); + set_reg(dev, REG_MAIN_STREAM_MISC1, 0); + set_reg(dev, REG_USER_PIXEL_WIDTH, 0); + set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, 0); + set_reg(dev, REG_M_VID, 0); + set_reg(dev, REG_N_VID, 0); + + set_reg(dev, REG_STREAM1, 0); + set_reg(dev, REG_TU_SIZE, 0); + set_reg(dev, REG_MIN_BYTES_PER_TU, 0); + set_reg(dev, REG_FRAC_BYTES_PER_TU, 0); + set_reg(dev, REG_INIT_WAIT, 0); +} + +/* + * Set the main stream attributes registers of the DisplayPort TX + * core with the values specified in the main stream attributes configuration + * structure. + */ +static void set_msa_values(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + struct main_stream_attributes *msa_config = + &dp_tx->main_stream_attributes; + + printf(" set MSA %u x %u\n", msa_config->h_active, + msa_config->v_active); + + set_reg(dev, REG_MAIN_STREAM_HTOTAL, msa_config->h_total); + set_reg(dev, REG_MAIN_STREAM_VTOTAL, msa_config->v_total); + set_reg(dev, REG_MAIN_STREAM_POLARITY, + msa_config->h_sync_polarity | + (msa_config->v_sync_polarity << + MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT)); + set_reg(dev, REG_MAIN_STREAM_HSWIDTH, msa_config->h_sync_width); + set_reg(dev, REG_MAIN_STREAM_VSWIDTH, msa_config->v_sync_width); + set_reg(dev, REG_MAIN_STREAM_HRES, msa_config->h_active); + set_reg(dev, REG_MAIN_STREAM_VRES, msa_config->v_active); + set_reg(dev, REG_MAIN_STREAM_HSTART, msa_config->h_start); + set_reg(dev, REG_MAIN_STREAM_VSTART, msa_config->v_start); + set_reg(dev, REG_MAIN_STREAM_MISC0, msa_config->misc_0); + set_reg(dev, REG_MAIN_STREAM_MISC1, msa_config->misc_1); + set_reg(dev, REG_USER_PIXEL_WIDTH, msa_config->user_pixel_width); + + set_reg(dev, REG_M_VID, msa_config->pixel_clock_hz / 1000); + set_reg(dev, REG_N_VID, msa_config->n_vid); + set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, msa_config->data_per_lane); + + set_line_reset(dev); + + set_reg(dev, REG_TU_SIZE, msa_config->transfer_unit_size); + set_reg(dev, REG_MIN_BYTES_PER_TU, msa_config->avg_bytes_per_tu / 1000); + set_reg(dev, REG_FRAC_BYTES_PER_TU, + (msa_config->avg_bytes_per_tu % 1000) * 1024 / 1000); + set_reg(dev, REG_INIT_WAIT, msa_config->init_wait); +} + +static void logicore_dp_tx_set_msa(struct udevice *dev, + struct logicore_dp_tx_msa *msa) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + + memset(&dp_tx->main_stream_attributes, 0, + sizeof(struct main_stream_attributes)); + + dp_tx->main_stream_attributes.pixel_clock_hz = msa->pixel_clock_hz; + dp_tx->main_stream_attributes.bits_per_color = msa->bits_per_color; + dp_tx->main_stream_attributes.h_active = msa->h_active; + dp_tx->main_stream_attributes.h_start = msa->h_start; + dp_tx->main_stream_attributes.h_sync_polarity = msa->h_sync_polarity; + dp_tx->main_stream_attributes.h_sync_width = msa->h_sync_width; + dp_tx->main_stream_attributes.h_total = msa->h_total; + dp_tx->main_stream_attributes.v_active = msa->v_active; + dp_tx->main_stream_attributes.v_start = msa->v_start; + dp_tx->main_stream_attributes.v_sync_polarity = msa->v_sync_polarity; + dp_tx->main_stream_attributes.v_sync_width = msa->v_sync_width; + dp_tx->main_stream_attributes.v_total = msa->v_total; + dp_tx->main_stream_attributes.override_user_pixel_width = + msa->override_user_pixel_width; + dp_tx->main_stream_attributes.user_pixel_width = msa->user_pixel_width; + dp_tx->main_stream_attributes.synchronous_clock_mode = 0; +} + +/* + * external API + */ + +int logicore_dp_tx_video_enable(struct udevice *dev, + struct logicore_dp_tx_msa *msa) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + int res; + u8 power = 0x01; + + if (!is_connected(dev)) { + printf(" no DP sink connected\n"); + return -EIO; + } + + initialize(dev); + + disable_main_link(dev); + + logicore_dp_tx_set_msa(dev, msa); + + get_rx_capabilities(dev); + + printf(" DP sink connected\n"); + aux_write(dev, DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &power); + set_enhanced_frame_mode(dev, true); + cfg_main_link_max(dev); + res = establish_link(dev); + printf(" establish_link: %s, vs: %d, pe: %d\n", + res ? "failed" : "ok", dp_tx->link_config.vs_level, + dp_tx->link_config.pe_level); + + cfg_msa_recalculate(dev); + + clear_msa_values(dev); + set_msa_values(dev); + + enable_main_link(dev); + + return 0; +} + +int logicore_dp_tx_power_on(struct udevice *dev, void *data) +{ + struct clk pixclock; + struct logicore_dp_tx_msa *msa; + struct logicore_dp_tx_msa mode_640_480_60 = { + .pixel_clock_hz = 25175000, + .bits_per_color = 8, + .h_active = 640, + .h_start = 144, + .h_sync_polarity = false, + .h_sync_width = 96, + .h_total = 800, + .v_active = 480, + .v_start = 35, + .v_sync_polarity = false, + .v_sync_width = 2, + .v_total = 525, + .override_user_pixel_width = false, + .user_pixel_width = 0, + }; + + struct logicore_dp_tx_msa mode_720_400_70 = { + .pixel_clock_hz = 28300000, + .bits_per_color = 8, + .h_active = 720, + .h_start = 162, + .h_sync_polarity = false, + .h_sync_width = 108, + .h_total = 900, + .v_active = 400, + .v_start = 37, + .v_sync_polarity = true, + .v_sync_width = 2, + .v_total = 449, + .override_user_pixel_width = false, + .user_pixel_width = 0, + }; + + struct logicore_dp_tx_msa mode_1024_768_60 = { + .pixel_clock_hz = 65000000, + .bits_per_color = 8, + .h_active = 1024, + .h_start = 296, + .h_sync_polarity = false, + .h_sync_width = 136, + .h_total = 1344, + .v_active = 768, + .v_start = 35, + .v_sync_polarity = false, + .v_sync_width = 2, + .v_total = 806, + .override_user_pixel_width = false, + .user_pixel_width = 0, + }; + + if (!strcmp(data, "1024_768_60")) + msa = &mode_1024_768_60; + else if (!strcmp(data, "720_400_70")) + msa = &mode_720_400_70; + else + msa = &mode_640_480_60; + + if (clk_get_by_index(dev, 0, &pixclock)) { + printf("%s: Could not get pixelclock\n", dev->name); + return -1; + } + clk_set_rate(&pixclock, msa->pixel_clock_hz); + + return logicore_dp_tx_video_enable(dev, msa); +} + +int logicore_dp_tx_power_off(struct udevice *dev) +{ + return 0; +} + +int logicore_dp_tx_probe(struct udevice *dev) +{ + struct dp_tx *dp_tx = dev_get_priv(dev); + + dp_tx->s_axi_clk = S_AXI_CLK_DEFAULT; + dp_tx->train_adaptive = false; + dp_tx->max_link_rate = DPCD_MAX_LINK_RATE_540GBPS; + dp_tx->max_lane_count = DPCD_MAX_LANE_COUNT_4; + + dp_tx->base = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "reg", -1); + + return 0; +} + +struct transmitter_ops logicore_dp_tx_ops = { + .power_on = logicore_dp_tx_power_on, + .power_off = logicore_dp_tx_power_off, +}; + +static const struct udevice_id logicore_dp_tx_ids[] = { + { .compatible = "gdsys,logicore_dp_tx" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(logicore_dp_tx) = { + .name = "logicore_dp_tx", + .id = UCLASS_TRANSMITTER, + .of_match = logicore_dp_tx_ids, + .probe = logicore_dp_tx_probe, + //.ofdata_to_platdata = logicore_dp_tx_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct dp_tx), + .ops = &logicore_dp_tx_ops, +}; diff --git a/drivers/transmitter/logicore_dp_tx.h b/drivers/transmitter/logicore_dp_tx.h new file mode 100644 index 0000000000..32f9649b9c --- /dev/null +++ b/drivers/transmitter/logicore_dp_tx.h @@ -0,0 +1,40 @@ +/* + * logicore_dp_tx.h + * + * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source) + * + * (C) Copyright 2016 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __GDSYS_LOGICORE_DP_TX_H__ +#define __GDSYS_LOGICORE_DP_TX_H__ + +/* + * this is a stripped down version of struct main_stream_attributes that contains + * only the parameters that are not set by cfg_msa_recalculate() + */ +struct logicore_dp_tx_msa { + u32 pixel_clock_hz; /* The pixel clock of the stream (in Hz). */ + u32 bits_per_color; /* Number of bits per color component. */ + u16 h_active; /* Horizontal active resolution (pixels) */ + u32 h_start; /* Horizontal blank start (in pixels). */ + bool h_sync_polarity; /* Horizontal sync polarity (0=negative|1=positive) */ + u16 h_sync_width; /* Horizontal sync width (pixels) */ + u16 h_total; /* Horizontal total (pixels) */ + u16 v_active; /* Vertical active resolution (lines) */ + u32 v_start; /* Vertical blank start (in lines). */ + bool v_sync_polarity; /* Vertical sync polarity (0=negative|1=positive) */ + u16 v_sync_width; /* Vertical sync width (lines) */ + u16 v_total; /* Vertical total (lines) */ + bool override_user_pixel_width; /* If true, the value stored for + user_pixel_width will be used as + the pixel width. */ + u32 user_pixel_width; /* The width of the user data input port. */ +}; + +int logicore_dp_tx_video_enable(struct udevice *dev, struct logicore_dp_tx_msa *msa); + +#endif /* __GDSYS_LOGICORE_DP_TX_H__ */ diff --git a/drivers/transmitter/logicore_dp_tx_regif.h b/drivers/transmitter/logicore_dp_tx_regif.h new file mode 100644 index 0000000000..c4105605c9 --- /dev/null +++ b/drivers/transmitter/logicore_dp_tx_regif.h @@ -0,0 +1,365 @@ +/* + * logicore_dp_tx_regif.h + * + * Register interface definition for XILINX LogiCore DisplayPort v6.1 TX (Source) + * based on Xilinx dp_v3_1 driver sources + * + * (C) Copyright 2016 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __GDSYS_LOGICORE_DP_TX_REGIF_H__ +#define __GDSYS_LOGICORE_DP_TX_REGIF_H__ + +enum { + /* link configuration field */ + REG_LINK_BW_SET = 0x000, + REG_LANE_COUNT_SET = 0x004, + REG_ENHANCED_FRAME_EN = 0x008, + REG_TRAINING_PATTERN_SET = 0x00C, + REG_LINK_QUAL_PATTERN_SET = 0x010, + REG_SCRAMBLING_DISABLE = 0x014, + REG_DOWNSPREAD_CTRL = 0x018, + REG_SOFT_RESET = 0x01C, + + /* core enables */ + REG_ENABLE = 0x080, + REG_ENABLE_MAIN_STREAM = 0x084, + REG_ENABLE_SEC_STREAM = 0x088, + REG_FORCE_SCRAMBLER_RESET = 0x0C0, + REG_MST_CONFIG = 0x0D0, + REG_LINE_RESET_DISABLE = 0x0F0, + + /* core ID */ + REG_VERSION = 0x0F8, + REG_CORE_ID = 0x0FC, + + /* AUX channel interface */ + REG_AUX_CMD = 0x100, + REG_AUX_WRITE_FIFO = 0x104, + REG_AUX_ADDRESS = 0x108, + REG_AUX_CLK_DIVIDER = 0x10C, + REG_USER_FIFO_OVERFLOW = 0x110, + REG_INTERRUPT_SIG_STATE = 0x130, + REG_AUX_REPLY_DATA = 0x134, + REG_AUX_REPLY_CODE = 0x138, + REG_AUX_REPLY_COUNT = 0x13C, + REG_INTERRUPT_STATUS = 0x140, + REG_INTERRUPT_MASK = 0x144, + REG_REPLY_DATA_COUNT = 0x148, + REG_REPLY_STATUS = 0x14C, + REG_HPD_DURATION = 0x150, + + /* main stream attributes for SST / MST STREAM1 */ + REG_STREAM1_MSA_START = 0x180, + REG_MAIN_STREAM_HTOTAL = 0x180, + REG_MAIN_STREAM_VTOTAL = 0x184, + REG_MAIN_STREAM_POLARITY = 0x188, + REG_MAIN_STREAM_HSWIDTH = 0x18C, + REG_MAIN_STREAM_VSWIDTH = 0x190, + REG_MAIN_STREAM_HRES = 0x194, + REG_MAIN_STREAM_VRES = 0x198, + REG_MAIN_STREAM_HSTART = 0x19C, + REG_MAIN_STREAM_VSTART = 0x1A0, + REG_MAIN_STREAM_MISC0 = 0x1A4, + REG_MAIN_STREAM_MISC1 = 0x1A8, + REG_M_VID = 0x1AC, + REG_TU_SIZE = 0x1B0, + REG_N_VID = 0x1B4, + REG_USER_PIXEL_WIDTH = 0x1B8, + REG_USER_DATA_COUNT_PER_LANE =0x1BC, + REG_MAIN_STREAM_INTERLACED = 0x1C0, + REG_MIN_BYTES_PER_TU = 0x1C4, + REG_FRAC_BYTES_PER_TU = 0x1C8, + REG_INIT_WAIT = 0x1CC, + REG_STREAM1 = 0x1D0, + REG_STREAM2 = 0x1D4, + REG_STREAM3 = 0x1D8, + REG_STREAM4 = 0x1DC, + + /* PHY configuration status */ + REG_PHY_CONFIG = 0x200, + REG_PHY_VOLTAGE_DIFF_LANE_0 = 0x220, + REG_PHY_VOLTAGE_DIFF_LANE_1 = 0x224, + REG_PHY_VOLTAGE_DIFF_LANE_2 = 0x228, + REG_PHY_VOLTAGE_DIFF_LANE_3 = 0x22C, + REG_PHY_TRANSMIT_PRBS7 = 0x230, + REG_PHY_CLOCK_SELECT = 0x234, + REG_PHY_POWER_DOWN = 0x238, + REG_PHY_PRECURSOR_LANE_0 = 0x23C, + REG_PHY_PRECURSOR_LANE_1 = 0x240, + REG_PHY_PRECURSOR_LANE_2 = 0x244, + REG_PHY_PRECURSOR_LANE_3 = 0x248, + REG_PHY_POSTCURSOR_LANE_0 = 0x24C, + REG_PHY_POSTCURSOR_LANE_1 = 0x250, + REG_PHY_POSTCURSOR_LANE_2 = 0x254, + REG_PHY_POSTCURSOR_LANE_3 = 0x258, + REG_PHY_STATUS = 0x280, + REG_GT_DRP_COMMAND = 0x2A0, + REG_GT_DRP_READ_DATA = 0x2A4, + REG_GT_DRP_CHANNEL_STATUS = 0x2A8, + + /* DisplayPort audio */ + REG_AUDIO_CONTROL = 0x300, + REG_AUDIO_CHANNELS = 0x304, + REG_AUDIO_INFO_DATA = 0x308, + REG_AUDIO_MAUD = 0x328, + REG_AUDIO_NAUD = 0x32C, + REG_AUDIO_EXT_DATA = 0x330, + + /* HDCP */ + REG_HDCP_ENABLE = 0x400, + + /* main stream attributes for MST STREAM2, 3, and 4 */ + REG_STREAM2_MSA_START = 0x500, + REG_STREAM3_MSA_START = 0x550, + REG_STREAM4_MSA_START = 0x5A0, + + REG_VC_PAYLOAD_BUFFER_ADDR = 0x800, +}; + +enum { + LINK_BW_SET_162GBPS = 0x06, + LINK_BW_SET_270GBPS = 0x0A, + LINK_BW_SET_540GBPS = 0x14, +}; + +enum { + LANE_COUNT_SET_1 = 0x1, + LANE_COUNT_SET_2 = 0x2, + LANE_COUNT_SET_4 = 0x4, +}; + +enum { + TRAINING_PATTERN_SET_OFF = 0x0, + /* training pattern 1 used for clock recovery */ + TRAINING_PATTERN_SET_TP1 = 0x1, + /* training pattern 2 used for channel equalization */ + TRAINING_PATTERN_SET_TP2 = 0x2, + /* training pattern 3 used for channel equalization for cores with DP v1.2 */ + TRAINING_PATTERN_SET_TP3 = 0x3, +}; + +enum { + LINK_QUAL_PATTERN_SET_OFF = 0x0, + /* D10.2 unscrambled test pattern transmitted */ + LINK_QUAL_PATTERN_SET_D102_TEST = 0x1, + /* symbol error rate measurement pattern transmitted */ + LINK_QUAL_PATTERN_SET_SER_MES = 0x2, + /* pseudo random bit sequence 7 transmitted */ + LINK_QUAL_PATTERN_SET_PRBS7 = 0x3, +}; + +enum { + SOFT_RESET_VIDEO_STREAM1_MASK = 0x00000001, + SOFT_RESET_VIDEO_STREAM2_MASK = 0x00000002, + SOFT_RESET_VIDEO_STREAM3_MASK = 0x00000004, + SOFT_RESET_VIDEO_STREAM4_MASK = 0x00000008, + SOFT_RESET_AUX_MASK = 0x00000080, + SOFT_RESET_VIDEO_STREAM_ALL_MASK = 0x0000000F, +}; + +enum { + MST_CONFIG_MST_EN_MASK = 0x00000001, +}; + +enum { + LINE_RESET_DISABLE_MASK = 0x1, +}; + +#define AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F + +#define AUX_CMD_SHIFT 8 +#define AUX_CMD_MASK 0x00000F00 +enum { + AUX_CMD_I2C_WRITE = 0x0, + AUX_CMD_I2C_READ = 0x1, + AUX_CMD_I2C_WRITE_STATUS = 0x2, + AUX_CMD_I2C_WRITE_MOT = 0x4, + AUX_CMD_I2C_READ_MOT = 0x5, + AUX_CMD_I2C_WRITE_STATUS_MOT = 0x6, + AUX_CMD_WRITE = 0x8, + AUX_CMD_READ = 0x9, +}; + +#define AUX_CLK_DIVIDER_VAL_MASK 0x00FF + +#define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 +#define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 + +enum { + INTERRUPT_SIG_STATE_HPD_STATE_MASK = 0x00000001, + INTERRUPT_SIG_STATE_REQUEST_STATE_MASK = 0x00000002, + INTERRUPT_SIG_STATE_REPLY_STATE_MASK = 0x00000004, + INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK = 0x00000008, +}; + +enum { + AUX_REPLY_CODE_ACK = 0x0, + AUX_REPLY_CODE_I2C_ACK = 0x0, + AUX_REPLY_CODE_NACK = 0x1, + AUX_REPLY_CODE_DEFER = 0x2, + AUX_REPLY_CODE_I2C_NACK = 0x4, + AUX_REPLY_CODE_I2C_DEFER = 0x8, +}; + +enum { + INTERRUPT_STATUS_HPD_IRQ_MASK = 0x00000001, + INTERRUPT_STATUS_HPD_EVENT_MASK = 0x00000002, + INTERRUPT_STATUS_REPLY_RECEIVED_MASK = 0x00000004, + INTERRUPT_STATUS_REPLY_TIMEOUT_MASK = 0x00000008, + INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK = 0x00000010, + INTERRUPT_STATUS_EXT_PKT_TXD_MASK = 0x00000020, +}; + +enum { + INTERRUPT_MASK_HPD_IRQ_MASK = 0x00000001, + INTERRUPT_MASK_HPD_EVENT_MASK = 0x00000002, + INTERRUPT_MASK_REPLY_RECEIVED_MASK = 0x00000004, + INTERRUPT_MASK_REPLY_TIMEOUT_MASK = 0x00000008, + INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK = 0x00000010, + INTERRUPT_MASK_EXT_PKT_TXD_MASK = 0x00000020, +}; + +#define REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4 +#define REPLY_STATUS_REPLY_STATUS_STATE_MASK 0x00000FF0 +enum { + REPLY_STATUS_REPLY_RECEIVED_MASK = 0x00000001, + REPLY_STATUS_REPLY_IN_PROGRESS_MASK = 0x00000002, + REPLY_STATUS_REQUEST_IN_PROGRESS_MASK = 0x00000004, + REPLY_STATUS_REPLY_ERROR_MASK = 0x00000008, +}; + +#define MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1 +enum { + MAIN_STREAMX_POLARITY_HSYNC_POL_MASK = 0x00000001, + MAIN_STREAMX_POLARITY_VSYNC_POL_MASK = 0x00000002, +}; + +enum { + MAIN_STREAMX_MISC0_SYNC_CLK_MASK = 0x00000001, +}; + +#define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1 +#define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006 +enum { + MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB = 0x0, + MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 = 0x1, + MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 = 0x2, +}; + +#define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3 +#define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008 + +#define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4 +#define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010 + +#define MAIN_STREAMX_MISC0_BDC_SHIFT 5 +#define MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0 +enum { + MAIN_STREAMX_MISC0_BDC_6BPC = 0x0, + MAIN_STREAMX_MISC0_BDC_8BPC = 0x1, + MAIN_STREAMX_MISC0_BDC_10BPC = 0x2, + MAIN_STREAMX_MISC0_BDC_12BPC = 0x3, + MAIN_STREAMX_MISC0_BDC_16BPC = 0x4, +}; + +enum { + PHY_CONFIG_PHY_RESET_ENABLE_MASK = 0x0000000, + PHY_CONFIG_PHY_RESET_MASK = 0x0000001, + PHY_CONFIG_GTTX_RESET_MASK = 0x0000002, + PHY_CONFIG_GT_ALL_RESET_MASK = 0x0000003, + PHY_CONFIG_TX_PHY_PMA_RESET_MASK = 0x0000100, + PHY_CONFIG_TX_PHY_PCS_RESET_MASK = 0x0000200, + PHY_CONFIG_TX_PHY_POLARITY_MASK = 0x0000800, + PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK = 0x0001000, + PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK = 0x0010000, + PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK = 0x0020000, + PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK = 0x0040000, + PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK = 0x0080000, + PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK = 0x0100000, + PHY_CONFIG_TX_PHY_8B10BEN_MASK = 0x0200000, +}; + +#define PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13 +#define PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x000E000 + +enum { + PHY_CLOCK_SELECT_162GBPS = 0x1, + PHY_CLOCK_SELECT_270GBPS = 0x3, + PHY_CLOCK_SELECT_540GBPS = 0x5, +}; + +enum { + VS_LEVEL_0 = 0x2, + VS_LEVEL_1 = 0x5, + VS_LEVEL_2 = 0x8, + VS_LEVEL_3 = 0xF, + VS_LEVEL_OFFSET = 0x4, +}; + +enum { + PE_LEVEL_0 = 0x00, + PE_LEVEL_1 = 0x0E, + PE_LEVEL_2 = 0x14, + PE_LEVEL_3 = 0x1B, +}; + +enum { + PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT = 2, + PHY_STATUS_TX_ERROR_LANE_0_SHIFT = 18, + PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT = 20, + PHY_STATUS_TX_ERROR_LANE_1_SHIFT = 22, + PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT = 16, + PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT = 24, + PHY_STATUS_TX_ERROR_LANE_2_SHIFT = 26, + PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT = 28, + PHY_STATUS_TX_ERROR_LANE_3_SHIFT = 30, +}; + +enum { + PHY_STATUS_RESET_LANE_0_DONE_MASK = 0x00000001, + PHY_STATUS_RESET_LANE_1_DONE_MASK = 0x00000002, + PHY_STATUS_RESET_LANE_2_3_DONE_MASK = 0x0000000C, + PHY_STATUS_PLL_LANE0_1_LOCK_MASK = 0x00000010, + PHY_STATUS_PLL_LANE2_3_LOCK_MASK = 0x00000020, + PHY_STATUS_PLL_FABRIC_LOCK_MASK = 0x00000040, + PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK = 0x00030000, + PHY_STATUS_TX_ERROR_LANE_0_MASK = 0x000C0000, + PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK = 0x00300000, + PHY_STATUS_TX_ERROR_LANE_1_MASK = 0x00C00000, + PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK = 0x03000000, + PHY_STATUS_TX_ERROR_LANE_2_MASK = 0x0C000000, + PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK = 0x30000000, + PHY_STATUS_TX_ERROR_LANE_3_MASK = 0xC0000000, +}; + +#define PHY_STATUS_LANE_0_READY_MASK \ + (PHY_STATUS_RESET_LANE_0_DONE_MASK | \ + PHY_STATUS_PLL_LANE0_1_LOCK_MASK) +#define PHY_STATUS_LANES_0_1_READY_MASK \ + (PHY_STATUS_LANE_0_READY_MASK | \ + PHY_STATUS_RESET_LANE_1_DONE_MASK) +/* + * PHY_STATUS_ALL_LANES_READY_MASK seems zo be missing lanes 0 and 1 in + * Xilinx dp_v3_0 implementation + */ +#define PHY_STATUS_ALL_LANES_READY_MASK \ + (PHY_STATUS_LANES_0_1_READY_MASK | \ + PHY_STATUS_RESET_LANE_2_3_DONE_MASK | \ + PHY_STATUS_PLL_LANE2_3_LOCK_MASK) +#define PHY_STATUS_LANES_READY_MASK(n) \ + (((n) > 2) ? PHY_STATUS_ALL_LANES_READY_MASK : \ + ((n) == 2) ? PHY_STATUS_LANES_0_1_READY_MASK : \ + PHY_STATUS_LANE_0_READY_MASK) + +#define GT_DRP_COMMAND_DRP_ADDR_MASK 0x000F +#define GT_DRP_COMMAND_DRP_RW_CMD_MASK 0x0080 +#define GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16 +#define GT_DRP_COMMAND_DRP_W_DATA_MASK 0xFF00 + +#define HDCP_ENABLE_BYPASS_DISABLE_MASK 0x0001 + +#endif /* __GDSYS_LOGICORE_DP_TX_REGIF_H__ */