Albert, Fabio, All,

On Tue, Sep 22, 2015 at 09:21:37PM +0200, Albert ARIBAUD wrote:

Hi Fabio,

Le Tue, 22 Sep 2015 16:01:05 -0300, Fabio Estevam <festevam at gmail.com> a ?crit :

...

Hi,

On a mx6q (armv7) board when I disable and enable the Data Cache the following issue is observed:

=> dcache Data (writethrough) Cache is ON => dcache off => dcache on data abort pc : [<4ff3d340>] lr : [<4ff3b598>] reloc pc : [<17802340>] lr : [<17800598>] sp : 4f538d50 ip : 00000000 fp : 4f841188 r10: 4ffa4fd4 r9 : 4f538eb0 r8 : 00000002 r7 : 4f539de8 r6 : 00000000 r5 : 00000000 r4 : 00000000 r3 : 00a02000 r2 : 32450000 r1 : 4ff94732 r0 : 00000001 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ...

resetting ...

U-Boot 2015.10-rc3-24232-g324714b-dirty (Sep 22 2015 - 15:08:16 -0300)

CPU: Freescale i.MX6DL rev1.1 996 MHz (running at 792 MHz)

Does anyone have any ideas about this?

No idea with so little context, but the (reloc) pc should indicate where in the code the abort happened. Maybe that will give us a clue.

Does anyone have an update on this issue? I just experienced the same problem with an i.MX6SX: Hit any key to stop autoboot: 0 => dcache off => dcache on data abort pc : [<bff4a564>] lr : [<bff4a5f4>] reloc pc : [<87800564>] lr : [<878005f4>] sp : bf347d70 ip : 00000000 fp : bf34bb48 r10: bffa3c58 r9 : bf347ed8 r8 : 00000002 r7 : bf349c28 r6 : 00000000 r5 : 00000000 r4 : 00000000 r3 : 00a02000 r2 : 32430000 r1 : bff99a70 r0 : 00000001 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ...

Looking at the reloc pc: 87800550 <v7_outer_cache_enable>: 87800550: e59f304c ldr r3, [pc, #76] ; 878005a4 <v7_outer_cache_enable+0x54> 87800554: e5932104 ldr r2, [r3, #260] ; 0x104 87800558: e3822501 orr r2, r2, #4194304 ; 0x400000 8780055c: e5832104 str r2, [r3, #260] ; 0x104 87800560: e5932100 ldr r2, [r3, #256] ; 0x100 87800564: e3c22001 bic r2, r2, #1

Then looking at arch/arm/cpu/armv7/mx6/soc.c, it looks like the cause is: http://git.denx.de/?p=u-boot.git;a=commit;h=b4ed9f8

When commenting out "setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE)", the problem disappears.

Should we unset the bit22 when disabling cache?

Regards, Gary

Hi Gary,

On Tue, Nov 24, 2015 at 9:38 AM, Gary Bisson gary.bisson@boundarydevices.com wrote:

...

Does anyone have an update on this issue? I just experienced the same problem with an i.MX6SX: Hit any key to stop autoboot: 0 => dcache off => dcache on data abort pc : [<bff4a564>] lr : [<bff4a5f4>] reloc pc : [<87800564>] lr : [<878005f4>] sp : bf347d70 ip : 00000000 fp : bf34bb48 r10: bffa3c58 r9 : bf347ed8 r8 : 00000002 r7 : bf349c28 r6 : 00000000 r5 : 00000000 r4 : 00000000 r3 : 00a02000 r2 : 32430000 r1 : bff99a70 r0 : 00000001 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ...

Looking at the reloc pc: 87800550 <v7_outer_cache_enable>: 87800550: e59f304c ldr r3, [pc, #76] ; 878005a4 <v7_outer_cache_enable+0x54> 87800554: e5932104 ldr r2, [r3, #260] ; 0x104 87800558: e3822501 orr r2, r2, #4194304 ; 0x400000 8780055c: e5832104 str r2, [r3, #260] ; 0x104 87800560: e5932100 ldr r2, [r3, #256] ; 0x100 87800564: e3c22001 bic r2, r2, #1

Then looking at arch/arm/cpu/armv7/mx6/soc.c, it looks like the cause is: http://git.denx.de/?p=u-boot.git;a=commit;h=b4ed9f8

When commenting out "setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE)", the problem disappears.

Should we unset the bit22 when disabling cache?

Thanks for looking into this.

Catalin,

Do you know if we should unset L310_SHARED_ATT_OVERRIDE_ENABLE bit when disabling cache?

Any suggestions?

Thanks,

Fabio Estevam