This driver support the standard PWM API for MediaTek MT7623, MT7622 and MT7629 SoCs

Signed-off-by: Sam Shih sam.shih@mediatek.com --- drivers/pwm/Kconfig | 7 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-mtk.c | 188 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 196 insertions(+) create mode 100644 drivers/pwm/pwm-mtk.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 1f36fc78fa..edb3f0f538 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -23,6 +23,13 @@ config PWM_IMX help This PWM is found i.MX27 and later i.MX SoCs.

+config PWM_MTK + bool "Enable support for MediaTek PWM" + depends on DM_PWM + help + This PWM is found on MT7622, MT7623, and MT7629. It supports a + programmable period and duty cycle. + config PWM_ROCKCHIP bool "Enable support for the Rockchip PWM" depends on DM_PWM diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index a837c35ed2..2c3a069006 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o

obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o +obj-$(CONFIG_PWM_MTK) += pwm-mtk.o obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o obj-$(CONFIG_PWM_SANDBOX) += sandbox_pwm.o obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c new file mode 100644 index 0000000000..97ed477025 --- /dev/null +++ b/drivers/pwm/pwm-mtk.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Sam Shih sam.shih@mediatek.com + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <pwm.h> +#include <div64.h> +#include <linux/bitops.h> +#include <linux/io.h> + +/* PWM registers and bits definitions */ +#define PWMCON 0x00 +#define PWMHDUR 0x04 +#define PWMLDUR 0x08 +#define PWMGDUR 0x0c +#define PWMWAVENUM 0x28 +#define PWMDWIDTH 0x2c +#define PWM45DWIDTH_FIXUP 0x30 +#define PWMTHRES 0x30 +#define PWM45THRES_FIXUP 0x34 + +#define PWM_CLK_DIV_MAX 7 +#define MAX_PWM_NUM 8 + +#define NSEC_PER_SEC 1000000000L + +static const unsigned int mtk_pwm_reg_offset[] = { + 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 +}; + +struct mtk_pwm_soc { + unsigned int num_pwms; + bool pwm45_fixup; +}; + +struct mtk_pwm_priv { + void __iomem *base; + struct clk top_clk; + struct clk main_clk; + struct clk pwm_clks[MAX_PWM_NUM]; + const struct mtk_pwm_soc *soc; +}; + +static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val) +{ + struct mtk_pwm_priv *priv = dev_get_priv(dev); + u32 offset = mtk_pwm_reg_offset[channel]; + + writel(val, priv->base + offset + reg); +} + +static int mtk_pwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct mtk_pwm_priv *priv = dev_get_priv(dev); + u32 clkdiv = 0, clksel = 0, cnt_period, cnt_duty, + reg_width = PWMDWIDTH, reg_thres = PWMTHRES; + u64 resolution; + int ret = 0; + + clk_enable(&priv->top_clk); + clk_enable(&priv->main_clk); + /* Using resolution in picosecond gets accuracy higher */ + resolution = (u64)NSEC_PER_SEC * 1000; + do_div(resolution, clk_get_rate(&priv->pwm_clks[channel])); + cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); + while (cnt_period > 8191) { + resolution *= 2; + clkdiv++; + cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, + resolution); + if (clkdiv > PWM_CLK_DIV_MAX && clksel == 0) { + clksel = 1; + clkdiv = 0; + resolution = (u64)NSEC_PER_SEC * 1000 * 1625; + do_div(resolution, + clk_get_rate(&priv->pwm_clks[channel])); + cnt_period = DIV_ROUND_CLOSEST_ULL( + (u64)period_ns * 1000, resolution); + clk_enable(&priv->pwm_clks[channel]); + } + } + if (clkdiv > PWM_CLK_DIV_MAX && clksel == 1) { + printf("pwm period %u not supported\n", period_ns); + return -EINVAL; + } + if (priv->soc->pwm45_fixup && channel > 2) { + /* + * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES + * from the other PWMs on MT7623. + */ + reg_width = PWM45DWIDTH_FIXUP; + reg_thres = PWM45THRES_FIXUP; + } + cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); + if (clksel == 1) + mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | BIT(3) | clkdiv); + else + mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | clkdiv); + mtk_pwm_w32(dev, channel, reg_width, cnt_period); + mtk_pwm_w32(dev, channel, reg_thres, cnt_duty); + + return ret; +}; + +static int mtk_pwm_set_enable(struct udevice *dev, uint channel, bool enable) +{ + struct mtk_pwm_priv *priv = dev_get_priv(dev); + u32 val = 0; + + val = readl(priv->base); + if (enable) + val |= BIT(channel); + else + val &= ~BIT(channel); + writel(val, priv->base); + + return 0; +}; + +static int mtk_pwm_probe(struct udevice *dev) +{ + struct mtk_pwm_priv *priv = dev_get_priv(dev); + int ret = 0; + int i; + + priv->soc = (struct mtk_pwm_soc *)dev_get_driver_data(dev); + priv->base = (void __iomem *)devfdt_get_addr(dev); + if (!priv->base) + return -EINVAL; + ret = clk_get_by_name(dev, "top", &priv->top_clk); + if (ret < 0) + return ret; + ret = clk_get_by_name(dev, "main", &priv->main_clk); + if (ret < 0) + return ret; + for (i = 0; i < priv->soc->num_pwms; i++) { + char name[8]; + + snprintf(name, sizeof(name), "pwm%d", i + 1); + ret = clk_get_by_name(dev, name, &priv->pwm_clks[i]); + if (ret < 0) + return ret; + } + + return ret; +} + +static const struct pwm_ops mtk_pwm_ops = { + .set_config = mtk_pwm_set_config, + .set_enable = mtk_pwm_set_enable, +}; + +static const struct mtk_pwm_soc mt7622_data = { + .num_pwms = 6, + .pwm45_fixup = false, +}; + +static const struct mtk_pwm_soc mt7623_data = { + .num_pwms = 5, + .pwm45_fixup = true, +}; + +static const struct mtk_pwm_soc mt7629_data = { + .num_pwms = 1, + .pwm45_fixup = false, +}; + +static const struct udevice_id mtk_pwm_ids[] = { + { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data }, + { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data }, + { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data }, + { } +}; + +U_BOOT_DRIVER(mtk_pwm) = { + .name = "mtk_pwm", + .id = UCLASS_PWM, + .of_match = mtk_pwm_ids, + .ops = &mtk_pwm_ops, + .probe = mtk_pwm_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pwm_priv), +};

This patch add pwm support for mt7622, mt7623 and mt7629 SoCs

Signed-off-by: Sam Shih sam.shih@mediatek.com --- arch/arm/dts/mt7622.dtsi | 19 +++++++++++++++++++ arch/arm/dts/mt7623.dtsi | 17 +++++++++++++++++ arch/arm/dts/mt7629.dtsi | 16 ++++++++++++++++ 3 files changed, 52 insertions(+)

diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 1e8ec9b48b..f9ce0c6c3e 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -227,4 +227,23 @@ #clock-cells = <1>; };

+ pwm: pwm@11006000 { + compatible = "mediatek,mt7622-pwm"; + reg = <0x11006000 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM_PD>, + <&pericfg CLK_PERI_PWM1_PD>, + <&pericfg CLK_PERI_PWM2_PD>, + <&pericfg CLK_PERI_PWM3_PD>, + <&pericfg CLK_PERI_PWM4_PD>, + <&pericfg CLK_PERI_PWM5_PD>, + <&pericfg CLK_PERI_PWM6_PD>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", + "pwm5", "pwm6"; + status = "disabled"; + }; + }; diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 1f45dea575..0452889ef8 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -400,4 +400,21 @@ mediatek,ethsys = <&ethsys>; status = "disabled"; }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt7623-pwm"; + reg = <0x11006000 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM>, + <&pericfg CLK_PERI_PWM1>, + <&pericfg CLK_PERI_PWM2>, + <&pericfg CLK_PERI_PWM3>, + <&pericfg CLK_PERI_PWM4>, + <&pericfg CLK_PERI_PWM5>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", + "pwm5"; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index a33a74a556..644d2da4a8 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -281,4 +281,20 @@ reg = <0x1b130000 0x1000>; #clock-cells = <1>; }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt7629-pwm"; + reg = <0x11006000 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM_PD>, + <&pericfg CLK_PERI_PWM1_PD>; + clock-names = "top", "main", "pwm1"; + assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>; + status = "disabled"; + }; + };

The binman-option BINMAN_FDT is introduced by this commit: commit 3c10dc95bdd0 ("binman: Add a library to access binman entries") BINMAN_FDT being selected when BINMAN=y that resulting in mt7623 and mt7622 are unable to boot. The root cause of this issue is commit: commit cbd2fba1eca1 ("arm: MediaTek: add basic support for MT7629 boards") select BINMAN=y in all mediatek SoCs, and others mediatek SoCs not expect to use BINMAN_FDT. This patch remove BINMAN=y option when ARCH_MEDIATEK=y and move this to the specify SoCs part config.

Signed-off-by: Sam Shih sam.shih@mediatek.com --- arch/arm/Kconfig | 1 - arch/arm/mach-mediatek/Kconfig | 1 + 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8d9f7fcce7..9ca3d90aa2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -778,7 +778,6 @@ config ARCH_MESON

config ARCH_MEDIATEK bool "MediaTek SoCs" - select BINMAN select DM select OF_CONTROL select SPL_DM if SPL diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 17b84db5a8..0042e57017 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -36,6 +36,7 @@ config TARGET_MT7629 bool "MediaTek MT7629 SoC" select CPU_V7A select SPL + select BINMAN help The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,