[U-Boot] [PATCH 0/5] sunxi: GPIO, AHCI and Cubieboard 2 support.
The following enables AHCI support for sun7i boards, which in turn requires GPIO support. It also adds support for the Cubieboard2 board.
This is based on Hans' "sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements" series[0]. (Other than e.g. boards.cfg and Makefile diff context it only actually depends on "sunxi: Add support for using MII phy-s with the GMAC nic").
I've also pushed to my gitorious tree.
The following changes since commit b0d49d895cd07ae14e81aa429b570a13ab82bb08:
sunxi: Add support for using MII phy-s with the GMAC nic (2014-05-31 10:26:47 +0200)
are available in the git repository at:
git://gitorious.org/ijc/u-boot.git sunxi-gpio-ahci-and-cubieboard2
for you to fetch changes up to a0fd41759d6ef9313a532c418e518be15ec37fd7:
ahci: provide sunxi SATA driver using AHCI platform framework (2014-05-31 17:23:28 +0100)
---------------------------------------------------------------- Ian Campbell (5): AHCI: Increase link timeout to 200ms board_r: run scsi init() on ARM too sunxi: add Cubieboard2 support sunxi: add gpio driver ahci: provide sunxi SATA driver using AHCI platform framework
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 7 +- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 11 ++- arch/arm/include/asm/arch-sunxi/gpio.h | 2 + board/sunxi/Makefile | 2 + board/sunxi/ahci.c | 84 +++++++++++++++++++++ board/sunxi/dram_cubieboard2.c | 31 ++++++++ boards.cfg | 8 +- common/board_r.c | 6 +- drivers/block/ahci.c | 18 ++++- drivers/gpio/Makefile | 1 + drivers/gpio/sunxi_gpio.c | 102 ++++++++++++++++++++++++++ include/ahci.h | 4 + include/configs/sunxi-common.h | 16 ++++ 13 files changed, 278 insertions(+), 14 deletions(-) create mode 100644 board/sunxi/ahci.c create mode 100644 board/sunxi/dram_cubieboard2.c create mode 100644 drivers/gpio/sunxi_gpio.c
Ian.
[0] https://github.com/jwrdegoede/u-boot-sunxi/tree/sun4i-upstreaming-v1
In 73545f75b66d "ahci: wait longer for link" I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Karsten Merker merker@debian.org --- drivers/block/ahci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index c8f6573..4df8046 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -41,7 +41,7 @@ u16 *ataid[AHCI_MAX_PORTS]; #define WAIT_MS_SPINUP 20000 #define WAIT_MS_DATAIO 5000 #define WAIT_MS_FLUSH 5000 -#define WAIT_MS_LINKUP 40 +#define WAIT_MS_LINKUP 200
static inline u32 ahci_port_base(u32 base, u32 port) {
On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote:
In 73545f75b66d "ahci: wait longer for link" I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Karsten Merker merker@debian.org
Is there no way to poll for this condition instead of using an ever-growing timeout?
Best regards, Marek Vasut
On Fri, 2014-07-04 at 16:58 +0200, Marek Vasut wrote:
On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote:
In 73545f75b66d "ahci: wait longer for link" I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Karsten Merker merker@debian.org
Is there no way to poll for this condition instead of using an ever-growing timeout?
This timeout is the maximum time to poll for. If the device is ready sooner (likely) then we'll notice that and carry one.
Ian.
On Friday, July 04, 2014 at 05:26:40 PM, Ian Campbell wrote:
On Fri, 2014-07-04 at 16:58 +0200, Marek Vasut wrote:
On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote:
In 73545f75b66d "ahci: wait longer for link" I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Karsten Merker merker@debian.org
Is there no way to poll for this condition instead of using an ever-growing timeout?
This timeout is the maximum time to poll for. If the device is ready sooner (likely) then we'll notice that and carry one.
And if the device is never ready, then we will wait 200mS for nothing ?
Best regards, Marek Vasut
On Fri, 2014-07-04 at 17:44 +0200, Marek Vasut wrote:
On Friday, July 04, 2014 at 05:26:40 PM, Ian Campbell wrote:
On Fri, 2014-07-04 at 16:58 +0200, Marek Vasut wrote:
On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote:
In 73545f75b66d "ahci: wait longer for link" I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Karsten Merker merker@debian.org
Is there no way to poll for this condition instead of using an ever-growing timeout?
This timeout is the maximum time to poll for. If the device is ready sooner (likely) then we'll notice that and carry one.
And if the device is never ready, then we will wait 200mS for nothing ?
If you've typed "scsi scan", yes.
Does u-boot have any mechanisms to do anything else though?
Ian.
This has been disabled for ARM in initr_scsi since that function was introduced. However it works fine for me on Cubieboard and Cubietruck (with the upcoming AHCI glue patch).
I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI: - highbank worked fine (on midway hardware) - omap5_uevm built OK and I confirmed using objdump that things were as expected (i.e. the default weak scsi_init nop was used).
While there remove the mismatched comment from the #endif (omitting the comment seems to be the prevailing style in this file) and add a missing return to initr_doc which I happened to spot while editing.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Simon Glass sjg@chromium.org --- common/board_r.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c index 602a239..427ee67 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -588,21 +588,19 @@ static int initr_status_led(void) #if defined(CONFIG_CMD_SCSI) static int initr_scsi(void) { - /* Not supported properly on ARM yet */ -#ifndef CONFIG_ARM puts("SCSI: "); scsi_init(); -#endif
return 0; } -#endif /* CONFIG_CMD_NET */ +#endif
#if defined(CONFIG_CMD_DOC) static int initr_doc(void) { puts("DOC: "); doc_init(); + return 0 } #endif
Hi Ian,
On 31 May 2014 10:36, Ian Campbell ijc@hellion.org.uk wrote:
This has been disabled for ARM in initr_scsi since that function was introduced. However it works fine for me on Cubieboard and Cubietruck (with the upcoming AHCI glue patch).
I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI:
- highbank worked fine (on midway hardware)
- omap5_uevm built OK and I confirmed using objdump that things were as expected (i.e. the default weak scsi_init nop was used).
While there remove the mismatched comment from the #endif (omitting the comment seems to be the prevailing style in this file) and add a missing return to initr_doc which I happened to spot while editing.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Simon Glass sjg@chromium.org
I see no build breakage for ARM boards with this patch.
Acked-by: Simon Glass sjg@chromium.org
Regards, Simon
On Saturday, May 31, 2014 at 06:36:12 PM, Ian Campbell wrote:
This has been disabled for ARM in initr_scsi since that function was introduced. However it works fine for me on Cubieboard and Cubietruck (with the upcoming AHCI glue patch).
Does this break bisectability ?
I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI: - highbank worked fine (on midway hardware)
- omap5_uevm built OK and I confirmed using objdump that things were as expected (i.e. the default weak scsi_init nop was used).
While there remove the mismatched comment from the #endif (omitting the comment seems to be the prevailing style in this file) and add a missing return to initr_doc which I happened to spot while editing.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Simon Glass sjg@chromium.org
Make sure to check no ARM boards call scsi_init() from their board files.
Best regards, Marek Vasut
On Fri, 2014-07-04 at 16:59 +0200, Marek Vasut wrote:
On Saturday, May 31, 2014 at 06:36:12 PM, Ian Campbell wrote:
This has been disabled for ARM in initr_scsi since that function was introduced. However it works fine for me on Cubieboard and Cubietruck (with the upcoming AHCI glue patch).
Does this break bisectability ?
Not if this patch goes in first.
I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI: - highbank worked fine (on midway hardware)
- omap5_uevm built OK and I confirmed using objdump that things were as expected (i.e. the default weak scsi_init nop was used).
While there remove the mismatched comment from the #endif (omitting the comment seems to be the prevailing style in this file) and add a missing return to initr_doc which I happened to spot while editing.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Simon Glass sjg@chromium.org
Make sure to check no ARM boards call scsi_init() from their board files.
I grepped around and couldn't find any.
On Friday, July 04, 2014 at 05:25:10 PM, Ian Campbell wrote:
On Fri, 2014-07-04 at 16:59 +0200, Marek Vasut wrote:
On Saturday, May 31, 2014 at 06:36:12 PM, Ian Campbell wrote:
This has been disabled for ARM in initr_scsi since that function was introduced. However it works fine for me on Cubieboard and Cubietruck (with the upcoming AHCI glue patch).
Does this break bisectability ?
Not if this patch goes in first.
I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI: - highbank worked fine (on midway hardware)
- omap5_uevm built OK and I confirmed using objdump that things were
as
expected (i.e. the default weak scsi_init nop was used).
While there remove the mismatched comment from the #endif (omitting the comment seems to be the prevailing style in this file) and add a missing return to initr_doc which I happened to spot while editing.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Simon Glass sjg@chromium.org
Make sure to check no ARM boards call scsi_init() from their board files.
I grepped around and couldn't find any.
OK, thanks!
Best regards, Marek Vasut
This is a sun7i (A20) based followup to the sun4i (A10) Cubieboard. It has GMAC using MII mode.
Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Hans de Goede hdegoede@redhat.com --- board/sunxi/Makefile | 1 + board/sunxi/dram_cubieboard2.c | 31 +++++++++++++++++++++++++++++++ boards.cfg | 2 ++ 3 files changed, 34 insertions(+) create mode 100644 board/sunxi/dram_cubieboard2.c
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 7083632..62acb8f 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -12,5 +12,6 @@ obj-y += board.o obj-$(CONFIG_SUNXI_GMAC) += gmac.o obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o +obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o diff --git a/board/sunxi/dram_cubieboard2.c b/board/sunxi/dram_cubieboard2.c new file mode 100644 index 0000000..9e75367 --- /dev/null +++ b/board/sunxi/dram_cubieboard2.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 480, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 32, + .cas = 9, + .zq = 0x7f, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0x0, + .tpr4 = 0x1, + .tpr5 = 0x0, + .emr1 = 0x4, + .emr2 = 0x10, + .emr3 = 0x0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/boards.cfg b/boards.cfg index 1d31e4d..c000910 100644 --- a/boards.cfg +++ b/boards.cfg @@ -383,6 +383,8 @@ Active arm armv7 s5pc1xx samsung smdkc100 Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede hdegoede@redhat.com Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC Hans de Goede hdegoede@redhat.com +Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC Hans de Goede hdegoede@redhat.com:Ian Campbell ijc@hellion.org.uk +Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC Hans de Goede hdegoede@redhat.com:Ian Campbell ijc@hellion.org.uk Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Hans de Goede hdegoede@redhat.com Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Hans de Goede hdegoede@redhat.com Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER Hans de Goede hdegoede@redhat.com
This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well as providing the common gpio API (gpio_request/free, direction in/out, get/set etc).
Signed-off-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Hans de Goede hdegoede@redhat.com Signed-off-by: Ma Haijun mahaijuns@gmail.com Signed-off-by: Oliver Schinagl oliver@schinagl.nl Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Henrik Nordström henrik@henriknordstrom.net Cc: Tom Cubie Mr.hipboi@gmail.com --- arch/arm/include/asm/arch-sunxi/gpio.h | 2 + drivers/gpio/Makefile | 1 + drivers/gpio/sunxi_gpio.c | 102 +++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 4 ++ 4 files changed, 109 insertions(+) create mode 100644 drivers/gpio/sunxi_gpio.c
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 892479c..f7f3d8c 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -143,5 +143,7 @@ int sunxi_gpio_set_cfgpin(u32 pin, u32 val); int sunxi_gpio_get_cfgpin(u32 pin); int sunxi_gpio_set_drv(u32 pin, u32 val); int sunxi_gpio_set_pull(u32 pin, u32 val); +int sunxi_name_to_gpio(const char *name); +#define name_to_gpio(name) sunxi_name_to_gpio(name)
#endif /* _SUNXI_GPIO_H */ diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 4e001e1..86813b9 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -34,3 +34,4 @@ obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o obj-$(CONFIG_TCA642X) += tca642x.o oby-$(CONFIG_SX151X) += sx151x.o +obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c new file mode 100644 index 0000000..0c50a8f --- /dev/null +++ b/drivers/gpio/sunxi_gpio.c @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom henrik@henriknordstrom.net + * + * Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c: + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/gpio.h> + +static int sunxi_gpio_output(u32 pin, u32 val) +{ + u32 dat; + u32 bank = GPIO_BANK(pin); + u32 num = GPIO_NUM(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + dat = readl(&pio->dat); + if (val) + dat |= 0x1 << num; + else + dat &= ~(0x1 << num); + + writel(dat, &pio->dat); + + return 0; +} + +static int sunxi_gpio_input(u32 pin) +{ + u32 dat; + u32 bank = GPIO_BANK(pin); + u32 num = GPIO_NUM(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + dat = readl(&pio->dat); + dat >>= num; + + return dat & 0x1; +} + +int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +int gpio_free(unsigned gpio) +{ + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT); + + return sunxi_gpio_input(gpio); +} + +int gpio_direction_output(unsigned gpio, int value) +{ + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT); + + return sunxi_gpio_output(gpio, value); +} + +int gpio_get_value(unsigned gpio) +{ + return sunxi_gpio_input(gpio); +} + +int gpio_set_value(unsigned gpio, int value) +{ + return sunxi_gpio_output(gpio, value); +} + +int sunxi_name_to_gpio(const char *name) +{ + int group = 0; + int groupsize = 9 * 32; + long pin; + char *eptr; + if (*name == 'P' || *name == 'p') + name++; + if (*name >= 'A') { + group = *name - (*name > 'a' ? 'a' : 'A'); + groupsize = 32; + name++; + } + + pin = simple_strtol(name, &eptr, 10); + if (!*name || *eptr) + return -1; + if (pin < 0 || pin > groupsize || group >= 9) + return -1; + return group * 32 + pin; +} diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index a9d104a..ebb9f7a 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -179,6 +179,10 @@ #define CONFIG_CONS_INDEX 1 /* UART0 */ #endif
+/* GPIO */ +#define CONFIG_SUNXI_GPIO +#define CONFIG_CMD_GPIO + /* Ethernet support */ #ifdef CONFIG_SUNXI_EMAC #define CONFIG_MII /* MII PHY management */
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platforms with sata included.
The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented.
The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef.
This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.
Signed-off-by: Ian Campbell ijc@hellion.org.uk --- arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 7 ++- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 11 ++-- board/sunxi/Makefile | 1 + board/sunxi/ahci.c | 84 +++++++++++++++++++++++++++ boards.cfg | 10 ++-- drivers/block/ahci.c | 16 +++++ include/ahci.h | 4 ++ include/configs/sunxi-common.h | 12 ++++ 8 files changed, 134 insertions(+), 11 deletions(-) create mode 100644 board/sunxi/ahci.c
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 5a7da3c..ecbdb01 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -36,10 +36,13 @@ void clock_init_safe(void) CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); #ifdef CONFIG_SUN7I - writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0), - &ccm->ahb_gate0); + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); #endif writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); +#ifdef CONFIG_SUNXI_AHCI + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); + setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); +#endif } #endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 928f3f2..2531cbd 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -218,10 +218,13 @@ struct sunxi_ccm_reg { #define CCM_PLL5_CTRL_BYPASS (0x1 << 30) #define CCM_PLL5_CTRL_EN (0x1 << 31)
-#define CCM_PLL6_CTRL_N_SHIFT 8 -#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) -#define CCM_PLL6_CTRL_K_SHIFT 4 -#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) +#define CCM_PLL6_CTRL_EN 31 +#define CCM_PLL6_CTRL_BYPASS_EN 30 +#define CCM_PLL6_CTRL_SATA_EN_SHIFT 14 +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_K_SHIFT 4 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
#define CCM_GPS_CTRL_RESET (0x1 << 0) #define CCM_GPS_CTRL_GATE (0x1 << 1) diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 62acb8f..03f55cc 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -10,6 +10,7 @@ # obj-y += board.o obj-$(CONFIG_SUNXI_GMAC) += gmac.o +obj-$(CONFIG_SUNXI_AHCI) += ahci.o obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c new file mode 100644 index 0000000..0c262ea --- /dev/null +++ b/board/sunxi/ahci.c @@ -0,0 +1,84 @@ +#include <common.h> +#include <ahci.h> +#include <scsi.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/gpio.h> + +#define AHCI_PHYCS0R 0x00c0 +#define AHCI_PHYCS1R 0x00c4 +#define AHCI_PHYCS2R 0x00c8 +#define AHCI_RWCR 0x00fc + +/* This magic PHY initialisation was taken from the Allwinner releases + * and Linux driver, but is completely undocumented. + */ +static int sunxi_ahci_phy_init(u32 base) +{ + u8 *reg_base = (u8 *)base; + u32 reg_val; + int timeout; + + writel(0, reg_base + AHCI_RWCR); + mdelay(5); + + setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); + clrsetbits_le32(reg_base + AHCI_PHYCS0R, + (0x7 << 24), + (0x5 << 24) | (0x1 << 23) | (0x1 << 18)); + clrsetbits_le32(reg_base + AHCI_PHYCS1R, + (0x3 << 16) | (0x1f << 8) | (0x3 << 6), + (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); + setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); + clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); + clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); + clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); + mdelay(5); + + setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); + + timeout = 250; /* Power up takes approx 50 us */ + for (;;) { + reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28); + if (reg_val == (0x2 << 28)) + break; + if (--timeout == 0) { + printf("AHCI PHY power up failed.\n"); + return -EIO; + } + udelay(1); + }; + + setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24)); + + timeout = 100; /* Calibration takes approx 10 us */ + for (;;) { + reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24); + if (reg_val == 0x0) + break; + if (--timeout == 0) { + printf("AHCI PHY calibration failed.\n"); + return -EIO; + } + udelay(1); + } + + mdelay(15); + + writel(0x7, reg_base + AHCI_RWCR); + + return 0; +} + +void scsi_init(void) +{ + printf("SUNXI SCSI INIT\n"); +#ifdef CONFIG_SATAPWR + gpio_direction_output(CONFIG_SATAPWR, 1); +#endif + + if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0) + return; + + ahci_init(SUNXI_SATA_BASE); +} diff --git a/boards.cfg b/boards.cfg index c000910..83f39ca 100644 --- a/boards.cfg +++ b/boards.cfg @@ -382,11 +382,11 @@ Active arm armv7 s5pc1xx samsung goni Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang mk7.kang@samsung.com Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede hdegoede@redhat.com -Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC Hans de Goede hdegoede@redhat.com -Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC Hans de Goede hdegoede@redhat.com:Ian Campbell ijc@hellion.org.uk -Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC Hans de Goede hdegoede@redhat.com:Ian Campbell ijc@hellion.org.uk -Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Hans de Goede hdegoede@redhat.com -Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Hans de Goede hdegoede@redhat.com +Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8) Hans de Goede hdegoede@redhat.com +Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8) Hans de Goede hdegoede@redhat.com:Ian Campbell ijc@hellion.org.uk +Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8) Hans de Goede hdegoede@redhat.com:Ian Campbell ijc@hellion.org.uk +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12) Hans de Goede hdegoede@redhat.com +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12) Hans de Goede hdegoede@redhat.com Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER Hans de Goede hdegoede@redhat.com Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier mathieu.poirier@linaro.org Active arm armv7 u8500 st-ericsson u8500 u8500_href - - diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 4df8046..dce99ad 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -129,6 +129,14 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) return 1; }
+#ifdef CONFIG_SUNXI_AHCI +/* The sunxi AHCI controller requires this undocumented setup */ +static void sunxi_dma_init(volatile u8 *port_mmio) +{ + clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); +} +#endif + static int ahci_host_init(struct ahci_probe_ent *probe_ent) { #ifndef CONFIG_SCSI_AHCI_PLAT @@ -213,6 +221,10 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) msleep(500); }
+#ifdef CONFIG_SUNXI_AHCI + sunxi_dma_init(port_mmio); +#endif + /* Add the spinup command to whatever mode bits may * already be on in the command register. */ @@ -545,6 +557,10 @@ static int ahci_port_start(u8 port)
writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+#ifdef CONFIG_SUNXI_AHCI + sunxi_dma_init(port_mmio); +#endif + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | PORT_CMD_START, port_mmio + PORT_CMD); diff --git a/include/ahci.h b/include/ahci.h index 90e8509..35b8a8c 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -58,6 +58,10 @@ #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
+#ifdef CONFIG_SUNXI_AHCI +#define PORT_P0DMACR 0x70 /* SUNXI specific "DMA register" */ +#endif + /* PORT_IRQ_{STAT,MASK} bits */ #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ebb9f7a..34fac50 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -57,6 +57,18 @@ #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
+#ifdef CONFIG_AHCI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SUNXI_AHCI +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_CMD_SCSI +#endif + #define CONFIG_CMD_MEMORY #define CONFIG_CMD_SETEXPR
Hi Ian,
On 05/31/2014 06:36 PM, Ian Campbell wrote:
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platformsw with sata included.
The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented.
The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef.
This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.
Signed-off-by: Ian Campbell ijc@hellion.org.uk
Patches 1-4 of this set look ok and are:
Acked-by: Hans de Goede hdegoede@redhat.com
I've some 1 minor comment on this patch below, with those fixed, this patch is:
Acked-by: Hans de Goede hdegoede@redhat.com
too.
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 7 ++- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 11 ++-- board/sunxi/Makefile | 1 + board/sunxi/ahci.c | 84 +++++++++++++++++++++++++++ boards.cfg | 10 ++-- drivers/block/ahci.c | 16 +++++ include/ahci.h | 4 ++ include/configs/sunxi-common.h | 12 ++++ 8 files changed, 134 insertions(+), 11 deletions(-) create mode 100644 board/sunxi/ahci.c
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 5a7da3c..ecbdb01 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -36,10 +36,13 @@ void clock_init_safe(void) CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); #ifdef CONFIG_SUN7I
- writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
&ccm->ahb_gate0);
- setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); #endif writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
Please split out the above change in a separate patch.
Regards,
Hans
+#ifdef CONFIG_SUNXI_AHCI
- setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
- setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
+#endif } #endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 928f3f2..2531cbd 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -218,10 +218,13 @@ struct sunxi_ccm_reg { #define CCM_PLL5_CTRL_BYPASS (0x1 << 30) #define CCM_PLL5_CTRL_EN (0x1 << 31)
-#define CCM_PLL6_CTRL_N_SHIFT 8 -#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) -#define CCM_PLL6_CTRL_K_SHIFT 4 -#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) +#define CCM_PLL6_CTRL_EN 31 +#define CCM_PLL6_CTRL_BYPASS_EN 30 +#define CCM_PLL6_CTRL_SATA_EN_SHIFT 14 +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_K_SHIFT 4 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
#define CCM_GPS_CTRL_RESET (0x1 << 0) #define CCM_GPS_CTRL_GATE (0x1 << 1) diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 62acb8f..03f55cc 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -10,6 +10,7 @@ # obj-y += board.o obj-$(CONFIG_SUNXI_GMAC) += gmac.o +obj-$(CONFIG_SUNXI_AHCI) += ahci.o obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c new file mode 100644 index 0000000..0c262ea --- /dev/null +++ b/board/sunxi/ahci.c @@ -0,0 +1,84 @@ +#include <common.h> +#include <ahci.h> +#include <scsi.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/gpio.h>
+#define AHCI_PHYCS0R 0x00c0 +#define AHCI_PHYCS1R 0x00c4 +#define AHCI_PHYCS2R 0x00c8 +#define AHCI_RWCR 0x00fc
+/* This magic PHY initialisation was taken from the Allwinner releases
- and Linux driver, but is completely undocumented.
- */
+static int sunxi_ahci_phy_init(u32 base) +{
- u8 *reg_base = (u8 *)base;
- u32 reg_val;
- int timeout;
- writel(0, reg_base + AHCI_RWCR);
- mdelay(5);
- setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
- clrsetbits_le32(reg_base + AHCI_PHYCS0R,
(0x7 << 24),(0x5 << 24) | (0x1 << 23) | (0x1 << 18));- clrsetbits_le32(reg_base + AHCI_PHYCS1R,
(0x3 << 16) | (0x1f << 8) | (0x3 << 6),(0x2 << 16) | (0x6 << 8) | (0x2 << 6));- setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
- clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
- clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
- clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
- mdelay(5);
- setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
- timeout = 250; /* Power up takes approx 50 us */
- for (;;) {
reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);if (reg_val == (0x2 << 28))break;if (--timeout == 0) {printf("AHCI PHY power up failed.\n");return -EIO;}udelay(1);- };
- setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
- timeout = 100; /* Calibration takes approx 10 us */
- for (;;) {
reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);if (reg_val == 0x0)break;if (--timeout == 0) {printf("AHCI PHY calibration failed.\n");return -EIO;}udelay(1);- }
- mdelay(15);
- writel(0x7, reg_base + AHCI_RWCR);
- return 0;
+}
+void scsi_init(void) +{
- printf("SUNXI SCSI INIT\n");
+#ifdef CONFIG_SATAPWR
- gpio_direction_output(CONFIG_SATAPWR, 1);
+#endif
- if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
return;- ahci_init(SUNXI_SATA_BASE);
+} diff --git a/boards.cfg b/boards.cfg index c000910..83f39ca 100644 --- a/boards.cfg +++ b/boards.cfg @@ -382,11 +382,11 @@ Active arm armv7 s5pc1xx samsung goni Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang mk7.kang@samsung.com Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede hdegoede@redhat.com -Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC Hans de Goede hdegoede@redhat.com -Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC Hans de Goede hdegoede@redhat.com:Ian Campbell ijc@hellion.org.uk -Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC Hans de Goede hdegoede@redhat.com:Ian Campbell ijc@hellion.org.uk -Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Hans de Goede hdegoede@redhat.com -Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Hans de Goede hdegoede@redhat.com +Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8) Hans de Goede hdegoede@redhat.com +Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8) Hans de Goede hdegoede@redhat.com:Ian Campbell ijc@hellion.org.uk +Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8) Hans de Goede hdegoede@redhat.com:Ian Campbell ijc@hellion.org.uk +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12) Hans de Goede hdegoede@redhat.com +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12) Hans de Goede hdegoede@redhat.com Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER Hans de Goede hdegoede@redhat.com Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier mathieu.poirier@linaro.org Active arm armv7 u8500 st-ericsson u8500 u8500_href - - diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 4df8046..dce99ad 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -129,6 +129,14 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) return 1; }
+#ifdef CONFIG_SUNXI_AHCI +/* The sunxi AHCI controller requires this undocumented setup */ +static void sunxi_dma_init(volatile u8 *port_mmio) +{
- clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
+} +#endif
- static int ahci_host_init(struct ahci_probe_ent *probe_ent) { #ifndef CONFIG_SCSI_AHCI_PLAT
@@ -213,6 +221,10 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) msleep(500); }
+#ifdef CONFIG_SUNXI_AHCI
sunxi_dma_init(port_mmio);+#endif
- /* Add the spinup command to whatever mode bits may
*/
- already be on in the command register.
@@ -545,6 +557,10 @@ static int ahci_port_start(u8 port)
writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+#ifdef CONFIG_SUNXI_AHCI
- sunxi_dma_init(port_mmio);
+#endif
- writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | PORT_CMD_START, port_mmio + PORT_CMD);
diff --git a/include/ahci.h b/include/ahci.h index 90e8509..35b8a8c 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -58,6 +58,10 @@ #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
+#ifdef CONFIG_SUNXI_AHCI +#define PORT_P0DMACR 0x70 /* SUNXI specific "DMA register" */ +#endif
- /* PORT_IRQ_{STAT,MASK} bits */ #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ebb9f7a..34fac50 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -57,6 +57,18 @@ #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
+#ifdef CONFIG_AHCI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SUNXI_AHCI +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)+#define CONFIG_CMD_SCSI +#endif
- #define CONFIG_CMD_MEMORY #define CONFIG_CMD_SETEXPR
On Tue, 2014-06-03 at 21:49 +0200, Hans de Goede wrote:
Hi Ian,
On 05/31/2014 06:36 PM, Ian Campbell wrote:
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platformsw with sata included.
The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented.
The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef.
This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.
Signed-off-by: Ian Campbell ijc@hellion.org.uk
Patches 1-4 of this set look ok and are:
Acked-by: Hans de Goede hdegoede@redhat.com
Thanks.
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 5a7da3c..ecbdb01 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -36,10 +36,13 @@ void clock_init_safe(void) CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); #ifdef CONFIG_SUN7I
- writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
&ccm->ahb_gate0);
- setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); #endif writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
Please split out the above change in a separate patch.
Certainly. I'll rebase onto your v2 series and repost ASAP.
Ian.
participants (4)
-
Hans de Goede -
Ian Campbell -
Marek Vasut -
Simon Glass