[PATCH v1 00/17] Agilex5 Platform Enablement
Intel Agilex5 is a midrange FPGAs optimized for applications requiring high performance, lower power, and smaller form factors and lower logic densities. U-Boot is one of the bootloader to boot along with ARM trusted Firmware to boot the board up.
*** BLURB HERE ***
Jit Loon Lim (16): arch: arm: update kconfig for new platform agilex5 arch: arm: dts: add dts and dtsi for new platform agilex5 arch: arm: mach-socfpga: add new platform agilex5 mach-socfpga enablement arch: arm: mach-socfpga: include: mach: add new platform agilex5 mach-socfpga enablement board: intel: add new platform agilex5 socdk configs: add new platform agilex5 defconfig doc: device-tree-bindings: misc: add secreg text file for agilex5 drivers: ddr: altera: add ddr support for agilex5 drivers: clk: altera: add clock support for agilex5 drivers: misc: update driver misc for agilex5 drivers: mmc: add mmc/cadence driver for agilex5 drivers: phy: add combo phy driver for agilex5 drivers: reset: add reset driver for agilex5 drivers: sysreset: add system driver for agilex5 drivers: watchdog: update watchdog driver for agilex5 includes: add and update configuration for agilex5
Sieu Mun Tang (1): tools: binman: update binman tool for agilex5
arch/arm/Kconfig | 5 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 459 ++++++++++ arch/arm/dts/socfpga_agilex5.dtsi | 634 +++++++++++++ .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 131 +++ arch/arm/dts/socfpga_agilex5_socdk.dts | 165 ++++ arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 38 +- arch/arm/dts/socfpga_soc64_u-boot.dtsi | 120 +++ arch/arm/dts/socfpga_stratix10.dtsi | 0 .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 0 arch/arm/dts/socfpga_stratix10_socdk.dts | 0 arch/arm/mach-socfpga/Kconfig | 92 ++ arch/arm/mach-socfpga/Makefile | 69 +- arch/arm/mach-socfpga/board.c | 65 +- arch/arm/mach-socfpga/clock_manager_agilex5.c | 82 ++ arch/arm/mach-socfpga/firewall.c | 107 --- .../include/mach/base_addr_soc64.h | 43 +- .../mach-socfpga/include/mach/clock_manager.h | 5 +- .../include/mach/clock_manager_agilex5.h | 12 + arch/arm/mach-socfpga/include/mach/firewall.h | 42 +- .../mach-socfpga/include/mach/handoff_soc64.h | 25 +- .../mach-socfpga/include/mach/mailbox_s10.h | 32 +- .../include/mach/reset_manager_soc64.h | 33 +- .../mach-socfpga/include/mach/smmu_agilex5.h | 30 + arch/arm/mach-socfpga/include/mach/smmu_s10.h | 73 ++ .../include/mach/system_manager_soc64.h | 126 ++- arch/arm/mach-socfpga/include/mach/timer.h | 30 + arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 61 ++ arch/arm/mach-socfpga/lowlevel_init_soc64.S | 167 +++- arch/arm/mach-socfpga/mailbox_s10.c | 21 + arch/arm/mach-socfpga/misc.c | 19 +- arch/arm/mach-socfpga/misc_soc64.c | 33 +- arch/arm/mach-socfpga/mmu-arm64_s10.c | 43 +- arch/arm/mach-socfpga/reset_manager_s10.c | 271 +++++- arch/arm/mach-socfpga/secure_reg_helper.c | 4 +- arch/arm/mach-socfpga/smmu_agilex5.c | 34 + arch/arm/mach-socfpga/smmu_s10.c | 126 +++ arch/arm/mach-socfpga/spl_agilex5.c | 180 ++++ arch/arm/mach-socfpga/spl_soc64.c | 188 +++- arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 93 ++ arch/arm/mach-socfpga/wrap_handoff_soc64.c | 7 +- board/intel/agilex5-socdk/MAINTAINERS | 8 + board/intel/agilex5-socdk/Makefile | 7 + board/intel/agilex5-socdk/socfpga.c | 7 + configs/socfpga_agilex5_defconfig | 125 +++ configs/socfpga_agilex5_legacy_defconfig | 87 ++ .../misc/socfpga_secreg.txt | 397 ++++++++ drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex5.c | 736 +++++++++++++++ drivers/clk/altera/clk-agilex5.h | 263 ++++++ drivers/ddr/altera/Makefile | 5 +- drivers/ddr/altera/iossm_mailbox.c | 786 ++++++++++++++++ drivers/ddr/altera/iossm_mailbox.h | 141 +++ drivers/ddr/altera/sdram_agilex5.c | 329 +++++++ drivers/ddr/altera/sdram_soc64.c | 78 +- drivers/ddr/altera/sdram_soc64.h | 17 +- drivers/misc/Kconfig | 9 + drivers/misc/Makefile | 1 + drivers/misc/socfpga_secreg.c | 116 +++ drivers/mmc/mmc.c | 27 +- drivers/mmc/sdhci-cadence.c | 164 +++- drivers/phy/cadence/Kconfig | 9 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-combophy.c | 855 ++++++++++++++++++ drivers/reset/reset-socfpga.c | 28 +- drivers/sysreset/Kconfig | 7 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_socfpga_agilex5.c | 44 + drivers/watchdog/Kconfig | 2 +- include/configs/socfpga_agilex5_socdk.h | 12 + include/configs/socfpga_soc64_common.h | 214 ++++- include/dt-bindings/clock/agilex5-clock.h | 71 ++ include/dt-bindings/reset/altr,rst-mgr-agx5.h | 82 ++ tools/binman/control.py | 8 +- 74 files changed, 8019 insertions(+), 285 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c delete mode 100644 arch/arm/mach-socfpga/firewall.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h create mode 100644 arch/arm/mach-socfpga/include/mach/smmu_agilex5.h create mode 100644 arch/arm/mach-socfpga/include/mach/smmu_s10.h create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S create mode 100644 arch/arm/mach-socfpga/smmu_agilex5.c create mode 100644 arch/arm/mach-socfpga/smmu_s10.c create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds create mode 100644 board/intel/agilex5-socdk/MAINTAINERS create mode 100644 board/intel/agilex5-socdk/Makefile create mode 100644 board/intel/agilex5-socdk/socfpga.c create mode 100644 configs/socfpga_agilex5_defconfig create mode 100644 configs/socfpga_agilex5_legacy_defconfig create mode 100644 doc/device-tree-bindings/misc/socfpga_secreg.txt create mode 100644 drivers/clk/altera/clk-agilex5.c create mode 100644 drivers/clk/altera/clk-agilex5.h create mode 100644 drivers/ddr/altera/iossm_mailbox.c create mode 100644 drivers/ddr/altera/iossm_mailbox.h create mode 100644 drivers/ddr/altera/sdram_agilex5.c create mode 100644 drivers/misc/socfpga_secreg.c create mode 100644 drivers/phy/cadence/phy-cadence-combophy.c create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c create mode 100644 include/configs/socfpga_agilex5_socdk.h create mode 100644 include/dt-bindings/clock/agilex5-clock.h create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h
This is for new platform enablement for agilex5
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 99264a6478..8e36456fa8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1093,6 +1093,8 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 + select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 + select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG @@ -1101,7 +1103,8 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 + select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && TARGET_SOCFPGA_SOC64 + imply SYSRESET_SOCFPGA_AGILEX5 if TARGET_SOCFPGA_AGILEX5 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY
Hi Jit Loon,
-----Original Message----- From: Lim, Jit Loon jit.loon.lim@intel.com Sent: Wednesday, 21 June, 2023 11:16 AM To: u-boot@lists.denx.de Cc: Jagan Teki jagan@amarulasolutions.com; Vignesh R vigneshr@ti.com; Vasut, Marek marex@denx.de; Simon simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Hea, Kok Kiang kok.kiang.hea@intel.com; Lokanathan, Raaj raaj.lokanathan@intel.com; Maniyam, Dinesh dinesh.maniyam@intel.com; Ng, Boon Khai boon.khai.ng@intel.com; Yuslaimi, Alif Zakuan alif.zakuan.yuslaimi@intel.com; Chong, Teik Heng teik.heng.chong@intel.com; Zamri, Muhammad Hazim Izzat muhammad.hazim.izzat.zamri@intel.com; Lim, Jit Loon jit.loon.lim@intel.com; Tang, Sieu Mun sieu.mun.tang@intel.com Subject: [PATCH v1 01/17] arch: arm: update kconfig for new platform agilex5
This is for new platform enablement for agilex5
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com
arch/arm/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 99264a6478..8e36456fa8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1093,6 +1093,8 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
- select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
- select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64
Please exclude these changes for now because this driver is not in mainline yet. You can submit another patch for these changes once the driver is accepted into mainline.
select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG @@ -1101,7 +1103,8 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
- select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5
&& TARGET_SOCFPGA_SOC64
- imply SYSRESET_SOCFPGA_AGILEX5 if TARGET_SOCFPGA_AGILEX5
Please update your commit message, your message should be clear and accurate to reflect your changes here.
imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY -- 2.26.2
Thanks and regards, Tien Fong
-----Original Message----- From: Chee, Tien Fong tien.fong.chee@intel.com Sent: Wednesday, 28 June, 2023 4:17 PM To: Lim, Jit Loon jit.loon.lim@intel.com; u-boot@lists.denx.de Cc: Jagan Teki jagan@amarulasolutions.com; Vignesh R vigneshr@ti.com; Vasut, Marek marex@denx.de; Simon simon.k.r.goldschmidt@gmail.com; Hea, Kok Kiang kok.kiang.hea@intel.com; Lokanathan, Raaj raaj.lokanathan@intel.com; Maniyam, Dinesh dinesh.maniyam@intel.com; Ng, Boon Khai boon.khai.ng@intel.com; Yuslaimi, Alif Zakuan alif.zakuan.yuslaimi@intel.com; Chong, Teik Heng teik.heng.chong@intel.com; Zamri, Muhammad Hazim Izzat muhammad.hazim.izzat.zamri@intel.com; Tang, Sieu Mun sieu.mun.tang@intel.com Subject: RE: [PATCH v1 01/17] arch: arm: update kconfig for new platform agilex5
Hi Jit Loon,
-----Original Message----- From: Lim, Jit Loon jit.loon.lim@intel.com Sent: Wednesday, 21 June, 2023 11:16 AM To: u-boot@lists.denx.de Cc: Jagan Teki jagan@amarulasolutions.com; Vignesh R vigneshr@ti.com; Vasut, Marek marex@denx.de; Simon simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Hea, Kok Kiang kok.kiang.hea@intel.com; Lokanathan, Raaj raaj.lokanathan@intel.com; Maniyam, Dinesh dinesh.maniyam@intel.com; Ng, Boon Khai boon.khai.ng@intel.com; Yuslaimi, Alif Zakuan alif.zakuan.yuslaimi@intel.com; Chong, Teik Heng teik.heng.chong@intel.com; Zamri, Muhammad Hazim Izzat muhammad.hazim.izzat.zamri@intel.com; Lim, Jit Loon jit.loon.lim@intel.com; Tang, Sieu Mun sieu.mun.tang@intel.com Subject: [PATCH v1 01/17] arch: arm: update kconfig for new platform agilex5
This is for new platform enablement for agilex5
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com
arch/arm/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 99264a6478..8e36456fa8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1093,6 +1093,8 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
- select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
- select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64
Please exclude these changes for now because this driver is not in mainline yet. You can submit another patch for these changes once the driver is accepted into mainline.
select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG @@ -1101,7 +1103,8 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
- select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5
&& TARGET_SOCFPGA_SOC64
- imply SYSRESET_SOCFPGA_AGILEX5 if TARGET_SOCFPGA_AGILEX5
Please update your commit message, your message should be clear and accurate to reflect your changes here.
imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY -- 2.26.2
Thanks and regards, Tien Fong
Ok. Will update commit message and send out in v2 for review.
This is for new platform enablement for agilex5. Add agilex5 dtsi and dts. Update checkpatch error for stratix10.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 459 +++++++++++++ arch/arm/dts/socfpga_agilex5.dtsi | 634 ++++++++++++++++++ .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 131 ++++ arch/arm/dts/socfpga_agilex5_socdk.dts | 165 +++++ arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 38 +- arch/arm/dts/socfpga_soc64_u-boot.dtsi | 120 ++++ arch/arm/dts/socfpga_stratix10.dtsi | 0 .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 0 arch/arm/dts/socfpga_stratix10_socdk.dts | 0 10 files changed, 1534 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 480269fa60..2e4bc556e1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -456,6 +456,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \ + socfpga_agilex5_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_2.dtb \ diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi new file mode 100644 index 0000000000..6a1299901a --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + */ + +#include "socfpga_soc64_u-boot.dtsi" +#include "socfpga_soc64_fit-u-boot.dtsi" + +/{ + memory { + #address-cells = <2>; + #size-cells = <2>; + bootph-all; + }; + + soc { + bootph-all; + + socfpga_secreg: socfpga-secreg { + compatible = "intel,socfpga-secreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* DSU */ + i_ccu_caiu0@1c000000 { + reg = <0x1c000000 0x00001000>; + intel,offset-settings = + /* CAIUAMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* CAIUMIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* DII2_GICREGS */ + <0x00000424 0x0001d000 0xffffffff>, + <0x00000428 0x00000000 0x000000ff>, + <0x00000420 0xc0800400 0xc1f03e1f>, + /* NCAIU0_LWSOC2FPGA */ + <0x00000444 0x00020000 0xffffffff>, + <0x00000448 0x00000000 0x000000ff>, + <0x00000440 0xc1100006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_1G */ + <0x00000454 0x00040000 0xffffffff>, + <0x00000458 0x00000000 0x000000ff>, + <0x00000450 0xc1200006 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + <0x00000460 0x81300006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_16G */ + <0x00000474 0x00400000 0xffffffff>, + <0x00000478 0x00000000 0x000000ff>, + <0x00000470 0xc1600006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + <0x00000480 0x81700006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_256G */ + <0x00000494 0x04000000 0xffffffff>, + <0x00000498 0x00000000 0x000000ff>, + <0x00000490 0xc1a00006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>, + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* FPGA2SOC */ + i_ccu_ncaiu0@1c001000 { + reg = <0x1c001000 0x00001000>; + intel,offset-settings = + /* NCAIU0AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* NCAIU0MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* PSS */ + <0x00000404 0x00010000 0xffffffff>, + <0x00000408 0x00000000 0x000000ff>, + <0x00000400 0xC0F00000 0xc1f03e1f>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* NCAIU0_LWSOC2FPGA */ + <0x00000444 0x00020000 0xffffffff>, + <0x00000448 0x00000000 0x000000ff>, + <0x00000440 0xc1100006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_1G */ + <0x00000454 0x00040000 0xffffffff>, + <0x00000458 0x00000000 0x000000ff>, + <0x00000450 0xc1200006 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + <0x00000460 0x81300006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_16G */ + <0x00000474 0x00400000 0xffffffff>, + <0x00000478 0x00000000 0x000000ff>, + <0x00000470 0xc1600006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + <0x00000480 0x81700006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_256G */ + <0x00000494 0x04000000 0xffffffff>, + <0x00000498 0x00000000 0x000000ff>, + <0x00000490 0xc1a00006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>, + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* GIC_M */ + i_ccu_ncaiu1@1c002000 { + reg = <0x1c002000 0x00001000>; + intel,offset-settings = + /* NCAIU1AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* NCAIU1MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>, + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* PSS NOC */ + i_ccu_ncaiu3@1c004000 { + reg = <0x1c004000 0x00001000>; + intel,offset-settings = + /* NCAIU3AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* NCAIU3MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>, + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE0 */ + i_ccu_dce0@1c005000 { + reg = <0x1c005000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR0 */ + <0x000003c0 0x00000003 0x0000001f>, + /* DCEUMIFSR0 */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>, + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE1 */ + i_ccu_dce1@1c006000 { + reg = <0x1c006000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR1 */ + <0x000003c0 0x00000003 0x0000001f>, + /* DCEUMIFSR1 */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>, + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* DMI0 */ + i_ccu_dmi0@1c007000 { + reg = <0x1c007000 0x00001000>; + intel,offset-settings = + /* DMIUSMCTCR */ + <0x00000300 0x00000003 0x00000003>; + bootph-all; + }; + + /* DMI1 */ + i_ccu_dmi0@1c008000 { + reg = <0x1c008000 0x00001000>; + intel,offset-settings = + /* DMIUSMCTCR */ + <0x00000300 0x00000003 0x00000003>; + bootph-all; + }; + + /* L4 peripherals firewall */ + noc_fw_l4_per@10d21000 { + reg = <0x10d21000 0x0000008c>; + intel,offset-settings = + /* NAND */ + <0x00000000 0x01010001 0x01010001>, + /* USB0 */ + <0x0000000c 0x01010001 0x01010001>, + /* USB1 */ + <0x00000010 0x01010001 0x01010001>, + /* SPI_MAIN0 */ + <0x0000001c 0x01010301 0x01010301>, + /* SPI_MAIN1 */ + <0x00000020 0x01010301 0x01010301>, + /* SPI_SECONDARY0 */ + <0x00000024 0x01010301 0x01010301>, + /* SPI_SECONDARY1 */ + <0x00000028 0x01010301 0x01010301>, + /* EMAC0 */ + <0x0000002c 0x01010001 0x01010001>, + /* EMAC1 */ + <0x00000030 0x01010001 0x01010001>, + /* EMAC2 */ + <0x00000034 0x01010001 0x01010001>, + /* SDMMC */ + <0x00000040 0x01010001 0x01010001>, + /* GPIO0 */ + <0x00000044 0x01010301 0x01010301>, + /* GPIO1 */ + <0x00000048 0x01010301 0x01010301>, + /* I2C0 */ + <0x00000050 0x01010301 0x01010301>, + /* I2C1 */ + <0x00000054 0x01010301 0x01010301>, + /* I2C2 */ + <0x00000058 0x01010301 0x01010301>, + /* I2C3 */ + <0x0000005c 0x01010301 0x01010301>, + /* I2C4 */ + <0x00000060 0x01010301 0x01010301>, + /* SP_TIMER0 */ + <0x00000064 0x01010301 0x01010301>, + /* SP_TIMER1 */ + <0x00000068 0x01010301 0x01010301>, + /* UART0 */ + <0x0000006c 0x01010301 0x01010301>, + /* UART1 */ + <0x00000070 0x01010301 0x01010301>, + /* I3C0 */ + <0x00000074 0x01010301 0x01010301>, + /* I3C1 */ + <0x00000078 0x01010301 0x01010301>, + /* DMA0 */ + <0x0000007c 0x01010001 0x01010001>, + /* DMA1 */ + <0x00000080 0x01010001 0x01010001>, + /* COMBO_PHY */ + <0x00000084 0x01010001 0x01010001>, + /* NAND_SDMA */ + <0x00000088 0x01010301 0x01010301>; + bootph-all; + }; + + /* L4 system firewall */ + noc_fw_l4_sys@10d21100 { + reg = <0x10d21100 0x00000098>; + intel,offset-settings = + /* DMA_ECC */ + <0x00000008 0x01010001 0x01010001>, + /* EMAC0RX_ECC */ + <0x0000000c 0x01010001 0x01010001>, + /* EMAC0TX_ECC */ + <0x00000010 0x01010001 0x01010001>, + /* EMAC1RX_ECC */ + <0x00000014 0x01010001 0x01010001>, + /* EMAC1TX_ECC */ + <0x00000018 0x01010001 0x01010001>, + /* EMAC2RX_ECC */ + <0x0000001c 0x01010001 0x01010001>, + /* EMAC2TX_ECC */ + <0x00000020 0x01010001 0x01010001>, + /* NAND_ECC */ + <0x0000002c 0x01010001 0x01010001>, + /* NAND_READ_ECC */ + <0x00000030 0x01010001 0x01010001>, + /* NAND_WRITE_ECC */ + <0x00000034 0x01010001 0x01010001>, + /* OCRAM_ECC */ + <0x00000038 0x01010001 0x01010001>, + /* SDMMC_ECC */ + <0x00000040 0x01010001 0x01010001>, + /* USB0_ECC */ + <0x00000044 0x01010001 0x01010001>, + /* USB1_CACHEECC */ + <0x00000048 0x01010001 0x01010001>, + /* CLOCK_MANAGER */ + <0x0000004c 0x01010001 0x01010001>, + /* IO_MANAGER */ + <0x00000054 0x01010001 0x01010001>, + /* RESET_MANAGER */ + <0x00000058 0x01010001 0x01010001>, + /* SYSTEM_MANAGER */ + <0x0000005c 0x01010001 0x01010001>, + /* OSC0_TIMER */ + <0x00000060 0x01010301 0x01010301>, + /* OSC1_TIMER0*/ + <0x00000064 0x01010301 0x01010301>, + /* WATCHDOG0 */ + <0x00000068 0x01010301 0x01010301>, + /* WATCHDOG1 */ + <0x0000006c 0x01010301 0x01010301>, + /* WATCHDOG2 */ + <0x00000070 0x01010301 0x01010301>, + /* WATCHDOG3 */ + <0x00000074 0x01010301 0x01010301>, + /* DAP */ + <0x00000078 0x03010001 0x03010001>, + /* WATCHDOG4 */ + <0x0000007c 0x01010301 0x01010301>, + /* POWER_MANAGER */ + <0x00000080 0x01010001 0x01010001>, + /* USB1_RXECC */ + <0x00000084 0x01010001 0x01010001>, + /* USB1_TXECC */ + <0x00000088 0x01010001 0x01010001>, + /* L4_NOC_PROBES */ + <0x00000090 0x01010001 0x01010001>, + /* L4_NOC_QOS */ + <0x00000094 0x01010001 0x01010001>; + bootph-all; + }; + + /* Light weight SoC2FPGA */ + noc_fw_lwsoc2fpga@10d21300 { + reg = <0x10d21300 0x0000004>; + intel,offset-settings = + /* LWSOC2FPGA_CSR */ + <0x00000000 0x0ffe0301>; + bootph-all; + }; + + /* SoC2FPGA */ + noc_fw_soc2fpga@10d21200 { + reg = <0x10d21200 0x0000004>; + intel,offset-settings = + /* SOC2FPGA_CSR */ + <0x00000000 0x0ffe0301 0x0ffe0301>; + bootph-all; + }; + + /* TCU */ + noc_fw_tcu@10d21400 { + reg = <0x10d21400 0x0000004>; + intel,offset-settings = + /* TCU_CSR */ + <0x00000000 0x01010001 0x01010001>; + bootph-all; + }; + }; + }; +}; + +&clkmgr { + bootph-all; +}; + +&i2c0 { + reset-names = "i2c"; +}; + +&i2c1 { + reset-names = "i2c"; +}; + +&i2c2 { + reset-names = "i2c"; +}; + +&i2c3 { + reset-names = "i2c"; +}; + +&mmc { + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&qspi { + bootph-all; +}; + +&rst { + compatible = "altr,rst-mgr"; + altr,modrst-offset = <0x24>; + bootph-all; +}; + +&sdr { + compatible = "intel,sdr-ctl-agilex5"; + reg = <0x18000000 0x400000>, + <0x18400000 0x400000>, + <0x18800000 0x400000>; + resets = <&rst DDRSCH_RESET>; + bootph-all; +}; + +&sysmgr { + compatible = "altr,sys-mgr", "syscon"; + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi new file mode 100644 index 0000000000..f445bc04ad --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -0,0 +1,634 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022, Intel Corporation + */ + +/dts-v1/; +#include <dt-bindings/reset/altr,rst-mgr-agx5.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/agilex5-clock.h> + +/ { + compatible = "intel,socfpga-agilex"; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x0 0x0 0x1000000>; + alignment = <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a76"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a76"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + interrupt-parent = <&intc>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: intc@fffc1000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1d000000 0x0 0x10000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges = <0 0 0 0xffffffff>; + + base_fpga_region { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + + clkmgr: clock-controller@10d10000 { + compatible = "intel,agilex5-clkmgr"; + reg = <0x10d10000 0x1000>; + #clock-cells = <1>; + }; + + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + gmac0: ethernet@10810000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0x10810000 0x3500>; + interrupts = <0 90 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 1>; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + clocks = <&clkmgr AGILEX5_EMAC0_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gmac1: ethernet@10820000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0x10820000 0x3500>; + interrupts = <0 91 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 2>; + altr,sysmgr-syscon = <&sysmgr 0x48 8>; + clocks = <&clkmgr AGILEX5_EMAC1_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gmac2: ethernet@10830000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0x10830000 0x3500>; + interrupts = <0 92 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 3>; + altr,sysmgr-syscon = <&sysmgr 0x4c 16>; + clocks = <&clkmgr AGILEX5_EMAC2_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gpio0: gpio@10c03200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03200 0x80>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 110 4>; + }; + }; + + gpio1: gpio@10c03300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03300 0x80>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 111 4>; + }; + }; + + i2c0: i2c@10c02800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02800 0x100>; + interrupts = <0 103 4>; + resets = <&rst I2C0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c1: i2c@10c02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02900 0x100>; + interrupts = <0 104 4>; + resets = <&rst I2C1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c2: i2c@10c02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02a00 0x100>; + interrupts = <0 105 4>; + resets = <&rst I2C2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c3: i2c@10c02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02b00 0x100>; + interrupts = <0 106 4>; + resets = <&rst I2C3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c4: i2c@10c02c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02c00 0x100>; + interrupts = <0 107 4>; + resets = <&rst I2C4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + combophy0: combophy@0 { + #phy-cells = <0>; + phy-type = <1>; + compatible = "cdns,combophy"; + reg = <0x10808000 0x1000>; + resets = <&rst COMBOPHY_RESET>; + reset-names = "reset"; + status = "disabled"; + }; + + mmc: mmc0@10808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cdns,sd4hc"; + reg = <0x10808000 0x1000>; + interrupts = <0 96 4>; + phys = <&combophy0>; + phy-names = "combo-phy"; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>, + <&clkmgr AGILEX5_SDMMC_CLK>; + clock-names = "biu", "ciu"; + fifo-depth = <0x800>; + resets = <&rst SDMMC_RESET>; + reset-names = "reset"; + iommus = <&smmu 5>; + status = "disabled"; + }; + + nand: nand@10b80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0x10b80000 0x1038>, + <0xffb80000 0x1000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 97 4>; + clocks = <&clkmgr AGILEX5_NAND_CLK>, + <&clkmgr AGILEX5_NAND_X_CLK>; + clock-names = "nand", "nand_x"; + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; + status = "disabled"; + }; + + ocram: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0x200000>; + }; + + rst: rstmgr@10d11000 { + #reset-cells = <1>; + compatible = "altr,stratix10-rst-mgr"; + reg = <0x10d11000 0x1000>; + }; + + smmu: iommu@16000000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0x16000000 0x40000>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 128 4>, /* Global Secure Fault */ + <0 129 4>, /* Global Non-secure Fault */ + /* Non-secure Context Interrupts (32) */ + <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, + <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, + <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, + <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, + <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, + <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, + <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, + <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; + stream-match-mask = <0x7ff0>; + status = "disabled"; + }; + + spi0: spi@10da4000 { + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10da4000 0x1000>; + interrupts = <0 99 4>; + resets = <&rst SPIM0_RESET>; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + status = "disabled"; + }; + + spi1: spi@10da5000 { + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10da5000 0x1000>; + interrupts = <0 100 4>; + resets = <&rst SPIM1_RESET>; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + status = "disabled"; + }; + + sysmgr: sysmgr@10d12000 { + compatible = "altr,sys-mgr-s10","altr,sys-mgr"; + reg = <0x10d12000 0x500>; + }; + + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + timer0: timer0@10c03000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 113 4>; + reg = <0x10c03000 0x100>; + resets = <&rst SPTIMER0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + timer1: timer1@10c03100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 114 4>; + reg = <0x10c03100 0x100>; + resets = <&rst SPTIMER1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + timer2: timer2@10d00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 4>; + reg = <0x10d00000 0x100>; + resets = <&rst L4SYSTIMER0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + timer3: timer3@10d00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 4>; + reg = <0x10d00100 0x100>; + resets = <&rst L4SYSTIMER1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + uart0: serial0@10c02000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02000 0x100>; + interrupts = <0 108 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-frequency = <100000000>; + }; + + uart1: serial1@10c02100 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02100 0x100>; + interrupts = <0 109 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&clkmgr AGILEX5_USB_CLK>; + status = "disabled"; + }; + + usb0: usb@10b00000 { + compatible = "snps,dwc2"; + reg = <0x10b00000 0x40000>; + interrupts = <0 93 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr AGILEX5_USB_CLK>; + iommus = <&smmu 6>; + status = "disabled"; + }; + + usb31: usb31@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0x100000>; + resets = <&rst USB1_RESET>; + phys = <&usbphy0>, <&usbphy0>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + + watchdog0: watchdog@10d00200 { + compatible = "snps,dw-wdt"; + reg = <0x10d00200 0x100>; + interrupts = <0 117 4>; + resets = <&rst WATCHDOG0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog1: watchdog@10d00300 { + compatible = "snps,dw-wdt"; + reg = <0x10d00300 0x100>; + interrupts = <0 118 4>; + resets = <&rst WATCHDOG1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog2: watchdog@10d00400 { + compatible = "snps,dw-wdt"; + reg = <0x10d00400 0x100>; + interrupts = <0 125 4>; + resets = <&rst WATCHDOG2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog3: watchdog@10d00500 { + compatible = "snps,dw-wdt"; + reg = <0x10d00500 0x100>; + interrupts = <0 126 4>; + resets = <&rst WATCHDOG3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog4: watchdog@10d00600 { + compatible = "snps,dw-wdt"; + reg = <0x10d00600 0x100>; + interrupts = <0 175 4>; + resets = <&rst WATCHDOG4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + sdr: sdr@10d21000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0x10d21000 0xc0>; + }; + + /* TODO: Update the ECC registers */ + eccmgr { + compatible = "altr,socfpga-s10-ecc-manager", + "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 15 4>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + sdramedac { + compatible = "altr,sdram-edac-s10"; + altr,sdr-syscon = <&sdr>; + interrupts = <16 4>; + }; + + ocram-ecc@ff8cc000 { + compatible = "altr,socfpga-s10-ocram-ecc", + "altr,socfpga-a10-ocram-ecc"; + reg = <0xff8cc000 0x100>; + altr,ecc-parent = <&ocram>; + interrupts = <1 4>; + }; + + usb0-ecc@ff8c4000 { + compatible = "altr,socfpga-s10-usb-ecc", + "altr,socfpga-usb-ecc"; + reg = <0xff8c4000 0x100>; + altr,ecc-parent = <&usb0>; + interrupts = <2 4>; + }; + + emac0-rx-ecc@ff8c0000 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0000 0x100>; + altr,ecc-parent = <&gmac0>; + interrupts = <4 4>; + }; + + emac0-tx-ecc@ff8c0400 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0400 0x100>; + altr,ecc-parent = <&gmac0>; + interrupts = <5 4>; + }; + + sdmmca-ecc@ff8c8c00 { + compatible = "altr,socfpga-s10-sdmmc-ecc", + "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c8c00 0x100>; + altr,ecc-parent = <&mmc>; + interrupts = <14 4>, + <15 4>; + }; + }; + + /* QSPI address not available yet */ + qspi: spi@108d2000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x108d2000 0x100>, + <0x10900000 0x100000>; + interrupts = <0 3 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + + status = "disabled"; + }; + + firmware { + svc { + compatible = "intel,stratix10-svc"; + method = "smc"; + memory-region = <&service_reserved>; + + fpga_mgr: fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi new file mode 100644 index 0000000000..ad170353f8 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2022 Intel Corporation <www.intel.com> + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; + }; + + memory { + /* 2GB on Simics*/ + reg = <0 0x80000000 0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,"/memory"; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; +}; + +&nand { + status = "okay"; + nand-bus-width = <16>; + bootph-all; +}; + +&mmc { + status = "okay"; + bus-width = <4>; + sd-uhs-sdr50; + cap-mmc-highspeed; + bootph-all; +}; + +&combophy0 { + status = "okay"; + bootph-all; + cdns,phy-use-ext-lpbk-dqs = <1>; + cdns,phy-use-lpbk-dqs = <1>; + cdns,phy-use-phony-dqs = <1>; + cdns,phy-use-phony-dqs-cmd = <1>; + cdns,phy-io-mask-always-on = <0>; + cdns,phy-io-mask-end = <5>; + cdns,phy-io-mask-start = <0>; + cdns,phy-data-select-oe-end = <1>; + cdns,phy-sync-method = <1>; + cdns,phy-sw-half-cycle-shift = <0>; + cdns,phy-rd-del-sel = <52>; + cdns,phy-underrun-suppress = <1>; + cdns,phy-gate-cfg-always-on = <1>; + cdns,phy-param-dll-bypass-mode = <1>; + cdns,phy-param-phase-detect-sel = <2>; + cdns,phy-param-dll-start-point = <254>; + cdns,phy-read-dqs-cmd-delay = <0>; + cdns,phy-clk-wrdqs-delay = <0>; + cdns,phy-clk-wr-delay = <0>; + cdns,phy-read-dqs-delay = <0>; + cdns,phy-phony-dqs-timing = <0>; + cdns,hrs09-rddata-en = <1>; + cdns,hrs09-rdcmd-en = <1>; + cdns,hrs09-extended-wr-mode = <1>; + cdns,hrs09-extended-rd-mode = <1>; + cdns,hrs10-hcsdclkadj = <3>; + cdns,hrs16-wrdata1-sdclk-dly = <0>; + cdns,hrs16-wrdata0-sdclk-dly = <0>; + cdns,hrs16-wrcmd1-sdclk-dly = <0>; + cdns,hrs16-wrcmd0-sdclk-dly = <0>; + cdns,hrs16-wrdata1-dly = <0>; + cdns,hrs16-wrdata0-dly = <0>; + cdns,hrs16-wrcmd1-dly = <0>; + cdns,hrs16-wrcmd0-dly = <0>; + cdns,hrs07-rw-compensate = <10>; + cdns,hrs07-idelay-val = <0>; +}; + +&qspi { + status = "okay"; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; + +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&fdt_0_blob { + filename = "arch/arm/dts/socfpga_agilex5_socdk.dtb"; +}; + +/* To add NAND dtb when ready in future */ + +&binman { + /delete-node/ kernel; +}; +#endif diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts new file mode 100644 index 0000000000..1a39426561 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022, Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 SoCDK"; + + aliases { + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&mmc { + status = "okay"; +}; + +&combophy0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&usb31 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&watchdog2 { + status = "okay"; +}; + +&watchdog3 { + status = "okay"; +}; + +&watchdog4 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mt25qu02g"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x034B0000>; + }; + + qspi_rootfs: partition@34B0000 { + label = "Root Filesystem - JFFS2"; + reg = <0x034B0000 0x0EB50000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 84b91e8df0..1ca721f070 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2020 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2022 Intel Corporation <www.intel.com> */
#if defined(CONFIG_FIT) @@ -21,14 +21,18 @@ description = "FIT with firmware and bootloader"; #address-cells = <1>;
- images { + images: images { uboot { description = "U-Boot SoC64"; type = "standalone"; os = "U-Boot"; arch = "arm64"; compression = "none"; + #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + load = <0x80200000>; + #else load = <0x00200000>; + #endif uboot_blob: blob-ext { filename = "u-boot-nodtb.bin"; }; @@ -43,8 +47,13 @@ os = "arm-trusted-firmware"; arch = "arm64"; compression = "none"; + #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + load = <0x80000000>; + entry = <0x80000000>; + #else load = <0x00001000>; entry = <0x00001000>; + #endif atf_blob: blob-ext { filename = "bl31.bin"; }; @@ -53,11 +62,11 @@ }; };
- fdt { - description = "U-Boot SoC64 flat device-tree"; + fdt-0 { + description = "socfpga_socdk"; type = "flat_dt"; compression = "none"; - uboot_fdt_blob: blob-ext { + fdt_0_blob: blob-ext { filename = "u-boot.dtb"; }; hash { @@ -66,17 +75,18 @@ }; };
- configurations { - default = "conf"; - conf { - description = "Intel SoC64 FPGA"; + board_config: configurations { + default = "board-0"; + + board-0 { + description = "board_0"; firmware = "atf"; loadables = "uboot"; - fdt = "fdt"; + fdt = "fdt-0"; signature { algo = "crc32"; key-name-hint = "dev"; - sign-images = "atf", "fdt", "uboot"; + sign-images = "atf", "uboot", "fdt-0"; }; }; }; @@ -96,8 +106,8 @@ arch = "arm64"; os = "linux"; compression = "none"; - load = <0x4080000>; - entry = <0x4080000>; + load = <0x6000000>; + entry = <0x6000000>; kernel_blob: blob-ext { filename = "Image"; }; @@ -146,7 +156,7 @@ filename = "signed-bl31.bin"; };
-&uboot_fdt_blob { +&fdt_0_blob { filename = "signed-u-boot.dtb"; };
diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi new file mode 100644 index 0000000000..add9890de3 --- /dev/null +++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2021-2022 Intel Corporation <www.intel.com> + */ + +/ { + soc { + socfpga_secreg: socfpga-secreg { + compatible = "intel,socfpga-secreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + i_sys_mgr_core@ffd12000 { + reg = <0xffd12000 0x00000230>; + intel,offset-settings = + /* Enable non-secure interface to DMA */ + <0x00000020 0xff010000 0xff010011>, + /* Enable non-secure interface to DMA periph */ + <0x00000024 0xffffffff 0xffffffff>; + bootph-all; + }; + + noc_fw_l4_per_l4_per_scr@ffd21000 { + reg = <0xffd21000 0x00000074>; + intel,offset-settings = + /* Disable L4 periphs firewall */ + <0x00000000 0x01010001 0x01010001>, + <0x00000004 0x01010001 0x01010001>, + <0x0000000c 0x01010001 0x01010001>, + <0x00000010 0x01010001 0x01010001>, + <0x0000001c 0x01010001 0x01010101>, + <0x00000020 0x01010001 0x01010101>, + <0x00000024 0x01010001 0x01010101>, + <0x00000028 0x01010001 0x01010101>, + <0x0000002c 0x01010001 0x01010001>, + <0x00000030 0x01010001 0x01010001>, + <0x00000034 0x01010001 0x01010001>, + <0x00000040 0x01010001 0x01010001>, + <0x00000044 0x01010001 0x01010101>, + <0x00000048 0x01010001 0x01010101>, + <0x00000050 0x01010001 0x01010101>, + <0x00000054 0x01010001 0x01010101>, + <0x00000058 0x01010001 0x01010101>, + <0x0000005c 0x01010001 0x01010101>, + <0x00000060 0x01010001 0x01010101>, + <0x00000064 0x01010001 0x01010101>, + <0x00000068 0x01010001 0x01010101>, + <0x0000006c 0x01010001 0x01010101>, + <0x00000070 0x01010001 0x01010101>; + bootph-all; + }; + + noc_fw_l4_sys_l4_sys_scr@ffd21100 { + reg = <0xffd21100 0x00000098>; + intel,offset-settings = + /* Disable L4 system firewall */ + <0x00000008 0x01010001 0x01010001>, + <0x0000000c 0x01010001 0x01010001>, + <0x00000010 0x01010001 0x01010001>, + <0x00000014 0x01010001 0x01010001>, + <0x00000018 0x01010001 0x01010001>, + <0x0000001c 0x01010001 0x01010001>, + <0x00000020 0x01010001 0x01010001>, + <0x0000002c 0x01010001 0x01010001>, + <0x00000030 0x01010001 0x01010001>, + <0x00000034 0x01010001 0x01010001>, + <0x00000038 0x01010001 0x01010001>, + <0x00000040 0x01010001 0x01010001>, + <0x00000044 0x01010001 0x01010001>, + <0x00000048 0x01010001 0x01010001>, + <0x0000004c 0x01010001 0x01010001>, + <0x00000054 0x01010001 0x01010001>, + <0x00000058 0x01010001 0x01010001>, + <0x0000005c 0x01010001 0x01010001>, + <0x00000060 0x01010001 0x01010101>, + <0x00000064 0x01010001 0x01010101>, + <0x00000068 0x01010001 0x01010101>, + <0x0000006c 0x01010001 0x01010101>, + <0x00000070 0x01010001 0x01010101>, + <0x00000074 0x01010001 0x01010101>, + <0x00000078 0x01010001 0x03010001>, + <0x00000090 0x01010001 0x01010001>, + <0x00000094 0x01010001 0x01010001>; + bootph-all; + }; + + noc_fw_soc2fpga_soc2fpga_scr@ffd21200 { + reg = <0xffd21200 0x00000004>; + /* Disable soc2fpga security access */ + intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>; + bootph-all; + }; + + noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 { + reg = <0xffd21300 0x00000004>; + /* Disable lightweight soc2fpga security access */ + intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>; + bootph-all; + }; + + noc_fw_tcu_tcu_scr@ffd21400 { + reg = <0xffd21400 0x00000004>; + /* Disable DMA ECC security access, for SMMU use */ + intel,offset-settings = <0x00000000 0x01010001 0x01010001>; + bootph-all; + }; + + noc_fw_priv_MemoryMap_priv@ffd24800 { + reg = <0xffd24800 0x0000000c>; + intel,offset-settings = + /* Enable non-prviledged access to various periphs */ + <0x00000000 0xfff73ffb 0xfff73ffb>; + bootph-all; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi old mode 100755 new mode 100644 diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi old mode 100755 new mode 100644 diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts old mode 100755 new mode 100644
Hi Jit Loon,
-----Original Message----- From: Lim, Jit Loon jit.loon.lim@intel.com Sent: Wednesday, 21 June, 2023 11:16 AM To: u-boot@lists.denx.de Cc: Jagan Teki jagan@amarulasolutions.com; Vignesh R vigneshr@ti.com; Vasut, Marek marex@denx.de; Simon simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Hea, Kok Kiang kok.kiang.hea@intel.com; Lokanathan, Raaj raaj.lokanathan@intel.com; Maniyam, Dinesh dinesh.maniyam@intel.com; Ng, Boon Khai boon.khai.ng@intel.com; Yuslaimi, Alif Zakuan alif.zakuan.yuslaimi@intel.com; Chong, Teik Heng teik.heng.chong@intel.com; Zamri, Muhammad Hazim Izzat muhammad.hazim.izzat.zamri@intel.com; Lim, Jit Loon jit.loon.lim@intel.com; Tang, Sieu Mun sieu.mun.tang@intel.com Subject: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new platform agilex5
This is for new platform enablement for agilex5. Add agilex5 dtsi and dts. Update checkpatch error for stratix10.
Why having checkpatch error for Stratix10? This should be in a separate patch.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 459 +++++++++++++ arch/arm/dts/socfpga_agilex5.dtsi | 634 ++++++++++++++++++ .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 131 ++++ arch/arm/dts/socfpga_agilex5_socdk.dts | 165 +++++ arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 38 +- arch/arm/dts/socfpga_soc64_u-boot.dtsi | 120 ++++ arch/arm/dts/socfpga_stratix10.dtsi | 0 .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 0 arch/arm/dts/socfpga_stratix10_socdk.dts | 0 10 files changed, 1534 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk-u- boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 480269fa60..2e4bc556e1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -456,6 +456,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \
- socfpga_agilex5_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_2.dtb \
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi new file mode 100644 index 0000000000..6a1299901a --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- U-Boot additions
- Copyright (C) 2019-2022 Intel Corporation <www.intel.com> */
+#include "socfpga_soc64_u-boot.dtsi" +#include "socfpga_soc64_fit-u-boot.dtsi"
+/{
- memory {
#address-cells = <2>;#size-cells = <2>;bootph-all;- };
- soc {
bootph-all;socfpga_secreg: socfpga-secreg {compatible = "intel,socfpga-secreg";#address-cells = <1>;#size-cells = <1>;bootph-all;/* DSU */i_ccu_caiu0@1c000000 {reg = <0x1c000000 0x00001000>;intel,offset-settings =/* CAIUAMIGR */<0x000003c0 0x00000003 0x0000001f>,/* CAIUMIFSR */<0x000003c4 0x000000000x07070777>,
/* DII1_MPFEREGS */<0x00000414 0x00018000 0xffffffff>,<0x00000418 0x00000000 0x000000ff>,<0x00000410 0xc0e00200 0xc1f03e1f>,/* DII2_GICREGS */<0x00000424 0x0001d000 0xffffffff>,<0x00000428 0x00000000 0x000000ff>,<0x00000420 0xc0800400 0xc1f03e1f>,/* NCAIU0_LWSOC2FPGA */<0x00000444 0x00020000 0xffffffff>,<0x00000448 0x00000000 0x000000ff>,<0x00000440 0xc1100006 0xc1f03e1f>,/* NCAIU0_SOC2FPGA_1G */<0x00000454 0x00040000 0xffffffff>,<0x00000458 0x00000000 0x000000ff>,<0x00000450 0xc1200006 0xc1f03e1f>,/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x00000000 0x000000ff>,<0x00000460 0x81300006 0xc1f03e1f>,/* NCAIU0_SOC2FPGA_16G */<0x00000474 0x00400000 0xffffffff>,<0x00000478 0x00000000 0x000000ff>,<0x00000470 0xc1600006 0xc1f03e1f>,/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x00000000 0x000000ff>,<0x00000480 0x81700006 0xc1f03e1f>,/* NCAIU0_SOC2FPGA_256G */<0x00000494 0x04000000 0xffffffff>,<0x00000498 0x00000000 0x000000ff>,<0x00000490 0xc1a00006 0xc1f03e1f>,/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x00000000 0x000000ff>,<0x000004a0 0x81b00006 0xc1f03e1f>;bootph-all;};/* FPGA2SOC */i_ccu_ncaiu0@1c001000 {reg = <0x1c001000 0x00001000>;intel,offset-settings =/* NCAIU0AMIGR */<0x000003c0 0x00000003 0x0000001f>,/* NCAIU0MIFSR */<0x000003c4 0x000000000x07070777>,
/* PSS */<0x00000404 0x00010000 0xffffffff>,<0x00000408 0x00000000 0x000000ff>,<0x00000400 0xC0F00000 0xc1f03e1f>,/* DII1_MPFEREGS */<0x00000414 0x00018000 0xffffffff>,<0x00000418 0x00000000 0x000000ff>,<0x00000410 0xc0e00200 0xc1f03e1f>,/* NCAIU0_LWSOC2FPGA */<0x00000444 0x00020000 0xffffffff>,<0x00000448 0x00000000 0x000000ff>,<0x00000440 0xc1100006 0xc1f03e1f>,/* NCAIU0_SOC2FPGA_1G */<0x00000454 0x00040000 0xffffffff>,<0x00000458 0x00000000 0x000000ff>,<0x00000450 0xc1200006 0xc1f03e1f>,/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x00000000 0x000000ff>,<0x00000460 0x81300006 0xc1f03e1f>,/* NCAIU0_SOC2FPGA_16G */<0x00000474 0x00400000 0xffffffff>,<0x00000478 0x00000000 0x000000ff>,<0x00000470 0xc1600006 0xc1f03e1f>,/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x00000000 0x000000ff>,<0x00000480 0x81700006 0xc1f03e1f>,/* NCAIU0_SOC2FPGA_256G */<0x00000494 0x04000000 0xffffffff>,<0x00000498 0x00000000 0x000000ff>,<0x00000490 0xc1a00006 0xc1f03e1f>,/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x00000000 0x000000ff>,<0x000004a0 0x81b00006 0xc1f03e1f>;bootph-all;};/* GIC_M */i_ccu_ncaiu1@1c002000 {reg = <0x1c002000 0x00001000>;intel,offset-settings =/* NCAIU1AMIGR */<0x000003c0 0x00000003 0x0000001f>,/* NCAIU1MIFSR */<0x000003c4 0x000000000x07070777>,
/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x00000000 0x000000ff>,<0x00000460 0x81300006 0xc1f03e1f>,/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x00000000 0x000000ff>,<0x00000480 0x81700006 0xc1f03e1f>,/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x00000000 0x000000ff>,<0x000004a0 0x81b00006 0xc1f03e1f>;bootph-all;};/* PSS NOC */i_ccu_ncaiu3@1c004000 {reg = <0x1c004000 0x00001000>;intel,offset-settings =/* NCAIU3AMIGR */<0x000003c0 0x00000003 0x0000001f>,/* NCAIU3MIFSR */<0x000003c4 0x000000000x07070777>,
/* DII1_MPFEREGS */<0x00000414 0x00018000 0xffffffff>,<0x00000418 0x00000000 0x000000ff>,<0x00000410 0xc0e00200 0xc1f03e1f>,/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x00000000 0x000000ff>,<0x00000460 0x81300006 0xc1f03e1f>,/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x00000000 0x000000ff>,<0x00000480 0x81700006 0xc1f03e1f>,/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x00000000 0x000000ff>,<0x000004a0 0x81b00006 0xc1f03e1f>;bootph-all;};/* DCE0 */i_ccu_dce0@1c005000 {reg = <0x1c005000 0x00001000>;intel,offset-settings =/* DCEUAMIGR0 */<0x000003c0 0x00000003 0x0000001f>,/* DCEUMIFSR0 */<0x000003c4 0x000000000x07070777>,
/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x00000000 0x000000ff>,<0x00000460 0x81300006 0xc1f03e1f>,/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x00000000 0x000000ff>,<0x00000480 0x81700006 0xc1f03e1f>,/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x00000000 0x000000ff>,<0x000004a0 0x81b00006 0xc1f03e1f>;bootph-all;};/* DCE1 */i_ccu_dce1@1c006000 {reg = <0x1c006000 0x00001000>;intel,offset-settings =/* DCEUAMIGR1 */<0x000003c0 0x00000003 0x0000001f>,/* DCEUMIFSR1 */<0x000003c4 0x000000000x07070777>,
/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x00000000 0x000000ff>,<0x00000460 0x81300006 0xc1f03e1f>,/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x00000000 0x000000ff>,<0x00000480 0x81700006 0xc1f03e1f>,/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x00000000 0x000000ff>,<0x000004a0 0x81b00006 0xc1f03e1f>;bootph-all;};/* DMI0 */i_ccu_dmi0@1c007000 {reg = <0x1c007000 0x00001000>;intel,offset-settings =/* DMIUSMCTCR */<0x00000300 0x000000030x00000003>;
bootph-all;};
Please exclude above secreg changes for now because this driver is not in mainline yet. You can submit another patch for these changes once the driver is accepted into mainline.
/* DMI1 */i_ccu_dmi0@1c008000 {reg = <0x1c008000 0x00001000>;intel,offset-settings =/* DMIUSMCTCR */<0x00000300 0x000000030x00000003>;
bootph-all;};/* L4 peripherals firewall */noc_fw_l4_per@10d21000 {reg = <0x10d21000 0x0000008c>;intel,offset-settings =/* NAND */<0x00000000 0x010100010x01010001>,
/* USB0 */<0x0000000c 0x010100010x01010001>,
/* USB1 */<0x00000010 0x010100010x01010001>,
/* SPI_MAIN0 */<0x0000001c 0x010103010x01010301>,
/* SPI_MAIN1 */<0x00000020 0x010103010x01010301>,
/* SPI_SECONDARY0 */<0x00000024 0x010103010x01010301>,
/* SPI_SECONDARY1 */<0x00000028 0x010103010x01010301>,
/* EMAC0 */<0x0000002c 0x010100010x01010001>,
/* EMAC1 */<0x00000030 0x010100010x01010001>,
/* EMAC2 */<0x00000034 0x010100010x01010001>,
/* SDMMC */<0x00000040 0x010100010x01010001>,
/* GPIO0 */<0x00000044 0x010103010x01010301>,
/* GPIO1 */<0x00000048 0x010103010x01010301>,
/* I2C0 */<0x00000050 0x010103010x01010301>,
/* I2C1 */<0x00000054 0x010103010x01010301>,
/* I2C2 */<0x00000058 0x010103010x01010301>,
/* I2C3 */<0x0000005c 0x010103010x01010301>,
/* I2C4 */<0x00000060 0x010103010x01010301>,
/* SP_TIMER0 */<0x00000064 0x010103010x01010301>,
/* SP_TIMER1 */<0x00000068 0x010103010x01010301>,
/* UART0 */<0x0000006c 0x010103010x01010301>,
/* UART1 */<0x00000070 0x010103010x01010301>,
/* I3C0 */<0x00000074 0x010103010x01010301>,
/* I3C1 */<0x00000078 0x010103010x01010301>,
/* DMA0 */<0x0000007c 0x010100010x01010001>,
/* DMA1 */<0x00000080 0x010100010x01010001>,
/* COMBO_PHY */<0x00000084 0x010100010x01010001>,
/* NAND_SDMA */<0x00000088 0x010103010x01010301>;
bootph-all;};/* L4 system firewall */noc_fw_l4_sys@10d21100 {reg = <0x10d21100 0x00000098>;intel,offset-settings =/* DMA_ECC */<0x00000008 0x010100010x01010001>,
/* EMAC0RX_ECC */<0x0000000c 0x010100010x01010001>,
/* EMAC0TX_ECC */<0x00000010 0x010100010x01010001>,
/* EMAC1RX_ECC */<0x00000014 0x010100010x01010001>,
/* EMAC1TX_ECC */<0x00000018 0x010100010x01010001>,
/* EMAC2RX_ECC */<0x0000001c 0x010100010x01010001>,
/* EMAC2TX_ECC */<0x00000020 0x010100010x01010001>,
/* NAND_ECC */<0x0000002c 0x010100010x01010001>,
/* NAND_READ_ECC */<0x00000030 0x010100010x01010001>,
/* NAND_WRITE_ECC */<0x00000034 0x010100010x01010001>,
/* OCRAM_ECC */<0x00000038 0x010100010x01010001>,
/* SDMMC_ECC */<0x00000040 0x010100010x01010001>,
/* USB0_ECC */<0x00000044 0x010100010x01010001>,
/* USB1_CACHEECC */<0x00000048 0x010100010x01010001>,
/* CLOCK_MANAGER */<0x0000004c 0x010100010x01010001>,
/* IO_MANAGER */<0x00000054 0x010100010x01010001>,
/* RESET_MANAGER */<0x00000058 0x010100010x01010001>,
/* SYSTEM_MANAGER */<0x0000005c 0x010100010x01010001>,
/* OSC0_TIMER */<0x00000060 0x010103010x01010301>,
/* OSC1_TIMER0*/<0x00000064 0x010103010x01010301>,
/* WATCHDOG0 */<0x00000068 0x010103010x01010301>,
/* WATCHDOG1 */<0x0000006c 0x010103010x01010301>,
/* WATCHDOG2 */<0x00000070 0x010103010x01010301>,
/* WATCHDOG3 */<0x00000074 0x010103010x01010301>,
/* DAP */<0x00000078 0x030100010x03010001>,
/* WATCHDOG4 */<0x0000007c 0x010103010x01010301>,
/* POWER_MANAGER */<0x00000080 0x010100010x01010001>,
/* USB1_RXECC */<0x00000084 0x010100010x01010001>,
/* USB1_TXECC */<0x00000088 0x010100010x01010001>,
/* L4_NOC_PROBES */<0x00000090 0x010100010x01010001>,
/* L4_NOC_QOS */<0x00000094 0x010100010x01010001>;
bootph-all;};/* Light weight SoC2FPGA */noc_fw_lwsoc2fpga@10d21300 {reg = <0x10d21300 0x0000004>;intel,offset-settings =/* LWSOC2FPGA_CSR */<0x00000000 0x0ffe0301>;bootph-all;};/* SoC2FPGA */noc_fw_soc2fpga@10d21200 {reg = <0x10d21200 0x0000004>;intel,offset-settings =/* SOC2FPGA_CSR */<0x00000000 0x0ffe0301 0x0ffe0301>;bootph-all;};/* TCU */noc_fw_tcu@10d21400 {reg = <0x10d21400 0x0000004>;intel,offset-settings =/* TCU_CSR */<0x00000000 0x010100010x01010001>;
bootph-all;};};- };
+};
+&clkmgr {
- bootph-all;
+};
+&i2c0 {
- reset-names = "i2c";
+};
+&i2c1 {
- reset-names = "i2c";
+};
+&i2c2 {
- reset-names = "i2c";
+};
+&i2c3 {
- reset-names = "i2c";
+};
+&mmc {
- resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; };
+&porta {
- bank-name = "porta";
+};
+&portb {
- bank-name = "portb";
+};
+&qspi {
- bootph-all;
+};
+&rst {
- compatible = "altr,rst-mgr";
- altr,modrst-offset = <0x24>;
- bootph-all;
+};
+&sdr {
- compatible = "intel,sdr-ctl-agilex5";
- reg = <0x18000000 0x400000>,
<0x18400000 0x400000>,<0x18800000 0x400000>;- resets = <&rst DDRSCH_RESET>;
- bootph-all;
+};
+&sysmgr {
- compatible = "altr,sys-mgr", "syscon";
- bootph-all;
+};
+&uart0 {
- bootph-all;
+};
+&watchdog0 {
- bootph-all;
+}; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi new file mode 100644 index 0000000000..f445bc04ad --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -0,0 +1,634 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2022, Intel Corporation */
+/dts-v1/; +#include <dt-bindings/reset/altr,rst-mgr-agx5.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/agilex5-clock.h>
+/ {
- compatible = "intel,socfpga-agilex";
- #address-cells = <2>;
- #size-cells = <2>;
- reserved-memory {
#address-cells = <2>;#size-cells = <2>;ranges;service_reserved: svcbuffer@0 {compatible = "shared-dma-pool";reg = <0x0 0x0 0x0 0x1000000>;alignment = <0x1000>;no-map;};- };
- cpus {
#address-cells = <1>;#size-cells = <0>;cpu0: cpu@0 {compatible = "arm,cortex-a55";device_type = "cpu";enable-method = "psci";reg = <0x0>;};cpu1: cpu@1 {compatible = "arm,cortex-a55";device_type = "cpu";enable-method = "psci";reg = <0x1>;};cpu2: cpu@2 {compatible = "arm,cortex-a76";device_type = "cpu";enable-method = "psci";reg = <0x2>;};cpu3: cpu@3 {compatible = "arm,cortex-a76";device_type = "cpu";enable-method = "psci";reg = <0x3>;};- };
- pmu {
compatible = "arm,armv8-pmuv3";interrupts = <0 170 4>,<0 171 4>,<0 172 4>,<0 173 4>;interrupt-affinity = <&cpu0>,<&cpu1>,<&cpu2>,<&cpu3>;interrupt-parent = <&intc>;- };
- psci {
compatible = "arm,psci-0.2";method = "smc";- };
- intc: intc@fffc1000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";#interrupt-cells = <3>;interrupt-controller;reg = <0x0 0x1d000000 0x0 0x10000>;- };
- soc {
#address-cells = <1>;#size-cells = <1>;compatible = "simple-bus";device_type = "soc";interrupt-parent = <&intc>;ranges = <0 0 0 0xffffffff>;base_fpga_region {#address-cells = <0x1>;#size-cells = <0x1>;compatible = "fpga-region";fpga-mgr = <&fpga_mgr>;};clkmgr: clock-controller@10d10000 {compatible = "intel,agilex5-clkmgr";reg = <0x10d10000 0x1000>;#clock-cells = <1>;};clocks {cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {#clock-cells = <0>;compatible = "fixed-clock";};cb_intosc_ls_clk: cb-intosc-ls-clk {#clock-cells = <0>;compatible = "fixed-clock";};f2s_free_clk: f2s-free-clk {#clock-cells = <0>;compatible = "fixed-clock";};osc1: osc1 {#clock-cells = <0>;compatible = "fixed-clock";};qspi_clk: qspi-clk {#clock-cells = <0>;compatible = "fixed-clock";clock-frequency = <200000000>;};};gmac0: ethernet@10810000 {compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0x10810000 0x3500>;interrupts = <0 90 4>;interrupt-names = "macirq";mac-address = [00 00 00 00 00 00];resets = <&rst EMAC0_RESET>, <&rstEMAC0_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";tx-fifo-depth = <16384>;rx-fifo-depth = <16384>;snps,multicast-filter-bins = <256>;iommus = <&smmu 1>;altr,sysmgr-syscon = <&sysmgr 0x44 0>;clocks = <&clkmgr AGILEX5_EMAC0_CLK>;clock-names = "stmmaceth";status = "disabled";};gmac1: ethernet@10820000 {compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0x10820000 0x3500>;interrupts = <0 91 4>;interrupt-names = "macirq";mac-address = [00 00 00 00 00 00];resets = <&rst EMAC1_RESET>, <&rstEMAC1_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";tx-fifo-depth = <16384>;rx-fifo-depth = <16384>;snps,multicast-filter-bins = <256>;iommus = <&smmu 2>;altr,sysmgr-syscon = <&sysmgr 0x48 8>;clocks = <&clkmgr AGILEX5_EMAC1_CLK>;clock-names = "stmmaceth";status = "disabled";};gmac2: ethernet@10830000 {compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0x10830000 0x3500>;interrupts = <0 92 4>;interrupt-names = "macirq";mac-address = [00 00 00 00 00 00];resets = <&rst EMAC2_RESET>, <&rstEMAC2_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";tx-fifo-depth = <16384>;rx-fifo-depth = <16384>;snps,multicast-filter-bins = <256>;iommus = <&smmu 3>;altr,sysmgr-syscon = <&sysmgr 0x4c 16>;clocks = <&clkmgr AGILEX5_EMAC2_CLK>;clock-names = "stmmaceth";status = "disabled";};gpio0: gpio@10c03200 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,dw-apb-gpio";reg = <0x10c03200 0x80>;resets = <&rst GPIO0_RESET>;status = "disabled";porta: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;snps,nr-gpios = <24>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <0 110 4>;};};gpio1: gpio@10c03300 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,dw-apb-gpio";reg = <0x10c03300 0x80>;resets = <&rst GPIO1_RESET>;status = "disabled";portb: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;snps,nr-gpios = <24>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <0 111 4>;};};i2c0: i2c@10c02800 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0x10c02800 0x100>;interrupts = <0 103 4>;resets = <&rst I2C0_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};i2c1: i2c@10c02900 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0x10c02900 0x100>;interrupts = <0 104 4>;resets = <&rst I2C1_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};i2c2: i2c@10c02a00 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0x10c02a00 0x100>;interrupts = <0 105 4>;resets = <&rst I2C2_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};i2c3: i2c@10c02b00 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0x10c02b00 0x100>;interrupts = <0 106 4>;resets = <&rst I2C3_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};i2c4: i2c@10c02c00 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0x10c02c00 0x100>;interrupts = <0 107 4>;resets = <&rst I2C4_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};combophy0: combophy@0 {#phy-cells = <0>;phy-type = <1>;compatible = "cdns,combophy";reg = <0x10808000 0x1000>;resets = <&rst COMBOPHY_RESET>;reset-names = "reset";status = "disabled";};mmc: mmc0@10808000 {#address-cells = <1>;#size-cells = <0>;compatible = "cdns,sd4hc";reg = <0x10808000 0x1000>;interrupts = <0 96 4>;phys = <&combophy0>;phy-names = "combo-phy";clocks = <&clkmgr AGILEX5_L4_MP_CLK>,<&clkmgr AGILEX5_SDMMC_CLK>;clock-names = "biu", "ciu";fifo-depth = <0x800>;resets = <&rst SDMMC_RESET>;reset-names = "reset";iommus = <&smmu 5>;status = "disabled";};nand: nand@10b80000 {#address-cells = <1>;#size-cells = <0>;compatible = "altr,socfpga-denali-nand";reg = <0x10b80000 0x1038>,<0xffb80000 0x1000>;reg-names = "nand_data", "denali_reg";interrupts = <0 97 4>;clocks = <&clkmgr AGILEX5_NAND_CLK>,<&clkmgr AGILEX5_NAND_X_CLK>;clock-names = "nand", "nand_x";resets = <&rst NAND_RESET>, <&rstNAND_OCP_RESET>;
status = "disabled";};ocram: sram@00000000 {compatible = "mmio-sram";reg = <0x00000000 0x200000>;};rst: rstmgr@10d11000 {#reset-cells = <1>;compatible = "altr,stratix10-rst-mgr";reg = <0x10d11000 0x1000>;};smmu: iommu@16000000 {compatible = "arm,mmu-500", "arm,smmu-v2";reg = <0x16000000 0x40000>;#global-interrupts = <2>;#iommu-cells = <1>;interrupt-parent = <&intc>;interrupts = <0 128 4>, /* Global Secure Fault */<0 129 4>, /* Global Non-secure Fault *//* Non-secure Context Interrupts (32) */<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;stream-match-mask = <0x7ff0>;status = "disabled";};spi0: spi@10da4000 {compatible = "intel,agilex-spi","snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;#size-cells = <0>;reg = <0x10da4000 0x1000>;interrupts = <0 99 4>;resets = <&rst SPIM0_RESET>;reg-io-width = <4>;num-cs = <4>;clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;status = "disabled";};spi1: spi@10da5000 {compatible = "intel,agilex-spi","snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;#size-cells = <0>;reg = <0x10da5000 0x1000>;interrupts = <0 100 4>;resets = <&rst SPIM1_RESET>;reg-io-width = <4>;num-cs = <4>;clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;status = "disabled";};sysmgr: sysmgr@10d12000 {compatible = "altr,sys-mgr-s10","altr,sys-mgr";reg = <0x10d12000 0x500>;};/* Local timer */timer {compatible = "arm,armv8-timer";interrupts = <1 13 0xf08>,<1 14 0xf08>,<1 11 0xf08>,<1 10 0xf08>;};timer0: timer0@10c03000 {compatible = "snps,dw-apb-timer";interrupts = <0 113 4>;reg = <0x10c03000 0x100>;resets = <&rst SPTIMER0_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;clock-names = "timer";status = "disabled";};timer1: timer1@10c03100 {compatible = "snps,dw-apb-timer";interrupts = <0 114 4>;reg = <0x10c03100 0x100>;resets = <&rst SPTIMER1_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;clock-names = "timer";status = "disabled";};timer2: timer2@10d00000 {compatible = "snps,dw-apb-timer";interrupts = <0 115 4>;reg = <0x10d00000 0x100>;resets = <&rst L4SYSTIMER0_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;clock-names = "timer";status = "disabled";};timer3: timer3@10d00100 {compatible = "snps,dw-apb-timer";interrupts = <0 116 4>;reg = <0x10d00100 0x100>;resets = <&rst L4SYSTIMER1_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;clock-names = "timer";status = "disabled";};uart0: serial0@10c02000 {compatible = "snps,dw-apb-uart";reg = <0x10c02000 0x100>;interrupts = <0 108 4>;reg-shift = <2>;reg-io-width = <4>;resets = <&rst UART0_RESET>;status = "disabled";clocks = <&clkmgr AGILEX5_L4_SP_CLK>;clock-frequency = <100000000>;};uart1: serial1@10c02100 {compatible = "snps,dw-apb-uart";reg = <0x10c02100 0x100>;interrupts = <0 109 4>;reg-shift = <2>;reg-io-width = <4>;resets = <&rst UART1_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};usbphy0: usbphy@0 {#phy-cells = <0>;compatible = "usb-nop-xceiv";clocks = <&clkmgr AGILEX5_USB_CLK>;status = "disabled";};usb0: usb@10b00000 {compatible = "snps,dwc2";reg = <0x10b00000 0x40000>;interrupts = <0 93 4>;phys = <&usbphy0>;phy-names = "usb2-phy";resets = <&rst USB0_RESET>, <&rstUSB0_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";clocks = <&clkmgr AGILEX5_USB_CLK>;iommus = <&smmu 6>;status = "disabled";};usb31: usb31@11000000 {compatible = "snps,dwc3";reg = <0x11000000 0x100000>;resets = <&rst USB1_RESET>;phys = <&usbphy0>, <&usbphy0>;phy-names = "usb2-phy", "usb3-phy";dr_mode = "host";maximum-speed = "super-speed";snps,dis_u2_susphy_quirk;status = "disabled";};watchdog0: watchdog@10d00200 {compatible = "snps,dw-wdt";reg = <0x10d00200 0x100>;interrupts = <0 117 4>;resets = <&rst WATCHDOG0_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;status = "disabled";};watchdog1: watchdog@10d00300 {compatible = "snps,dw-wdt";reg = <0x10d00300 0x100>;interrupts = <0 118 4>;resets = <&rst WATCHDOG1_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;status = "disabled";};watchdog2: watchdog@10d00400 {compatible = "snps,dw-wdt";reg = <0x10d00400 0x100>;interrupts = <0 125 4>;resets = <&rst WATCHDOG2_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;status = "disabled";};watchdog3: watchdog@10d00500 {compatible = "snps,dw-wdt";reg = <0x10d00500 0x100>;interrupts = <0 126 4>;resets = <&rst WATCHDOG3_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;status = "disabled";};watchdog4: watchdog@10d00600 {compatible = "snps,dw-wdt";reg = <0x10d00600 0x100>;interrupts = <0 175 4>;resets = <&rst WATCHDOG4_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;status = "disabled";};sdr: sdr@10d21000 {compatible = "altr,sdr-ctl", "syscon";reg = <0x10d21000 0xc0>;};/* TODO: Update the ECC registers */eccmgr {compatible = "altr,socfpga-s10-ecc-manager","altr,socfpga-a10-ecc-manager";altr,sysmgr-syscon = <&sysmgr>;#address-cells = <1>;#size-cells = <1>;interrupts = <0 15 4>;interrupt-controller;#interrupt-cells = <2>;ranges;sdramedac {compatible = "altr,sdram-edac-s10";altr,sdr-syscon = <&sdr>;interrupts = <16 4>;};ocram-ecc@ff8cc000 {compatible = "altr,socfpga-s10-ocram-ecc","altr,socfpga-a10-ocram-ecc";reg = <0xff8cc000 0x100>;altr,ecc-parent = <&ocram>;interrupts = <1 4>;};usb0-ecc@ff8c4000 {compatible = "altr,socfpga-s10-usb-ecc","altr,socfpga-usb-ecc";reg = <0xff8c4000 0x100>;altr,ecc-parent = <&usb0>;interrupts = <2 4>;};emac0-rx-ecc@ff8c0000 {compatible = "altr,socfpga-s10-eth-mac-ecc","altr,socfpga-eth-mac-ecc";reg = <0xff8c0000 0x100>;altr,ecc-parent = <&gmac0>;interrupts = <4 4>;};emac0-tx-ecc@ff8c0400 {compatible = "altr,socfpga-s10-eth-mac-ecc","altr,socfpga-eth-mac-ecc";reg = <0xff8c0400 0x100>;altr,ecc-parent = <&gmac0>;interrupts = <5 4>;};sdmmca-ecc@ff8c8c00 {compatible = "altr,socfpga-s10-sdmmc-ecc","altr,socfpga-sdmmc-ecc";reg = <0xff8c8c00 0x100>;altr,ecc-parent = <&mmc>;interrupts = <14 4>,<15 4>;};};/* QSPI address not available yet */qspi: spi@108d2000 {compatible = "cdns,qspi-nor";#address-cells = <1>;#size-cells = <0>;reg = <0x108d2000 0x100>,<0x10900000 0x100000>;interrupts = <0 3 4>;cdns,fifo-depth = <128>;cdns,fifo-width = <4>;cdns,trigger-address = <0x00000000>;clocks = <&qspi_clk>;status = "disabled";};firmware {svc {compatible = "intel,stratix10-svc";method = "smc";memory-region = <&service_reserved>;fpga_mgr: fpga-mgr {compatible = "intel,stratix10-soc-fpga-mgr";
};};};- };
+}; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi new file mode 100644 index 0000000000..ad170353f8 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- U-Boot additions
- Copyright (C) 2022 Intel Corporation <www.intel.com> */
+#include "socfpga_agilex5-u-boot.dtsi"
+/{
- aliases {
spi0 = &qspi;freeze_br0 = &freeze_controller;- };
- soc {
freeze_controller: freeze_controller@f9000450 {compatible = "altr,freeze-bridge-controller";reg = <0xf9000450 0x00000010>;status = "disabled";};- };
- memory {
/* 2GB on Simics*/reg = <0 0x80000000 0 0x80000000>;- };
- chosen {
stdout-path = "serial0:115200n8";u-boot,spl-boot-order = &mmc,&flash0,"/memory";- };
+};
+&flash0 {
- compatible = "jedec,spi-nor";
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- bootph-all;
+};
+&nand {
- status = "okay";
- nand-bus-width = <16>;
- bootph-all;
+};
+&mmc {
- status = "okay";
- bus-width = <4>;
- sd-uhs-sdr50;
- cap-mmc-highspeed;
- bootph-all;
+};
+&combophy0 {
- status = "okay";
- bootph-all;
- cdns,phy-use-ext-lpbk-dqs = <1>;
- cdns,phy-use-lpbk-dqs = <1>;
- cdns,phy-use-phony-dqs = <1>;
- cdns,phy-use-phony-dqs-cmd = <1>;
- cdns,phy-io-mask-always-on = <0>;
- cdns,phy-io-mask-end = <5>;
- cdns,phy-io-mask-start = <0>;
- cdns,phy-data-select-oe-end = <1>;
- cdns,phy-sync-method = <1>;
- cdns,phy-sw-half-cycle-shift = <0>;
- cdns,phy-rd-del-sel = <52>;
- cdns,phy-underrun-suppress = <1>;
- cdns,phy-gate-cfg-always-on = <1>;
- cdns,phy-param-dll-bypass-mode = <1>;
- cdns,phy-param-phase-detect-sel = <2>;
- cdns,phy-param-dll-start-point = <254>;
- cdns,phy-read-dqs-cmd-delay = <0>;
- cdns,phy-clk-wrdqs-delay = <0>;
- cdns,phy-clk-wr-delay = <0>;
- cdns,phy-read-dqs-delay = <0>;
- cdns,phy-phony-dqs-timing = <0>;
- cdns,hrs09-rddata-en = <1>;
- cdns,hrs09-rdcmd-en = <1>;
- cdns,hrs09-extended-wr-mode = <1>;
- cdns,hrs09-extended-rd-mode = <1>;
- cdns,hrs10-hcsdclkadj = <3>;
- cdns,hrs16-wrdata1-sdclk-dly = <0>;
- cdns,hrs16-wrdata0-sdclk-dly = <0>;
- cdns,hrs16-wrcmd1-sdclk-dly = <0>;
- cdns,hrs16-wrcmd0-sdclk-dly = <0>;
- cdns,hrs16-wrdata1-dly = <0>;
- cdns,hrs16-wrdata0-dly = <0>;
- cdns,hrs16-wrcmd1-dly = <0>;
- cdns,hrs16-wrcmd0-dly = <0>;
- cdns,hrs07-rw-compensate = <10>;
- cdns,hrs07-idelay-val = <0>;
+};
+&qspi {
- status = "okay";
+};
+&timer0 {
- bootph-all;
+};
+&timer1 {
- bootph-all;
+};
+&timer2 {
- bootph-all;
+};
+&timer3 {
- bootph-all;
+};
+&watchdog0 {
- bootph-all;
+};
+#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&fdt_0_blob {
- filename = "arch/arm/dts/socfpga_agilex5_socdk.dtb";
+};
+/* To add NAND dtb when ready in future */
+&binman {
- /delete-node/ kernel;
+}; +#endif diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts new file mode 100644 index 0000000000..1a39426561 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019-2022, Intel Corporation */ #include
+"socfpga_agilex5.dtsi"
+/ {
- model = "SoCFPGA Agilex5 SoCDK";
- aliases {
serial0 = &uart0;- };
- leds {
compatible = "gpio-leds";hps0 {label = "hps_led0";gpios = <&portb 20 GPIO_ACTIVE_HIGH>;};hps1 {label = "hps_led1";gpios = <&portb 19 GPIO_ACTIVE_HIGH>;};hps2 {label = "hps_led2";gpios = <&portb 21 GPIO_ACTIVE_HIGH>;};- };
- memory {
device_type = "memory";/* We expect the bootloader to fill in the reg */reg = <0 0 0 0>;- };
- soc {
clocks {osc1 {clock-frequency = <25000000>;};};- };
+};
+&gpio0 {
- status = "okay";
+};
+&gpio1 {
- status = "okay";
+};
+&i2c0 {
- status = "okay";
+};
+&i2c1 {
- status = "okay";
+};
+&mmc {
- status = "okay";
+};
+&combophy0 {
- status = "okay";
+};
+&uart0 {
- status = "okay";
+};
+&usbphy0 {
- status = "okay";
+};
+&usb0 {
- status = "okay";
- disable-over-current;
+};
+&usb31 {
- status = "okay";
+};
+&watchdog0 {
- status = "okay";
+};
+&watchdog1 {
- status = "okay";
+};
+&watchdog2 {
- status = "okay";
+};
+&watchdog3 {
- status = "okay";
+};
+&watchdog4 {
- status = "okay";
+};
+&timer0 {
- status = "okay";
+};
+&timer1 {
- status = "okay";
+};
+&timer2 {
- status = "okay";
+};
+&timer3 {
- status = "okay";
+};
+&spi0 {
- status = "okay";
+};
+&spi1 {
- status = "okay";
+};
+&qspi {
- flash0: flash@0 {
#address-cells = <1>;#size-cells = <1>;compatible = "mt25qu02g";reg = <0>;spi-max-frequency = <100000000>;m25p,fast-read;cdns,page-size = <256>;cdns,block-size = <16>;cdns,read-delay = <1>;cdns,tshsl-ns = <50>;cdns,tsd2d-ns = <50>;cdns,tchsh-ns = <4>;cdns,tslch-ns = <4>;partitions {compatible = "fixed-partitions";#address-cells = <1>;#size-cells = <1>;qspi_boot: partition@0 {label = "Boot and fpga data";reg = <0x0 0x034B0000>;};qspi_rootfs: partition@34B0000 {label = "Root Filesystem - JFFS2";reg = <0x034B0000 0x0EB50000>;};};- };
+}; diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 84b91e8df0..1ca721f070 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -2,7 +2,7 @@ /*
- U-Boot additions
- Copyright (C) 2020 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
#if defined(CONFIG_FIT) @@ -21,14 +21,18 @@ description = "FIT with firmware and bootloader"; #address-cells = <1>;
images {
images: images { uboot { description = "U-Boot SoC64"; type = "standalone"; os = "U-Boot"; arch = "arm64"; compression = "none";#ifIS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
load = <0x80200000>;#else load = <0x00200000>;#endif uboot_blob: blob-ext { filename = "u-boot-nodtb.bin"; }; @@ -43,8 +47,13 @@ os = "arm-trusted-firmware"; arch = "arm64"; compression = "none";
#ifIS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
load = <0x80000000>;entry = <0x80000000>;#else load = <0x00001000>; entry = <0x00001000>;#endif atf_blob: blob-ext { filename = "bl31.bin"; };@@ -53,11 +62,11 @@ }; };
fdt {description = "U-Boot SoC64 flatdevice-tree";
fdt-0 {description = "socfpga_socdk"; type = "flat_dt"; compression = "none";
uboot_fdt_blob: blob-ext {
fdt_0_blob: blob-ext { filename = "u-boot.dtb"; }; hash {@@ -66,17 +75,18 @@ }; };
configurations {default = "conf";conf {description = "Intel SoC64 FPGA";
board_config: configurations {default = "board-0";board-0 {description = "board_0"; firmware = "atf"; loadables = "uboot";
fdt = "fdt";
fdt = "fdt-0"; signature { algo = "crc32"; key-name-hint = "dev";
sign-images = "atf", "fdt","uboot";
sign-images = "atf", "uboot","fdt-0"; }; }; }; @@ -96,8 +106,8 @@ arch = "arm64"; os = "linux"; compression = "none";
load = <0x4080000>;entry = <0x4080000>;
load = <0x6000000>;entry = <0x6000000>; kernel_blob: blob-ext { filename = "Image"; };@@ -146,7 +156,7 @@ filename = "signed-bl31.bin"; };
-&uboot_fdt_blob { +&fdt_0_blob { filename = "signed-u-boot.dtb"; };
diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi new file mode 100644 index 0000000000..add9890de3 --- /dev/null +++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- U-Boot additions
- Copyright (C) 2021-2022 Intel Corporation <www.intel.com> */
+/ {
- soc {
socfpga_secreg: socfpga-secreg {compatible = "intel,socfpga-secreg";#address-cells = <1>;#size-cells = <1>;bootph-all;i_sys_mgr_core@ffd12000 {reg = <0xffd12000 0x00000230>;intel,offset-settings =/* Enable non-secure interface toDMA */
<0x00000020 0xff010000 0xff010011>,/* Enable non-secure interface toDMA periph */
<0x00000024 0xffffffff 0xffffffff>;bootph-all;};noc_fw_l4_per_l4_per_scr@ffd21000 {reg = <0xffd21000 0x00000074>;intel,offset-settings =/* Disable L4 periphs firewall */<0x00000000 0x010100010x01010001>,
<0x00000004 0x010100010x01010001>,
<0x0000000c 0x010100010x01010001>,
<0x00000010 0x010100010x01010001>,
<0x0000001c 0x010100010x01010101>,
<0x00000020 0x010100010x01010101>,
<0x00000024 0x010100010x01010101>,
<0x00000028 0x010100010x01010101>,
<0x0000002c 0x010100010x01010001>,
<0x00000030 0x010100010x01010001>,
<0x00000034 0x010100010x01010001>,
<0x00000040 0x010100010x01010001>,
<0x00000044 0x010100010x01010101>,
<0x00000048 0x010100010x01010101>,
<0x00000050 0x010100010x01010101>,
<0x00000054 0x010100010x01010101>,
<0x00000058 0x010100010x01010101>,
<0x0000005c 0x010100010x01010101>,
<0x00000060 0x010100010x01010101>,
<0x00000064 0x010100010x01010101>,
<0x00000068 0x010100010x01010101>,
<0x0000006c 0x010100010x01010101>,
<0x00000070 0x010100010x01010101>;
bootph-all;};noc_fw_l4_sys_l4_sys_scr@ffd21100 {reg = <0xffd21100 0x00000098>;intel,offset-settings =/* Disable L4 system firewall */<0x00000008 0x010100010x01010001>,
<0x0000000c 0x010100010x01010001>,
<0x00000010 0x010100010x01010001>,
<0x00000014 0x010100010x01010001>,
<0x00000018 0x010100010x01010001>,
<0x0000001c 0x010100010x01010001>,
<0x00000020 0x010100010x01010001>,
<0x0000002c 0x010100010x01010001>,
<0x00000030 0x010100010x01010001>,
<0x00000034 0x010100010x01010001>,
<0x00000038 0x010100010x01010001>,
<0x00000040 0x010100010x01010001>,
<0x00000044 0x010100010x01010001>,
<0x00000048 0x010100010x01010001>,
<0x0000004c 0x010100010x01010001>,
<0x00000054 0x010100010x01010001>,
<0x00000058 0x010100010x01010001>,
<0x0000005c 0x010100010x01010001>,
<0x00000060 0x010100010x01010101>,
<0x00000064 0x010100010x01010101>,
<0x00000068 0x010100010x01010101>,
<0x0000006c 0x010100010x01010101>,
<0x00000070 0x010100010x01010101>,
<0x00000074 0x010100010x01010101>,
<0x00000078 0x010100010x03010001>,
<0x00000090 0x010100010x01010001>,
<0x00000094 0x010100010x01010001>;
bootph-all;};noc_fw_soc2fpga_soc2fpga_scr@ffd21200 {reg = <0xffd21200 0x00000004>;/* Disable soc2fpga security access */intel,offset-settings = <0x000000000x0ffe0101 0x0ffe0101>;
bootph-all;};noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 {reg = <0xffd21300 0x00000004>;/* Disable lightweight soc2fpga securityaccess */
intel,offset-settings = <0x000000000x0ffe0101 0x0ffe0101>;
bootph-all;};noc_fw_tcu_tcu_scr@ffd21400 {reg = <0xffd21400 0x00000004>;/* Disable DMA ECC security access, forSMMU use */
intel,offset-settings = <0x000000000x01010001 0x01010001>;
bootph-all;};noc_fw_priv_MemoryMap_priv@ffd24800 {reg = <0xffd24800 0x0000000c>;intel,offset-settings =/* Enable non-prviledged access tovarious periphs */
<0x00000000 0xfff73ffb 0xfff73ffb>;bootph-all;};};- };
+}; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi old mode 100755 new mode 100644 diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi old mode 100755 new mode 100644 diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts old mode 100755 new mode 100644 -- 2.26.2
-----Original Message----- From: Chee, Tien Fong tien.fong.chee@intel.com Sent: Wednesday, 28 June, 2023 5:14 PM To: Lim, Jit Loon jit.loon.lim@intel.com; u-boot@lists.denx.de Cc: Jagan Teki jagan@amarulasolutions.com; Vignesh R vigneshr@ti.com; Vasut, Marek marex@denx.de; Simon simon.k.r.goldschmidt@gmail.com; Hea, Kok Kiang kok.kiang.hea@intel.com; Lokanathan, Raaj raaj.lokanathan@intel.com; Maniyam, Dinesh dinesh.maniyam@intel.com; Ng, Boon Khai boon.khai.ng@intel.com; Yuslaimi, Alif Zakuan alif.zakuan.yuslaimi@intel.com; Chong, Teik Heng teik.heng.chong@intel.com; Zamri, Muhammad Hazim Izzat muhammad.hazim.izzat.zamri@intel.com; Tang, Sieu Mun sieu.mun.tang@intel.com Subject: RE: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new platform agilex5
Hi Jit Loon,
-----Original Message----- From: Lim, Jit Loon jit.loon.lim@intel.com Sent: Wednesday, 21 June, 2023 11:16 AM To: u-boot@lists.denx.de Cc: Jagan Teki jagan@amarulasolutions.com; Vignesh R vigneshr@ti.com; Vasut, Marek marex@denx.de; Simon simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Hea, Kok Kiang kok.kiang.hea@intel.com; Lokanathan, Raaj raaj.lokanathan@intel.com; Maniyam, Dinesh dinesh.maniyam@intel.com; Ng, Boon Khai boon.khai.ng@intel.com; Yuslaimi, Alif Zakuan alif.zakuan.yuslaimi@intel.com; Chong, Teik Heng teik.heng.chong@intel.com; Zamri, Muhammad Hazim Izzat muhammad.hazim.izzat.zamri@intel.com; Lim, Jit Loon jit.loon.lim@intel.com; Tang, Sieu Mun sieu.mun.tang@intel.com Subject: [PATCH v1 02/17] arch: arm: dts: add dts and dtsi for new platform agilex5
This is for new platform enablement for agilex5. Add agilex5 dtsi and dts. Update checkpatch error for stratix10.
Why having checkpatch error for Stratix10? This should be in a separate patch.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 459 +++++++++++++ arch/arm/dts/socfpga_agilex5.dtsi | 634 ++++++++++++++++++ .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 131 ++++ arch/arm/dts/socfpga_agilex5_socdk.dts | 165 +++++ arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 38 +- arch/arm/dts/socfpga_soc64_u-boot.dtsi | 120 ++++ arch/arm/dts/socfpga_stratix10.dtsi | 0 .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 0 arch/arm/dts/socfpga_stratix10_socdk.dts | 0 10 files changed, 1534 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk-u- boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 480269fa60..2e4bc556e1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -456,6 +456,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \
- socfpga_agilex5_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_2.dtb \
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi new file mode 100644 index 0000000000..6a1299901a --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- U-Boot additions
- Copyright (C) 2019-2022 Intel Corporation <www.intel.com> */
+#include "socfpga_soc64_u-boot.dtsi" +#include "socfpga_soc64_fit-u-boot.dtsi"
+/{
- memory {
#address-cells = <2>;#size-cells = <2>;bootph-all;- };
- soc {
bootph-all;socfpga_secreg: socfpga-secreg {compatible = "intel,socfpga-secreg";#address-cells = <1>;#size-cells = <1>;bootph-all;/* DSU */i_ccu_caiu0@1c000000 {reg = <0x1c000000 0x00001000>;intel,offset-settings =/* CAIUAMIGR */<0x000003c0 0x000000030x0000001f>,
/* CAIUMIFSR */<0x000003c4 0x000000000x07070777>,
/* DII1_MPFEREGS */<0x00000414 0x00018000 0xffffffff>,<0x00000418 0x000000000x000000ff>,
<0x00000410 0xc0e002000xc1f03e1f>,
/* DII2_GICREGS */<0x00000424 0x0001d000 0xffffffff>,<0x00000428 0x000000000x000000ff>,
<0x00000420 0xc08004000xc1f03e1f>,
/* NCAIU0_LWSOC2FPGA */<0x00000444 0x00020000 0xffffffff>,<0x00000448 0x000000000x000000ff>,
<0x00000440 0xc11000060xc1f03e1f>,
/* NCAIU0_SOC2FPGA_1G */<0x00000454 0x00040000 0xffffffff>,<0x00000458 0x000000000x000000ff>,
<0x00000450 0xc12000060xc1f03e1f>,
/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x000000000x000000ff>,
<0x00000460 0x813000060xc1f03e1f>,
/* NCAIU0_SOC2FPGA_16G */<0x00000474 0x00400000 0xffffffff>,<0x00000478 0x000000000x000000ff>,
<0x00000470 0xc16000060xc1f03e1f>,
/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x000000000x000000ff>,
<0x00000480 0x817000060xc1f03e1f>,
/* NCAIU0_SOC2FPGA_256G */<0x00000494 0x04000000 0xffffffff>,<0x00000498 0x000000000x000000ff>,
<0x00000490 0xc1a000060xc1f03e1f>,
/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x000000000x000000ff>,
<0x000004a0 0x81b000060xc1f03e1f>;
bootph-all;};/* FPGA2SOC */i_ccu_ncaiu0@1c001000 {reg = <0x1c001000 0x00001000>;intel,offset-settings =/* NCAIU0AMIGR */<0x000003c0 0x000000030x0000001f>,
/* NCAIU0MIFSR */<0x000003c4 0x000000000x07070777>,
/* PSS */<0x00000404 0x00010000 0xffffffff>,<0x00000408 0x000000000x000000ff>,
<0x00000400 0xC0F000000xc1f03e1f>,
/* DII1_MPFEREGS */<0x00000414 0x00018000 0xffffffff>,<0x00000418 0x000000000x000000ff>,
<0x00000410 0xc0e002000xc1f03e1f>,
/* NCAIU0_LWSOC2FPGA */<0x00000444 0x00020000 0xffffffff>,<0x00000448 0x000000000x000000ff>,
<0x00000440 0xc11000060xc1f03e1f>,
/* NCAIU0_SOC2FPGA_1G */<0x00000454 0x00040000 0xffffffff>,<0x00000458 0x000000000x000000ff>,
<0x00000450 0xc12000060xc1f03e1f>,
/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x000000000x000000ff>,
<0x00000460 0x813000060xc1f03e1f>,
/* NCAIU0_SOC2FPGA_16G */<0x00000474 0x00400000 0xffffffff>,<0x00000478 0x000000000x000000ff>,
<0x00000470 0xc16000060xc1f03e1f>,
/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x000000000x000000ff>,
<0x00000480 0x817000060xc1f03e1f>,
/* NCAIU0_SOC2FPGA_256G */<0x00000494 0x04000000 0xffffffff>,<0x00000498 0x000000000x000000ff>,
<0x00000490 0xc1a000060xc1f03e1f>,
/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x000000000x000000ff>,
<0x000004a0 0x81b000060xc1f03e1f>;
bootph-all;};/* GIC_M */i_ccu_ncaiu1@1c002000 {reg = <0x1c002000 0x00001000>;intel,offset-settings =/* NCAIU1AMIGR */<0x000003c0 0x000000030x0000001f>,
/* NCAIU1MIFSR */<0x000003c4 0x000000000x07070777>,
/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x000000000x000000ff>,
<0x00000460 0x813000060xc1f03e1f>,
/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x000000000x000000ff>,
<0x00000480 0x817000060xc1f03e1f>,
/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x000000000x000000ff>,
<0x000004a0 0x81b000060xc1f03e1f>;
bootph-all;};/* PSS NOC */i_ccu_ncaiu3@1c004000 {reg = <0x1c004000 0x00001000>;intel,offset-settings =/* NCAIU3AMIGR */<0x000003c0 0x000000030x0000001f>,
/* NCAIU3MIFSR */<0x000003c4 0x000000000x07070777>,
/* DII1_MPFEREGS */<0x00000414 0x00018000 0xffffffff>,<0x00000418 0x000000000x000000ff>,
<0x00000410 0xc0e002000xc1f03e1f>,
/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x000000000x000000ff>,
<0x00000460 0x813000060xc1f03e1f>,
/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x000000000x000000ff>,
<0x00000480 0x817000060xc1f03e1f>,
/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x000000000x000000ff>,
<0x000004a0 0x81b000060xc1f03e1f>;
bootph-all;};/* DCE0 */i_ccu_dce0@1c005000 {reg = <0x1c005000 0x00001000>;intel,offset-settings =/* DCEUAMIGR0 */<0x000003c0 0x000000030x0000001f>,
/* DCEUMIFSR0 */<0x000003c4 0x000000000x07070777>,
/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x000000000x000000ff>,
<0x00000460 0x813000060xc1f03e1f>,
/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x000000000x000000ff>,
<0x00000480 0x817000060xc1f03e1f>,
/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x000000000x000000ff>,
<0x000004a0 0x81b000060xc1f03e1f>;
bootph-all;};/* DCE1 */i_ccu_dce1@1c006000 {reg = <0x1c006000 0x00001000>;intel,offset-settings =/* DCEUAMIGR1 */<0x000003c0 0x000000030x0000001f>,
/* DCEUMIFSR1 */<0x000003c4 0x000000000x07070777>,
/* DMI_SDRAM_2G */<0x00000464 0x00080000 0xffffffff>,<0x00000468 0x000000000x000000ff>,
<0x00000460 0x813000060xc1f03e1f>,
/* DMI_SDRAM_30G */<0x00000484 0x00800000 0xffffffff>,<0x00000488 0x000000000x000000ff>,
<0x00000480 0x817000060xc1f03e1f>,
/* DMI_SDRAM_480G */<0x000004a4 0x08000000 0xffffffff>,<0x000004a8 0x000000000x000000ff>,
<0x000004a0 0x81b000060xc1f03e1f>;
bootph-all;};/* DMI0 */i_ccu_dmi0@1c007000 {reg = <0x1c007000 0x00001000>;intel,offset-settings =/* DMIUSMCTCR */<0x00000300 0x000000030x00000003>;
bootph-all;};Please exclude above secreg changes for now because this driver is not in mainline yet. You can submit another patch for these changes once the driver is accepted into mainline.
/* DMI1 */i_ccu_dmi0@1c008000 {reg = <0x1c008000 0x00001000>;intel,offset-settings =/* DMIUSMCTCR */<0x00000300 0x000000030x00000003>;
bootph-all;};/* L4 peripherals firewall */noc_fw_l4_per@10d21000 {reg = <0x10d21000 0x0000008c>;intel,offset-settings =/* NAND */<0x00000000 0x010100010x01010001>,
/* USB0 */<0x0000000c 0x010100010x01010001>,
/* USB1 */<0x00000010 0x010100010x01010001>,
/* SPI_MAIN0 */<0x0000001c 0x010103010x01010301>,
/* SPI_MAIN1 */<0x00000020 0x010103010x01010301>,
/* SPI_SECONDARY0 */<0x00000024 0x010103010x01010301>,
/* SPI_SECONDARY1 */<0x00000028 0x010103010x01010301>,
/* EMAC0 */<0x0000002c 0x010100010x01010001>,
/* EMAC1 */<0x00000030 0x010100010x01010001>,
/* EMAC2 */<0x00000034 0x010100010x01010001>,
/* SDMMC */<0x00000040 0x010100010x01010001>,
/* GPIO0 */<0x00000044 0x010103010x01010301>,
/* GPIO1 */<0x00000048 0x010103010x01010301>,
/* I2C0 */<0x00000050 0x010103010x01010301>,
/* I2C1 */<0x00000054 0x010103010x01010301>,
/* I2C2 */<0x00000058 0x010103010x01010301>,
/* I2C3 */<0x0000005c 0x010103010x01010301>,
/* I2C4 */<0x00000060 0x010103010x01010301>,
/* SP_TIMER0 */<0x00000064 0x010103010x01010301>,
/* SP_TIMER1 */<0x00000068 0x010103010x01010301>,
/* UART0 */<0x0000006c 0x010103010x01010301>,
/* UART1 */<0x00000070 0x010103010x01010301>,
/* I3C0 */<0x00000074 0x010103010x01010301>,
/* I3C1 */<0x00000078 0x010103010x01010301>,
/* DMA0 */<0x0000007c 0x010100010x01010001>,
/* DMA1 */<0x00000080 0x010100010x01010001>,
/* COMBO_PHY */<0x00000084 0x010100010x01010001>,
/* NAND_SDMA */<0x00000088 0x010103010x01010301>;
bootph-all;};/* L4 system firewall */noc_fw_l4_sys@10d21100 {reg = <0x10d21100 0x00000098>;intel,offset-settings =/* DMA_ECC */<0x00000008 0x010100010x01010001>,
/* EMAC0RX_ECC */<0x0000000c 0x010100010x01010001>,
/* EMAC0TX_ECC */<0x00000010 0x010100010x01010001>,
/* EMAC1RX_ECC */<0x00000014 0x010100010x01010001>,
/* EMAC1TX_ECC */<0x00000018 0x010100010x01010001>,
/* EMAC2RX_ECC */<0x0000001c 0x010100010x01010001>,
/* EMAC2TX_ECC */<0x00000020 0x010100010x01010001>,
/* NAND_ECC */<0x0000002c 0x010100010x01010001>,
/* NAND_READ_ECC */<0x00000030 0x010100010x01010001>,
/* NAND_WRITE_ECC */<0x00000034 0x010100010x01010001>,
/* OCRAM_ECC */<0x00000038 0x010100010x01010001>,
/* SDMMC_ECC */<0x00000040 0x010100010x01010001>,
/* USB0_ECC */<0x00000044 0x010100010x01010001>,
/* USB1_CACHEECC */<0x00000048 0x010100010x01010001>,
/* CLOCK_MANAGER */<0x0000004c 0x010100010x01010001>,
/* IO_MANAGER */<0x00000054 0x010100010x01010001>,
/* RESET_MANAGER */<0x00000058 0x010100010x01010001>,
/* SYSTEM_MANAGER */<0x0000005c 0x010100010x01010001>,
/* OSC0_TIMER */<0x00000060 0x010103010x01010301>,
/* OSC1_TIMER0*/<0x00000064 0x010103010x01010301>,
/* WATCHDOG0 */<0x00000068 0x010103010x01010301>,
/* WATCHDOG1 */<0x0000006c 0x010103010x01010301>,
/* WATCHDOG2 */<0x00000070 0x010103010x01010301>,
/* WATCHDOG3 */<0x00000074 0x010103010x01010301>,
/* DAP */<0x00000078 0x030100010x03010001>,
/* WATCHDOG4 */<0x0000007c 0x010103010x01010301>,
/* POWER_MANAGER */<0x00000080 0x010100010x01010001>,
/* USB1_RXECC */<0x00000084 0x010100010x01010001>,
/* USB1_TXECC */<0x00000088 0x010100010x01010001>,
/* L4_NOC_PROBES */<0x00000090 0x010100010x01010001>,
/* L4_NOC_QOS */<0x00000094 0x010100010x01010001>;
bootph-all;};/* Light weight SoC2FPGA */noc_fw_lwsoc2fpga@10d21300 {reg = <0x10d21300 0x0000004>;intel,offset-settings =/* LWSOC2FPGA_CSR */<0x00000000 0x0ffe0301>;bootph-all;};/* SoC2FPGA */noc_fw_soc2fpga@10d21200 {reg = <0x10d21200 0x0000004>;intel,offset-settings =/* SOC2FPGA_CSR */<0x00000000 0x0ffe0301 0x0ffe0301>;bootph-all;};/* TCU */noc_fw_tcu@10d21400 {reg = <0x10d21400 0x0000004>;intel,offset-settings =/* TCU_CSR */<0x00000000 0x010100010x01010001>;
bootph-all;};};- };
+};
+&clkmgr {
- bootph-all;
+};
+&i2c0 {
- reset-names = "i2c";
+};
+&i2c1 {
- reset-names = "i2c";
+};
+&i2c2 {
- reset-names = "i2c";
+};
+&i2c3 {
- reset-names = "i2c";
+};
+&mmc {
- resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; };
+&porta {
- bank-name = "porta";
+};
+&portb {
- bank-name = "portb";
+};
+&qspi {
- bootph-all;
+};
+&rst {
- compatible = "altr,rst-mgr";
- altr,modrst-offset = <0x24>;
- bootph-all;
+};
+&sdr {
- compatible = "intel,sdr-ctl-agilex5";
- reg = <0x18000000 0x400000>,
<0x18400000 0x400000>,<0x18800000 0x400000>;- resets = <&rst DDRSCH_RESET>;
- bootph-all;
+};
+&sysmgr {
- compatible = "altr,sys-mgr", "syscon";
- bootph-all;
+};
+&uart0 {
- bootph-all;
+};
+&watchdog0 {
- bootph-all;
+}; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi new file mode 100644 index 0000000000..f445bc04ad --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -0,0 +1,634 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2022, Intel Corporation */
+/dts-v1/; +#include <dt-bindings/reset/altr,rst-mgr-agx5.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/agilex5-clock.h>
+/ {
- compatible = "intel,socfpga-agilex";
- #address-cells = <2>;
- #size-cells = <2>;
- reserved-memory {
#address-cells = <2>;#size-cells = <2>;ranges;service_reserved: svcbuffer@0 {compatible = "shared-dma-pool";reg = <0x0 0x0 0x0 0x1000000>;alignment = <0x1000>;no-map;};- };
- cpus {
#address-cells = <1>;#size-cells = <0>;cpu0: cpu@0 {compatible = "arm,cortex-a55";device_type = "cpu";enable-method = "psci";reg = <0x0>;};cpu1: cpu@1 {compatible = "arm,cortex-a55";device_type = "cpu";enable-method = "psci";reg = <0x1>;};cpu2: cpu@2 {compatible = "arm,cortex-a76";device_type = "cpu";enable-method = "psci";reg = <0x2>;};cpu3: cpu@3 {compatible = "arm,cortex-a76";device_type = "cpu";enable-method = "psci";reg = <0x3>;};- };
- pmu {
compatible = "arm,armv8-pmuv3";interrupts = <0 170 4>,<0 171 4>,<0 172 4>,<0 173 4>;interrupt-affinity = <&cpu0>,<&cpu1>,<&cpu2>,<&cpu3>;interrupt-parent = <&intc>;- };
- psci {
compatible = "arm,psci-0.2";method = "smc";- };
- intc: intc@fffc1000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";#interrupt-cells = <3>;interrupt-controller;reg = <0x0 0x1d000000 0x0 0x10000>;- };
- soc {
#address-cells = <1>;#size-cells = <1>;compatible = "simple-bus";device_type = "soc";interrupt-parent = <&intc>;ranges = <0 0 0 0xffffffff>;base_fpga_region {#address-cells = <0x1>;#size-cells = <0x1>;compatible = "fpga-region";fpga-mgr = <&fpga_mgr>;};clkmgr: clock-controller@10d10000 {compatible = "intel,agilex5-clkmgr";reg = <0x10d10000 0x1000>;#clock-cells = <1>;};clocks {cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {#clock-cells = <0>;compatible = "fixed-clock";};cb_intosc_ls_clk: cb-intosc-ls-clk {#clock-cells = <0>;compatible = "fixed-clock";};f2s_free_clk: f2s-free-clk {#clock-cells = <0>;compatible = "fixed-clock";};osc1: osc1 {#clock-cells = <0>;compatible = "fixed-clock";};qspi_clk: qspi-clk {#clock-cells = <0>;compatible = "fixed-clock";clock-frequency = <200000000>;};};gmac0: ethernet@10810000 {compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0x10810000 0x3500>;interrupts = <0 90 4>;interrupt-names = "macirq";mac-address = [00 00 00 00 00 00];resets = <&rst EMAC0_RESET>, <&rstEMAC0_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";tx-fifo-depth = <16384>;rx-fifo-depth = <16384>;snps,multicast-filter-bins = <256>;iommus = <&smmu 1>;altr,sysmgr-syscon = <&sysmgr 0x44 0>;clocks = <&clkmgr AGILEX5_EMAC0_CLK>;clock-names = "stmmaceth";status = "disabled";};gmac1: ethernet@10820000 {compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0x10820000 0x3500>;interrupts = <0 91 4>;interrupt-names = "macirq";mac-address = [00 00 00 00 00 00];resets = <&rst EMAC1_RESET>, <&rstEMAC1_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";tx-fifo-depth = <16384>;rx-fifo-depth = <16384>;snps,multicast-filter-bins = <256>;iommus = <&smmu 2>;altr,sysmgr-syscon = <&sysmgr 0x48 8>;clocks = <&clkmgr AGILEX5_EMAC1_CLK>;clock-names = "stmmaceth";status = "disabled";};gmac2: ethernet@10830000 {compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0x10830000 0x3500>;interrupts = <0 92 4>;interrupt-names = "macirq";mac-address = [00 00 00 00 00 00];resets = <&rst EMAC2_RESET>, <&rstEMAC2_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";tx-fifo-depth = <16384>;rx-fifo-depth = <16384>;snps,multicast-filter-bins = <256>;iommus = <&smmu 3>;altr,sysmgr-syscon = <&sysmgr 0x4c 16>;clocks = <&clkmgr AGILEX5_EMAC2_CLK>;clock-names = "stmmaceth";status = "disabled";};gpio0: gpio@10c03200 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,dw-apb-gpio";reg = <0x10c03200 0x80>;resets = <&rst GPIO0_RESET>;status = "disabled";porta: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;snps,nr-gpios = <24>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <0 110 4>;};};gpio1: gpio@10c03300 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,dw-apb-gpio";reg = <0x10c03300 0x80>;resets = <&rst GPIO1_RESET>;status = "disabled";portb: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;snps,nr-gpios = <24>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <0 111 4>;};};i2c0: i2c@10c02800 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0x10c02800 0x100>;interrupts = <0 103 4>;resets = <&rst I2C0_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};i2c1: i2c@10c02900 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0x10c02900 0x100>;interrupts = <0 104 4>;resets = <&rst I2C1_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};i2c2: i2c@10c02a00 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0x10c02a00 0x100>;interrupts = <0 105 4>;resets = <&rst I2C2_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};i2c3: i2c@10c02b00 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0x10c02b00 0x100>;interrupts = <0 106 4>;resets = <&rst I2C3_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};i2c4: i2c@10c02c00 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0x10c02c00 0x100>;interrupts = <0 107 4>;resets = <&rst I2C4_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};combophy0: combophy@0 {#phy-cells = <0>;phy-type = <1>;compatible = "cdns,combophy";reg = <0x10808000 0x1000>;resets = <&rst COMBOPHY_RESET>;reset-names = "reset";status = "disabled";};mmc: mmc0@10808000 {#address-cells = <1>;#size-cells = <0>;compatible = "cdns,sd4hc";reg = <0x10808000 0x1000>;interrupts = <0 96 4>;phys = <&combophy0>;phy-names = "combo-phy";clocks = <&clkmgr AGILEX5_L4_MP_CLK>,<&clkmgr AGILEX5_SDMMC_CLK>;clock-names = "biu", "ciu";fifo-depth = <0x800>;resets = <&rst SDMMC_RESET>;reset-names = "reset";iommus = <&smmu 5>;status = "disabled";};nand: nand@10b80000 {#address-cells = <1>;#size-cells = <0>;compatible = "altr,socfpga-denali-nand";reg = <0x10b80000 0x1038>,<0xffb80000 0x1000>;reg-names = "nand_data", "denali_reg";interrupts = <0 97 4>;clocks = <&clkmgr AGILEX5_NAND_CLK>,<&clkmgr AGILEX5_NAND_X_CLK>;clock-names = "nand", "nand_x";resets = <&rst NAND_RESET>, <&rstNAND_OCP_RESET>;
status = "disabled";};ocram: sram@00000000 {compatible = "mmio-sram";reg = <0x00000000 0x200000>;};rst: rstmgr@10d11000 {#reset-cells = <1>;compatible = "altr,stratix10-rst-mgr";reg = <0x10d11000 0x1000>;};smmu: iommu@16000000 {compatible = "arm,mmu-500", "arm,smmu-v2";reg = <0x16000000 0x40000>;#global-interrupts = <2>;#iommu-cells = <1>;interrupt-parent = <&intc>;interrupts = <0 128 4>, /* Global Secure Fault */<0 129 4>, /* Global Non-secure Fault *//* Non-secure Context Interrupts (32) */<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;stream-match-mask = <0x7ff0>;status = "disabled";};spi0: spi@10da4000 {compatible = "intel,agilex-spi","snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;#size-cells = <0>;reg = <0x10da4000 0x1000>;interrupts = <0 99 4>;resets = <&rst SPIM0_RESET>;reg-io-width = <4>;num-cs = <4>;clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;status = "disabled";};spi1: spi@10da5000 {compatible = "intel,agilex-spi","snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;#size-cells = <0>;reg = <0x10da5000 0x1000>;interrupts = <0 100 4>;resets = <&rst SPIM1_RESET>;reg-io-width = <4>;num-cs = <4>;clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;status = "disabled";};sysmgr: sysmgr@10d12000 {compatible = "altr,sys-mgr-s10","altr,sys-mgr";reg = <0x10d12000 0x500>;};/* Local timer */timer {compatible = "arm,armv8-timer";interrupts = <1 13 0xf08>,<1 14 0xf08>,<1 11 0xf08>,<1 10 0xf08>;};timer0: timer0@10c03000 {compatible = "snps,dw-apb-timer";interrupts = <0 113 4>;reg = <0x10c03000 0x100>;resets = <&rst SPTIMER0_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;clock-names = "timer";status = "disabled";};timer1: timer1@10c03100 {compatible = "snps,dw-apb-timer";interrupts = <0 114 4>;reg = <0x10c03100 0x100>;resets = <&rst SPTIMER1_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;clock-names = "timer";status = "disabled";};timer2: timer2@10d00000 {compatible = "snps,dw-apb-timer";interrupts = <0 115 4>;reg = <0x10d00000 0x100>;resets = <&rst L4SYSTIMER0_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;clock-names = "timer";status = "disabled";};timer3: timer3@10d00100 {compatible = "snps,dw-apb-timer";interrupts = <0 116 4>;reg = <0x10d00100 0x100>;resets = <&rst L4SYSTIMER1_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;clock-names = "timer";status = "disabled";};uart0: serial0@10c02000 {compatible = "snps,dw-apb-uart";reg = <0x10c02000 0x100>;interrupts = <0 108 4>;reg-shift = <2>;reg-io-width = <4>;resets = <&rst UART0_RESET>;status = "disabled";clocks = <&clkmgr AGILEX5_L4_SP_CLK>;clock-frequency = <100000000>;};uart1: serial1@10c02100 {compatible = "snps,dw-apb-uart";reg = <0x10c02100 0x100>;interrupts = <0 109 4>;reg-shift = <2>;reg-io-width = <4>;resets = <&rst UART1_RESET>;clocks = <&clkmgr AGILEX5_L4_SP_CLK>;status = "disabled";};usbphy0: usbphy@0 {#phy-cells = <0>;compatible = "usb-nop-xceiv";clocks = <&clkmgr AGILEX5_USB_CLK>;status = "disabled";};usb0: usb@10b00000 {compatible = "snps,dwc2";reg = <0x10b00000 0x40000>;interrupts = <0 93 4>;phys = <&usbphy0>;phy-names = "usb2-phy";resets = <&rst USB0_RESET>, <&rstUSB0_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";clocks = <&clkmgr AGILEX5_USB_CLK>;iommus = <&smmu 6>;status = "disabled";};usb31: usb31@11000000 {compatible = "snps,dwc3";reg = <0x11000000 0x100000>;resets = <&rst USB1_RESET>;phys = <&usbphy0>, <&usbphy0>;phy-names = "usb2-phy", "usb3-phy";dr_mode = "host";maximum-speed = "super-speed";snps,dis_u2_susphy_quirk;status = "disabled";};watchdog0: watchdog@10d00200 {compatible = "snps,dw-wdt";reg = <0x10d00200 0x100>;interrupts = <0 117 4>;resets = <&rst WATCHDOG0_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;status = "disabled";};watchdog1: watchdog@10d00300 {compatible = "snps,dw-wdt";reg = <0x10d00300 0x100>;interrupts = <0 118 4>;resets = <&rst WATCHDOG1_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;status = "disabled";};watchdog2: watchdog@10d00400 {compatible = "snps,dw-wdt";reg = <0x10d00400 0x100>;interrupts = <0 125 4>;resets = <&rst WATCHDOG2_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;status = "disabled";};watchdog3: watchdog@10d00500 {compatible = "snps,dw-wdt";reg = <0x10d00500 0x100>;interrupts = <0 126 4>;resets = <&rst WATCHDOG3_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;status = "disabled";};watchdog4: watchdog@10d00600 {compatible = "snps,dw-wdt";reg = <0x10d00600 0x100>;interrupts = <0 175 4>;resets = <&rst WATCHDOG4_RESET>;clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;status = "disabled";};sdr: sdr@10d21000 {compatible = "altr,sdr-ctl", "syscon";reg = <0x10d21000 0xc0>;};/* TODO: Update the ECC registers */eccmgr {compatible = "altr,socfpga-s10-ecc-manager","altr,socfpga-a10-ecc-manager";altr,sysmgr-syscon = <&sysmgr>;#address-cells = <1>;#size-cells = <1>;interrupts = <0 15 4>;interrupt-controller;#interrupt-cells = <2>;ranges;sdramedac {compatible = "altr,sdram-edac-s10";altr,sdr-syscon = <&sdr>;interrupts = <16 4>;};ocram-ecc@ff8cc000 {compatible = "altr,socfpga-s10-ocram-ecc","altr,socfpga-a10-ocram-ecc";reg = <0xff8cc000 0x100>;altr,ecc-parent = <&ocram>;interrupts = <1 4>;};usb0-ecc@ff8c4000 {compatible = "altr,socfpga-s10-usb-ecc","altr,socfpga-usb-ecc";reg = <0xff8c4000 0x100>;altr,ecc-parent = <&usb0>;interrupts = <2 4>;};emac0-rx-ecc@ff8c0000 {compatible = "altr,socfpga-s10-eth-mac-ecc","altr,socfpga-eth-mac-ecc";reg = <0xff8c0000 0x100>;altr,ecc-parent = <&gmac0>;interrupts = <4 4>;};emac0-tx-ecc@ff8c0400 {compatible = "altr,socfpga-s10-eth-mac-ecc","altr,socfpga-eth-mac-ecc";reg = <0xff8c0400 0x100>;altr,ecc-parent = <&gmac0>;interrupts = <5 4>;};sdmmca-ecc@ff8c8c00 {compatible = "altr,socfpga-s10-sdmmc-ecc","altr,socfpga-sdmmc-ecc";reg = <0xff8c8c00 0x100>;altr,ecc-parent = <&mmc>;interrupts = <14 4>,<15 4>;};};/* QSPI address not available yet */qspi: spi@108d2000 {compatible = "cdns,qspi-nor";#address-cells = <1>;#size-cells = <0>;reg = <0x108d2000 0x100>,<0x10900000 0x100000>;interrupts = <0 3 4>;cdns,fifo-depth = <128>;cdns,fifo-width = <4>;cdns,trigger-address = <0x00000000>;clocks = <&qspi_clk>;status = "disabled";};firmware {svc {compatible = "intel,stratix10-svc";method = "smc";memory-region = <&service_reserved>;fpga_mgr: fpga-mgr {compatible = "intel,stratix10-soc-fpga-mgr";
};};};- };
+}; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi new file mode 100644 index 0000000000..ad170353f8 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- U-Boot additions
- Copyright (C) 2022 Intel Corporation <www.intel.com> */
+#include "socfpga_agilex5-u-boot.dtsi"
+/{
- aliases {
spi0 = &qspi;freeze_br0 = &freeze_controller;- };
- soc {
freeze_controller: freeze_controller@f9000450 {compatible = "altr,freeze-bridge-controller";reg = <0xf9000450 0x00000010>;status = "disabled";};- };
- memory {
/* 2GB on Simics*/reg = <0 0x80000000 0 0x80000000>;- };
- chosen {
stdout-path = "serial0:115200n8";u-boot,spl-boot-order = &mmc,&flash0,"/memory";- };
+};
+&flash0 {
- compatible = "jedec,spi-nor";
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- bootph-all;
+};
+&nand {
- status = "okay";
- nand-bus-width = <16>;
- bootph-all;
+};
+&mmc {
- status = "okay";
- bus-width = <4>;
- sd-uhs-sdr50;
- cap-mmc-highspeed;
- bootph-all;
+};
+&combophy0 {
- status = "okay";
- bootph-all;
- cdns,phy-use-ext-lpbk-dqs = <1>;
- cdns,phy-use-lpbk-dqs = <1>;
- cdns,phy-use-phony-dqs = <1>;
- cdns,phy-use-phony-dqs-cmd = <1>;
- cdns,phy-io-mask-always-on = <0>;
- cdns,phy-io-mask-end = <5>;
- cdns,phy-io-mask-start = <0>;
- cdns,phy-data-select-oe-end = <1>;
- cdns,phy-sync-method = <1>;
- cdns,phy-sw-half-cycle-shift = <0>;
- cdns,phy-rd-del-sel = <52>;
- cdns,phy-underrun-suppress = <1>;
- cdns,phy-gate-cfg-always-on = <1>;
- cdns,phy-param-dll-bypass-mode = <1>;
- cdns,phy-param-phase-detect-sel = <2>;
- cdns,phy-param-dll-start-point = <254>;
- cdns,phy-read-dqs-cmd-delay = <0>;
- cdns,phy-clk-wrdqs-delay = <0>;
- cdns,phy-clk-wr-delay = <0>;
- cdns,phy-read-dqs-delay = <0>;
- cdns,phy-phony-dqs-timing = <0>;
- cdns,hrs09-rddata-en = <1>;
- cdns,hrs09-rdcmd-en = <1>;
- cdns,hrs09-extended-wr-mode = <1>;
- cdns,hrs09-extended-rd-mode = <1>;
- cdns,hrs10-hcsdclkadj = <3>;
- cdns,hrs16-wrdata1-sdclk-dly = <0>;
- cdns,hrs16-wrdata0-sdclk-dly = <0>;
- cdns,hrs16-wrcmd1-sdclk-dly = <0>;
- cdns,hrs16-wrcmd0-sdclk-dly = <0>;
- cdns,hrs16-wrdata1-dly = <0>;
- cdns,hrs16-wrdata0-dly = <0>;
- cdns,hrs16-wrcmd1-dly = <0>;
- cdns,hrs16-wrcmd0-dly = <0>;
- cdns,hrs07-rw-compensate = <10>;
- cdns,hrs07-idelay-val = <0>;
+};
+&qspi {
- status = "okay";
+};
+&timer0 {
- bootph-all;
+};
+&timer1 {
- bootph-all;
+};
+&timer2 {
- bootph-all;
+};
+&timer3 {
- bootph-all;
+};
+&watchdog0 {
- bootph-all;
+};
+#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&fdt_0_blob {
- filename = "arch/arm/dts/socfpga_agilex5_socdk.dtb";
+};
+/* To add NAND dtb when ready in future */
+&binman {
- /delete-node/ kernel;
+}; +#endif diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts new file mode 100644 index 0000000000..1a39426561 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019-2022, Intel Corporation */ #include
+"socfpga_agilex5.dtsi"
+/ {
- model = "SoCFPGA Agilex5 SoCDK";
- aliases {
serial0 = &uart0;- };
- leds {
compatible = "gpio-leds";hps0 {label = "hps_led0";gpios = <&portb 20 GPIO_ACTIVE_HIGH>;};hps1 {label = "hps_led1";gpios = <&portb 19 GPIO_ACTIVE_HIGH>;};hps2 {label = "hps_led2";gpios = <&portb 21 GPIO_ACTIVE_HIGH>;};- };
- memory {
device_type = "memory";/* We expect the bootloader to fill in the reg */reg = <0 0 0 0>;- };
- soc {
clocks {osc1 {clock-frequency = <25000000>;};};- };
+};
+&gpio0 {
- status = "okay";
+};
+&gpio1 {
- status = "okay";
+};
+&i2c0 {
- status = "okay";
+};
+&i2c1 {
- status = "okay";
+};
+&mmc {
- status = "okay";
+};
+&combophy0 {
- status = "okay";
+};
+&uart0 {
- status = "okay";
+};
+&usbphy0 {
- status = "okay";
+};
+&usb0 {
- status = "okay";
- disable-over-current;
+};
+&usb31 {
- status = "okay";
+};
+&watchdog0 {
- status = "okay";
+};
+&watchdog1 {
- status = "okay";
+};
+&watchdog2 {
- status = "okay";
+};
+&watchdog3 {
- status = "okay";
+};
+&watchdog4 {
- status = "okay";
+};
+&timer0 {
- status = "okay";
+};
+&timer1 {
- status = "okay";
+};
+&timer2 {
- status = "okay";
+};
+&timer3 {
- status = "okay";
+};
+&spi0 {
- status = "okay";
+};
+&spi1 {
- status = "okay";
+};
+&qspi {
- flash0: flash@0 {
#address-cells = <1>;#size-cells = <1>;compatible = "mt25qu02g";reg = <0>;spi-max-frequency = <100000000>;m25p,fast-read;cdns,page-size = <256>;cdns,block-size = <16>;cdns,read-delay = <1>;cdns,tshsl-ns = <50>;cdns,tsd2d-ns = <50>;cdns,tchsh-ns = <4>;cdns,tslch-ns = <4>;partitions {compatible = "fixed-partitions";#address-cells = <1>;#size-cells = <1>;qspi_boot: partition@0 {label = "Boot and fpga data";reg = <0x0 0x034B0000>;};qspi_rootfs: partition@34B0000 {label = "Root Filesystem - JFFS2";reg = <0x034B0000 0x0EB50000>;};};- };
+}; diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 84b91e8df0..1ca721f070 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -2,7 +2,7 @@ /*
- U-Boot additions
- Copyright (C) 2020 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
#if defined(CONFIG_FIT) @@ -21,14 +21,18 @@ description = "FIT with firmware and bootloader"; #address-cells = <1>;
images {
images: images { uboot { description = "U-Boot SoC64"; type = "standalone"; os = "U-Boot"; arch = "arm64"; compression = "none";#ifIS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
load = <0x80200000>;#else load = <0x00200000>;#endif uboot_blob: blob-ext { filename = "u-boot-nodtb.bin"; }; @@ -43,8 +47,13 @@ os = "arm-trusted-firmware"; arch = "arm64"; compression = "none";
#ifIS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
load = <0x80000000>;entry = <0x80000000>;#else load = <0x00001000>; entry = <0x00001000>;#endif atf_blob: blob-ext { filename = "bl31.bin"; };@@ -53,11 +62,11 @@ }; };
fdt {description = "U-Boot SoC64 flatdevice-tree";
fdt-0 {description = "socfpga_socdk"; type = "flat_dt"; compression = "none";
uboot_fdt_blob: blob-ext {
fdt_0_blob: blob-ext { filename = "u-boot.dtb"; }; hash {@@ -66,17 +75,18 @@ }; };
configurations {default = "conf";conf {description = "Intel SoC64 FPGA";
board_config: configurations {default = "board-0";board-0 {description = "board_0"; firmware = "atf"; loadables = "uboot";
fdt = "fdt";
fdt = "fdt-0"; signature { algo = "crc32"; key-name-hint = "dev";
sign-images = "atf", "fdt","uboot";
sign-images = "atf", "uboot","fdt-0"; }; }; }; @@ -96,8 +106,8 @@ arch = "arm64"; os = "linux"; compression = "none";
load = <0x4080000>;entry = <0x4080000>;
load = <0x6000000>;entry = <0x6000000>; kernel_blob: blob-ext { filename = "Image"; };@@ -146,7 +156,7 @@ filename = "signed-bl31.bin"; };
-&uboot_fdt_blob { +&fdt_0_blob { filename = "signed-u-boot.dtb"; };
diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi new file mode 100644 index 0000000000..add9890de3 --- /dev/null +++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- U-Boot additions
- Copyright (C) 2021-2022 Intel Corporation <www.intel.com> */
+/ {
- soc {
socfpga_secreg: socfpga-secreg {compatible = "intel,socfpga-secreg";#address-cells = <1>;#size-cells = <1>;bootph-all;i_sys_mgr_core@ffd12000 {reg = <0xffd12000 0x00000230>;intel,offset-settings =/* Enable non-secure interface toDMA */
<0x00000020 0xff010000 0xff010011>,/* Enable non-secure interface toDMA periph */
<0x00000024 0xffffffff 0xffffffff>;bootph-all;};noc_fw_l4_per_l4_per_scr@ffd21000 {reg = <0xffd21000 0x00000074>;intel,offset-settings =/* Disable L4 periphs firewall */<0x00000000 0x010100010x01010001>,
<0x00000004 0x010100010x01010001>,
<0x0000000c 0x010100010x01010001>,
<0x00000010 0x010100010x01010001>,
<0x0000001c 0x010100010x01010101>,
<0x00000020 0x010100010x01010101>,
<0x00000024 0x010100010x01010101>,
<0x00000028 0x010100010x01010101>,
<0x0000002c 0x010100010x01010001>,
<0x00000030 0x010100010x01010001>,
<0x00000034 0x010100010x01010001>,
<0x00000040 0x010100010x01010001>,
<0x00000044 0x010100010x01010101>,
<0x00000048 0x010100010x01010101>,
<0x00000050 0x010100010x01010101>,
<0x00000054 0x010100010x01010101>,
<0x00000058 0x010100010x01010101>,
<0x0000005c 0x010100010x01010101>,
<0x00000060 0x010100010x01010101>,
<0x00000064 0x010100010x01010101>,
<0x00000068 0x010100010x01010101>,
<0x0000006c 0x010100010x01010101>,
<0x00000070 0x010100010x01010101>;
bootph-all;};noc_fw_l4_sys_l4_sys_scr@ffd21100 {reg = <0xffd21100 0x00000098>;intel,offset-settings =/* Disable L4 system firewall */<0x00000008 0x010100010x01010001>,
<0x0000000c 0x010100010x01010001>,
<0x00000010 0x010100010x01010001>,
<0x00000014 0x010100010x01010001>,
<0x00000018 0x010100010x01010001>,
<0x0000001c 0x010100010x01010001>,
<0x00000020 0x010100010x01010001>,
<0x0000002c 0x010100010x01010001>,
<0x00000030 0x010100010x01010001>,
<0x00000034 0x010100010x01010001>,
<0x00000038 0x010100010x01010001>,
<0x00000040 0x010100010x01010001>,
<0x00000044 0x010100010x01010001>,
<0x00000048 0x010100010x01010001>,
<0x0000004c 0x010100010x01010001>,
<0x00000054 0x010100010x01010001>,
<0x00000058 0x010100010x01010001>,
<0x0000005c 0x010100010x01010001>,
<0x00000060 0x010100010x01010101>,
<0x00000064 0x010100010x01010101>,
<0x00000068 0x010100010x01010101>,
<0x0000006c 0x010100010x01010101>,
<0x00000070 0x010100010x01010101>,
<0x00000074 0x010100010x01010101>,
<0x00000078 0x010100010x03010001>,
<0x00000090 0x010100010x01010001>,
<0x00000094 0x010100010x01010001>;
bootph-all;};noc_fw_soc2fpga_soc2fpga_scr@ffd21200 {reg = <0xffd21200 0x00000004>;/* Disable soc2fpga security access */intel,offset-settings = <0x000000000x0ffe0101 0x0ffe0101>;
bootph-all;};noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 {reg = <0xffd21300 0x00000004>;/* Disable lightweight soc2fpga securityaccess */
intel,offset-settings = <0x000000000x0ffe0101 0x0ffe0101>;
bootph-all;};noc_fw_tcu_tcu_scr@ffd21400 {reg = <0xffd21400 0x00000004>;/* Disable DMA ECC security access, forSMMU use */
intel,offset-settings = <0x000000000x01010001 0x01010001>;
bootph-all;};noc_fw_priv_MemoryMap_priv@ffd24800 {reg = <0xffd24800 0x0000000c>;intel,offset-settings =/* Enable non-prviledged access tovarious periphs */
<0x00000000 0xfff73ffb 0xfff73ffb>;bootph-all;};};- };
+}; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi old mode 100755 new mode 100644 diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi old mode 100755 new mode 100644 diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts old mode 100755 new mode 100644 -- 2.26.2
The fix is to solve checkpatch issue. Will submit S10 separately.
This is for new platform enablement for agilex5. Add platform related files to enable new product.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/mach-socfpga/Kconfig | 37 +++ arch/arm/mach-socfpga/Makefile | 69 ++++- arch/arm/mach-socfpga/board.c | 65 ++++- arch/arm/mach-socfpga/clock_manager_agilex5.c | 82 ++++++ arch/arm/mach-socfpga/firewall.c | 107 ------- arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 61 ++++ arch/arm/mach-socfpga/lowlevel_init_soc64.S | 167 ++++++++++- arch/arm/mach-socfpga/mailbox_s10.c | 21 ++ arch/arm/mach-socfpga/misc.c | 19 +- arch/arm/mach-socfpga/misc_soc64.c | 33 ++- arch/arm/mach-socfpga/mmu-arm64_s10.c | 43 ++- arch/arm/mach-socfpga/reset_manager_s10.c | 271 +++++++++++++++--- arch/arm/mach-socfpga/secure_reg_helper.c | 4 +- arch/arm/mach-socfpga/smmu_agilex5.c | 34 +++ arch/arm/mach-socfpga/smmu_s10.c | 126 ++++++++ arch/arm/mach-socfpga/spl_agilex5.c | 180 ++++++++++++ arch/arm/mach-socfpga/spl_soc64.c | 188 +++++++++++- arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 93 ++++++ arch/arm/mach-socfpga/wrap_handoff_soc64.c | 7 +- 19 files changed, 1429 insertions(+), 178 deletions(-) create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c delete mode 100644 arch/arm/mach-socfpga/firewall.c create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S create mode 100644 arch/arm/mach-socfpga/smmu_agilex5.c create mode 100644 arch/arm/mach-socfpga/smmu_s10.c create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 503c82d388..562c3796ec 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -44,6 +44,15 @@ config TEXT_BASE default 0x01000040 if TARGET_SOCFPGA_ARRIA10 default 0x01000040 if TARGET_SOCFPGA_GEN5
+config ARMV8_PSCI_NR_CPUS + default 4 if TARGET_SOCFPGA_SOC64 + +config ARMV8_SECURE_BASE + default 0x00001000 if TARGET_SOCFPGA_SOC64 && ARMV8_PSCI + +config SYS_HAS_ARMV8_SECURE_BASE + default y if TARGET_SOCFPGA_SOC64 && ARMV8_PSCI + config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY @@ -51,10 +60,31 @@ config TARGET_SOCFPGA_AGILEX select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX + select GICV2 + select NCORE_CACHE + select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 + +config TARGET_SOCFPGA_AGILEX5 + bool + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select GICV3 select NCORE_CACHE select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64
+config TARGET_SOCFPGA_AGILEX5_EMU + bool "Enable build that bootable only on Agilex5 Emulator" + help + This is to use for Agilex5 Emulator. + +config TARGET_SOCFPGA_AGILEX5_SIMICS + bool "Enable build that bootable only on Agilex5 Simics platform" + help + This is to use for Agilex5 Simics. + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -126,6 +156,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" select TARGET_SOCFPGA_AGILEX
+config TARGET_SOCFPGA_AGILEX5_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex5)" + select TARGET_SOCFPGA_AGILEX5 + config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -199,6 +233,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice
config SYS_BOARD + default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK @@ -220,6 +255,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -242,6 +278,7 @@ config SYS_SOC default "socfpga"
config SYS_CONFIG_NAME + default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index ec38b64dd4..771e7ce77d 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -35,10 +35,22 @@ obj-y += mailbox_s10.o obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o +obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-y += rsu.o +obj-y += rsu_ll_qspi.o +obj-y += rsu_misc.o +obj-y += rsu_s10.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o +endif endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX @@ -49,11 +61,46 @@ obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-y += rsu.o +obj-y += rsu_ll_qspi.o +obj-y += rsu_misc.o +obj-y += rsu_s10.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o +endif +endif + +ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +obj-y += clock_manager_agilex5.o +obj-y += lowlevel_init_agilex5.o +obj-y += mailbox_s10.o +obj-y += misc_soc64.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += smmu_agilex5.o +obj-y += system_manager_soc64.o +obj-y += timer_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o +obj-y += wrap_handoff_soc64.o +obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o +endif endif
ifdef CONFIG_TARGET_SOCFPGA_N5X @@ -64,11 +111,22 @@ obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-y += rsu.o +obj-y += rsu_ll_qspi.o +obj-y += rsu_misc.o +obj-y += rsu_s10.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o +endif endif
ifdef CONFIG_SPL_BUILD @@ -79,21 +137,24 @@ obj-y += wrap_iocsr_config.o obj-y += wrap_pinmux_config.o obj-y += wrap_sdram_config.o endif -ifdef CONFIG_TARGET_SOCFPGA_SOC64 -obj-y += firewall.o -obj-y += spl_soc64.o -endif ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 obj-y += spl_a10.o endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += spl_s10.o +obj-y += spl_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += spl_agilex.o +obj-y += spl_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += spl_n5x.o +obj-y += spl_soc64.o +endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +obj-y += spl_agilex5.o +obj-y += spl_soc64.o endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 09e09192fb..140a520ab7 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -7,9 +7,11 @@
#include <common.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/secure_vab.h> +#include <asm/arch/smc_api.h> #include <asm/global_data.h> #include <asm/io.h> #include <errno.h> @@ -23,6 +25,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define DEFAULT_JTAG_USERCODE 0xFFFFFFFF + void s_init(void) { #ifndef CONFIG_ARM64 /* @@ -46,7 +50,7 @@ void s_init(void) { int board_init(void) { /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0; } @@ -92,13 +96,55 @@ int g_dnl_board_usb_cable_connected(void) } #endif
-#ifdef CONFIG_SPL_BUILD -__weak int board_fit_config_name_match(const char *name) +u8 socfpga_get_board_id(void) { - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); + u8 board_id = 0; + u32 jtag_usercode; + int err;
- return 0; +#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF) + err = smc_get_usercode(&jtag_usercode); +#else + u32 resp_len = 1; + + err = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_GET_USERCODE, MBOX_CMD_DIRECT, 0, + NULL, 0, &resp_len, &jtag_usercode); +#endif + + if (err) { + puts("Fail to read JTAG Usercode. Default Board ID to 0\n"); + return board_id; + } + + debug("Valid JTAG Usercode: %u\n", jtag_usercode); + + if (jtag_usercode == DEFAULT_JTAG_USERCODE) { + debug("JTAG Usercode is not set. Default Board ID to 0\n"); + } else if (jtag_usercode >= 0 && jtag_usercode <= 255) { + board_id = jtag_usercode; + debug("Valid JTAG Usercode. Set Board ID to %u\n", board_id); + } else { + puts("Board ID is not in range 0 to 255\n"); + } + + return board_id; +} + +#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +int board_fit_config_name_match(const char *name) +{ + char board_name[10]; + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || \ +IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU) + sprintf(board_name, "board_%u", 0); /* Hardcoded board ID since Simics no support */ +#else + sprintf(board_name, "board_%u", socfpga_get_board_id()); +#endif + + debug("Board name: %s\n", board_name); + + return strcmp(name, board_name); } #endif
@@ -116,6 +162,8 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, #if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT) void board_prep_linux(struct bootm_headers *images) { + bool use_fit = false; + if (!images->fit_uname_cfg) { if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) && !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) { @@ -127,14 +175,17 @@ void board_prep_linux(struct bootm_headers *images) hang(); } } else { + use_fit = true; /* Update fdt_addr in enviroment variable */ env_set_hex("fdt_addr", (ulong)images->ft_addr); debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr); }
- if (IS_ENABLED(CONFIG_CADENCE_QSPI)) { + if (use_fit && IS_ENABLED(CONFIG_CADENCE_QSPI)) { if (env_get("linux_qspi_enable")) run_command(env_get("linux_qspi_enable"), 0); + if (env_get("rsu_status")) + run_command(env_get("rsu_status"), 0); } } #endif diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c new file mode 100644 index 0000000000..46b6bc5d40 --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + * + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <log.h> +#include <malloc.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <dt-bindings/clock/agilex5-clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +static ulong cm_get_rate_dm(u32 id) +{ + struct udevice *dev; + struct clk clk; + ulong rate; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(socfpga_agilex5_clk), + &dev); + if (ret) + return 0; + + clk.id = id; + ret = clk_request(dev, &clk); + if (ret < 0) + return 0; + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + if ((rate == (unsigned long)-ENOSYS) || + (rate == (unsigned long)-ENXIO) || + (rate == (unsigned long)-EIO)) { + debug("%s id %u: clk_get_rate err: %ld\n", + __func__, id, rate); + return 0; + } + + return rate; +} + +static u32 cm_get_rate_dm_khz(u32 id) +{ + return cm_get_rate_dm(id) / 1000; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + return cm_get_rate_dm(AGILEX5_MPU_CLK); +} + +unsigned int cm_get_l4_sys_free_clk_hz(void) +{ + return cm_get_rate_dm(AGILEX5_L4_SYS_FREE_CLK); +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %10d kHz\n", + cm_get_rate_dm_khz(AGILEX5_MPU_CLK)); + printf("L4 Main %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_MAIN_CLK)); + printf("L4 sys free %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_SYS_FREE_CLK)); + printf("L4 MP %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_MP_CLK)); + printf("L4 SP %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_SP_CLK)); + printf("SDMMC %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_SDMMC_CLK)); +} diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c deleted file mode 100644 index 69229dc651..0000000000 --- a/arch/arm/mach-socfpga/firewall.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> - * - */ - -#include <asm/io.h> -#include <common.h> -#include <asm/arch/firewall.h> -#include <asm/arch/system_manager.h> - -static void firewall_l4_per_disable(void) -{ - const struct socfpga_firwall_l4_per *firwall_l4_per_base = - (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; - u32 i; - const u32 *addr[] = { - &firwall_l4_per_base->nand, - &firwall_l4_per_base->nand_data, - &firwall_l4_per_base->usb0, - &firwall_l4_per_base->usb1, - &firwall_l4_per_base->spim0, - &firwall_l4_per_base->spim1, - &firwall_l4_per_base->emac0, - &firwall_l4_per_base->emac1, - &firwall_l4_per_base->emac2, - &firwall_l4_per_base->sdmmc, - &firwall_l4_per_base->gpio0, - &firwall_l4_per_base->gpio1, - &firwall_l4_per_base->i2c0, - &firwall_l4_per_base->i2c1, - &firwall_l4_per_base->i2c2, - &firwall_l4_per_base->i2c3, - &firwall_l4_per_base->i2c4, - &firwall_l4_per_base->timer0, - &firwall_l4_per_base->timer1, - &firwall_l4_per_base->uart0, - &firwall_l4_per_base->uart1 - }; - - /* - * The following lines of code will enable non-secure access - * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This - * is needed as most OS run in non-secure mode. Thus we need to - * enable non-secure access to these peripherals in order for the - * OS to use these peripherals. - */ - for (i = 0; i < ARRAY_SIZE(addr); i++) - writel(FIREWALL_L4_DISABLE_ALL, addr[i]); -} - -static void firewall_l4_sys_disable(void) -{ - const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = - (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; - u32 i; - const u32 *addr[] = { - &firwall_l4_sys_base->dma_ecc, - &firwall_l4_sys_base->emac0rx_ecc, - &firwall_l4_sys_base->emac0tx_ecc, - &firwall_l4_sys_base->emac1rx_ecc, - &firwall_l4_sys_base->emac1tx_ecc, - &firwall_l4_sys_base->emac2rx_ecc, - &firwall_l4_sys_base->emac2tx_ecc, - &firwall_l4_sys_base->nand_ecc, - &firwall_l4_sys_base->nand_read_ecc, - &firwall_l4_sys_base->nand_write_ecc, - &firwall_l4_sys_base->ocram_ecc, - &firwall_l4_sys_base->sdmmc_ecc, - &firwall_l4_sys_base->usb0_ecc, - &firwall_l4_sys_base->usb1_ecc, - &firwall_l4_sys_base->clock_manager, - &firwall_l4_sys_base->io_manager, - &firwall_l4_sys_base->reset_manager, - &firwall_l4_sys_base->system_manager, - &firwall_l4_sys_base->watchdog0, - &firwall_l4_sys_base->watchdog1, - &firwall_l4_sys_base->watchdog2, - &firwall_l4_sys_base->watchdog3 - }; - - for (i = 0; i < ARRAY_SIZE(addr); i++) - writel(FIREWALL_L4_DISABLE_ALL, addr[i]); -} - -static void firewall_bridge_disable(void) -{ - /* disable lwsocf2fpga and soc2fpga bridge security */ - writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); - writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); -} - -void firewall_setup(void) -{ - firewall_l4_per_disable(); - firewall_l4_sys_disable(); - firewall_bridge_disable(); - - /* disable SMMU security */ - writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); - - /* enable non-secure interface to DMA330 DMA and peripherals */ - writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, - socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA); - writel(SYSMGR_DMAPERIPH_ALL_NS, - socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH); -} diff --git a/arch/arm/mach-socfpga/lowlevel_init_agilex5.S b/arch/arm/mach-socfpga/lowlevel_init_agilex5.S new file mode 100644 index 0000000000..15e5066767 --- /dev/null +++ b/arch/arm/mach-socfpga/lowlevel_init_agilex5.S @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2022-2023 Intel Corporation <www.intel.com> + * + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> +#include <asm/arch/reset_manager_soc64.h> + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) +.align 3 +_el3_exception_vectors: + .quad el3_exception_vectors; +#endif + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#ifdef CONFIG_SPL_BUILD + branch_if_slave x0, 3f + + /* Check rstmgr.stat for warm reset status */ + ldr w1, =SOCFPGA_RSTMGR_ADDRESS + ldr w0, [x1] + /* Check whether any L4 watchdogs or SDM had triggered warm reset */ + ldr x2, =RSTMGR_L4WD_MPU_WARMRESET_MASK + ands x0, x0, x2 + /* + * If current Reset Manager's status is warm reset just reload the + * .data section by copying the data from data preserve section. + * Otherwise, copy the .data section to the data preserve section to + * keep an original copy of .data section. This ensure SPL is + * reentrant after warm reset. + */ + b.ne reload_data_section + /* Copy from .data to preserved .data to backup the SPL state */ + ldr x0, =__data_start + ldr x1, =__preserve_data_start + ldr x2, =__preserve_data_end + b copy_loop +reload_data_section: + /* Copy from preserved .data to .data to restore the SPL state */ + ldr x0, =__preserve_data_start + ldr x1, =__data_start + ldr x2, =__data_end +copy_loop: + ldr w3, [x0] + add x0, x0, #4 + str w3, [x1] + add x1, x1, #4 + cmp x1, x2 + b.ne copy_loop +3: +#endif + + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S index 875927cc4d..5680553f68 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -1,7 +1,7 @@ -/* - * Copyright (C) 2020 Intel Corporation. All rights reserved +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2022-2023 Intel Corporation <www.intel.com> * - * SPDX-License-Identifier: GPL-2.0 */
#include <asm-offsets.h> @@ -9,11 +9,101 @@ #include <linux/linkage.h> #include <asm/macro.h>
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) +.align 3 +_el3_exception_vectors: + .quad el3_exception_vectors; +#endif + ENTRY(lowlevel_init) mov x29, lr /* Save LR */
+#ifdef CONFIG_SPL_BUILD + /* Check for L2 reset magic word */ + ldr x4, =L2_RESET_DONE_REG + ldr x5, [x4] + ldr x1, =L2_RESET_DONE_STATUS + cmp x1, x5 + /* No L2 reset, skip warm reset */ + b.ne skipwarmreset + /* Put all slaves CPUs into WFI mode */ + branch_if_slave x0, put_cpu_in_wfi + /* L2 reset completed */ + str xzr, [x4] + /* Clear previous CPU release address */ + ldr x4, =CPU_RELEASE_ADDR + str wzr, [x4] + /* Master CPU (CPU0) request for warm reset */ + mrs x1, rmr_el3 + orr x1, x1, #0x02 + msr rmr_el3, x1 + isb + dsb sy +put_cpu_in_wfi: + wfi + b put_cpu_in_wfi +skipwarmreset: +#endif + #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + + /* + * In ATF flow, need to clear the old CPU address when cold reset + * being triggered, but shouldn't clear CPU address if it is reset + * by CPU-ON, so that the core can correctly jump to ATF code after + * reset by CPU-ON. CPU-ON trigger the reset via mpumodrst. + * + * Hardware will set 1 to core*_irq in mpurststat register in + * reset manager if the core is reset by mpumodrst. + * + * The following code will check the mpurststat to identify if the + * core is reset by mpumodrst, and it will skip CPU address clearing + * if the core is reset by mpumodrst. At last, the code need to clear + * the core*_irq by set it to 1. So that it can reflect the correct + * and latest status in next reset. + */ + + /* Check if it is a master core off/on from kernel using boot scratch + * cold register 8 bit 19. This bit is set by ATF. + */ + ldr x4, =BOOT_SCRATCH_COLD8 + ldr x5, [x4] + and x6, x5, #0x80000 + cbnz x6, wait_for_atf_master + + /* Retrieve mpurststat register in reset manager */ + ldr x4, =SOCFPGA_RSTMGR_ADDRESS + ldr w5, [x4, #0x04] + + /* Set mask based on current core id */ + mrs x0, mpidr_el1 + and x1, x0, #0xF + ldr x2, =0x00000100 + lsl x2, x2, x1 + + /* Skip if core*_irq register is set */ + and x6, x5, x2 + cbnz x6, skip_clear_cpu_address + + /* + * Reach here means core*_irq is 0, means the core is + * reset by cold, warm or watchdog reset. + * Clear previous CPU release address + */ + ldr x4, =CPU_RELEASE_ADDR + str wzr, [x4] + b skip_clear_core_irq + +skip_clear_cpu_address: + /* Clear core*_irq register by writing 1 */ + ldr x4, =SOCFPGA_RSTMGR_ADDRESS + str w2, [x4, #0x04] + +skip_clear_core_irq: + /* Master CPU (CPU0) does not need to wait for atf */ + branch_if_master x0, master_cpu + wait_for_atf: ldr x4, =CPU_RELEASE_ADDR ldr x5, [x4] @@ -21,6 +111,16 @@ wait_for_atf: br x5 slave_wait_atf: branch_if_slave x0, wait_for_atf + +wait_for_atf_master: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, master_wait_atf + br x5 +master_wait_atf: + branch_if_master x0, wait_for_atf_master + +master_cpu: #else branch_if_slave x0, 1f #endif @@ -52,6 +152,18 @@ slave_wait_atf: bl gic_wait_for_interrupt #endif
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_ATF) + /* + * Read the u-boot's PSCI exception handler's vector base + * address from the sysmgr.boot_scratch_cold6 & 7 and update + * their VBAR_EL3 respectively. + */ +wait_vbar_el3: + ldr x4, =VBAR_EL3_BASE_ADDR + ldr x5, [x4] + cbz x5, wait_vbar_el3 + msr vbar_el3, x5 +#endif /* * All slaves will enter EL2 and optionally EL1. */ @@ -71,6 +183,55 @@ lowlevel_in_el1: #endif /* CONFIG_ARMV8_MULTIENTRY */
2: +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) + /* + * Write the u-boot PSCI exception handler's vector base address + * into a sysmgr.boot_scratch_cold6 & 7 so that other slave cpus + * are able to get the vector base address and update their VBAR_EL3 + * respectively. + */ + adr x0, _el3_exception_vectors + ldr x5, [x0] + ldr x4, =VBAR_EL3_BASE_ADDR + str x5, [x4] +#endif + +#ifdef CONFIG_SPL_BUILD + branch_if_slave x0, 3f + + /* Check rstmgr.stat for warm reset status */ + ldr x1, =SOCFPGA_RSTMGR_ADDRESS + ldr x0, [x1] + /* Check whether any L4 watchdogs or MPUs had triggered warm reset */ + ldr x2, =0x000F0F00 + ands x0, x0, x2 + /* + * If current Reset Manager's status is warm reset just reload the + * .data section by copying the data from data preserve section. + * Otherwise, copy the .data section to the data preserve section to + * keep an original copy of .data section. This ensure SPL is + * reentrant after warm reset. + */ + b.ne reload_data_section + /* Copy from .data to preserved .data to backup the SPL state */ + ldr x0, =__data_start + ldr x1, =__preserve_data_start + ldr x2, =__preserve_data_end + b copy_loop +reload_data_section: + /* Copy from preserved .data to .data to restore the SPL state */ + ldr x0, =__preserve_data_start + ldr x1, =__data_start + ldr x2, =__data_end +copy_loop: + ldr w3, [x0] + add x0, x0, #4 + str w3, [x1] + add x1, x1, #4 + cmp x1, x2 + b.ne copy_loop +3: +#endif mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 101af23855..7846596c17 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -7,7 +7,9 @@ #include <common.h> #include <asm/arch/clock_manager.h> #include <asm/arch/mailbox_s10.h> +#include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> +#include <asm/arch/timer.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/secure.h> @@ -454,6 +456,14 @@ static __always_inline int mbox_get_fpga_config_status_common(u32 cmd) return MBOX_CFGSTAT_STATE_CONFIG; }
+#ifdef CONFIG_ARMV8_PSCI +int __secure mbox_hps_stage_notify_psci(u32 execution_stage) +{ + return mbox_send_cmd_psci(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY, + MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL); +} +#endif + int mbox_get_fpga_config_status(u32 cmd) { return mbox_get_fpga_config_status_common(cmd); @@ -479,6 +489,17 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, urgent, resp_buf_len, resp_buf); }
+int mbox_hps_stage_notify(u32 execution_stage) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + return smc_send_mailbox(MBOX_HPS_STAGE_NOTIFY, 1, &execution_stage, + 0, 0, NULL); +#else + return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY, + MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL); +#endif +} + int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) { return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 5b5a81a255..024b714ecb 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2023 Altera Corporation <www.altera.com> */
#include <common.h> @@ -34,7 +34,7 @@ phys_addr_t socfpga_sysmgr_base __section(".data");
#ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = - (struct pl310_regs *)CFG_SYS_PL310_BASE; + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; #endif
struct bsel bsel_str[] = { @@ -164,7 +164,10 @@ int arch_cpu_init(void) * timeout value is still active which might too short for Linux * booting. */ +#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || \ +IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)) hw_watchdog_init(); +#endif #else /* * If the HW watchdog is NOT enabled, make sure it is not running, @@ -208,10 +211,11 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, }
U_BOOT_CMD(bridge, 3, 1, do_bridge, - "SoCFPGA HPS FPGA bridge control", - "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "" + "SoCFPGA HPS FPGA bridge control", + "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges \n" + "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges\n" + "Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10\n" + "" );
#endif @@ -257,6 +261,9 @@ void socfpga_get_managers_addr(void) #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) ret = socfpga_get_base_addr("intel,n5x-clkmgr", &socfpga_clkmgr_base); +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + ret = socfpga_get_base_addr("intel,agilex5-clkmgr", + &socfpga_clkmgr_base); #else ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); #endif diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 2acdfad07b..7dd6f834e1 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2023 Intel Corporation <www.intel.com> * */
@@ -18,8 +18,12 @@ #include <log.h> #include <mach/clock_manager.h>
+#define RSU_DEFAULT_LOG_LEVEL 7 + DECLARE_GLOBAL_DATA_PTR;
+u8 socfpga_get_board_id(void); + /* * FPGA programming support for SoC FPGA Stratix 10 */ @@ -47,8 +51,11 @@ static Altera_desc altera_fpga[] = { #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A55/A76)\n"); +#else puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); - +#endif return 0; } #endif @@ -56,11 +63,26 @@ int print_cpuinfo(void) #ifdef CONFIG_ARCH_MISC_INIT int arch_misc_init(void) { +#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || \ +IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)) char qspi_string[13]; + char level[4]; + char id[3]; + + snprintf(level, sizeof(level), "%u", RSU_DEFAULT_LOG_LEVEL);
sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); env_set("qspi_clock", qspi_string);
+ /* for RSU, set log level to default if log level is not set */ + if (!env_get("rsu_log_level")) + env_set("rsu_log_level", level); + + /* Export board_id as environment variable */ + sprintf(id, "%u", socfpga_get_board_id()); + env_set("board_id", id); +#endif + return 0; } #endif @@ -87,5 +109,10 @@ void do_bridge_reset(int enable, unsigned int mask) return; }
- socfpga_bridges_reset(enable); + socfpga_bridges_reset(enable, mask); +} + +void arch_preboot_os(void) +{ + mbox_hps_stage_notify(HPS_EXECUTION_STATE_OS); } diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index a55b7b7cf3..0951233cad 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2022 Intel Corporation <www.intel.com> * */
@@ -10,6 +10,46 @@
DECLARE_GLOBAL_DATA_PTR;
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +static struct mm_region socfpga_agilex5_mem_map[] = { + { + /* OCRAM 1MB but available 256KB */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x00040000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* DEVICE */ + .virt = 0x10808000UL, + .phys = 0x10808000UL, + .size = 0x0F7F8000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* FPGA 1.5GB */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x60000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* MEM 2GB */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* List terminator */ + }, +}; + +struct mm_region *mem_map = socfpga_agilex5_mem_map; + +#else static struct mm_region socfpga_stratix10_mem_map[] = { { /* MEM 2GB*/ @@ -70,3 +110,4 @@ static struct mm_region socfpga_stratix10_mem_map[] = { };
struct mm_region *mem_map = socfpga_stratix10_mem_map; +#endif diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index f47fec10a0..1bf6a74648 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -1,22 +1,58 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2023 Intel Corporation <www.intel.com> * */
#include <common.h> +#include <errno.h> #include <hang.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/secure.h> #include <asm/arch/reset_manager.h> #include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> +#include <asm/arch/timer.h> #include <dt-bindings/reset/altr,rst-mgr-s10.h> +#include <exports.h> #include <linux/iopoll.h> #include <linux/intel-smc.h>
DECLARE_GLOBAL_DATA_PTR;
+#define TIMEOUT_300MS 300 + +/* F2S manager registers */ +#define F2SDRAM_SIDEBAND_FLAGINSTATUS0 0x14 +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54 + +static __always_inline int wait_for_bit(u32 *reg, const u32 mask, bool set, + unsigned int timeout_ms) +{ + u32 val; + int timeout = timeout_ms; + + while (1) { + val = readl(reg); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (!timeout) + break; + + timeout--; + __socfpga_udelay(1000); + } + + return -ETIMEDOUT; +} + /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) { @@ -57,66 +93,221 @@ void socfpga_per_reset_all(void) writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); }
-void socfpga_bridges_reset(int enable) +static __always_inline void socfpga_f2s_bridges_reset(int enable, + unsigned int mask) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) - u64 arg = enable; + int ret; + u32 brg_mask; + u32 flagout_idlereq = 0; + u32 flagoutset_fdrain = 0; + u32 flagoutset_en = 0; + u32 flaginstatus_idleack = 0; + u32 flaginstatus_respempty = 0; + + if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) { + /* Support fpga2soc and f2sdram */ + brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK | + RSTMGR_BRGMODRST_F2SDRAM0_MASK | + RSTMGR_BRGMODRST_F2SDRAM1_MASK | + RSTMGR_BRGMODRST_F2SDRAM2_MASK); + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM0_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM1_MASK) { + flagout_idlereq |= BIT(3); + flaginstatus_idleack |= BIT(5); + flagoutset_fdrain |= BIT(5); + flagoutset_en |= BIT(4); + flaginstatus_respempty |= BIT(7); + }
- int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0); - if (ret) { - printf("SMC call failed with error %d in %s.\n", ret, __func__); + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM2_MASK) { + flagout_idlereq |= BIT(6); + flaginstatus_idleack |= BIT(9); + flagoutset_fdrain |= BIT(8); + flagoutset_en |= BIT(7); + flaginstatus_respempty |= BIT(11); + } + } else { + /* Support fpga2soc only */ + brg_mask = mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK; + if (brg_mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + } + + /* mask is not set, return here */ + if (!brg_mask) return; + + if (enable) { + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + brg_mask); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagout_idlereq); + + /* Wait for mpfe noc idleack to 0 */ + wait_for_bit((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_idleack, false, TIMEOUT_300MS); + + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagoutset_fdrain); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); + + __socfpga_udelay(1); /* wait 1us */ + } else { + if (readl((socfpga_get_rstmgr_addr() + + RSTMGR_SOC64_BRGMODRST) & brg_mask)) { + /* Bridge cannot be reset twice */ + return; + } + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKEN, + RSTMGR_HDSKEN_FPGAHSEN); + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, + RSTMGR_HDSKREQ_FPGAHSREQ); + + /* Wait for FPGA ack the handshake request to 1 */ + wait_for_bit((u32 *)(socfpga_get_rstmgr_addr() + + RSTMGR_SOC64_HDSKACK), RSTMGR_HDSKREQ_FPGAHSREQ, + true, TIMEOUT_300MS); + + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, flagoutset_en); + + __socfpga_udelay(1); + + /* Requests MPFE NoC to idle */ + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagout_idlereq); + + /* Force F2S bridge to drain */ + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_fdrain); + + /* Wait for respond queue empty status to 1 (resp idle) */ + ret = wait_for_bit((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_respempty, true, + TIMEOUT_300MS); + + /* Confirm again */ + if (!ret) + ret = wait_for_bit((u32 *) + (SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_respempty, true, + TIMEOUT_300MS); + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + brg_mask & ~RSTMGR_BRGMODRST_FPGA2SOC_MASK); + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, + RSTMGR_HDSKREQ_FPGAHSREQ); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagout_idlereq); + } +} + +static __always_inline void socfpga_s2f_bridges_reset(int enable, + unsigned int mask) +{ + unsigned int noc_mask = 0; + unsigned int brg_mask = 0; + + if (mask & RSTMGR_BRGMODRST_SOC2FPGA_MASK) { + noc_mask = SYSMGR_NOC_H2F_MSK; + brg_mask = RSTMGR_BRGMODRST_SOC2FPGA_MASK; } -#else - u32 reg; + + if (mask & RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) { + noc_mask |= SYSMGR_NOC_LWH2F_MSK; + brg_mask |= RSTMGR_BRGMODRST_LWSOC2FPGA_MASK; + } + + /* s2f mask is not set, return here */ + if (!brg_mask) + return;
if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0); + SYSMGR_SOC64_NOC_IDLEREQ_CLR, noc_mask);
- /* Release all bridges from reset state */ + /* Release SOC2FPGA bridges from reset state */ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - ~0); + brg_mask);
- /* Poll until all idleack to 0 */ - read_poll_timeout(readl, reg, !reg, 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK); + /* Wait for all NOC master ack to 0 */ + wait_for_bit((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK), noc_mask, false, + TIMEOUT_300MS); } else { /* set idle request to all bridges */ - writel(~0, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_SET); + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEREQ_SET, noc_mask);
/* Enable the NOC timeout */ writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
- /* Poll until all idleack to 1 */ - read_poll_timeout(readl, reg, - reg == (SYSMGR_NOC_H2F_MSK | - SYSMGR_NOC_LWH2F_MSK), - 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK); - - /* Poll until all idlestatus to 1 */ - read_poll_timeout(readl, reg, - reg == (SYSMGR_NOC_H2F_MSK | - SYSMGR_NOC_LWH2F_MSK), - 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLESTATUS); - - /* Reset all bridges (except NOR DDR scheduler & F2S) */ + /* Wait for all NOC master ack to 1 */ + wait_for_bit((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK), noc_mask, true, + TIMEOUT_300MS); + + /* Wait for all NOC master idlestatus to 1 */ + wait_for_bit((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLESTATUS), noc_mask, true, + TIMEOUT_300MS); + + /* Reset all SOC2FPGA bridges */ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - ~(RSTMGR_BRGMODRST_DDRSCH_MASK | - RSTMGR_BRGMODRST_FPGA2SOC_MASK)); + brg_mask);
/* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } -#endif +} + +void socfpga_bridges_reset(int enable, unsigned int mask) +{ + if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { + u64 arg[2]; + int ret; + + /* Set bit-1 to indicate has mask value in arg[1]. */ + arg[0] = (enable & BIT(0)) | BIT(1); + arg[1] = mask; + + ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, arg, + ARRAY_SIZE(arg), NULL, 0); + if (ret) + printf("Failed to %s the HPS bridges, error %d\n", + enable ? "enable" : "disable", ret); + } else { + socfpga_s2f_bridges_reset(enable, mask); + socfpga_f2s_bridges_reset(enable, mask); + } +} + +void __secure socfpga_bridges_reset_psci(int enable, unsigned int mask) +{ + socfpga_s2f_bridges_reset(enable, mask); + socfpga_f2s_bridges_reset(enable, mask); }
/* @@ -125,7 +316,7 @@ void socfpga_bridges_reset(int enable) int cpu_has_been_warmreset(void) { return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) & - RSTMGR_L4WD_MPU_WARMRESET_MASK; + (RSTMGR_L4WD_MPU_WARMRESET_MASK); }
void print_reset_info(void) diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-socfpga/secure_reg_helper.c index 0d4f45f33d..23595d242a 100644 --- a/arch/arm/mach-socfpga/secure_reg_helper.c +++ b/arch/arm/mach-socfpga/secure_reg_helper.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2022 Intel Corporation <www.intel.com> * */
@@ -18,9 +18,11 @@ int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t *reg_addr) { switch (id) { +#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC: *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC; break; +#endif case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0: *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0; break; diff --git a/arch/arm/mach-socfpga/smmu_agilex5.c b/arch/arm/mach-socfpga/smmu_agilex5.c new file mode 100644 index 0000000000..05e74926aa --- /dev/null +++ b/arch/arm/mach-socfpga/smmu_agilex5.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Intel Corporation. All rights reserved + * + */ + +#include <common.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/firewall.h> +#include <asm/arch/smmu_agilex5.h> +#include <asm/arch/system_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static inline void setup_smmu_firewall(void) +{ + u32 i; + + /* Off the DDR secure transaction for all TBU supported peripherals */ + for (i = SYSMGR_DMA0_SID_ADDR; i < SYSMGR_TSN2_SID_ADDR; i += + SOCFPGA_NEXT_TBU_PERIPHERAL) { + /* skip this, future use register */ + if (i == SYSMGR_USB3_SID_ADDR) + continue; + + writel(SECURE_TRANS_RESET, (uintptr_t)i); + } +} + +void socfpga_init_smmu(void) +{ + setup_smmu_firewall(); +} diff --git a/arch/arm/mach-socfpga/smmu_s10.c b/arch/arm/mach-socfpga/smmu_s10.c new file mode 100644 index 0000000000..106834cc9a --- /dev/null +++ b/arch/arm/mach-socfpga/smmu_s10.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018-2023 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/firewall.h> +#include <asm/arch/smmu_s10.h> +#include <asm/arch/system_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct smmu_stream_id dev_stream_id[] = { + {SYSMGR_EMAC0_SID_ADDR, 0x01, EMAC_W_OFST, EMAC_R_OFST}, + {SYSMGR_EMAC1_SID_ADDR, 0x02, EMAC_W_OFST, EMAC_R_OFST}, + {SYSMGR_EMAC2_SID_ADDR, 0x03, EMAC_W_OFST, EMAC_R_OFST}, + {SYSMGR_NAND_SID_ADDR, 0x04, NAND_W_OFST, NAND_R_OFST}, + {SYSMGR_SDMMC_SID_ADDR, 0x05, SDMMC_OFST, SDMMC_OFST}, + {SYSMGR_USB0_SID_ADDR, 0x06, USB_OFST, USB_OFST}, + {SYSMGR_USB1_SID_ADDR, 0x07, USB_OFST, USB_OFST}, + {SYSMGR_DMA_SID_ADDR, 0x08, DMA_W_OFST, DMA_R_OFST}, + {SYSMGR_ETR_SID_ADDR, 0x09, ETR_W_OFST, ETR_R_OFST}, +}; + +static void set_smmu_streamid(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(dev_stream_id); i++) { + u32 mask = SMMU_SET_STREAMID(0x3FF, + dev_stream_id[i].r_bit_ofst, + dev_stream_id[i].w_bit_ofst); + u32 value = SMMU_SET_STREAMID(dev_stream_id[i].sid, + dev_stream_id[i].r_bit_ofst, + dev_stream_id[i].w_bit_ofst); + + clrbits_le32(dev_stream_id[i].addr, mask); + setbits_le32(dev_stream_id[i].addr, value); + } +} + +/* + * Need to set the Secure bit (to make it non-secure) on each peripheral + * so that SMMU can access the peripheral + */ +static void set_smmu_accessible_reg(void) +{ + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0, + BIT(27) | BIT(25)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1, + BIT(27) | BIT(25)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2, + BIT(27) | BIT(25)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NANDGRP_L3MASTER, + BIT(21) | BIT(17)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC_L3MASTER, + BIT(5)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB0_L3MASTER, + BIT(9)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB1_L3MASTER, + BIT(9)); +} + +static inline void setup_smmu_firewall(void) +{ + /* Enable nonsecure SMMU accesses */ + writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); +} + +void socfpga_init_smmu(void) +{ + setup_smmu_firewall(); + set_smmu_streamid(); + set_smmu_accessible_reg(); +} + +int is_smmu_bypass(void) +{ + return readl(SOCFPGA_SMMU_ADDRESS + SMMU_SCR0) & SMMU_SCR0_CLIENTPD; +} + +int is_smmu_stream_id_enabled(u32 stream_id) +{ + int i; + u32 smrg_num; + u32 smr, s2cr, sid_mask; + u32 cb, cb_index, cb_num; + + if (is_smmu_bypass()) + return 0; + + /* Get number of Stream Mapping Register Groups */ + smrg_num = readl(SOCFPGA_SMMU_ADDRESS + SMMU_SIDR0) & + SMMU_SIDR0_NUMSMRG_MASK; + + /* Get number of Context Bank */ + cb_num = readl(SOCFPGA_SMMU_ADDRESS + SMMU_SIDR1) & + SMMU_SIDR1_NUMCB_MASK; + + for (i = 0; i < smrg_num; i++) { + smr = readl(SOCFPGA_SMMU_ADDRESS + SMMU_GR0_SMR((u64)i)); + sid_mask = (smr & SMMU_SMR_MASK) >> 16; + + /* Skip if Stream ID is invalid or not matched */ + if (!(smr & SMMU_SMR_VALID) || (smr & sid_mask) != stream_id) + continue; + + /* Get Context Bank index from valid matching Stream ID */ + s2cr = readl(SOCFPGA_SMMU_ADDRESS + SMMU_GR0_S2CR((u64)i)); + cb_index = s2cr & SMMU_S2CR_CBNDX; + + /* Skip if Context Bank is invalid or not Translation mode */ + if (cb_index >= cb_num || (s2cr & SMMU_S2CR_TYPE)) + continue; + + cb = readl(SOCFPGA_SMMU_ADDRESS + SMMU_GR0_CB((u64)cb_index, + SMMU_CB_SCTLR)); + /* Return MMU enable status for this Context Bank */ + return (cb & SMMU_CB_SCTLR_M); + } + + return 0; +} diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c new file mode 100644 index 0000000000..da91bf5917 --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2023 Intel Corporation <www.intel.com> + * + */ + +#include <init.h> +#include <log.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <common.h> +#include <hang.h> +#include <image.h> +#include <spl.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/smmu_s10.h> +#include <asm/arch/system_manager.h> +#include <wdt.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define USE_HARDCODED_HANDOFF + +#ifdef USE_HARDCODED_HANDOFF +static const u32 hardcoded_handoff_data[402] = { +0x544f4f42, 0x01000500, 0x00000000, 0x00000000, 0x58554d50, 0x90010000, +0x00000000, 0x00000000, 0x00000000, 0x03000000, 0x04000000, 0x03000000, +0x08000000, 0x03000000, 0x0c000000, 0x03000000, 0x10000000, 0x03000000, +0x14000000, 0x03000000, 0x18000000, 0x03000000, 0x1c000000, 0x03000000, +0x20000000, 0x03000000, 0x24000000, 0x03000000, 0x28000000, 0x03000000, +0x2c000000, 0x03000000, 0x30000000, 0x03000000, 0x34000000, 0x03000000, +0x38000000, 0x03000000, 0x3c000000, 0x03000000, 0x40000000, 0x00000000, +0x44000000, 0x00000000, 0x48000000, 0x00000000, 0x4c000000, 0x00000000, +0x50000000, 0x00000000, 0x54000000, 0x00000000, 0x58000000, 0x04000000, +0x5c000000, 0x04000000, 0x60000000, 0x08000000, 0x64000000, 0x08000000, +0x68000000, 0x05000000, 0x6c000000, 0x05000000, 0x70000000, 0x08000000, +0x74000000, 0x08000000, 0x78000000, 0x04000000, 0x7c000000, 0x04000000, +0x80000000, 0x07000000, 0x84000000, 0x07000000, 0x88000000, 0x07000000, +0x8c000000, 0x07000000, 0x90000000, 0x01000000, 0x94000000, 0x01000000, +0x98000000, 0x01000000, 0x9c000000, 0x01000000, 0x00010000, 0x01000000, +0x04010000, 0x01000000, 0x08010000, 0x09000000, 0x0c010000, 0x08000000, +0x10010000, 0x08000000, 0x14010000, 0x08000000, 0x18010000, 0x05000000, +0x1c010000, 0x05000000, 0x54434f49, 0x90010000, 0x00000000, 0x00000000, +0x00000000, 0x34000000, 0x04000000, 0x14000000, 0x08000000, 0x34000000, +0x0c000000, 0x34000000, 0x10000000, 0x34000000, 0x14000000, 0x34000000, +0x18000000, 0x34000000, 0x1c000000, 0x34000000, 0x20000000, 0x34000000, +0x24000000, 0x34000000, 0x28000000, 0x34000000, 0x2c000000, 0x34000000, +0x30000000, 0x16000000, 0x34000000, 0x14000000, 0x38000000, 0x34000000, +0x3c000000, 0x34000000, 0x40000000, 0x14000000, 0x44000000, 0x14000000, +0x48000000, 0x34000000, 0x4c000000, 0x34000000, 0x50000000, 0x14000000, +0x54000000, 0x14000000, 0x58000000, 0x34000000, 0x5c000000, 0x34000000, +0x60000000, 0x35000000, 0x64000000, 0x35000000, 0x68000000, 0x16000000, +0x6c000000, 0x34000000, 0xd0000000, 0x35000000, 0xd4000000, 0x35000000, +0xd8000000, 0x3e000000, 0xdc000000, 0x3e000000, 0xe0000000, 0x34000000, +0xe4000000, 0x34000000, 0xe8000000, 0x16000000, 0xec000000, 0x34000000, +0xf0000000, 0x34000000, 0xf4000000, 0x34000000, 0xf8000000, 0x14000000, +0xfc000000, 0x34000000, 0x00010000, 0x34000000, 0x04010000, 0x34000000, +0x08010000, 0x34000000, 0x0c010000, 0x35000000, 0x10010000, 0x35000000, +0x14010000, 0x35000000, 0x18010000, 0x3e000000, 0x1c010000, 0x16000000, +0x41475046, 0xc0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x04000000, 0x00000000, 0x08000000, 0x00000000, 0x0c000000, 0x00000000, +0x10000000, 0x00000000, 0x14000000, 0x00000000, 0x18000000, 0x00000000, +0x1c000000, 0x00000000, 0x20000000, 0x00000000, 0x28000000, 0x00000000, +0x2c000000, 0x00000000, 0x30000000, 0x00000000, 0x34000000, 0x00000000, +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU) +0x38000000, 0x01000000, 0x3c000000, 0x00000000, 0x40000000, 0x00000000, +#else +0x38000000, 0x00000000, 0x3c000000, 0x00000000, 0x40000000, 0x00000000, +#endif +0x44000000, 0x00000000, 0x48000000, 0x00000000, 0x50000000, 0x00000000, +0x54000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x59414c44, 0x90010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x04000000, 0x00000000, 0x08000000, 0x00000000, 0x0c000000, 0x00000000, +0x10000000, 0x00000000, 0x14000000, 0x00000000, 0x18000000, 0x00000000, +0x1c000000, 0x00000000, 0x20000000, 0x00000000, 0x24000000, 0x00000000, +0x28000000, 0x00000000, 0x2c000000, 0x00000000, 0x30000000, 0x00110000, +0x34000000, 0x00000000, 0x38000000, 0x00000000, 0x3c000000, 0x00000000, +0x40000000, 0x00000000, 0x44000000, 0x00000000, 0x48000000, 0x00000000, +0x4c000000, 0x00000000, 0x50000000, 0x00000000, 0x54000000, 0x00000000, +0x58000000, 0x00000000, 0x5c000000, 0x00000000, 0x60000000, 0x00000000, +0x64000000, 0x00000000, 0x68000000, 0x00000000, 0x6c000000, 0x00000000, +0x70000000, 0x00000000, 0x74000000, 0x00000000, 0x78000000, 0x00000000, +0x7c000000, 0x00000000, 0x80000000, 0x00000000, 0x84000000, 0x00000000, +0x88000000, 0x00000000, 0x8c000000, 0x00000000, 0x90000000, 0x00000000, +0x94000000, 0x00000000, 0x98000000, 0x00000000, 0x9c000000, 0x00000000, +0xa0000000, 0x00000000, 0xa4000000, 0x00000000, 0xa8000000, 0x00000000, +0xac000000, 0x00000000, 0xb0000000, 0x00000000, 0xb4000000, 0x00000000, +0xb8000000, 0x00000000, 0xbC000000, 0x00000000, 0x534b4c43, 0xA0000000, +0x00000000, 0x00000000, 0x00000000, 0x98002618, 0x03010016, 0x00000000, +0x02000008, 0x04000008, 0x03000008, 0x09000008, 0x90000000, 0x00000000, +0x01000000, 0x03010015, 0x00000000, 0x02000008, 0x03000008, 0x7d000008, +0x06000008, 0x78000000, 0x01000100, 0x09000000, 0x00000100, 0x01000000, +0x00000100, 0x00000100, 0x00000100, 0x13000000, 0x01000000, 0x00000100, +0x00000000, 0x00000000, 0x00000000, 0x40787d01, 0x40787d01, 0x00000000, +0x00000000, 0x00000000, 0x49524550, 0x14000000, 0x00000000, 0x00000000, +0x40000000, 0x4d524453, 0x14000000, 0x00000000, 0x00000000, 0x00000000 +}; +#endif + +#define HARDCODED_HANDOFF_DATA_SIZE (sizeof(hardcoded_handoff_data) / sizeof(u32)) + +void board_init_f(ulong dummy) +{ + int ret; + struct udevice *dev; + + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_managers_addr(); + +#ifdef USE_HARDCODED_HANDOFF + /* Write hardcoded handoff value into OCRAM handoff area */ + u32 i; + + for (i = 0; i < HARDCODED_HANDOFF_DATA_SIZE; i++) + writel(hardcoded_handoff_data[i], + (u32 *)SOC64_HANDOFF_BASE + i); +#endif + + sysmgr_pinmux_init(); + + if (!(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU))) { + /* Ensure watchdog is paused when debugging is happening */ + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); + } + + timer_init(); + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("Clock init failed: %d\n", ret); + hang(); + } + + if (!(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU))) { + /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + } + + preloader_console_init(); + print_reset_info(); + cm_print_clock_quick_summary(); + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-secreg", &dev); + if (ret) { + printf("Firewall & secure settings init failed: %d\n", ret); + hang(); + } + +#if CONFIG_IS_ENABLED(ALTERA_SDRAM) + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + hang(); + } +#endif + + mbox_init(); + +#ifdef CONFIG_CADENCE_QSPI + mbox_qspi_open(); +#endif +} diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index ba6efc1d86..a4ac906ffd 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -1,25 +1,203 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 Intel Corporation. All rights reserved + * Copyright (C) 2020-2022 Intel Corporation. All rights reserved * */
+#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> #include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/ofnode.h> +#include <image.h> +#include <log.h> #include <spl.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/smmu_s10.h> +#include <watchdog.h> +#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void) { + int ret, size; + ofnode node; + const fdt32_t *phandle_p; + u32 phandle; + struct udevice *dev; + + node = ofnode_path("/chosen"); + if (!ofnode_valid(node)) { + debug("%s: /chosen node was not found.\n", __func__); + goto fallback; + } + + phandle_p = ofnode_get_property(node, "u-boot,boot0", &size); + if (!phandle_p) { + debug("%s: u-boot,boot0 property was not found.\n", + __func__); + goto fallback; + } + + phandle = fdt32_to_cpu(*phandle_p); + + node = ofnode_get_by_phandle(phandle); + + ret = device_get_global_by_ofnode(node, &dev); + if (ret) { + debug("%s: Boot device at not found, error: %d\n", __func__, + ret); + goto fallback; + } + + debug("%s: Found boot device %s\n", __func__, dev->name); + + switch (device_get_uclass_id(dev)) { + case UCLASS_SPI_FLASH: + return BOOT_DEVICE_SPI; + case UCLASS_MTD: + return BOOT_DEVICE_NAND; + case UCLASS_MMC: + return BOOT_DEVICE_MMC1; + default: + debug("%s: Booting from device uclass '%s' is not supported\n", + __func__, dev_get_uclass_name(dev)); + } + +fallback: + /* Return default boot device */ return BOOT_DEVICE_MMC1; }
#if IS_ENABLED(CONFIG_SPL_MMC) u32 spl_boot_mode(const u32 boot_device) { - if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) - return MMCSD_MODE_FS; - else - return MMCSD_MODE_RAW; +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif } #endif + +/* board specific function prior loading SSBL / U-Boot */ +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + /* Setup and Initialize SMMU */ + socfpga_init_smmu(); + +#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || \ +IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)) + mbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); +#endif +} + +/* This function is to map specified node onto SPL boot devices */ +static int spl_node_to_boot_device(int node) +{ + const void *blob = gd->fdt_blob; + struct udevice *parent; + const char *prop; + + if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) + return BOOT_DEVICE_MMC1; + else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) + return BOOT_DEVICE_SPI; + else if (!uclass_get_device_by_of_offset(UCLASS_MTD, node, &parent)) + return BOOT_DEVICE_NAND; + + prop = fdt_getprop(blob, node, "device_type", NULL); + if (prop) { + if (!strcmp(prop, "memory")) + return BOOT_DEVICE_RAM; + + printf("%s: unknown device_type %s\n", __func__, prop); + } + + return -1; +} + +static void default_spl_boot_list(u32 *spl_boot_list, int length) +{ + spl_boot_list[0] = BOOT_DEVICE_MMC1; + + if (length > 1) + spl_boot_list[1] = BOOT_DEVICE_SPI; + + if (length > 2) + spl_boot_list[2] = BOOT_DEVICE_NAND; +} + +void board_boot_order(u32 *spl_boot_list) +{ + int idx = 0; + const void *blob = gd->fdt_blob; + int chosen_node = fdt_path_offset(blob, "/chosen"); + const char *conf; + int elem; + int boot_device; + int node; + int length; + + /* expect valid initialized spl_boot_list */ + if (!spl_boot_list) + return; + + length = 1; + while (spl_boot_list[length] == spl_boot_list[length - 1]) + length++; + + debug("%s: chosen_node is %d\n", __func__, chosen_node); + if (chosen_node < 0) { + printf("%s: /chosen not found, using default\n", __func__); + default_spl_boot_list(spl_boot_list, length); + return; + } + + for (elem = 0; + (conf = fdt_stringlist_get(blob, chosen_node, + "u-boot,spl-boot-order", elem, NULL)); + elem++) { + if (idx >= length) { + printf("%s: limit %d to spl_boot_list exceeded\n", __func__, + length); + break; + } + + /* Resolve conf item as a path in device tree */ + node = fdt_path_offset(blob, conf); + if (node < 0) { + debug("%s: could not find %s in FDT\n", __func__, conf); + continue; + } + + /* Try to map spl node back onto SPL boot devices */ + boot_device = spl_node_to_boot_device(node); + if (boot_device < 0) { + debug("%s: could not map node @%x to a boot-device\n", + __func__, node); + continue; + } + + spl_boot_list[idx] = boot_device; + debug("%s: spl_boot_list[%d] = %u\n", __func__, idx, + spl_boot_list[idx]); + idx++; + } + + if (idx == 0) { + if (!conf && !elem) { + printf("%s: spl-boot-order invalid, using default\n", __func__); + default_spl_boot_list(spl_boot_list, length); + } else { + printf("%s: no valid element spl-boot-order list\n", __func__); + } + } +} diff --git a/arch/arm/mach-socfpga/u-boot-spl-soc64.lds b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds new file mode 100644 index 0000000000..8beef91d17 --- /dev/null +++ b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2018 + * Intel Corporation <www.intel.com> + * + * (C) Copyright 2013 + * David Feng fenghua@phytium.com.cn + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V aneesh@ti.com + * + * SPDX-License-Identifier: GPL-2.0 + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{ + .text : { + . = ALIGN(8); + __image_copy_start = .; + CPUDIR/start.o (.text*) + *(.text*) + } >.sram + + .rodata : { + . = ALIGN(8); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } >.sram + + .data : { + . = ALIGN(8); + /* Run time .data section starting at this location */ + __data_start = .; + *(.data*) + /* Run time .data section ending at this location */ + __data_end = .; + } >.sram + + . = ALIGN(8); + /* Preserve original .data section starting at this location */ + __preserve_data_start = .; + . = __preserve_data_start + (__data_end - __data_start); + /* Preserve original .data section ending at this location */ + __preserve_data_end = .; + + . = ALIGN(8); + __u_boot_list . : { + KEEP(*(SORT(__u_boot_list*))); + } >.sram + + .image_copy_end : { + . = ALIGN(8); + *(.__image_copy_end) + } >.sram + + .end : { + . = ALIGN(8); + *(.__end) + } >.sram + + _image_binary_end = .; + + .bss_start (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.__bss_start)); + } >.sdram + + .bss (NOLOAD) : { + *(.bss*) + . = ALIGN(8); + } >.sdram + + .bss_end (NOLOAD) : { + KEEP(*(.__bss_end)); + } >.sdram + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index e7cb5ea89c..23434dbf6c 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2022 Intel Corporation <www.intel.com> * */
@@ -19,7 +19,12 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_MAGIC_FPGA: case SOC64_HANDOFF_MAGIC_DELAY: case SOC64_HANDOFF_MAGIC_CLOCK: +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + case SOC64_HANDOFF_MAGIC_PERI: + case SOC64_HANDOFF_MAGIC_SDRAM: +#else case SOC64_HANDOFF_MAGIC_MISC: +#endif return BIG_ENDIAN; #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) case SOC64_HANDOFF_DDR_UMCTL2_MAGIC:
Hi Jit Loon,
-----Original Message----- From: Lim, Jit Loon jit.loon.lim@intel.com Sent: Wednesday, 21 June, 2023 11:16 AM To: u-boot@lists.denx.de Cc: Jagan Teki jagan@amarulasolutions.com; Vignesh R vigneshr@ti.com; Vasut, Marek marex@denx.de; Simon simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Hea, Kok Kiang kok.kiang.hea@intel.com; Lokanathan, Raaj raaj.lokanathan@intel.com; Maniyam, Dinesh dinesh.maniyam@intel.com; Ng, Boon Khai boon.khai.ng@intel.com; Yuslaimi, Alif Zakuan alif.zakuan.yuslaimi@intel.com; Chong, Teik Heng teik.heng.chong@intel.com; Zamri, Muhammad Hazim Izzat muhammad.hazim.izzat.zamri@intel.com; Lim, Jit Loon jit.loon.lim@intel.com; Tang, Sieu Mun sieu.mun.tang@intel.com Subject: [PATCH v1 03/17] arch: arm: mach-socfpga: add new platform agilex5 mach-socfpga enablement
This is for new platform enablement for agilex5. Add platform related files to enable new product.
You should not squash all IP drivers such as clock manager, reset manager into one patch, this is not the right way to generate the patch, very hard for me to review the codes.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com
arch/arm/mach-socfpga/Kconfig | 37 +++ arch/arm/mach-socfpga/Makefile | 69 ++++- arch/arm/mach-socfpga/board.c | 65 ++++- arch/arm/mach-socfpga/clock_manager_agilex5.c | 82 ++++++ arch/arm/mach-socfpga/firewall.c | 107 ------- arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 61 ++++ arch/arm/mach-socfpga/lowlevel_init_soc64.S | 167 ++++++++++- arch/arm/mach-socfpga/mailbox_s10.c | 21 ++ arch/arm/mach-socfpga/misc.c | 19 +- arch/arm/mach-socfpga/misc_soc64.c | 33 ++- arch/arm/mach-socfpga/mmu-arm64_s10.c | 43 ++- arch/arm/mach-socfpga/reset_manager_s10.c | 271 +++++++++++++++--
arch/arm/mach-socfpga/secure_reg_helper.c | 4 +- arch/arm/mach-socfpga/smmu_agilex5.c | 34 +++ arch/arm/mach-socfpga/smmu_s10.c | 126 ++++++++ arch/arm/mach-socfpga/spl_agilex5.c | 180 ++++++++++++ arch/arm/mach-socfpga/spl_soc64.c | 188 +++++++++++- arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 93 ++++++ arch/arm/mach-socfpga/wrap_handoff_soc64.c | 7 +- 19 files changed, 1429 insertions(+), 178 deletions(-) create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c delete mode 100644 arch/arm/mach-socfpga/firewall.c create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S create mode 100644 arch/arm/mach-socfpga/smmu_agilex5.c create mode 100644 arch/arm/mach-socfpga/smmu_s10.c create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach- socfpga/Kconfig index 503c82d388..562c3796ec 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -44,6 +44,15 @@ config TEXT_BASE default 0x01000040 if TARGET_SOCFPGA_ARRIA10 default 0x01000040 if TARGET_SOCFPGA_GEN5
+config ARMV8_PSCI_NR_CPUS
- default 4 if TARGET_SOCFPGA_SOC64
+config ARMV8_SECURE_BASE
- default 0x00001000 if TARGET_SOCFPGA_SOC64 && ARMV8_PSCI
+config SYS_HAS_ARMV8_SECURE_BASE
- default y if TARGET_SOCFPGA_SOC64 && ARMV8_PSCI
config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY @@ -51,10 +60,31 @@ config TARGET_SOCFPGA_AGILEX select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX
- select GICV2
- select NCORE_CACHE
- select SPL_CLK if SPL
- select TARGET_SOCFPGA_SOC64
+config TARGET_SOCFPGA_AGILEX5
- bool
- select BINMAN if SPL_ATF
- select CLK
- select FPGA_INTEL_SDM_MAILBOX
- select GICV3 select NCORE_CACHE select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64
+config TARGET_SOCFPGA_AGILEX5_EMU
- bool "Enable build that bootable only on Agilex5 Emulator"
- help
This is to use for Agilex5 Emulator.+config TARGET_SOCFPGA_AGILEX5_SIMICS
- bool "Enable build that bootable only on Agilex5 Simics platform"
- help
This is to use for Agilex5 Simics.config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -126,6 +156,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" select TARGET_SOCFPGA_AGILEX
+config TARGET_SOCFPGA_AGILEX5_SOCDK
- bool "Intel SOCFPGA SoCDK (Agilex5)"
- select TARGET_SOCFPGA_AGILEX5
config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -199,6 +233,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice
config SYS_BOARD
- default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
@@ -220,6 +255,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
config SYS_VENDOR
- default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
@@ -242,6 +278,7 @@ config SYS_SOC default "socfpga"
config SYS_CONFIG_NAME
- default "socfpga_agilex5_socdk" if
TARGET_SOCFPGA_AGILEX5_SOCDK default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach- socfpga/Makefile index ec38b64dd4..771e7ce77d 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -35,10 +35,22 @@ obj-y += mailbox_s10.o obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o +obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-y += rsu.o +obj-y += rsu_ll_qspi.o +obj-y += rsu_misc.o +obj-y += rsu_s10.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o
There are no rsu, smc and including secreg drivers in mainline yet, you have to upstream these drivers first or excluding these drivers related in this series. You can submit separate patches for these changes once these drivers are available in mainline.
+endif endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX @@ -49,11 +61,46 @@ obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-y += rsu.o +obj-y += rsu_ll_qspi.o +obj-y += rsu_misc.o +obj-y += rsu_s10.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o +endif +endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +obj-y += clock_manager_agilex5.o +obj-y += lowlevel_init_agilex5.o +obj-y += mailbox_s10.o +obj-y += misc_soc64.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += smmu_agilex5.o +obj-y += system_manager_soc64.o +obj-y += timer_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o +obj-y += wrap_handoff_soc64.o +obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o +endif endif
ifdef CONFIG_TARGET_SOCFPGA_N5X @@ -64,11 +111,22 @@ obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-y += rsu.o +obj-y += rsu_ll_qspi.o +obj-y += rsu_misc.o +obj-y += rsu_s10.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o +endif endif
ifdef CONFIG_SPL_BUILD @@ -79,21 +137,24 @@ obj-y += wrap_iocsr_config.o obj-y += wrap_pinmux_config.o obj-y += wrap_sdram_config.o endif -ifdef CONFIG_TARGET_SOCFPGA_SOC64 -obj-y += firewall.o -obj-y += spl_soc64.o -endif ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 obj-y += spl_a10.o endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += spl_s10.o +obj-y += spl_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += spl_agilex.o +obj-y += spl_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += spl_n5x.o +obj-y += spl_soc64.o +endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +obj-y += spl_agilex5.o +obj-y += spl_soc64.o endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach- socfpga/board.c index 09e09192fb..140a520ab7 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -7,9 +7,11 @@
#include <common.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/secure_vab.h> +#include <asm/arch/smc_api.h> #include <asm/global_data.h> #include <asm/io.h> #include <errno.h> @@ -23,6 +25,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define DEFAULT_JTAG_USERCODE 0xFFFFFFFF
void s_init(void) { #ifndef CONFIG_ARM64 /* @@ -46,7 +50,7 @@ void s_init(void) { int board_init(void) { /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
} @@ -92,13 +96,55 @@ int g_dnl_board_usb_cable_connected(void) } #endif
-#ifdef CONFIG_SPL_BUILD -__weak int board_fit_config_name_match(const char *name) +u8 socfpga_get_board_id(void) {
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
- u8 board_id = 0;
- u32 jtag_usercode;
- int err;
- return 0;
+#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)
- err = smc_get_usercode(&jtag_usercode);
+#else
- u32 resp_len = 1;
- err = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_GET_USERCODE,
MBOX_CMD_DIRECT, 0,
NULL, 0, &resp_len, &jtag_usercode);+#endif
- if (err) {
puts("Fail to read JTAG Usercode. Default Board ID to 0\n");return board_id;- }
- debug("Valid JTAG Usercode: %u\n", jtag_usercode);
- if (jtag_usercode == DEFAULT_JTAG_USERCODE) {
debug("JTAG Usercode is not set. Default Board ID to 0\n");- } else if (jtag_usercode >= 0 && jtag_usercode <= 255) {
board_id = jtag_usercode;debug("Valid JTAG Usercode. Set Board ID to %u\n",board_id);
- } else {
puts("Board ID is not in range 0 to 255\n");- }
- return board_id;
+}
+#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +int board_fit_config_name_match(const char *name) +{
- char board_name[10];
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || \ +IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)
- sprintf(board_name, "board_%u", 0); /* Hardcoded board ID since
Simics no support */ +#else
- sprintf(board_name, "board_%u", socfpga_get_board_id());
+#endif
- debug("Board name: %s\n", board_name);
- return strcmp(name, board_name);
} #endif
@@ -116,6 +162,8 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, #if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT) void board_prep_linux(struct bootm_headers *images) {
bool use_fit = false;
if (!images->fit_uname_cfg) { if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
!IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) { @@ -127,14 +175,17 @@ void board_prep_linux(struct bootm_headers *images) hang(); } } else {
use_fit = true;ft_addr);
}
- if (IS_ENABLED(CONFIG_CADENCE_QSPI)) {
- if (use_fit && IS_ENABLED(CONFIG_CADENCE_QSPI)) { if (env_get("linux_qspi_enable")) run_command(env_get("linux_qspi_enable"), 0);
if (env_get("rsu_status"))run_command(env_get("rsu_status"), 0);} #endif diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c new file mode 100644 index 0000000000..46b6bc5d40 --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
- */
+#include <clk.h> +#include <common.h> +#include <dm.h> +#include <log.h> +#include <malloc.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <dt-bindings/clock/agilex5-clock.h>
+DECLARE_GLOBAL_DATA_PTR;
+static ulong cm_get_rate_dm(u32 id) +{
- struct udevice *dev;
- struct clk clk;
- ulong rate;
- int ret;
- ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_DRIVER_GET(socfpga_agilex5_clk),
&dev);- if (ret)
return 0;- clk.id = id;
- ret = clk_request(dev, &clk);
- if (ret < 0)
return 0;- rate = clk_get_rate(&clk);
- clk_free(&clk);
- if ((rate == (unsigned long)-ENOSYS) ||
(rate == (unsigned long)-ENXIO) ||(rate == (unsigned long)-EIO)) {debug("%s id %u: clk_get_rate err: %ld\n",__func__, id, rate);return 0;- }
- return rate;
+}
+static u32 cm_get_rate_dm_khz(u32 id) +{
- return cm_get_rate_dm(id) / 1000;
+}
+unsigned long cm_get_mpu_clk_hz(void) +{
- return cm_get_rate_dm(AGILEX5_MPU_CLK);
+}
+unsigned int cm_get_l4_sys_free_clk_hz(void) +{
- return cm_get_rate_dm(AGILEX5_L4_SYS_FREE_CLK);
+}
+void cm_print_clock_quick_summary(void) +{
- printf("MPU %10d kHz\n",
cm_get_rate_dm_khz(AGILEX5_MPU_CLK));- printf("L4 Main %8d kHz\n",
cm_get_rate_dm_khz(AGILEX5_L4_MAIN_CLK));- printf("L4 sys free %8d kHz\n",
cm_get_rate_dm_khz(AGILEX5_L4_SYS_FREE_CLK));- printf("L4 MP %8d kHz\n",
cm_get_rate_dm_khz(AGILEX5_L4_MP_CLK));- printf("L4 SP %8d kHz\n",
cm_get_rate_dm_khz(AGILEX5_L4_SP_CLK));- printf("SDMMC %8d kHz\n",
cm_get_rate_dm_khz(AGILEX5_SDMMC_CLK));+} diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach- socfpga/firewall.c deleted file mode 100644 index 69229dc651..0000000000 --- a/arch/arm/mach-socfpga/firewall.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
- */
-#include <asm/io.h> -#include <common.h> -#include <asm/arch/firewall.h> -#include <asm/arch/system_manager.h>
-static void firewall_l4_per_disable(void) -{
- const struct socfpga_firwall_l4_per *firwall_l4_per_base =
(struct socfpga_firwall_l4_per*)SOCFPGA_FIREWALL_L4_PER;
- u32 i;
- const u32 *addr[] = {
&firwall_l4_per_base->nand,&firwall_l4_per_base->nand_data,&firwall_l4_per_base->usb0,&firwall_l4_per_base->usb1,&firwall_l4_per_base->spim0,&firwall_l4_per_base->spim1,&firwall_l4_per_base->emac0,&firwall_l4_per_base->emac1,&firwall_l4_per_base->emac2,&firwall_l4_per_base->sdmmc,&firwall_l4_per_base->gpio0,&firwall_l4_per_base->gpio1,&firwall_l4_per_base->i2c0,&firwall_l4_per_base->i2c1,&firwall_l4_per_base->i2c2,&firwall_l4_per_base->i2c3,&firwall_l4_per_base->i2c4,&firwall_l4_per_base->timer0,&firwall_l4_per_base->timer1,&firwall_l4_per_base->uart0,&firwall_l4_per_base->uart1};- /*
* The following lines of code will enable non-secure access* to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This* is needed as most OS run in non-secure mode. Thus we need to* enable non-secure access to these peripherals in order for the* OS to use these peripherals.*/- for (i = 0; i < ARRAY_SIZE(addr); i++)
writel(FIREWALL_L4_DISABLE_ALL, addr[i]);-}
-static void firewall_l4_sys_disable(void) -{
- const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;- u32 i;
- const u32 *addr[] = {
&firwall_l4_sys_base->dma_ecc,&firwall_l4_sys_base->emac0rx_ecc,&firwall_l4_sys_base->emac0tx_ecc,&firwall_l4_sys_base->emac1rx_ecc,&firwall_l4_sys_base->emac1tx_ecc,&firwall_l4_sys_base->emac2rx_ecc,&firwall_l4_sys_base->emac2tx_ecc,&firwall_l4_sys_base->nand_ecc,&firwall_l4_sys_base->nand_read_ecc,&firwall_l4_sys_base->nand_write_ecc,&firwall_l4_sys_base->ocram_ecc,&firwall_l4_sys_base->sdmmc_ecc,&firwall_l4_sys_base->usb0_ecc,&firwall_l4_sys_base->usb1_ecc,&firwall_l4_sys_base->clock_manager,&firwall_l4_sys_base->io_manager,&firwall_l4_sys_base->reset_manager,&firwall_l4_sys_base->system_manager,&firwall_l4_sys_base->watchdog0,&firwall_l4_sys_base->watchdog1,&firwall_l4_sys_base->watchdog2,&firwall_l4_sys_base->watchdog3};- for (i = 0; i < ARRAY_SIZE(addr); i++)
writel(FIREWALL_L4_DISABLE_ALL, addr[i]);-}
-static void firewall_bridge_disable(void) -{
- /* disable lwsocf2fpga and soc2fpga bridge security */
- writel(FIREWALL_BRIDGE_DISABLE_ALL,
SOCFPGA_FIREWALL_SOC2FPGA);
- writel(FIREWALL_BRIDGE_DISABLE_ALL,
SOCFPGA_FIREWALL_LWSOC2FPGA); -}
-void firewall_setup(void) -{
- firewall_l4_per_disable();
- firewall_l4_sys_disable();
- firewall_bridge_disable();
- /* disable SMMU security */
- writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
- /* enable non-secure interface to DMA330 DMA and peripherals */
- writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);- writel(SYSMGR_DMAPERIPH_ALL_NS,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);-} diff --git a/arch/arm/mach-socfpga/lowlevel_init_agilex5.S b/arch/arm/mach-socfpga/lowlevel_init_agilex5.S new file mode 100644 index 0000000000..15e5066767 --- /dev/null +++ b/arch/arm/mach-socfpga/lowlevel_init_agilex5.S @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2022-2023 Intel Corporation <www.intel.com>
- */
+#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> +#include <asm/arch/reset_manager_soc64.h>
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) +.align 3 +_el3_exception_vectors:
- .quad el3_exception_vectors;
+#endif
+ENTRY(lowlevel_init)
- mov x29, lr /* Save LR */
+#ifdef CONFIG_SPL_BUILD
- branch_if_slave x0, 3f
- /* Check rstmgr.stat for warm reset status */
- ldr w1, =SOCFPGA_RSTMGR_ADDRESS
- ldr w0, [x1]
- /* Check whether any L4 watchdogs or SDM had triggered warm
reset */
- ldr x2, =RSTMGR_L4WD_MPU_WARMRESET_MASK
- ands x0, x0, x2
- /*
* If current Reset Manager's status is warm reset just reload the* .data section by copying the data from data preserve section.* Otherwise, copy the .data section to the data preserve section to* keep an original copy of .data section. This ensure SPL is* reentrant after warm reset.*/- b.ne reload_data_section
- /* Copy from .data to preserved .data to backup the SPL state */
- ldr x0, =__data_start
- ldr x1, =__preserve_data_start
- ldr x2, =__preserve_data_end
- b copy_loop
+reload_data_section:
- /* Copy from preserved .data to .data to restore the SPL state */
- ldr x0, =__preserve_data_start
- ldr x1, =__data_start
- ldr x2, =__data_end
+copy_loop:
- ldr w3, [x0]
- add x0, x0, #4
- str w3, [x1]
- add x1, x1, #4
- cmp x1, x2
- b.ne copy_loop
+3: +#endif
- mov lr, x29 /* Restore LR */
- ret
+ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach- socfpga/lowlevel_init_soc64.S index 875927cc4d..5680553f68 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -1,7 +1,7 @@ -/*
- Copyright (C) 2020 Intel Corporation. All rights reserved
+/* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2022-2023 Intel Corporation <www.intel.com>
*/
- SPDX-License-Identifier: GPL-2.0
#include <asm-offsets.h> @@ -9,11 +9,101 @@ #include <linux/linkage.h> #include <asm/macro.h>
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI) +.align 3 +_el3_exception_vectors:
- .quad el3_exception_vectors;
+#endif
ENTRY(lowlevel_init) mov x29, lr /* Save LR */
+#ifdef CONFIG_SPL_BUILD
- /* Check for L2 reset magic word */
- ldr x4, =L2_RESET_DONE_REG
- ldr x5, [x4]
- ldr x1, =L2_RESET_DONE_STATUS
- cmp x1, x5
- /* No L2 reset, skip warm reset */
- b.ne skipwarmreset
- /* Put all slaves CPUs into WFI mode */
- branch_if_slave x0, put_cpu_in_wfi
- /* L2 reset completed */
- str xzr, [x4]
- /* Clear previous CPU release address */
- ldr x4, =CPU_RELEASE_ADDR
- str wzr, [x4]
- /* Master CPU (CPU0) request for warm reset */
- mrs x1, rmr_el3
- orr x1, x1, #0x02
- msr rmr_el3, x1
- isb
- dsb sy
+put_cpu_in_wfi:
- wfi
- b put_cpu_in_wfi
+skipwarmreset: +#endif
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
- /*
* In ATF flow, need to clear the old CPU address when cold reset* being triggered, but shouldn't clear CPU address if it is reset* by CPU-ON, so that the core can correctly jump to ATF code after* reset by CPU-ON. CPU-ON trigger the reset via mpumodrst.** Hardware will set 1 to core*_irq in mpurststat register in* reset manager if the core is reset by mpumodrst.** The following code will check the mpurststat to identify if the* core is reset by mpumodrst, and it will skip CPU address clearing* if the core is reset by mpumodrst. At last, the code need to clear* the core*_irq by set it to 1. So that it can reflect the correct* and latest status in next reset.*/- /* Check if it is a master core off/on from kernel using boot scratch
* cold register 8 bit 19. This bit is set by ATF.*/- ldr x4, =BOOT_SCRATCH_COLD8
- ldr x5, [x4]
- and x6, x5, #0x80000
- cbnz x6, wait_for_atf_master
- /* Retrieve mpurststat register in reset manager */
- ldr x4, =SOCFPGA_RSTMGR_ADDRESS
- ldr w5, [x4, #0x04]
- /* Set mask based on current core id */
- mrs x0, mpidr_el1
- and x1, x0, #0xF
- ldr x2, =0x00000100
- lsl x2, x2, x1
- /* Skip if core*_irq register is set */
- and x6, x5, x2
- cbnz x6, skip_clear_cpu_address
- /*
* Reach here means core*_irq is 0, means the core is* reset by cold, warm or watchdog reset.* Clear previous CPU release address*/- ldr x4, =CPU_RELEASE_ADDR
- str wzr, [x4]
- b skip_clear_core_irq
+skip_clear_cpu_address:
- /* Clear core*_irq register by writing 1 */
- ldr x4, =SOCFPGA_RSTMGR_ADDRESS
- str w2, [x4, #0x04]
+skip_clear_core_irq:
- /* Master CPU (CPU0) does not need to wait for atf */
- branch_if_master x0, master_cpu
wait_for_atf: ldr x4, =CPU_RELEASE_ADDR ldr x5, [x4] @@ -21,6 +111,16 @@ wait_for_atf: br x5 slave_wait_atf: branch_if_slave x0, wait_for_atf
+wait_for_atf_master:
- ldr x4, =CPU_RELEASE_ADDR
- ldr x5, [x4]
- cbz x5, master_wait_atf
- br x5
+master_wait_atf:
- branch_if_master x0, wait_for_atf_master
+master_cpu: #else branch_if_slave x0, 1f #endif @@ -52,6 +152,18 @@ slave_wait_atf: bl gic_wait_for_interrupt #endif
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_ATF)
- /*
* Read the u-boot's PSCI exception handler's vector base* address from the sysmgr.boot_scratch_cold6 & 7 and update* their VBAR_EL3 respectively.*/+wait_vbar_el3:
- ldr x4, =VBAR_EL3_BASE_ADDR
- ldr x5, [x4]
- cbz x5, wait_vbar_el3
- msr vbar_el3, x5
+#endif /* * All slaves will enter EL2 and optionally EL1. */ @@ -71,6 +183,55 @@ lowlevel_in_el1: #endif /* CONFIG_ARMV8_MULTIENTRY */
2: +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI)
- /*
* Write the u-boot PSCI exception handler's vector base address* into a sysmgr.boot_scratch_cold6 & 7 so that other slave cpus* are able to get the vector base address and update their VBAR_EL3* respectively.*/- adr x0, _el3_exception_vectors
- ldr x5, [x0]
- ldr x4, =VBAR_EL3_BASE_ADDR
- str x5, [x4]
+#endif
+#ifdef CONFIG_SPL_BUILD
- branch_if_slave x0, 3f
- /* Check rstmgr.stat for warm reset status */
- ldr x1, =SOCFPGA_RSTMGR_ADDRESS
- ldr x0, [x1]
- /* Check whether any L4 watchdogs or MPUs had triggered warm
reset */
- ldr x2, =0x000F0F00
- ands x0, x0, x2
- /*
* If current Reset Manager's status is warm reset just reload the* .data section by copying the data from data preserve section.* Otherwise, copy the .data section to the data preserve section to* keep an original copy of .data section. This ensure SPL is* reentrant after warm reset.*/- b.ne reload_data_section
- /* Copy from .data to preserved .data to backup the SPL state */
- ldr x0, =__data_start
- ldr x1, =__preserve_data_start
- ldr x2, =__preserve_data_end
- b copy_loop
+reload_data_section:
- /* Copy from preserved .data to .data to restore the SPL state */
- ldr x0, =__preserve_data_start
- ldr x1, =__data_start
- ldr x2, =__data_end
+copy_loop:
- ldr w3, [x0]
- add x0, x0, #4
- str w3, [x1]
- add x1, x1, #4
- cmp x1, x2
- b.ne copy_loop
+3: +#endif mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach- socfpga/mailbox_s10.c index 101af23855..7846596c17 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -7,7 +7,9 @@ #include <common.h> #include <asm/arch/clock_manager.h> #include <asm/arch/mailbox_s10.h> +#include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> +#include <asm/arch/timer.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/secure.h> @@ -454,6 +456,14 @@ static __always_inline int mbox_get_fpga_config_status_common(u32 cmd) return MBOX_CFGSTAT_STATE_CONFIG; }
+#ifdef CONFIG_ARMV8_PSCI +int __secure mbox_hps_stage_notify_psci(u32 execution_stage) +{
- return mbox_send_cmd_psci(MBOX_ID_UBOOT,
MBOX_HPS_STAGE_NOTIFY,
MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0,NULL); +} +#endif
int mbox_get_fpga_config_status(u32 cmd) { return mbox_get_fpga_config_status_common(cmd); @@ -479,6 +489,17 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, urgent, resp_buf_len, resp_buf); }
+int mbox_hps_stage_notify(u32 execution_stage) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
- return smc_send_mailbox(MBOX_HPS_STAGE_NOTIFY, 1,
&execution_stage,
0, 0, NULL);+#else
- return mbox_send_cmd(MBOX_ID_UBOOT,
MBOX_HPS_STAGE_NOTIFY,
MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0,NULL); +#endif +}
int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) { return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 5b5a81a255..024b714ecb 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /*
- Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
*/
- Copyright (C) 2012-2023 Altera Corporation <www.altera.com>
#include <common.h> @@ -34,7 +34,7 @@ phys_addr_t socfpga_sysmgr_base __section(".data");
#ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 =
- (struct pl310_regs *)CFG_SYS_PL310_BASE;
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
#endif
struct bsel bsel_str[] = { @@ -164,7 +164,10 @@ int arch_cpu_init(void) * timeout value is still active which might too short for Linux * booting. */ +#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || \ +IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)) hw_watchdog_init(); +#endif #else /* * If the HW watchdog is NOT enabled, make sure it is not running, @@ -208,10 +211,11 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, }
U_BOOT_CMD(bridge, 3, 1, do_bridge,
"SoCFPGA HPS FPGA bridge control","enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
"bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS,LWHPS-to-FPGA bridges\n"
""
- "SoCFPGA HPS FPGA bridge control",
- "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1),
FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges \n"
- "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA
(Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges\n"
- "Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10\n"
- ""
);
#endif @@ -257,6 +261,9 @@ void socfpga_get_managers_addr(void) #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) ret = socfpga_get_base_addr("intel,n5x-clkmgr", &socfpga_clkmgr_base); +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
- ret = socfpga_get_base_addr("intel,agilex5-clkmgr",
&socfpga_clkmgr_base);#else ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); #endif diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach- socfpga/misc_soc64.c index 2acdfad07b..7dd6f834e1 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /*
- Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
@@ -18,8 +18,12 @@ #include <log.h> #include <mach/clock_manager.h>
+#define RSU_DEFAULT_LOG_LEVEL 7
DECLARE_GLOBAL_DATA_PTR;
+u8 socfpga_get_board_id(void);
/*
- FPGA programming support for SoC FPGA Stratix 10
*/ @@ -47,8 +51,11 @@ static Altera_desc altera_fpga[] = { #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
- puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-
A55/A76)\n"); +#else puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex- A53)\n");
+#endif return 0; } #endif @@ -56,11 +63,26 @@ int print_cpuinfo(void) #ifdef CONFIG_ARCH_MISC_INIT int arch_misc_init(void) { +#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || \ +IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)) char qspi_string[13];
char level[4];
char id[3];
snprintf(level, sizeof(level), "%u", RSU_DEFAULT_LOG_LEVEL);
sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); env_set("qspi_clock", qspi_string);
/* for RSU, set log level to default if log level is not set */
if (!env_get("rsu_log_level"))
env_set("rsu_log_level", level);/* Export board_id as environment variable */
sprintf(id, "%u", socfpga_get_board_id());
env_set("board_id", id);
+#endif
- return 0;
} #endif @@ -87,5 +109,10 @@ void do_bridge_reset(int enable, unsigned int mask) return; }
- socfpga_bridges_reset(enable);
- socfpga_bridges_reset(enable, mask);
+}
+void arch_preboot_os(void) +{
- mbox_hps_stage_notify(HPS_EXECUTION_STATE_OS);
} diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach- socfpga/mmu-arm64_s10.c index a55b7b7cf3..0951233cad 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /*
- Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
@@ -10,6 +10,46 @@
DECLARE_GLOBAL_DATA_PTR;
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +static struct mm_region socfpga_agilex5_mem_map[] = {
- {
/* OCRAM 1MB but available 256KB */.virt = 0x00000000UL,.phys = 0x00000000UL,.size = 0x00040000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_INNER_SHARE,- }, {
/* DEVICE */.virt = 0x10808000UL,.phys = 0x10808000UL,.size = 0x0F7F8000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN | PTE_BLOCK_UXN,- }, {
/* FPGA 1.5GB */.virt = 0x20000000UL,.phys = 0x20000000UL,.size = 0x60000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN | PTE_BLOCK_UXN,- }, {
/* MEM 2GB */.virt = 0x80000000UL,.phys = 0x80000000UL,.size = 0x80000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_INNER_SHARE,- }, {
/* List terminator */- },
+};
+struct mm_region *mem_map = socfpga_agilex5_mem_map;
+#else static struct mm_region socfpga_stratix10_mem_map[] = { { /* MEM 2GB*/ @@ -70,3 +110,4 @@ static struct mm_region socfpga_stratix10_mem_map[] = { };
struct mm_region *mem_map = socfpga_stratix10_mem_map; +#endif diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach- socfpga/reset_manager_s10.c index f47fec10a0..1bf6a74648 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -1,22 +1,58 @@ // SPDX-License-Identifier: GPL-2.0 /*
- Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
#include <common.h> +#include <errno.h> #include <hang.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/secure.h> #include <asm/arch/reset_manager.h> #include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> +#include <asm/arch/timer.h> #include <dt-bindings/reset/altr,rst-mgr-s10.h> +#include <exports.h> #include <linux/iopoll.h> #include <linux/intel-smc.h>
DECLARE_GLOBAL_DATA_PTR;
+#define TIMEOUT_300MS 300
+/* F2S manager registers */ +#define F2SDRAM_SIDEBAND_FLAGINSTATUS0 0x14 +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54
+static __always_inline int wait_for_bit(u32 *reg, const u32 mask, bool set,
unsigned int timeout_ms)+{
- u32 val;
- int timeout = timeout_ms;
- while (1) {
val = readl(reg);if (!set)val = ~val;if ((val & mask) == mask)return 0;if (!timeout)break;timeout--;__socfpga_udelay(1000);- }
- return -ETIMEDOUT;
+}
/* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) { @@ -57,66 +93,221 @@ void socfpga_per_reset_all(void) writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); }
-void socfpga_bridges_reset(int enable) +static __always_inline void socfpga_f2s_bridges_reset(int enable,
unsigned int mask){ -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
- u64 arg = enable;
- int ret;
- u32 brg_mask;
- u32 flagout_idlereq = 0;
- u32 flagoutset_fdrain = 0;
- u32 flagoutset_en = 0;
- u32 flaginstatus_idleack = 0;
- u32 flaginstatus_respempty = 0;
- if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) {
/* Support fpga2soc and f2sdram */brg_mask = mask &(RSTMGR_BRGMODRST_FPGA2SOC_MASK |
RSTMGR_BRGMODRST_F2SDRAM0_MASK|
RSTMGR_BRGMODRST_F2SDRAM1_MASK|
RSTMGR_BRGMODRST_F2SDRAM2_MASK);if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM0_MASK) {flagout_idlereq |= BIT(0);flaginstatus_idleack |= BIT(1);flagoutset_fdrain |= BIT(2);flagoutset_en |= BIT(1);flaginstatus_respempty |= BIT(3);}if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM1_MASK) {flagout_idlereq |= BIT(3);flaginstatus_idleack |= BIT(5);flagoutset_fdrain |= BIT(5);flagoutset_en |= BIT(4);flaginstatus_respempty |= BIT(7);}
- int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1,
NULL, 0);
- if (ret) {
printf("SMC call failed with error %d in %s.\n", ret, __func__);
if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM2_MASK) {flagout_idlereq |= BIT(6);flaginstatus_idleack |= BIT(9);flagoutset_fdrain |= BIT(8);flagoutset_en |= BIT(7);flaginstatus_respempty |= BIT(11);}- } else {
/* Support fpga2soc only */brg_mask = mask &RSTMGR_BRGMODRST_FPGA2SOC_MASK;
if (brg_mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK) {flagout_idlereq |= BIT(0);flaginstatus_idleack |= BIT(1);flagoutset_fdrain |= BIT(2);flagoutset_en |= BIT(1);flaginstatus_respempty |= BIT(3);}- }
- /* mask is not set, return here */
- if (!brg_mask) return;
- if (enable) {
clrbits_le32(socfpga_get_rstmgr_addr() +RSTMGR_SOC64_BRGMODRST,
brg_mask);setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +F2SDRAM_SIDEBAND_FLAGOUTCLR0,flagout_idlereq);/* Wait for mpfe noc idleack to 0 */wait_for_bit((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS +F2SDRAM_SIDEBAND_FLAGINSTATUS0),flaginstatus_idleack, false, TIMEOUT_300MS);setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +F2SDRAM_SIDEBAND_FLAGOUTCLR0,flagoutset_fdrain);setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +F2SDRAM_SIDEBAND_FLAGOUTSET0,flagoutset_en);
__socfpga_udelay(1); /* wait 1us */- } else {
if (readl((socfpga_get_rstmgr_addr() +RSTMGR_SOC64_BRGMODRST) & brg_mask)) {/* Bridge cannot be reset twice */return;}setbits_le32(socfpga_get_rstmgr_addr() +RSTMGR_SOC64_HDSKEN,
RSTMGR_HDSKEN_FPGAHSEN);setbits_le32(socfpga_get_rstmgr_addr() +RSTMGR_SOC64_HDSKREQ,
RSTMGR_HDSKREQ_FPGAHSREQ);/* Wait for FPGA ack the handshake request to 1 */wait_for_bit((u32 *)(socfpga_get_rstmgr_addr() +RSTMGR_SOC64_HDSKACK),RSTMGR_HDSKREQ_FPGAHSREQ,
true, TIMEOUT_300MS);setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +F2SDRAM_SIDEBAND_FLAGOUTCLR0,flagoutset_en);
__socfpga_udelay(1);/* Requests MPFE NoC to idle */setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +F2SDRAM_SIDEBAND_FLAGOUTSET0,flagout_idlereq);
/* Force F2S bridge to drain */setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +F2SDRAM_SIDEBAND_FLAGOUTSET0,flagoutset_fdrain);
/* Wait for respond queue empty status to 1 (resp idle) */ret = wait_for_bit((u32*)(SOCFPGA_F2SDRAM_MGR_ADDRESS +
F2SDRAM_SIDEBAND_FLAGINSTATUS0),
flaginstatus_respempty, true,TIMEOUT_300MS);/* Confirm again */if (!ret)ret = wait_for_bit((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS +
F2SDRAM_SIDEBAND_FLAGINSTATUS0),
flaginstatus_respempty, true,TIMEOUT_300MS);setbits_le32(socfpga_get_rstmgr_addr() +RSTMGR_SOC64_BRGMODRST,
brg_mask &~RSTMGR_BRGMODRST_FPGA2SOC_MASK);
clrbits_le32(socfpga_get_rstmgr_addr() +RSTMGR_SOC64_HDSKREQ,
RSTMGR_HDSKREQ_FPGAHSREQ);setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +F2SDRAM_SIDEBAND_FLAGOUTCLR0,flagout_idlereq);- }
+}
+static __always_inline void socfpga_s2f_bridges_reset(int enable,
unsigned int mask)+{
- unsigned int noc_mask = 0;
- unsigned int brg_mask = 0;
- if (mask & RSTMGR_BRGMODRST_SOC2FPGA_MASK) {
noc_mask = SYSMGR_NOC_H2F_MSK;brg_mask = RSTMGR_BRGMODRST_SOC2FPGA_MASK;-#else
- u32 reg;
if (mask & RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) {
noc_mask |= SYSMGR_NOC_LWH2F_MSK;brg_mask |= RSTMGR_BRGMODRST_LWSOC2FPGA_MASK;}
/* s2f mask is not set, return here */
if (!brg_mask)
return;if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
SYSMGR_SOC64_NOC_IDLEREQ_CLR, noc_mask);
/* Release all bridges from reset state */
/* Release SOC2FPGA bridges from reset state */RSTMGR_SOC64_BRGMODRST,
~0);
brg_mask);
/* Poll until all idleack to 0 */read_poll_timeout(readl, reg, !reg, 1000, 300000,socfpga_get_sysmgr_addr() +SYSMGR_SOC64_NOC_IDLEACK);
/* Wait for all NOC master ack to 0 */wait_for_bit((u32 *)(socfpga_get_sysmgr_addr() +SYSMGR_SOC64_NOC_IDLEACK), noc_mask, false,TIMEOUT_300MS);
writel(~0,socfpga_get_sysmgr_addr() +SYSMGR_SOC64_NOC_IDLEREQ_SET);
setbits_le32(socfpga_get_sysmgr_addr() +SYSMGR_SOC64_NOC_IDLEREQ_SET, noc_mask);/* Enable the NOC timeout */ writel(1, socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_TIMEOUT);
/* Poll until all idleack to 1 */read_poll_timeout(readl, reg,reg == (SYSMGR_NOC_H2F_MSK |SYSMGR_NOC_LWH2F_MSK),1000, 300000,socfpga_get_sysmgr_addr() +SYSMGR_SOC64_NOC_IDLEACK);/* Poll until all idlestatus to 1 */read_poll_timeout(readl, reg,reg == (SYSMGR_NOC_H2F_MSK |SYSMGR_NOC_LWH2F_MSK),1000, 300000,socfpga_get_sysmgr_addr() +SYSMGR_SOC64_NOC_IDLESTATUS);/* Reset all bridges (except NOR DDR scheduler & F2S) */
/* Wait for all NOC master ack to 1 */wait_for_bit((u32 *)(socfpga_get_sysmgr_addr() +SYSMGR_SOC64_NOC_IDLEACK), noc_mask, true,TIMEOUT_300MS);/* Wait for all NOC master idlestatus to 1 */wait_for_bit((u32 *)(socfpga_get_sysmgr_addr() +SYSMGR_SOC64_NOC_IDLESTATUS), noc_mask,true,
TIMEOUT_300MS);/* Reset all SOC2FPGA bridges */RSTMGR_SOC64_BRGMODRST,
~(RSTMGR_BRGMODRST_DDRSCH_MASK |RSTMGR_BRGMODRST_FPGA2SOC_MASK));
brg_mask);/* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_TIMEOUT); } -#endif +}
+void socfpga_bridges_reset(int enable, unsigned int mask) +{
- if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
IS_ENABLED(CONFIG_SPL_ATF)) {
u64 arg[2];int ret;/* Set bit-1 to indicate has mask value in arg[1]. */arg[0] = (enable & BIT(0)) | BIT(1);arg[1] = mask;ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, arg,ARRAY_SIZE(arg), NULL, 0);if (ret)printf("Failed to %s the HPS bridges, error %d\n",enable ? "enable" : "disable", ret);- } else {
socfpga_s2f_bridges_reset(enable, mask);socfpga_f2s_bridges_reset(enable, mask);- }
+}
+void __secure socfpga_bridges_reset_psci(int enable, unsigned int mask) +{
- socfpga_s2f_bridges_reset(enable, mask);
- socfpga_f2s_bridges_reset(enable, mask);
}
/* @@ -125,7 +316,7 @@ void socfpga_bridges_reset(int enable) int cpu_has_been_warmreset(void) { return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
RSTMGR_L4WD_MPU_WARMRESET_MASK;
(RSTMGR_L4WD_MPU_WARMRESET_MASK);}
void print_reset_info(void) diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach- socfpga/secure_reg_helper.c index 0d4f45f33d..23595d242a 100644 --- a/arch/arm/mach-socfpga/secure_reg_helper.c +++ b/arch/arm/mach-socfpga/secure_reg_helper.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /*
- Copyright (C) 2020 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
@@ -18,9 +18,11 @@ int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t *reg_addr) { switch (id) { +#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC: *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC; break; +#endif case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0: *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0; break; diff --git a/arch/arm/mach-socfpga/smmu_agilex5.c b/arch/arm/mach- socfpga/smmu_agilex5.c new file mode 100644 index 0000000000..05e74926aa --- /dev/null +++ b/arch/arm/mach-socfpga/smmu_agilex5.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 Intel Corporation. All rights reserved
- */
+#include <common.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/firewall.h> +#include <asm/arch/smmu_agilex5.h> +#include <asm/arch/system_manager.h>
+DECLARE_GLOBAL_DATA_PTR;
+static inline void setup_smmu_firewall(void) +{
- u32 i;
- /* Off the DDR secure transaction for all TBU supported peripherals
*/
- for (i = SYSMGR_DMA0_SID_ADDR; i < SYSMGR_TSN2_SID_ADDR; i
+=
SOCFPGA_NEXT_TBU_PERIPHERAL) {/* skip this, future use register */if (i == SYSMGR_USB3_SID_ADDR)continue;writel(SECURE_TRANS_RESET, (uintptr_t)i);- }
+}
+void socfpga_init_smmu(void) +{
- setup_smmu_firewall();
+} diff --git a/arch/arm/mach-socfpga/smmu_s10.c b/arch/arm/mach- socfpga/smmu_s10.c new file mode 100644 index 0000000000..106834cc9a --- /dev/null +++ b/arch/arm/mach-socfpga/smmu_s10.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2018-2023 Intel Corporation <www.intel.com>
- */
+#include <common.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/firewall.h> +#include <asm/arch/smmu_s10.h> +#include <asm/arch/system_manager.h>
+DECLARE_GLOBAL_DATA_PTR;
+static const struct smmu_stream_id dev_stream_id[] = {
- {SYSMGR_EMAC0_SID_ADDR, 0x01, EMAC_W_OFST,
EMAC_R_OFST},
- {SYSMGR_EMAC1_SID_ADDR, 0x02, EMAC_W_OFST,
EMAC_R_OFST},
- {SYSMGR_EMAC2_SID_ADDR, 0x03, EMAC_W_OFST,
EMAC_R_OFST},
- {SYSMGR_NAND_SID_ADDR, 0x04, NAND_W_OFST, NAND_R_OFST},
- {SYSMGR_SDMMC_SID_ADDR, 0x05, SDMMC_OFST, SDMMC_OFST},
- {SYSMGR_USB0_SID_ADDR, 0x06, USB_OFST, USB_OFST},
- {SYSMGR_USB1_SID_ADDR, 0x07, USB_OFST, USB_OFST},
- {SYSMGR_DMA_SID_ADDR, 0x08, DMA_W_OFST, DMA_R_OFST},
- {SYSMGR_ETR_SID_ADDR, 0x09, ETR_W_OFST, ETR_R_OFST},
+};
+static void set_smmu_streamid(void) +{
- int i;
- for (i = 0; i < ARRAY_SIZE(dev_stream_id); i++) {
u32 mask = SMMU_SET_STREAMID(0x3FF,dev_stream_id[i].r_bit_ofst,dev_stream_id[i].w_bit_ofst);u32 value = SMMU_SET_STREAMID(dev_stream_id[i].sid,dev_stream_id[i].r_bit_ofst,dev_stream_id[i].w_bit_ofst);clrbits_le32(dev_stream_id[i].addr, mask);setbits_le32(dev_stream_id[i].addr, value);- }
+}
+/*
- Need to set the Secure bit (to make it non-secure) on each peripheral
- so that SMMU can access the peripheral
- */
+static void set_smmu_accessible_reg(void) +{
- setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0,
BIT(27) | BIT(25));- setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1,
BIT(27) | BIT(25));- setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2,
BIT(27) | BIT(25));- setbits_le32(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NANDGRP_L3MASTER,
BIT(21) | BIT(17));- setbits_le32(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_SDMMC_L3MASTER,
BIT(5));- setbits_le32(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_USB0_L3MASTER,
BIT(9));- setbits_le32(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_USB1_L3MASTER,
BIT(9));+}
+static inline void setup_smmu_firewall(void) +{
- /* Enable nonsecure SMMU accesses */
- writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
+}
+void socfpga_init_smmu(void) +{
- setup_smmu_firewall();
- set_smmu_streamid();
- set_smmu_accessible_reg();
+}
+int is_smmu_bypass(void) +{
- return readl(SOCFPGA_SMMU_ADDRESS + SMMU_SCR0) &
SMMU_SCR0_CLIENTPD; +}
+int is_smmu_stream_id_enabled(u32 stream_id) +{
- int i;
- u32 smrg_num;
- u32 smr, s2cr, sid_mask;
- u32 cb, cb_index, cb_num;
- if (is_smmu_bypass())
return 0;- /* Get number of Stream Mapping Register Groups */
- smrg_num = readl(SOCFPGA_SMMU_ADDRESS + SMMU_SIDR0) &
SMMU_SIDR0_NUMSMRG_MASK;- /* Get number of Context Bank */
- cb_num = readl(SOCFPGA_SMMU_ADDRESS + SMMU_SIDR1) &
SMMU_SIDR1_NUMCB_MASK;- for (i = 0; i < smrg_num; i++) {
smr = readl(SOCFPGA_SMMU_ADDRESS +SMMU_GR0_SMR((u64)i));
sid_mask = (smr & SMMU_SMR_MASK) >> 16;/* Skip if Stream ID is invalid or not matched */if (!(smr & SMMU_SMR_VALID) || (smr & sid_mask) !=stream_id)
continue;/* Get Context Bank index from valid matching Stream ID */s2cr = readl(SOCFPGA_SMMU_ADDRESS +SMMU_GR0_S2CR((u64)i));
cb_index = s2cr & SMMU_S2CR_CBNDX;/* Skip if Context Bank is invalid or not Translation mode */if (cb_index >= cb_num || (s2cr & SMMU_S2CR_TYPE))continue;cb = readl(SOCFPGA_SMMU_ADDRESS +SMMU_GR0_CB((u64)cb_index,
SMMU_CB_SCTLR));
/* Return MMU enable status for this Context Bank */return (cb & SMMU_CB_SCTLR_M);- }
- return 0;
+} diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach- socfpga/spl_agilex5.c new file mode 100644 index 0000000000..da91bf5917 --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019-2023 Intel Corporation <www.intel.com>
- */
+#include <init.h> +#include <log.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <common.h> +#include <hang.h> +#include <image.h> +#include <spl.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/smmu_s10.h> +#include <asm/arch/system_manager.h> +#include <wdt.h> +#include <dm/uclass.h>
+DECLARE_GLOBAL_DATA_PTR;
+#define USE_HARDCODED_HANDOFF
+#ifdef USE_HARDCODED_HANDOFF +static const u32 hardcoded_handoff_data[402] = { +0x544f4f42, 0x01000500, 0x00000000, 0x00000000, 0x58554d50, 0x90010000, +0x00000000, 0x00000000, 0x00000000, 0x03000000, 0x04000000, 0x03000000, +0x08000000, 0x03000000, 0x0c000000, 0x03000000, 0x10000000, 0x03000000, +0x14000000, 0x03000000, 0x18000000, 0x03000000, 0x1c000000, 0x03000000, +0x20000000, 0x03000000, 0x24000000, 0x03000000, 0x28000000, 0x03000000, +0x2c000000, 0x03000000, 0x30000000, 0x03000000, 0x34000000, 0x03000000, +0x38000000, 0x03000000, 0x3c000000, 0x03000000, 0x40000000, 0x00000000, +0x44000000, 0x00000000, 0x48000000, 0x00000000, 0x4c000000, 0x00000000, +0x50000000, 0x00000000, 0x54000000, 0x00000000, 0x58000000, 0x04000000, +0x5c000000, 0x04000000, 0x60000000, 0x08000000, 0x64000000, 0x08000000, +0x68000000, 0x05000000, 0x6c000000, 0x05000000, 0x70000000, 0x08000000, +0x74000000, 0x08000000, 0x78000000, 0x04000000, 0x7c000000, 0x04000000, +0x80000000, 0x07000000, 0x84000000, 0x07000000, 0x88000000, 0x07000000, +0x8c000000, 0x07000000, 0x90000000, 0x01000000, 0x94000000, 0x01000000, +0x98000000, 0x01000000, 0x9c000000, 0x01000000, 0x00010000, 0x01000000, +0x04010000, 0x01000000, 0x08010000, 0x09000000, 0x0c010000, 0x08000000, +0x10010000, 0x08000000, 0x14010000, 0x08000000, 0x18010000, 0x05000000, +0x1c010000, 0x05000000, 0x54434f49, 0x90010000, 0x00000000, 0x00000000, +0x00000000, 0x34000000, 0x04000000, 0x14000000, 0x08000000, 0x34000000, +0x0c000000, 0x34000000, 0x10000000, 0x34000000, 0x14000000, 0x34000000, +0x18000000, 0x34000000, 0x1c000000, 0x34000000, 0x20000000, 0x34000000, +0x24000000, 0x34000000, 0x28000000, 0x34000000, 0x2c000000, 0x34000000, +0x30000000, 0x16000000, 0x34000000, 0x14000000, 0x38000000, 0x34000000, +0x3c000000, 0x34000000, 0x40000000, 0x14000000, 0x44000000, 0x14000000, +0x48000000, 0x34000000, 0x4c000000, 0x34000000, 0x50000000, 0x14000000, +0x54000000, 0x14000000, 0x58000000, 0x34000000, 0x5c000000, 0x34000000, +0x60000000, 0x35000000, 0x64000000, 0x35000000, 0x68000000, 0x16000000, +0x6c000000, 0x34000000, 0xd0000000, 0x35000000, 0xd4000000, 0x35000000, +0xd8000000, 0x3e000000, 0xdc000000, 0x3e000000, 0xe0000000, 0x34000000, +0xe4000000, 0x34000000, 0xe8000000, 0x16000000, 0xec000000, 0x34000000, +0xf0000000, 0x34000000, 0xf4000000, 0x34000000, 0xf8000000, 0x14000000, +0xfc000000, 0x34000000, 0x00010000, 0x34000000, 0x04010000, 0x34000000, +0x08010000, 0x34000000, 0x0c010000, 0x35000000, 0x10010000, 0x35000000, +0x14010000, 0x35000000, 0x18010000, 0x3e000000, 0x1c010000, 0x16000000, +0x41475046, 0xc0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x04000000, 0x00000000, 0x08000000, 0x00000000, 0x0c000000, 0x00000000, +0x10000000, 0x00000000, 0x14000000, 0x00000000, 0x18000000, 0x00000000, +0x1c000000, 0x00000000, 0x20000000, 0x00000000, 0x28000000, 0x00000000, +0x2c000000, 0x00000000, 0x30000000, 0x00000000, 0x34000000, 0x00000000, +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU) +0x38000000, 0x01000000, 0x3c000000, 0x00000000, 0x40000000, 0x00000000, +#else +0x38000000, 0x00000000, 0x3c000000, 0x00000000, 0x40000000, 0x00000000, +#endif +0x44000000, 0x00000000, 0x48000000, 0x00000000, 0x50000000, 0x00000000, +0x54000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x59414c44, 0x90010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x04000000, 0x00000000, 0x08000000, 0x00000000, 0x0c000000, 0x00000000, +0x10000000, 0x00000000, 0x14000000, 0x00000000, 0x18000000, 0x00000000, +0x1c000000, 0x00000000, 0x20000000, 0x00000000, 0x24000000, 0x00000000, +0x28000000, 0x00000000, 0x2c000000, 0x00000000, 0x30000000, 0x00110000, +0x34000000, 0x00000000, 0x38000000, 0x00000000, 0x3c000000, 0x00000000, +0x40000000, 0x00000000, 0x44000000, 0x00000000, 0x48000000, 0x00000000, +0x4c000000, 0x00000000, 0x50000000, 0x00000000, 0x54000000, 0x00000000, +0x58000000, 0x00000000, 0x5c000000, 0x00000000, 0x60000000, 0x00000000, +0x64000000, 0x00000000, 0x68000000, 0x00000000, 0x6c000000, 0x00000000, +0x70000000, 0x00000000, 0x74000000, 0x00000000, 0x78000000, 0x00000000, +0x7c000000, 0x00000000, 0x80000000, 0x00000000, 0x84000000, 0x00000000, +0x88000000, 0x00000000, 0x8c000000, 0x00000000, 0x90000000, 0x00000000, +0x94000000, 0x00000000, 0x98000000, 0x00000000, 0x9c000000, 0x00000000, +0xa0000000, 0x00000000, 0xa4000000, 0x00000000, 0xa8000000, 0x00000000, +0xac000000, 0x00000000, 0xb0000000, 0x00000000, 0xb4000000, 0x00000000, +0xb8000000, 0x00000000, 0xbC000000, 0x00000000, 0x534b4c43, 0xA0000000, +0x00000000, 0x00000000, 0x00000000, 0x98002618, 0x03010016, 0x00000000, +0x02000008, 0x04000008, 0x03000008, 0x09000008, 0x90000000, 0x00000000, +0x01000000, 0x03010015, 0x00000000, 0x02000008, 0x03000008, 0x7d000008, +0x06000008, 0x78000000, 0x01000100, 0x09000000, 0x00000100, 0x01000000, +0x00000100, 0x00000100, 0x00000100, 0x13000000, 0x01000000, 0x00000100, +0x00000000, 0x00000000, 0x00000000, 0x40787d01, 0x40787d01, 0x00000000, +0x00000000, 0x00000000, 0x49524550, 0x14000000, 0x00000000, 0x00000000, +0x40000000, 0x4d524453, 0x14000000, 0x00000000, 0x00000000, 0x00000000 +}; +#endif
You should not hardcoded handoff here, it should be generated based on user inputs and designs in the platform designer.
+#define HARDCODED_HANDOFF_DATA_SIZE (sizeof(hardcoded_handoff_data) / sizeof(u32))
+void board_init_f(ulong dummy) +{
- int ret;
- struct udevice *dev;
- ret = spl_early_init();
- if (ret)
hang();- socfpga_get_managers_addr();
+#ifdef USE_HARDCODED_HANDOFF
- /* Write hardcoded handoff value into OCRAM handoff area */
- u32 i;
- for (i = 0; i < HARDCODED_HANDOFF_DATA_SIZE; i++)
writel(hardcoded_handoff_data[i],(u32 *)SOC64_HANDOFF_BASE + i);+#endif
- sysmgr_pinmux_init();
- if (!(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) ||
IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU))) {/* Ensure watchdog is paused when debugging is happening*/
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);- }
- timer_init();
- ret = uclass_get_device(UCLASS_CLK, 0, &dev);
- if (ret) {
debug("Clock init failed: %d\n", ret);hang();- }
- if (!(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) ||
IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU))) {/** Enable watchdog as early as possible before initializingother
* component. Watchdog need to be enabled after clockdriver because
* it will retrieve the clock frequency from clock driver.*/if (CONFIG_IS_ENABLED(WDT))initr_watchdog();- }
- preloader_console_init();
- print_reset_info();
- cm_print_clock_quick_summary();
- ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-secreg",
&dev);
- if (ret) {
printf("Firewall & secure settings init failed: %d\n", ret);hang();- }
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
debug("DRAM init failed: %d\n", ret);hang();- }
+#endif
- mbox_init();
+#ifdef CONFIG_CADENCE_QSPI
- mbox_qspi_open();
+#endif +} diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach- socfpga/spl_soc64.c index ba6efc1d86..a4ac906ffd 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -1,25 +1,203 @@ // SPDX-License-Identifier: GPL-2.0 /*
- Copyright (C) 2020 Intel Corporation. All rights reserved
*/
- Copyright (C) 2020-2022 Intel Corporation. All rights reserved
+#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> #include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/ofnode.h> +#include <image.h> +#include <log.h> #include <spl.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/smmu_s10.h> +#include <watchdog.h> +#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void) {
- int ret, size;
- ofnode node;
- const fdt32_t *phandle_p;
- u32 phandle;
- struct udevice *dev;
- node = ofnode_path("/chosen");
- if (!ofnode_valid(node)) {
debug("%s: /chosen node was not found.\n", __func__);goto fallback;- }
- phandle_p = ofnode_get_property(node, "u-boot,boot0", &size);
- if (!phandle_p) {
debug("%s: u-boot,boot0 property was not found.\n",__func__);goto fallback;- }
- phandle = fdt32_to_cpu(*phandle_p);
- node = ofnode_get_by_phandle(phandle);
- ret = device_get_global_by_ofnode(node, &dev);
- if (ret) {
debug("%s: Boot device at not found, error: %d\n",__func__,
ret);goto fallback;- }
- debug("%s: Found boot device %s\n", __func__, dev->name);
- switch (device_get_uclass_id(dev)) {
- case UCLASS_SPI_FLASH:
return BOOT_DEVICE_SPI;- case UCLASS_MTD:
return BOOT_DEVICE_NAND;- case UCLASS_MMC:
return BOOT_DEVICE_MMC1;- default:
debug("%s: Booting from device uclass '%s' is notsupported\n",
__func__, dev_get_uclass_name(dev));- }
+fallback:
- /* Return default boot device */ return BOOT_DEVICE_MMC1;
}
#if IS_ENABLED(CONFIG_SPL_MMC) u32 spl_boot_mode(const u32 boot_device) {
- if (IS_ENABLED(CONFIG_SPL_FS_FAT) ||
IS_ENABLED(CONFIG_SPL_FS_EXT4))
return MMCSD_MODE_FS;- else
return MMCSD_MODE_RAW;+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- return MMCSD_MODE_FS;
+#else
- return MMCSD_MODE_RAW;
+#endif } #endif
+/* board specific function prior loading SSBL / U-Boot */ +void spl_perform_fixups(struct spl_image_info *spl_image) +{
- /* Setup and Initialize SMMU */
- socfpga_init_smmu();
+#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) || \ +IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU))
- mbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
+#endif +}
+/* This function is to map specified node onto SPL boot devices */ +static int spl_node_to_boot_device(int node) +{
- const void *blob = gd->fdt_blob;
- struct udevice *parent;
- const char *prop;
- if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent))
return BOOT_DEVICE_MMC1;- else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
&parent))
return BOOT_DEVICE_SPI;- else if (!uclass_get_device_by_of_offset(UCLASS_MTD, node,
&parent))
return BOOT_DEVICE_NAND;- prop = fdt_getprop(blob, node, "device_type", NULL);
- if (prop) {
if (!strcmp(prop, "memory"))return BOOT_DEVICE_RAM;printf("%s: unknown device_type %s\n", __func__, prop);- }
- return -1;
+}
+static void default_spl_boot_list(u32 *spl_boot_list, int length) +{
- spl_boot_list[0] = BOOT_DEVICE_MMC1;
- if (length > 1)
spl_boot_list[1] = BOOT_DEVICE_SPI;- if (length > 2)
spl_boot_list[2] = BOOT_DEVICE_NAND;+}
+void board_boot_order(u32 *spl_boot_list) +{
- int idx = 0;
- const void *blob = gd->fdt_blob;
- int chosen_node = fdt_path_offset(blob, "/chosen");
- const char *conf;
- int elem;
- int boot_device;
- int node;
- int length;
- /* expect valid initialized spl_boot_list */
- if (!spl_boot_list)
return;- length = 1;
- while (spl_boot_list[length] == spl_boot_list[length - 1])
length++;- debug("%s: chosen_node is %d\n", __func__, chosen_node);
- if (chosen_node < 0) {
printf("%s: /chosen not found, using default\n", __func__);default_spl_boot_list(spl_boot_list, length);return;- }
- for (elem = 0;
(conf = fdt_stringlist_get(blob, chosen_node,"u-boot,spl-boot-order", elem, NULL));elem++) {if (idx >= length) {printf("%s: limit %d to spl_boot_list exceeded\n",__func__,
length);break;}/* Resolve conf item as a path in device tree */node = fdt_path_offset(blob, conf);if (node < 0) {debug("%s: could not find %s in FDT\n", __func__,conf);
continue;}/* Try to map spl node back onto SPL boot devices */boot_device = spl_node_to_boot_device(node);if (boot_device < 0) {debug("%s: could not map node @%x to a boot-device\n",
__func__, node);continue;}spl_boot_list[idx] = boot_device;debug("%s: spl_boot_list[%d] = %u\n", __func__, idx,spl_boot_list[idx]);idx++;- }
- if (idx == 0) {
if (!conf && !elem) {printf("%s: spl-boot-order invalid, using default\n",__func__);
default_spl_boot_list(spl_boot_list, length);} else {printf("%s: no valid element spl-boot-order list\n",__func__);
}- }
+} diff --git a/arch/arm/mach-socfpga/u-boot-spl-soc64.lds b/arch/arm/mach- socfpga/u-boot-spl-soc64.lds new file mode 100644 index 0000000000..8beef91d17 --- /dev/null +++ b/arch/arm/mach-socfpga/u-boot-spl-soc64.lds @@ -0,0 +1,93 @@ +/*
- (C) Copyright 2018
- Intel Corporation <www.intel.com>
- (C) Copyright 2013
- David Feng fenghua@phytium.com.cn
- (C) Copyright 2002
- Gary Jennejohn, DENX Software Engineering, garyj@denx.de
- (C) Copyright 2010
- Texas Instruments, <www.ti.com>
- Aneesh V aneesh@ti.com
- SPDX-License-Identifier: GPL-2.0
- */
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
LENGTH = CONFIG_SPL_MAX_SIZE }+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64- littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{
- .text : {
. = ALIGN(8);__image_copy_start = .;CPUDIR/start.o (.text*)*(.text*)- } >.sram
- .rodata : {
. = ALIGN(8);*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))- } >.sram
- .data : {
. = ALIGN(8);/* Run time .data section starting at this location */__data_start = .;*(.data*)/* Run time .data section ending at this location */__data_end = .;- } >.sram
- . = ALIGN(8);
- /* Preserve original .data section starting at this location */
- __preserve_data_start = .;
- . = __preserve_data_start + (__data_end - __data_start);
- /* Preserve original .data section ending at this location */
- __preserve_data_end = .;
- . = ALIGN(8);
- __u_boot_list . : {
KEEP(*(SORT(__u_boot_list*)));- } >.sram
- .image_copy_end : {
. = ALIGN(8);*(.__image_copy_end)- } >.sram
- .end : {
. = ALIGN(8);*(.__end)- } >.sram
- _image_binary_end = .;
- .bss_start (NOLOAD) : {
. = ALIGN(8);KEEP(*(.__bss_start));- } >.sdram
- .bss (NOLOAD) : {
*(.bss*). = ALIGN(8);- } >.sdram
- .bss_end (NOLOAD) : {
KEEP(*(.__bss_end));- } >.sdram
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+} diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index e7cb5ea89c..23434dbf6c 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /*
- Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
@@ -19,7 +19,12 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_MAGIC_FPGA: case SOC64_HANDOFF_MAGIC_DELAY: case SOC64_HANDOFF_MAGIC_CLOCK: +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
- case SOC64_HANDOFF_MAGIC_PERI:
- case SOC64_HANDOFF_MAGIC_SDRAM:
+#else case SOC64_HANDOFF_MAGIC_MISC: +#endif return BIG_ENDIAN; #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) case SOC64_HANDOFF_DDR_UMCTL2_MAGIC: -- 2.26.2
This is for new platform enablement for agilex5. Add platform related header files to enable new product.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- .../include/mach/base_addr_soc64.h | 43 +++++- .../mach-socfpga/include/mach/clock_manager.h | 5 +- .../include/mach/clock_manager_agilex5.h | 12 ++ arch/arm/mach-socfpga/include/mach/firewall.h | 42 +++++- .../mach-socfpga/include/mach/handoff_soc64.h | 25 +++- .../mach-socfpga/include/mach/mailbox_s10.h | 32 +++-- .../include/mach/reset_manager_soc64.h | 33 ++++- .../mach-socfpga/include/mach/smmu_agilex5.h | 30 +++++ arch/arm/mach-socfpga/include/mach/smmu_s10.h | 73 ++++++++++ .../include/mach/system_manager_soc64.h | 126 ++++++++++++++++-- arch/arm/mach-socfpga/include/mach/timer.h | 30 +++++ 11 files changed, 419 insertions(+), 32 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h create mode 100644 arch/arm/mach-socfpga/include/mach/smmu_agilex5.h create mode 100644 arch/arm/mach-socfpga/include/mach/smmu_s10.h
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 3f899fcfa3..4a88770638 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -1,21 +1,60 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2016-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2023 Intel Corporation <www.intel.com> */
#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ #define _SOCFPGA_SOC64_BASE_HARDWARE_H_
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOCFPGA_CCU_ADDRESS 0x1c000000 +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0x18001000 +#define SOCFPGA_SMMU_ADDRESS 0x16000000 +#define SOCFPGA_OCRAM_FIREWALL_ADDRESS 0x108cc400 +#define SOCFPGA_MAILBOX_ADDRESS 0x10a30000 +#define SOCFPGA_UART0_ADDRESS 0x10c02000 +#define SOCFPGA_UART1_ADDRESS 0x10c02100 +#define SOCFPGA_SPTIMER0_ADDRESS 0x10c03000 +#define SOCFPGA_SPTIMER1_ADDRESS 0x10c03100 +#define SOCFPGA_SYSTIMER0_ADDRESS 0x10d00000 +#define SOCFPGA_SYSTIMER1_ADDRESS 0x10d00100 +#define SOCFPGA_L4WD0_ADDRESS 0x10d00200 +#define SOCFPGA_L4WD1_ADDRESS 0x10d00300 +#define SOCFPGA_L4WD2_ADDRESS 0x10d00400 +#define SOCFPGA_L4WD3_ADDRESS 0x10d00500 +#define SOCFPGA_L4WD4_ADDRESS 0x10d00600 +#define SOCFPGA_GTIMER_SEC_ADDRESS 0x10d01000 +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0x10d02000 +#define SOCFPGA_CLKMGR_ADDRESS 0x10d10000 +#define SOCFPGA_RSTMGR_ADDRESS 0x10d11000 +#define SOCFPGA_SYSMGR_ADDRESS 0x10d12000 +#define SOCFPGA_OCRAM_ADDRESS 0x00000000 +#define SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS 0x18000800 +#define SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS 0x18000A00 +#define SOCFPGA_FW_TBU2NOC_ADDRESS 0x18000C00 +#define SOCFPGA_FIREWALL_L4_PER 0xffd21000 /* TODO */ +#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 /* TODO */ +#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 /* TODO */ +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 /* TODO */ +#define SOCFPGA_FIREWALL_TCU 0xffd21400 /* TODO */ +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0xffd24800 /* TODO */ +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 /* TODO */ +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 /* TODO */ +#define GICD_BASE 0x1d000000 +#define GICR_BASE 0x1d060000 +#else #define SOCFPGA_CCU_ADDRESS 0xf7000000 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_FW_MPFE_SCR_ADDRESS 0xf8020000 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #endif +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 @@ -39,10 +78,12 @@ #define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 #define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 #define SOCFPGA_FIREWALL_TCU 0xffd21400 +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0xffd24800 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 #define GICD_BASE 0xfffc1000 #define GICC_BASE 0xfffc2000 +#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */
#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index a8cb07a1c4..ef92536662 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2023 Altera Corporation <www.altera.com> */
#ifndef _CLOCK_MANAGER_H_ @@ -14,6 +14,7 @@ int cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void); unsigned long cm_get_mpu_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void);
#if defined(CONFIG_TARGET_SOCFPGA_SOC64) int cm_set_qspi_controller_clk_hz(u32 clk_hz); @@ -28,6 +29,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz); #include <asm/arch/clock_manager_s10.h> #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) #include <asm/arch/clock_manager_agilex.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX5) +#include <asm/arch/clock_manager_agilex5.h> #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #include <asm/arch/clock_manager_n5x.h> #endif diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h new file mode 100644 index 0000000000..cbad0fdec7 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + */ + +#ifndef _CLOCK_MANAGER_AGILEX5_ +#define _CLOCK_MANAGER_AGILEX5_ + +#include <asm/arch/clock_manager_soc64.h> +#include "../../../../../drivers/clk/altera/clk-agilex5.h" + +#endif /* _CLOCK_MANAGER_AGILEX5_ */ diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index 5cb7f23f8f..8dec4af0f3 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2023 Intel Corporation <www.intel.com> * */
@@ -75,6 +75,8 @@ struct socfpga_firwall_l4_sys { };
#define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16)) +#define FIREWALL_MPFE_SCR_DISABLE_ALL (BIT(0) | BIT(8) | BIT(16)) +#define FIREWALL_MPFE_SCR_DISABLE_MPU BIT(0) #define FIREWALL_BRIDGE_DISABLE_ALL (~0)
/* Cache coherency unit (CCU) registers */ @@ -104,6 +106,13 @@ struct socfpga_firwall_l4_sys { #define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0
+#define CCU_FPGA_MPRT_ADBASE_MEMSPACE0 0x105a0 +#define CCU_FPGA_MPRT_ADBASE_MEMSPACE1A 0x105c0 +#define CCU_FPGA_MPRT_ADBASE_MEMSPACE1B 0x105e0 +#define CCU_FPGA_MPRT_ADBASE_MEMSPACE1C 0x10600 +#define CCU_FPGA_MPRT_ADBASE_MEMSPACE1D 0x10620 +#define CCU_FPGA_MPRT_ADBASE_MEMSPACE1E 0x10640 + #define CCU_ADMASK_P_MASK BIT(0) #define CCU_ADMASK_NS_MASK BIT(1)
@@ -126,11 +135,42 @@ struct socfpga_firwall_l4_sys { #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff
+/* Firewall F2SDRAM DDR SCR registers */ +#define FW_F2SDRAM_DDR_SCR_EN 0x00 +#define FW_F2SDRAM_DDR_SCR_EN_SET 0x04 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE 0x10 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT 0x14 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT 0x18 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT 0x1c + +/* Firewall MPFE SCR Registers */ +#define FW_MPFE_SCR_HMC 0x00 +#define FW_MPFE_SCR_HMC_ADAPTOR 0x04 + #define MPUREGION0_ENABLE BIT(0) #define NONMPUREGION0_ENABLE BIT(8)
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define FW_MPU_DDR_SCR_WRITEL(data, reg) \ + writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \ + writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg)) +#define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg) \ + writel(data, SOCFPGA_FW_TBU2NOC_ADDRESS + (reg)) +#else #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg)) +#endif + +/* Secure Transaction Register */ +#define SECURE_TRANS_OFFS 0x190 +#define SECURE_TRANS_REG SOCFPGA_SYSMGR_ADDRESS +\ + SECURE_TRANS_OFFS +#define SECURE_TRANS_RESET 0x0 +#define SECURE_TRANS_SET 0x33 +#define OCRAM_SECURE_REGION1_OFFS 0x18 +#define OCRAM_SECURE_REGION1_REG SOCFPGA_OCRAM_FIREWALL_ADDRESS +\ + OCRAM_SECURE_REGION1_OFFS +#define NON_SECURE_ACCESS 0x0
void firewall_setup(void);
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 902fc6bfb5..27f545734f 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2023 Intel Corporation <www.intel.com> * */
@@ -17,7 +17,12 @@ #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_MAGIC_PERI 0x50455249 +#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d +#else #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 +#endif
#define SOC64_HANDOFF_OFFSET_LENGTH 0x4 #define SOC64_HANDOFF_OFFSET_DATA 0x10 @@ -27,6 +32,8 @@ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) #define SOC64_HANDOFF_BASE 0xFFE3F000 #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_BASE 0x0007F000 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOC64_HANDOFF_BASE 0xFFE5F000 #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630) @@ -58,13 +65,21 @@ #define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) #define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) #define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) +#define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) +#define SOC64_HANDOFF_SDRAM_LEN 1 +#endif
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) -#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) -#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x614) #else -#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc) -#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) #endif
#define SOC64_HANDOFF_MUX_LEN 96 diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index fbaf11597e..502b29bd49 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -112,17 +112,22 @@ enum ALT_SDM_MBOX_RESP_CODE { };
/* Mailbox command list */ -#define MBOX_RESTART 2 -#define MBOX_CONFIG_STATUS 4 -#define MBOX_RECONFIG 6 -#define MBOX_RECONFIG_MSEL 7 -#define MBOX_RECONFIG_DATA 8 -#define MBOX_RECONFIG_STATUS 9 +#define MBOX_RESTART 2 +#define MBOX_CONFIG_STATUS 4 +#define MBOX_RECONFIG 6 +#define MBOX_RECONFIG_MSEL 7 +#define MBOX_RECONFIG_DATA 8 +#define MBOX_RECONFIG_STATUS 9 #define MBOX_VAB_SRC_CERT 11 -#define MBOX_QSPI_OPEN 50 -#define MBOX_QSPI_CLOSE 51 -#define MBOX_QSPI_DIRECT 59 -#define MBOX_REBOOT_HPS 71 +#define MBOX_GET_USERCODE 19 +#define MBOX_QSPI_OPEN 50 +#define MBOX_QSPI_CLOSE 51 +#define MBOX_QSPI_DIRECT 59 +#define MBOX_REBOOT_HPS 71 +#define MBOX_GET_SUBPARTITION_TABLE 90 +#define MBOX_RSU_STATUS 91 +#define MBOX_RSU_UPDATE 92 +#define MBOX_HPS_STAGE_NOTIFY 93
/* Mailbox registers */ #define MBOX_CIN 0 /* command valid offset */ @@ -166,6 +171,11 @@ enum ALT_SDM_MBOX_RESP_CODE { #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) #define RCF_PIN_STATUS_NSTATUS BIT(31)
+/* Defines for HPS_STAGE_NOTIFY */ +#define HPS_EXECUTION_STATE_FSBL 0 +#define HPS_EXECUTION_STATE_SSBL 1 +#define HPS_EXECUTION_STATE_OS 2 + int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf); int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, @@ -182,6 +192,8 @@ int mbox_qspi_open(void); #endif
int mbox_reset_cold(void); +int mbox_hps_stage_notify(u32 execution_stage); +int mbox_hps_stage_notify_psci(u32 execution_stage); int mbox_get_fpga_config_status(u32 cmd); int mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index c8bb727aa2..0f6f1a43da 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -1,17 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2023 Intel Corporation <www.intel.com> */
#ifndef _RESET_MANAGER_SOC64_H_ #define _RESET_MANAGER_SOC64_H_
+#ifndef __ASSEMBLY__ void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); void print_reset_info(void); -void socfpga_bridges_reset(int enable); +void socfpga_bridges_reset(int enable, unsigned int mask); +void socfpga_bridges_reset_psci(int enable, unsigned int mask); +void l2_reset_cpu(void); +void l2_reset_cpu_psci(void); +#endif
#define RSTMGR_SOC64_STATUS 0x00 +#define RSTMGR_SOC64_HDSKEN 0x10 +#define RSTMGR_SOC64_HDSKREQ 0x14 +#define RSTMGR_SOC64_HDSKACK 0x18 #define RSTMGR_SOC64_MPUMODRST 0x20 #define RSTMGR_SOC64_PER0MODRST 0x24 #define RSTMGR_SOC64_PER1MODRST 0x28 @@ -19,18 +27,33 @@ void socfpga_bridges_reset(int enable);
#define RSTMGR_MPUMODRST_CORE0 0 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 -#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 -#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 + +#define RSTMGR_BRGMODRST_SOC2FPGA_MASK BIT(0) +#define RSTMGR_BRGMODRST_LWSOC2FPGA_MASK BIT(1) +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK BIT(2) +#define RSTMGR_BRGMODRST_F2SDRAM0_MASK BIT(3) +#define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4) +#define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5) +#define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6) + +#define RSTMGR_HDSKEN_FPGAHSEN BIT(2) +#define RSTMGR_HDSKREQ_FPGAHSREQ BIT(2)
/* SDM, Watchdogs and MPU warm reset mask */ -#define RSTMGR_STAT_SDMWARMRST BIT(1) +#define RSTMGR_STAT_SDMWARMRST 0x2 #define RSTMGR_STAT_MPU0RST_BITPOS 8 #define RSTMGR_STAT_L4WD0RST_BITPOS 16 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define RSTMGR_STAT_L4WD0RST_BIT 0x1F0000 +#define RSTMGR_L4WD_MPU_WARMRESET_MASK RSTMGR_STAT_SDMWARMRST | \ + RSTMGR_STAT_L4WD0RST_BIT +#else #define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \ RSTMGR_STAT_MPU0RST_BITPOS) | \ GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \ RSTMGR_STAT_L4WD0RST_BITPOS)) +#endif
/* * SocFPGA Stratix10 reset IDs, bank mapping is as follows: diff --git a/arch/arm/mach-socfpga/include/mach/smmu_agilex5.h b/arch/arm/mach-socfpga/include/mach/smmu_agilex5.h new file mode 100644 index 0000000000..0bb79896a3 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/smmu_agilex5.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Intel Corporation. All rights reserved + * + */ + +void socfpga_init_smmu(void); +#define SOCFPGA_NEXT_TBU_PERIPHERAL 4 +/* DMA0 STREAMID */ +#define SYSMGR_DMA0_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x17C +/* DMA1 STREAMID */ +#define SYSMGR_DMA1_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x180 +/* SDM STREAMID */ +#define SYSMGR_SDM_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x184 +/* USB2 STREAMID */ +#define SYSMGR_USB2_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x188 +/* USB3 STREAMID, FUTURE USE */ +#define SYSMGR_USB3_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x18C +/* SDMMC STREAMID */ +#define SYSMGR_SDMMC_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x190 +/* NAND STREAMID */ +#define SYSMGR_NAND_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x194 +/* ETR STREAMID */ +#define SYSMGR_ETR_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x198 +/* TSN0 STREAMID */ +#define SYSMGR_TSN0_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x19C +/* TSN1 STREAMID */ +#define SYSMGR_TSN1_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x1A0 +/* TSN2 STREAMID */ +#define SYSMGR_TSN2_SID_ADDR SOCFPGA_SYSMGR_ADDRESS + 0x1A4 diff --git a/arch/arm/mach-socfpga/include/mach/smmu_s10.h b/arch/arm/mach-socfpga/include/mach/smmu_s10.h new file mode 100644 index 0000000000..9fc3c68ba2 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/smmu_s10.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018-2023 Intel Corporation <www.intel.com> + * + */ + +/* SMMU registers */ +#define SMMU_SCR0 0 +#define SMMU_SIDR0 0x20 +#define SMMU_SIDR1 0x24 + +#define SMMU_SCR0_CLIENTPD BIT(0) +#define SMMU_SIDR0_NUMSMRG_MASK GENMASK(7, 0) +#define SMMU_SIDR1_NUMCB_MASK GENMASK(7, 0) + +/* Stream mapping registers */ +#define SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) +#define SMMU_SMR_VALID BIT(31) +#define SMMU_SMR_MASK GENMASK(30, 16) +#define SMMU_SMR_ID GENMASK(14, 0) + +#define SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) +#define SMMU_S2CR_TYPE GENMASK(17, 16) +#define SMMU_S2CR_CBNDX GENMASK(7, 0) + +/* Register groups for Context Bank */ +#define SMMU_GR0_CB(n, r) (0x20000 + ((n) << 12) + ((r) << 2)) +#define SMMU_CB_SCTLR 0 +#define SMMU_CB_SCTLR_M BIT(0) + +#define SMMU_SID_SDM2HPS_PSI_BE 0 + +#define SDM2HPS_PSI_BE_ADDR_BASE 0 +/* PSI BE 512MB address window */ +#define SDM2HPS_PSI_BE_WINDOW_SZ 0x20000000 +#define SDM2HPS_PSI_BE_ADDR_END \ + (SDM2HPS_PSI_BE_ADDR_BASE + SDM2HPS_PSI_BE_WINDOW_SZ - 1) + +void socfpga_init_smmu(void); +int is_smmu_bypass(void); +int is_smmu_stream_id_enabled(u32 stream_id); + +#define SMMU_SET_STREAMID(x, r, w) ((x << r) | (x << w)) + +#define SYSMGR_EMAC0_SID_ADDR 0xffd12050 /* EMAC0 (emac0_ace) */ +#define SYSMGR_EMAC1_SID_ADDR 0xffd12054 /* EMAC0 (emac1_ace) */ +#define SYSMGR_EMAC2_SID_ADDR 0xffd12058 /* EMAC0 (emac2_ace) */ +#define SYSMGR_NAND_SID_ADDR 0xffd1205c /* NAND (nand_axuser) */ +#define SYSMGR_SDMMC_SID_ADDR 0xffd1202c /* SDMMC (sdmmcgrp_l3master) */ +#define SYSMGR_USB0_SID_ADDR 0xffd12038 /* USB0 (usb0_l3master) */ +#define SYSMGR_USB1_SID_ADDR 0xffd1203c /* USB0 (usb1_l3master) */ +#define SYSMGR_DMA_SID_ADDR 0xffd12074 /* DMA (dma_l3master) */ +#define SYSMGR_ETR_SID_ADDR 0xffd12078 /* ETR (etr_l3master) */ + +/* Stream ID field offsets */ +#define EMAC_W_OFST 20 +#define EMAC_R_OFST 8 +#define NAND_W_OFST 0 +#define NAND_R_OFST 16 +#define SDMMC_OFST 16 +#define USB_OFST 16 +#define DMA_W_OFST 0 +#define DMA_R_OFST 16 +#define ETR_W_OFST 0 +#define ETR_R_OFST 16 + +struct smmu_stream_id { + unsigned long addr; + u32 sid; + u32 r_bit_ofst; + u32 w_bit_ofst; + u32 secure_bit_offset; +}; diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index a8009664fe..c2b886f8cb 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2023 Intel Corporation <www.intel.com> */
#ifndef _SYSTEM_MANAGER_SOC64_H_ @@ -11,11 +11,84 @@ void sysmgr_pinmux_init(void); void populate_sysmgr_fpgaintf_module(void); void populate_sysmgr_pinmux(void);
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SYSMGR_SOC64_SILICONID_1 0x00 +#define SYSMGR_SOC64_SILICONID_2 0x04 +#define SYSMGR_SOC64_WDDBG 0x08 +#define SYSMGR_SOC64_MPU_STATUS 0x10 +#define SYSMGR_SOC64_SDMMC 0x28 +#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c +#define SYSMGR_SOC64_COMBOPHY_DFISEL 0xfc +#define SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC 0x1 +#define SYSMGR_SOC64_NANDGRP_L3MASTER 0x34 +#define SYSMGR_SOC64_USB0_L3MASTER 0x38 +#define SYSMGR_SOC64_USB1_L3MASTER 0x3c +#define SYSMGR_SOC64_TSN_GLOBAL 0x40 +#define SYSMGR_SOC64_TSN_0 0x44 +#define SYSMGR_SOC64_TSN_1 0x48 +#define SYSMGR_SOC64_TSN_2 0x4C +#define SYSMGR_SOC64_TSN_0_ACE 0x50 +#define SYSMGR_SOC64_TSN_1_ACE 0x54 +#define SYSMGR_SOC64_TSN_2_ACE 0x58 +#define SYSMGR_SOC64_FPGAINTF_EN1 0x68 +#define SYSMGR_SOC64_FPGAINTF_EN2 0x6C +#define SYSMGR_SOC64_FPGAINTF_EN3 0x70 +#define SYSMGR_SOC64_DMAC0_L3_MASTER 0x74 +#define SYSMGR_SOC64_ETR_L3_MASTER 0x78 +#define SYSMGR_SOC64_DMAC1_L3_MASTER 0x7C +#define SYSMGR_SOC64_SEC_CTRL_SLT 0x80 +#define SYSMGR_SOC64_OSC_TRIM 0x84 +#define SYSMGR_SOC64_DMAC0_CTRL_STATUS_REG 0x88 +#define SYSMGR_SOC64_DMAC1_CTRL_STATUS_REG 0x8C +#define SYSMGR_SOC64_ECC_INTMASK_VALUE 0x90 +#define SYSMGR_SOC64_ECC_INTMASK_SET 0x94 +#define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98 +#define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C +#define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0 +#define SYSMGR_SOC64_NOC_TIMEOUT 0xC0 +#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4 +#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8 +#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xcc +#define SYSMGR_SOC64_NOC_IDLEACK 0xd0 +#define SYSMGR_SOC64_NOC_IDLESTATUS 0xD4 +#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xD8 +#define SYSMGR_SOC64_FPGA_CONFIG 0xDC +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20C +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21C +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 +#define SYSMGR_SOC64_MPFE_CONFIG 0x228 +#define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258 + +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(31, 0) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK GENMASK(31, 29) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_SHIFT 29 +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_DBE_MASK BIT(1) +#define ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK BIT(0) +#define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK BIT(0) + +#define SYSMGR_SOC64_EMAC_GLOBAL SYSMGR_SOC64_TSN_GLOBAL +#define SYSMGR_SOC64_EMAC0 SYSMGR_SOC64_TSN_0 +#define SYSMGR_SOC64_EMAC1 SYSMGR_SOC64_TSN_1 +#define SYSMGR_SOC64_EMAC2 SYSMGR_SOC64_TSN_2 +#define SYSMGR_SOC64_EMAC0_ACE SYSMGR_SOC64_TSN_0_ACE +#define SYSMGR_SOC64_EMAC1_ACE SYSMGR_SOC64_TSN_1_ACE +#define SYSMGR_SOC64_EMAC2_ACE SYSMGR_SOC64_TSN_2_ACE +#else #define SYSMGR_SOC64_WDDBG 0x08 #define SYSMGR_SOC64_DMA 0x20 #define SYSMGR_SOC64_DMA_PERIPH 0x24 #define SYSMGR_SOC64_SDMMC 0x28 #define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c +#define SYSMGR_SOC64_NANDGRP_L3MASTER 0x34 +#define SYSMGR_SOC64_USB0_L3MASTER 0x38 +#define SYSMGR_SOC64_USB1_L3MASTER 0x3c #define SYSMGR_SOC64_EMAC_GLOBAL 0x40 #define SYSMGR_SOC64_EMAC0 0x44 #define SYSMGR_SOC64_EMAC1 0x48 @@ -65,8 +138,37 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 /* store VBAR_EL3 value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c +/* store ECC DBE register */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 +/* store ECC DBE address */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 + +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0 + * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock (kHz) + */ +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK GENMASK(30, 28) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 + +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8 + * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ? + * + * Bit[30] reserved for FSBL to update the DDR init progress + * 1 - means in progress, 0 - haven't started / DDR is up running. + * + * Bit[19] store ATF CPU0 ON OFF value. + * + * Bit[17:1] - Setting by Linux EDAC. + * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) + */ +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/ + #define SYSMGR_SOC64_PINSEL0 0x1000 #define SYSMGR_SOC64_IOCTRL0 0x1130 #define SYSMGR_SOC64_EMAC0_USEFPGA 0x1300 @@ -91,17 +193,23 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_SDMMC_USEFPGA 0x1354 #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 #define SYSMGR_SOC64_IODELAY0 0x1400 +#define SYSMGR_SOC64_PERI 0x15D0
/* - * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0 - * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit - * storing qspi ref clock (kHz) + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8 + * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ? + * + * Bit[30] reserved for FSBL to update the DDR init progress + * 1 - means in progress, 0 - haven't started / DDR is up running. + * + * Bit[18] reserved for SDM to configure ACF + * Bit[17:1] - Setting by Linux EDAC. + * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) */ -#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) -#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) -#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) -#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) -#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK BIT(18) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT 18
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
diff --git a/arch/arm/mach-socfpga/include/mach/timer.h b/arch/arm/mach-socfpga/include/mach/timer.h index 82596e412e..ac44b2ea45 100644 --- a/arch/arm/mach-socfpga/include/mach/timer.h +++ b/arch/arm/mach-socfpga/include/mach/timer.h @@ -6,6 +6,9 @@ #ifndef _SOCFPGA_TIMER_H_ #define _SOCFPGA_TIMER_H_
+#include <asm/barriers.h> +#include <div64.h> + struct socfpga_timer { u32 load_val; u32 curr_val; @@ -14,4 +17,31 @@ struct socfpga_timer { u32 int_stat; };
+static __always_inline u64 __socfpga_get_time_stamp(void) +{ + u64 cntpct; + + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); + return cntpct; +} + +static __always_inline u64 __socfpga_usec_to_tick(u64 usec) +{ + u64 tick = usec; + u64 cntfrq; + + asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq)); + tick *= cntfrq; + do_div(tick, 1000000); + return tick; +} + +static __always_inline void __socfpga_udelay(u64 usec) +{ + u64 tmp = __socfpga_get_time_stamp() + __socfpga_usec_to_tick(usec); + + while (__socfpga_get_time_stamp() < tmp + 1) + ; +} #endif
This is for new platform enablement for agilex5. Add new platform socdk and update maintainer list.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- board/intel/agilex5-socdk/MAINTAINERS | 8 ++++++++ board/intel/agilex5-socdk/Makefile | 7 +++++++ board/intel/agilex5-socdk/socfpga.c | 7 +++++++ 3 files changed, 22 insertions(+) create mode 100644 board/intel/agilex5-socdk/MAINTAINERS create mode 100644 board/intel/agilex5-socdk/Makefile create mode 100644 board/intel/agilex5-socdk/socfpga.c
diff --git a/board/intel/agilex5-socdk/MAINTAINERS b/board/intel/agilex5-socdk/MAINTAINERS new file mode 100644 index 0000000000..f0bb2b796b --- /dev/null +++ b/board/intel/agilex5-socdk/MAINTAINERS @@ -0,0 +1,8 @@ +SOCFPGA BOARD +M: Tien Fong Chee tien.fong.chee@intel.com +M: Jit Loon Lim jit.loon.lim@intel.com +M: Sieu Mun Tang sieu.mun.tang@intel.com +S: Maintained +F: board/intel/agilex5-socdk/ +F: include/configs/socfpga_agilex5_socdk.h +F: configs/socfpga_agilex5_defconfig diff --git a/board/intel/agilex5-socdk/Makefile b/board/intel/agilex5-socdk/Makefile new file mode 100644 index 0000000000..52f7de8880 --- /dev/null +++ b/board/intel/agilex5-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2022 Intel Corporation <www.intel.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/intel/agilex5-socdk/socfpga.c b/board/intel/agilex5-socdk/socfpga.c new file mode 100644 index 0000000000..ae5c04557c --- /dev/null +++ b/board/intel/agilex5-socdk/socfpga.c @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + * + */ + +#include <common.h>
This is for new platform enablement for agilex5. Add new platform defconfig for new platform.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- configs/socfpga_agilex5_defconfig | 123 +++++++++++++++++++++++ configs/socfpga_agilex5_legacy_defconfig | 85 ++++++++++++++++ 2 files changed, 208 insertions(+) create mode 100644 configs/socfpga_agilex5_defconfig create mode 100644 configs/socfpga_agilex5_legacy_defconfig
diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig new file mode 100644 index 0000000000..6a90fa0b27 --- /dev/null +++ b/configs/socfpga_agilex5_defconfig @@ -0,0 +1,123 @@ +CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 +CONFIG_ARCH_SOCFPGA=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" +# CONFIG_SPL_MMC is not set +CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS=y +CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex5" +CONFIG_SPL_FS_FAT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x82000000 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" +CONFIG_LEGACY_IMAGE_FORMAT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_CRC32=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX5 # " +CONFIG_CMD_NVEDIT_SELECT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_PHY_CADENCE_COMBOPHY=y +CONFIG_DM_MMC=y +CONFIG_SPL_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_CMD_FAT=y +CONFIG_DOS_PARTITION=y +CONFIG_SPL_DOS_PARTITION=y +CONFIG_SPL_SYS_DISABLE_DCACHE_OPS=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),-(root)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_LIST="" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_UBI_SILENCE_MSG=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_NOP_PHY=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_UBIFS_SILENCE_MSG=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_WDT=y +CONFIG_CMD_WDT=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_SPL_WDT=y +CONFIG_WATCHDOG_AUTOSTART=n +CONFIG_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x8ff00000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0xffe3f000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8fa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_agilex5_legacy_defconfig b/configs/socfpga_agilex5_legacy_defconfig new file mode 100644 index 0000000000..cede11c880 --- /dev/null +++ b/configs/socfpga_agilex5_legacy_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x80001000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +# CONFIG_SPL_DM_SPI is not set +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" +CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS=y +CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex5" +CONFIG_SPL_FS_FAT=y +# CONFIG_SPL_SPI is not set +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_ARMV8_PSCI=y +# CONFIG_PSCI_RESET is not set +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon panic=-1" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" +CONFIG_LEGACY_IMAGE_FORMAT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_CACHE=y +# CONFIG_SPL_DM_SPI_FLASH is not set +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX5 # " +CONFIG_CMD_NVEDIT_SELECT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_PHY_CADENCE_COMBOPHY=y +CONFIG_DM_MMC=y +CONFIG_SPL_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_CMD_FAT=y +CONFIG_DOS_PARTITION=y +CONFIG_SPL_DOS_PARTITION=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),-(root)" +CONFIG_CMD_UBI=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_UBI_SILENCE_MSG=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +# CONFIG_SPL_WDT is not set +CONFIG_UBIFS_SILENCE_MSG=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y +CONFIG_SYSRESET_SOCFPGA_SOC64=y +CONFIG_SYSRESET_SOCFPGA_AGILEX5=n
This is for new platform enablement for agilex5. Add new secure register text file for new platform.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- .../misc/socfpga_secreg.txt | 397 ++++++++++++++++++ 1 file changed, 397 insertions(+) create mode 100644 doc/device-tree-bindings/misc/socfpga_secreg.txt
diff --git a/doc/device-tree-bindings/misc/socfpga_secreg.txt b/doc/device-tree-bindings/misc/socfpga_secreg.txt new file mode 100644 index 0000000000..97640b74d9 --- /dev/null +++ b/doc/device-tree-bindings/misc/socfpga_secreg.txt @@ -0,0 +1,397 @@ +* Firewall and privilege register settings in device tree + +Required properties: +-------------------- + +- compatible: should contain "intel,socfpga-secreg" +- reg: Physical base address and size of block register. +- intel,offset-settings: 32-bit offset address of block register, + followed by 32-bit value settings and + the masking bits, only masking bit + set to 1 allows modification. + +The device tree node which describes secure and privilege register access +configuration in compile time. + +Most of these registers are expected to work except for the case which some +registers configuration are required for granting access to some other +registers, for example CCU registers have to be properly configured before +allowing register configuration access to fpga2sdram firewall as shown in +below example. + +Some registers depend on runtime data for proper configuration are expected +to be part of driver that generating these data for example configuration for +soc_noc_fw_ddr_mpu_inst_0_ddr_scr block register depend on DDR size parsed from +memory device tree node. + +Please refer details of tested examples below for both fpga2sdram and QoS +configuration with default reset value and the comments. + +Example: +-------- + +Common configuration for all SoC64 devices: +Path: arch/arm/dts/socfpga_soc64_u-boot.dtsi + + socfpga_secreg: socfpga-secreg { + compatible = "intel,socfpga-secreg"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + i_sys_mgr_core@ffd12000 { + reg = <0xffd12000 0x00000230>; + intel,offset-settings = + /* Enable non-secure interface to DMA */ + <0x00000020 0xff010000 0xff010011>, + /* Enable non-secure interface to DMA periph */ + <0x00000024 0xffffffff 0xffffffff>; + u-boot,dm-pre-reloc; + }; + + noc_fw_l4_per_l4_per_scr@ffd21000 { + reg = <0xffd21000 0x00000074>; + intel,offset-settings = + /* Disable L4 periphs firewall */ + <0x00000000 0x01010001 0x01010001>, + <0x00000004 0x01010001 0x01010001>, + <0x0000000c 0x01010001 0x01010001>, + <0x00000010 0x01010001 0x01010001>, + <0x0000001c 0x01010001 0x01010101>, + <0x00000020 0x01010001 0x01010101>, + <0x00000024 0x01010001 0x01010101>, + <0x00000028 0x01010001 0x01010101>, + <0x0000002c 0x01010001 0x01010001>, + <0x00000030 0x01010001 0x01010001>, + <0x00000034 0x01010001 0x01010001>, + <0x00000040 0x01010001 0x01010001>, + <0x00000044 0x01010001 0x01010101>, + <0x00000048 0x01010001 0x01010101>, + <0x00000050 0x01010001 0x01010101>, + <0x00000054 0x01010001 0x01010101>, + <0x00000058 0x01010001 0x01010101>, + <0x0000005c 0x01010001 0x01010101>, + <0x00000060 0x01010001 0x01010101>, + <0x00000064 0x01010001 0x01010101>, + <0x00000068 0x01010001 0x01010101>, + <0x0000006c 0x01010001 0x01010101>, + <0x00000070 0x01010001 0x01010101>; + u-boot,dm-pre-reloc; + }; + + noc_fw_l4_sys_l4_sys_scr@ffd21100 { + reg = <0xffd21100 0x00000098>; + intel,offset-settings = + /* Disable L4 system firewall */ + <0x00000008 0x01010001 0x01010001>, + <0x0000000c 0x01010001 0x01010001>, + <0x00000010 0x01010001 0x01010001>, + <0x00000014 0x01010001 0x01010001>, + <0x00000018 0x01010001 0x01010001>, + <0x0000001c 0x01010001 0x01010001>, + <0x00000020 0x01010001 0x01010001>, + <0x0000002c 0x01010001 0x01010001>, + <0x00000030 0x01010001 0x01010001>, + <0x00000034 0x01010001 0x01010001>, + <0x00000038 0x01010001 0x01010001>, + <0x00000040 0x01010001 0x01010001>, + <0x00000044 0x01010001 0x01010001>, + <0x00000048 0x01010001 0x01010001>, + <0x0000004c 0x01010001 0x01010001>, + <0x00000054 0x01010001 0x01010001>, + <0x00000058 0x01010001 0x01010001>, + <0x0000005c 0x01010001 0x01010001>, + <0x00000060 0x01010001 0x01010101>, + <0x00000064 0x01010001 0x01010101>, + <0x00000068 0x01010001 0x01010101>, + <0x0000006c 0x01010001 0x01010101>, + <0x00000070 0x01010001 0x01010101>, + <0x00000074 0x01010001 0x01010101>, + <0x00000078 0x01010001 0x03010001>, + <0x00000090 0x01010001 0x01010001>, + <0x00000094 0x01010001 0x01010001>; + u-boot,dm-pre-reloc; + }; + + noc_fw_soc2fpga_soc2fpga_scr@ffd21200 { + reg = <0xffd21200 0x00000004>; + /* Disable soc2fpga security access */ + intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>; + u-boot,dm-pre-reloc; + }; + + noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 { + reg = <0xffd21300 0x00000004>; + /* Disable lightweight soc2fpga security access */ + intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>; + u-boot,dm-pre-reloc; + }; + + noc_fw_tcu_tcu_scr@ffd21400 { + reg = <0xffd21400 0x00000004>; + /* Disable DMA ECC security access, for SMMU use */ + intel,offset-settings = <0x00000000 0x01010001 0x01010001>; + u-boot,dm-pre-reloc; + }; + + noc_fw_priv_MemoryMap_priv@ffd24800 { + reg = <0xffd24800 0x0000000c>; + intel,offset-settings = + /* Enable non-prviledged access to various periphs */ + <0x00000000 0xfff73ffb 0xfff73ffb>; + u-boot,dm-pre-reloc; + }; + }; + +configuration for N5X device: +Path: arch/arm/dts/socfpga_n5x-u-boot.dtsi + + &socfpga_secreg { + coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 { + reg = <0xf7100200 0x00000014>; + intel,offset-settings = + /* Disable ocram security at CCU for non secure access */ + <0x0000004 0x8000ffff 0xe007ffff>, + <0x0000008 0x8000ffff 0xe007ffff>, + <0x000000c 0x8000ffff 0xe007ffff>, + <0x0000010 0x8000ffff 0xe007ffff>; + u-boot,dm-pre-reloc; + }; + + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + reg = <0xf8020000 0x0000001c>; + intel,offset-settings = + /* Disable MPFE firewall for SMMU */ + <0x00000000 0x00010101 0x00010101>, + /* Disable MPFE firewall for HMC adapter */ + <0x00000004 0x00000001 0x00010101>; + u-boot,dm-pre-reloc; + }; + }; + +configuration for Agilex device: +Path: arch/arm/dts/socfpga_agilex-u-boot.dtsi + + &socfpga_secreg { + CCU_coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 { + reg = <0xf7100200 0x00000014>; + intel,offset-settings = + /* Disable ocram security at CCU for non secure access */ + <0x0000004 0x8000ffff 0xe003ffff>, + <0x0000008 0x8000ffff 0xe003ffff>, + <0x000000c 0x8000ffff 0xe003ffff>, + <0x0000010 0x8000ffff 0xe003ffff>; + u-boot,dm-pre-reloc; + }; + + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + reg = <0xf8020000 0x0000001c>; + intel,offset-settings = + /* Disable MPFE firewall for SMMU */ + <0x00000000 0x00010101 0x00010101>, + /* Disable MPFE firewall for HMC adapter */ + <0x00000004 0x00000001 0x00010101>; + u-boot,dm-pre-reloc; + }; + + /* + * Below are all fpga2sdram firewall settings with default + * reset value for the sake of easy reference by users. + * Users may choose to remove any of these register + * configurations that they do not require in their specific + * implementation. + */ + soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020100 { + reg = <0xf8020100 0x00000050>; + intel,offset-settings = + <0x0000000 0x00000000 0x0000000f>, + <0x0000004 0x00000000 0x0000000f>, + <0x0000008 0x00000000 0x0000000f>, + <0x0000010 0x00000000 0xffff0000>, + <0x0000014 0x00000000 0x000000ff>, + <0x0000018 0x00000000 0xffff0000>, + <0x000001c 0x00000000 0x000000ff>, + <0x0000020 0x00000000 0xffff0000>, + <0x0000024 0x00000000 0x000000ff>, + <0x0000028 0x00000000 0xffff0000>, + <0x000002c 0x00000000 0x000000ff>, + <0x0000030 0x00000000 0xffff0000>, + <0x0000034 0x00000000 0x000000ff>, + <0x0000038 0x00000000 0xffff0000>, + <0x000003c 0x00000000 0x000000ff>, + <0x0000040 0x00000000 0xffff0000>, + <0x0000044 0x00000000 0x000000ff>, + <0x0000048 0x00000000 0xffff0000>, + <0x000004c 0x00000000 0x000000ff>; + u-boot,dm-pre-reloc; + }; + + /* + * Example of ccu_mem0_I_main QOS settings with + * default reset value for the sake of easy reference + * by users. Users may choose to remove any of these register + * configurations that they do not require in their specific + * implementation. + */ + soc_mpfe_noc_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 { + reg = <0xf8022080 0x0000001c>; + intel,offset-settings = + <0x0000008 0x00000200 0x00000303>, + <0x000000c 0x00000003 0x00000003>, + <0x0000010 0x00000BFE 0x00007fff>, + <0x0000014 0x00000008 0x000003ff>, + <0x0000018 0x00000000 0x0000000f>; + u-boot,dm-pre-reloc; + }; + }; + +configuration for Stratix 10 device: +Path: arch/arm/dts/socfpga_stratix10-u-boot.dtsi + + &socfpga_secreg { + i_ccu_noc_registers@f7000000 { + reg = <0xf7000000 0x00049e60>; + intel,offset-settings = + /* Enable access to DDR reg from CPU */ + <0x0004400 0xF8000000 0xffffffff>, + + /* Enable access to DDR region from CPU */ + <0x00045c0 0x00000000 0xffffffdf>, + <0x00045e0 0x00000000 0xffffffdf>, + <0x0004600 0x00000000 0xffffffdf>, + <0x0004620 0x00000000 0xffffffdf>, + <0x0004640 0x00000000 0xffffffdf>, + <0x0004660 0x00000000 0xffffffdf>, + + /* Disable ocram security at CCU for non secure access */ + <0x0004688 0xfffc0000 0xffffffcf>, + <0x0018628 0xfffc0000 0xffffffcf>, + + /* Enable access to DDR region from IO master */ + <0x00018560 0x00000000 0xffffffdf>, + <0x00018580 0x00000000 0xffffffdf>, + <0x000185a0 0x00000000 0xffffffdf>, + <0x000185c0 0x00000000 0xffffffdf>, + <0x000185e0 0x00000000 0xffffffdf>, + <0x00018600 0x00000000 0xffffffdf>, + + /* Enable access to DDR region from TCU */ + <0x0002c520 0x00000000 0xffffffdf>, + <0x0002c540 0x00000000 0xffffffdf>, + <0x0002c560 0x00000000 0xffffffdf>, + <0x0002c580 0x00000000 0xffffffdf>, + <0x0002c5a0 0x00000000 0xffffffdf>, + <0x0002c5c0 0x00000000 0xffffffdf>, + + /* Enable access to DDR region from FPGA */ + <0x000105a0 0x00000000 0xffffffdf>, + <0x000105c0 0x00000000 0xffffffdf>, + <0x000105e0 0x00000000 0xffffffdf>, + <0x00010600 0x00000000 0xffffffdf>, + <0x00010620 0x00000000 0xffffffdf>, + <0x00010640 0x00000000 0xffffffdf>; + u-boot,dm-pre-reloc; + }; + + /* + * Both firewall and QOS regs accessed by CPU in MPFE has + * dependency on CCU configuration above. + * + * Below are all fpga2sdram firewall settings with default + * reset value for the sake of easy reference by users. + * Users may choose to remove any of these register configurations + * that they do not require in their specific implementation. + */ + soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020200 { + reg = <0xf8020200 0x00000050>; + intel,offset-settings = + <0x0000000 0x00000000 0x0000000f>, + <0x0000004 0x00000000 0x0000000f>, + <0x0000008 0x00000000 0x0000000f>, + <0x0000010 0x00000000 0xffff0000>, + <0x0000014 0x00000000 0x0000001f>, + <0x0000018 0x00000000 0xffff0000>, + <0x000001c 0x00000000 0x0000001f>, + <0x0000020 0x00000000 0xffff0000>, + <0x0000024 0x00000000 0x0000001f>, + <0x0000028 0x00000000 0xffff0000>, + <0x000002c 0x00000000 0x0000001f>, + <0x0000030 0x00000000 0xffff0000>, + <0x0000034 0x00000000 0x0000001f>, + <0x0000038 0x00000000 0xffff0000>, + <0x000003c 0x00000000 0x0000001f>, + <0x0000040 0x00000000 0xffff0000>, + <0x0000044 0x00000000 0x0000001f>, + <0x0000048 0x00000000 0xffff0000>, + <0x000004c 0x00000000 0x0000001f>; + u-boot,dm-pre-reloc; + }; + + soc_noc_fw_ddr_fpga2sdram_inst_1_ddr_scr@f8020300 { + reg = <0xf8020300 0x00000050>; + intel,offset-settings = + <0x0000000 0x00000000 0x0000000f>, + <0x0000004 0x00000000 0x0000000f>, + <0x0000008 0x00000000 0x0000000f>, + <0x0000010 0x00000000 0xffff0000>, + <0x0000014 0x00000000 0x0000001f>, + <0x0000018 0x00000000 0xffff0000>, + <0x000001c 0x00000000 0x0000001f>, + <0x0000020 0x00000000 0xffff0000>, + <0x0000024 0x00000000 0x0000001f>, + <0x0000028 0x00000000 0xffff0000>, + <0x000002c 0x00000000 0x0000001f>, + <0x0000030 0x00000000 0xffff0000>, + <0x0000034 0x00000000 0x0000001f>, + <0x0000038 0x00000000 0xffff0000>, + <0x000003c 0x00000000 0x0000001f>, + <0x0000040 0x00000000 0xffff0000>, + <0x0000044 0x00000000 0x0000001f>, + <0x0000048 0x00000000 0xffff0000>, + <0x000004c 0x00000000 0x0000001f>; + u-boot,dm-pre-reloc; + }; + + soc_noc_fw_ddr_fpga2sdram_inst_2_ddr_scr@f8020400 { + reg = <0xf8020400 0x00000050>; + intel,offset-settings = + <0x0000000 0x00000000 0x0000000f>, + <0x0000004 0x00000000 0x0000000f>, + <0x0000008 0x00000000 0x0000000f>, + <0x0000010 0x00000000 0xffff0000>, + <0x0000014 0x00000000 0x0000001f>, + <0x0000018 0x00000000 0xffff0000>, + <0x000001c 0x00000000 0x0000001f>, + <0x0000020 0x00000000 0xffff0000>, + <0x0000024 0x00000000 0x0000001f>, + <0x0000028 0x00000000 0xffff0000>, + <0x000002c 0x00000000 0x0000001f>, + <0x0000030 0x00000000 0xffff0000>, + <0x0000034 0x00000000 0x0000001f>, + <0x0000038 0x00000000 0xffff0000>, + <0x000003c 0x00000000 0x0000001f>, + <0x0000040 0x00000000 0xffff0000>, + <0x0000044 0x00000000 0x0000001f>, + <0x0000048 0x00000000 0xffff0000>, + <0x000004c 0x00000000 0x0000001f>; + u-boot,dm-pre-reloc; + }; + + /* + * Example of ccu_mem0_I_main QOS settings with + * default reset value for the sake of easy reference + * by users. Users may choose to remove any of these register + * configurations that they do not require in their specific + * implementation. + */ + soc_ddr_scheduler_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 { + reg = <0xf8022080 0x0000001c>; + intel,offset-settings = + <0x0000008 0x00000000 0x00000303>, + <0x000000c 0x00000001 0x00000003>, + <0x0000010 0x00000BFE 0x00001fff>, + <0x0000014 0x00000008 0x000003ff>, + <0x0000018 0x00000000 0x00000007>; + u-boot,dm-pre-reloc; + }; + };
This is for new platform enablement for agilex5. Add new ddr and iossm mailbox files for new platform.Add
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/ddr/altera/Makefile | 5 +- drivers/ddr/altera/iossm_mailbox.c | 786 +++++++++++++++++++++++++++++ drivers/ddr/altera/iossm_mailbox.h | 141 ++++++ drivers/ddr/altera/sdram_agilex5.c | 329 ++++++++++++ drivers/ddr/altera/sdram_soc64.c | 78 ++- drivers/ddr/altera/sdram_soc64.h | 17 +- 6 files changed, 1345 insertions(+), 11 deletions(-) create mode 100644 drivers/ddr/altera/iossm_mailbox.c create mode 100644 drivers/ddr/altera/iossm_mailbox.h create mode 100644 drivers/ddr/altera/sdram_agilex5.c
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 9fa5d85a27..fa6c880b39 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -7,9 +7,10 @@ # Copyright (C) 2014-2021 Altera Corporation <www.altera.com>
ifdef CONFIG_$(SPL_)ALTERA_SDRAM -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_soc32.o sdram_gen5.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_soc32.o sdram_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o endif diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c new file mode 100644 index 0000000000..c7ceed7c45 --- /dev/null +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -0,0 +1,786 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + * + */ + +#define DEBUG +#include <common.h> +#include <hang.h> +#include <asm/io.h> +#include "iossm_mailbox.h" +#include <wait_bit.h> + +/* supported DDR type list */ +static const char *ddr_type_list[7] = { + "DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN" +}; + +/* Mailbox request function + * This function will send the request to IOSSM mailbox and wait for response return + * + * @io96b_csr_addr: CSR address for the target IO96B + * @ip_type: IP type for the specified memory interface + * @instance_id: IP instance ID for the specified memory interface + * @usr_cmd_type: User desire IOSSM mailbox command type + * @usr_cmd_opcode: User desire IOSSM mailbox command opcode + * @cmd_param_*: Parameters (if applicable) for the requested IOSSM mailbox command + * @resp_data_len: User desire extra response data fields other than + * CMD_RESPONSE_DATA_SHORT field on CMD_RESPONSE_STATUS + * @resp: Structure contain responses returned from the requested IOSSM + * mailbox command + */ +int io96b_mb_req(phys_addr_t io96b_csr_addr, u32 ip_type, u32 instance_id + , u32 usr_cmd_type, u32 usr_cmd_opcode, u32 cmd_param_0 + , u32 cmd_param_1, u32 cmd_param_2, u32 cmd_param_3 + , u32 cmd_param_4, u32 cmd_param_5, u32 cmd_param_6 + , u32 resp_data_len, struct io96b_mb_resp *resp) +{ + int i; + int ret; + u32 cmd_req, cmd_resp; + + /* Initialized zeros for responses*/ + resp->cmd_resp_status = 0; + resp->cmd_resp_data_0 = 0; + resp->cmd_resp_data_1 = 0; + resp->cmd_resp_data_2 = 0; + + /* Ensure CMD_REQ is cleared before write any command request */ + ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_REQ_OFFSET) + , GENMASK(31, 0), 0, TIMEOUT, false); + + if (ret) { + printf("%s: CMD_REQ not ready\n", __func__); + return -1; + } + + /* Write CMD_PARAM_* */ + for (i = 0; i < 6 ; i++) { + switch (i) { + case 0: + if (cmd_param_0) + writel(cmd_param_0, io96b_csr_addr + IOSSM_CMD_PARAM_0_OFFSET); + break; + case 1: + if (cmd_param_1) + writel(cmd_param_1, io96b_csr_addr + IOSSM_CMD_PARAM_1_OFFSET); + break; + case 2: + if (cmd_param_2) + writel(cmd_param_2, io96b_csr_addr + IOSSM_CMD_PARAM_2_OFFSET); + break; + case 3: + if (cmd_param_3) + writel(cmd_param_3, io96b_csr_addr + IOSSM_CMD_PARAM_3_OFFSET); + break; + case 4: + if (cmd_param_4) + writel(cmd_param_4, io96b_csr_addr + IOSSM_CMD_PARAM_4_OFFSET); + break; + case 5: + if (cmd_param_5) + writel(cmd_param_5, io96b_csr_addr + IOSSM_CMD_PARAM_5_OFFSET); + break; + case 6: + if (cmd_param_6) + writel(cmd_param_6, io96b_csr_addr + IOSSM_CMD_PARAM_6_OFFSET); + break; + default: + printf("%s: Invalid command parameter\n", __func__); + } + } + + /* Write CMD_REQ (IP_TYPE, IP_INSTANCE_ID, CMD_TYPE and CMD_OPCODE) */ + cmd_req = (usr_cmd_opcode << 0) | (usr_cmd_type << 16) | (instance_id << 24) | + (ip_type << 29); + writel(cmd_req, io96b_csr_addr + IOSSM_CMD_REQ_OFFSET); + debug("%s: Write 0x%x to IOSSM_CMD_REQ_OFFSET 0x%llx\n", __func__, cmd_req + , io96b_csr_addr + IOSSM_CMD_REQ_OFFSET); + + /* Read CMD_RESPONSE_READY in CMD_RESPONSE_STATUS*/ + ret = wait_for_bit_le32((const void *)(io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET), IOSSM_STATUS_COMMAND_RESPONSE_READY, 1, + TIMEOUT, false); + + if (ret) { + printf("%s: CMD_RESPONSE ERROR:\n", __func__); + cmd_resp = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + printf("%s: STATUS_GENERAL_ERROR: 0x%x\n", __func__, (cmd_resp >> 1) & 0xF); + printf("%s: STATUS_CMD_RESPONSE_ERROR: 0x%x\n", __func__, (cmd_resp >> 5) & 0x7); + } + + /* read CMD_RESPONSE_STATUS*/ + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + /* read CMD_RESPONSE_DATA_* */ + for (i = 0; i < resp_data_len; i++) { + switch (i) { + case 0: + resp->cmd_resp_data_0 = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET); + debug("%s: IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x%llx: 0x%x\n", __func__ + , io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET, + resp->cmd_resp_data_0); + break; + case 1: + resp->cmd_resp_data_1 = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET); + debug("%s: IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x%llx: 0x%x\n", __func__ + , io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET, + resp->cmd_resp_data_1); + break; + case 2: + resp->cmd_resp_data_2 = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET); + debug("%s: IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x%llx: 0x%x\n", __func__ + , io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET, + resp->cmd_resp_data_2); + break; + default: + printf("%s: Invalid response data\n", __func__); + } + } + + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + /* write CMD_RESPONSE_READY = 0 */ + clrbits_le32((u32 *)(uintptr_t)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET) + , IOSSM_STATUS_COMMAND_RESPONSE_READY); + + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + debug("%s: CMD_RESPONSE_READY 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + return 0; +} + +/* + * Initial function to be called to set memory interface IP type and instance ID + * IP type and instance ID need to be determined before sending mailbox command + */ +void io96b_mb_init(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_resp usr_resp; + u8 ip_type_ret, instance_id_ret; + int i, j, k; + + debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance); + for (i = 0; i < io96b_ctrl->num_instance; i++) { + debug("%s: get memory interface IO96B %d\n", __func__, i); + switch (i) { + case 0: + /* Get memory interface IP type & instance ID (IP identifier) */ + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr, 0, 0 + , CMD_GET_SYS_INFO, GET_MEM_INTF_INFO + , 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp); + debug("%s: get response from memory interface IO96B %d\n", __func__, i); + /* Retrieve number of memory interface(s) */ + io96b_ctrl->io96b_0.mb_ctrl.num_mem_interface = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & 0x3; + + /* Retrieve memory interface IP type and instance ID (IP identifier) */ + j = 0; + for (k = 0; k < MAX_MEM_INTERFACES_SUPPORTED; k++) { + switch (k) { + case 0: + ip_type_ret = (usr_resp.cmd_resp_data_0 >> 29) & 0x7; + instance_id_ret = (usr_resp.cmd_resp_data_0 >> 24) & 0x1F; + break; + case 1: + ip_type_ret = (usr_resp.cmd_resp_data_1 >> 29) & 0x7; + instance_id_ret = (usr_resp.cmd_resp_data_1 >> 24) & 0x1F; + break; + } + + if (ip_type_ret) { + io96b_ctrl->io96b_0.mb_ctrl.ip_type[j] = ip_type_ret; + io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j] = + instance_id_ret; + j++; + } + } + break; + case 1: + /* Get memory interface IP type and instance ID (IP identifier) */ + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr, 0, 0, CMD_GET_SYS_INFO + , GET_MEM_INTF_INFO, 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp); + debug("%s: get response from memory interface IO96B %d\n", __func__, i); + /* Retrieve number of memory interface(s) */ + io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & 0x3; + debug("%s: IO96B %d: num_mem_interface: 0x%x\n", __func__, i + , io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface); + + /* Retrieve memory interface IP type and instance ID (IP identifier) */ + j = 0; + for (k = 0; k < MAX_MEM_INTERFACES_SUPPORTED; k++) { + switch (k) { + case 0: + ip_type_ret = (usr_resp.cmd_resp_data_0 >> 29) & 0x7; + instance_id_ret = (usr_resp.cmd_resp_data_0 >> 24) & 0x1F; + break; + case 1: + ip_type_ret = (usr_resp.cmd_resp_data_1 >> 29) & 0x7; + instance_id_ret = (usr_resp.cmd_resp_data_1 >> 24) & 0x1F; + break; + } + + if (ip_type_ret) { + io96b_ctrl->io96b_1.mb_ctrl.ip_type[j] = ip_type_ret; + io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j] = + instance_id_ret; + j++; + } + } + break; + } + debug("%s: IO96B %d: ip_type_ret: 0x%x\n", __func__, i, ip_type_ret); + debug("%s: IO96B %d: instance_id_ret: 0x%x\n", __func__, i, instance_id_ret); + } +} + +int io96b_cal_status(phys_addr_t addr) +{ + int ret; + u32 cal_success, cal_fail; + phys_addr_t status_addr = addr + IOSSM_STATUS_OFFSET; + /* Ensure calibration completed */ + ret = wait_for_bit_le32((const void *)status_addr, IOSSM_STATUS_CAL_BUSY, false + , TIMEOUT, false); + if (ret) { + printf("%s: SDRAM calibration IO96b instance 0x%llx timeout\n", __func__ + , status_addr); + hang(); + } + + /* Calibration status */ + cal_success = readl(status_addr) & IOSSM_STATUS_CAL_SUCCESS; + cal_fail = readl(status_addr) & IOSSM_STATUS_CAL_FAIL; + + if (cal_success && !cal_fail) + return 0; + else + return -EPERM; +} + +void init_mem_cal(struct io96b_info *io96b_ctrl) +{ + int count, i, ret; + + /* Initialize overall calibration status */ + io96b_ctrl->overall_cal_status = false; + + /* Check initial calibration status for the assigned IO96B*/ + count = 0; + for (i = 0; i < io96b_ctrl->num_instance; i++) { + switch (i) { + case 0: + ret = io96b_cal_status(io96b_ctrl->io96b_0.io96b_csr_addr); + if (ret) { + io96b_ctrl->io96b_0.cal_status = false; + printf("%s: Initial DDR calibration IO96B_0 failed %d\n", __func__ + , ret); + break; + } + io96b_ctrl->io96b_0.cal_status = true; + printf("%s: Initial DDR calibration IO96B_0 succeed\n", __func__); + count++; + break; + case 1: + ret = io96b_cal_status(io96b_ctrl->io96b_1.io96b_csr_addr); + if (ret) { + io96b_ctrl->io96b_1.cal_status = false; + printf("%s: Initial DDR calibration IO96B_1 failed %d\n", __func__ + , ret); + break; + } + io96b_ctrl->io96b_1.cal_status = true; + printf("%s: Initial DDR calibration IO96B_1 succeed\n", __func__); + count++; + break; + } + } + + if (count == io96b_ctrl->num_instance) + io96b_ctrl->overall_cal_status = true; +} + +/* + * Trying 3 times re-calibration if initial calibration failed + */ +int trig_mem_cal(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_resp usr_resp; + bool recal_success; + int i; + u8 cal_stat; + + for (i = 0; i < io96b_ctrl->num_instance; i++) { + switch (i) { + case 0: + if (!(io96b_ctrl->io96b_0.cal_status)) { + /* Get the memory calibration status for first memory interface */ + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr, 0, 0 + , CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS, 0, 0, 0 + , 0, 0, 0, 0, 2, &usr_resp); + + recal_success = false; + + /* Re-calibration first memory interface with failed calibration */ + for (i = 0; i < 3; i++) { + cal_stat = usr_resp.cmd_resp_data_0 & GENMASK(2, 0); + if (cal_stat < 0x2) { + recal_success = true; + break; + } + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr + , io96b_ctrl->io96b_0.mb_ctrl.ip_type[0] + , io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[0] + , CMD_TRIG_MEM_CAL_OP, TRIG_MEM_CAL, 0, 0, 0, 0, 0 + , 0, 0, 2, &usr_resp); + + udelay(1); + + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr, 0, 0 + , CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS + , 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp); + } + + if (!recal_success) { + printf("%s: Error as SDRAM calibration failed\n", __func__); + hang(); + } + + /* Get the memory calibration status for second memory interface */ + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr, 0, 0 + , CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS, 0, 0, 0 + , 0, 0, 0, 0, 2, &usr_resp); + + recal_success = false; + + /* Re-calibration second memory interface with failed calibration */ + for (i = 0; i < 3; i++) { + cal_stat = usr_resp.cmd_resp_data_1 & GENMASK(2, 0); + if (cal_stat < 0x2) { + recal_success = true; + break; + } + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr + , io96b_ctrl->io96b_0.mb_ctrl.ip_type[1] + , io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[1] + , CMD_TRIG_MEM_CAL_OP, TRIG_MEM_CAL, 0, 0, 0, 0, 0 + , 0, 0, 2, &usr_resp); + + udelay(1); + + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr, 0, 0 + , CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS + , 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp); + } + + if (!recal_success) { + printf("%s: Error as SDRAM calibration failed\n", __func__); + hang(); + } + + io96b_ctrl->io96b_0.cal_status = true; + } + break; + case 1: + if (!(io96b_ctrl->io96b_1.cal_status)) { + /* Get the memory calibration status for first memory interface */ + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr, 0, 0 + , CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS, 0, 0, 0 + , 0, 0, 0, 0, 2, &usr_resp); + + recal_success = false; + + /* Re-calibration first memory interface with failed calibration */ + for (i = 0; i < 3; i++) { + cal_stat = usr_resp.cmd_resp_data_0 & GENMASK(2, 0); + if (cal_stat < 0x2) { + recal_success = true; + break; + } + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr + , io96b_ctrl->io96b_1.mb_ctrl.ip_type[0] + , io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[0] + , CMD_TRIG_MEM_CAL_OP, TRIG_MEM_CAL, 0, 0, 0, 0, 0 + , 0, 0, 2, &usr_resp); + + udelay(1); + + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr, 0, 0 + , CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS + , 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp); + } + + if (!recal_success) { + printf("%s: Error as SDRAM calibration failed\n", __func__); + hang(); + } + + /* Get the memory calibration status for second memory interface */ + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr, 0, 0 + , CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS, 0, 0, 0 + , 0, 0, 0, 0, 2, &usr_resp); + + recal_success = false; + + /* Re-calibration second memory interface with failed calibration */ + for (i = 0; i < 3; i++) { + cal_stat = usr_resp.cmd_resp_data_0 & GENMASK(2, 0); + if (cal_stat < 0x2) { + recal_success = true; + break; + } + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr + , io96b_ctrl->io96b_1.mb_ctrl.ip_type[1] + , io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[1] + , CMD_TRIG_MEM_CAL_OP, TRIG_MEM_CAL, 0, 0, 0, 0, 0 + , 0, 0, 2, &usr_resp); + + udelay(1); + + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr, 0, 0 + , CMD_TRIG_MEM_CAL_OP, GET_MEM_CAL_STATUS + , 0, 0, 0, 0, 0, 0, 0, 2, &usr_resp); + } + + if (!recal_success) { + printf("%s: Error as SDRAM calibration failed\n", __func__); + hang(); + } + + io96b_ctrl->io96b_1.cal_status = true; + } + break; + } + } + + if (io96b_ctrl->io96b_0.cal_status && io96b_ctrl->io96b_1.cal_status) { + debug("%s: Overall SDRAM calibration success\n", __func__); + io96b_ctrl->overall_cal_status = true; + } + + return 0; +} + +int get_mem_technology(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_resp usr_resp; + int i, j; + u8 ddr_type_ret; + + /* Initialize ddr type */ + io96b_ctrl->ddr_type = ddr_type_list[6]; + + /* Get and ensure all memory interface(s) same DDR type */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + switch (i) { + case 0: + for (j = 0; j < io96b_ctrl->io96b_0.mb_ctrl.num_mem_interface; j++) { + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr + , io96b_ctrl->io96b_0.mb_ctrl.ip_type[j] + , io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j] + , CMD_GET_MEM_INFO, GET_MEM_TECHNOLOGY, 0, 0, 0, 0 + , 0, 0, 0, 0, &usr_resp); + + ddr_type_ret = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(2, 0); + + if (!strcmp(io96b_ctrl->ddr_type, "UNKNOWN")) + io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret]; + + if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) { + printf("%s: Mismatch DDR type on IO96B_0\n", __func__); + return -ENOEXEC; + } + } + break; + case 1: + for (j = 0; j < io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface; j++) { + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr + , io96b_ctrl->io96b_1.mb_ctrl.ip_type[j] + , io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j] + , CMD_GET_MEM_INFO, GET_MEM_TECHNOLOGY, 0, 0, 0, 0 + , 0, 0, 0, 0, &usr_resp); + + ddr_type_ret = + IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(2, 0); + + if (!strcmp(io96b_ctrl->ddr_type, "UNKNOWN")) + io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret]; + + if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) { + printf("%s: Mismatch DDR type on IO96B_1\n", __func__); + return -ENOEXEC; + } + } + break; + } + } + + return 0; +} + +int get_mem_width_info(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_resp usr_resp; + int i, j; + u16 memory_size; + u16 total_memory_size = 0; + + /* Get all memory interface(s) total memory size on all instance(s) */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + switch (i) { + case 0: + memory_size = 0; + for (j = 0; j < io96b_ctrl->io96b_0.mb_ctrl.num_mem_interface; j++) { + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr + , io96b_ctrl->io96b_0.mb_ctrl.ip_type[j] + , io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j] + , CMD_GET_MEM_INFO, GET_MEM_WIDTH_INFO, 0, 0, 0, 0 + , 0, 0, 0, 2, &usr_resp); + + memory_size = memory_size + + (usr_resp.cmd_resp_data_1 & GENMASK(7, 0)); + } + + if (!memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + return -ENOEXEC; + } + + io96b_ctrl->io96b_0.size = memory_size; + + break; + case 1: + memory_size = 0; + for (j = 0; j < io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface; j++) { + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr + , io96b_ctrl->io96b_1.mb_ctrl.ip_type[j] + , io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j] + , CMD_GET_MEM_INFO, GET_MEM_WIDTH_INFO, 0, 0, 0, 0 + , 0, 0, 0, 2, &usr_resp); + + memory_size = memory_size + + (usr_resp.cmd_resp_data_1 & GENMASK(7, 0)); + } + + if (!memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + return -ENOEXEC; + } + + io96b_ctrl->io96b_1.size = memory_size; + + break; + } + + total_memory_size = total_memory_size + memory_size; + } + + if (!total_memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + return -ENOEXEC; + } + + io96b_ctrl->overall_size = total_memory_size; + + return 0; +} + +int ecc_enable_status(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_resp usr_resp; + int i, j; + bool ecc_stat_set = false; + bool ecc_stat; + + /* Initialize ECC status */ + io96b_ctrl->ecc_status = false; + + /* Get and ensure all memory interface(s) same ECC status */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + switch (i) { + case 0: + for (j = 0; j < io96b_ctrl->io96b_0.mb_ctrl.num_mem_interface; j++) { + debug("%s: ECC_ENABLE_STATUS\n", __func__); + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr + , io96b_ctrl->io96b_0.mb_ctrl.ip_type[j] + , io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j] + , CMD_TRIG_CONTROLLER_OP, ECC_ENABLE_STATUS, 0, 0, 0 + , 0, 0, 0, 0, 0, &usr_resp); + + ecc_stat = ((IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(1, 0)) == 0 ? false : true); + + if (!ecc_stat_set) { + io96b_ctrl->ecc_status = ecc_stat; + ecc_stat_set = true; + } + + if (ecc_stat != io96b_ctrl->ecc_status) { + printf("%s: Mismatch DDR ECC status on IO96B_0\n" + , __func__); + return -ENOEXEC; + } + } + break; + case 1: + for (j = 0; j < io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface; j++) { + debug("%s: ECC_ENABLE_STATUS\n", __func__); + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr + , io96b_ctrl->io96b_1.mb_ctrl.ip_type[j] + , io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j] + , CMD_TRIG_CONTROLLER_OP, ECC_ENABLE_STATUS, 0, 0, 0 + , 0, 0, 0, 0, 0, &usr_resp); + + ecc_stat = ((IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(1, 0)) == 0 ? false : true); + + if (!ecc_stat_set) { + io96b_ctrl->ecc_status = ecc_stat; + ecc_stat_set = true; + } + + if (ecc_stat != io96b_ctrl->ecc_status) { + printf("%s: Mismatch DDR ECC status on IO96B_1\n" + , __func__); + return -ENOEXEC; + } + } + break; + } + } + return 0; +} + +int bist_mem_init_start(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_resp usr_resp; + int i, j; + bool bist_start, bist_success; + u32 start; + + /* Full memory initialization BIST performed on all memory interface(s) */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + switch (i) { + case 0: + for (j = 0; j < io96b_ctrl->io96b_0.mb_ctrl.num_mem_interface; j++) { + bist_start = false; + bist_success = false; + + /* Start memory initialization BIST on full memory address */ + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr + , io96b_ctrl->io96b_0.mb_ctrl.ip_type[j] + , io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j] + , CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START, 0x40 + , 0, 0, 0, 0, 0, 0, 0, &usr_resp); + + bist_start = + (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0)); + + if (!bist_start) { + printf("%s: Failed to initialized memory on IO96B_0\n" + , __func__); + printf("%s: BIST_MEM_INIT_START Error code 0x%x\n", __func__ + , (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(2, 1)) > 0x1); + return -ENOEXEC; + } + + /* Polling for the initiated memory initialization BIST status */ + start = get_timer(0); + while (!bist_success) { + io96b_mb_req(io96b_ctrl->io96b_0.io96b_csr_addr + , io96b_ctrl->io96b_0.mb_ctrl.ip_type[j] + , io96b_ctrl->io96b_0.mb_ctrl.ip_instance_id[j] + , CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_STATUS, 0 + , 0, 0, 0, 0, 0, 0, 0, &usr_resp); + + bist_success = (IOSSM_CMD_RESPONSE_DATA_SHORT + (usr_resp.cmd_resp_status) & BIT(0)); + + if (!bist_success && (get_timer(start) > TIMEOUT)) { + printf("%s: Timeout initialize memory on IO96B_0\n" + , __func__); + printf("%s: BIST_MEM_INIT_STATUS Error code 0x%x\n" + , __func__, (IOSSM_CMD_RESPONSE_DATA_SHORT + (usr_resp.cmd_resp_status) + & GENMASK(2, 1)) > 0x1); + return -ETIMEDOUT; + } + + udelay(1); + } + } + + debug("%s: Memory initialized successfully on IO96B_0\n", __func__); + break; + case 1: + for (j = 0; j < io96b_ctrl->io96b_1.mb_ctrl.num_mem_interface; j++) { + bist_start = false; + bist_success = false; + + /* Start memory initialization BIST on full memory address */ + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr + , io96b_ctrl->io96b_1.mb_ctrl.ip_type[j] + , io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j] + , CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START, 0x40 + , 0, 0, 0, 0, 0, 0, 0, &usr_resp); + + bist_start = + (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0)); + + if (!bist_start) { + printf("%s: Failed to initialized memory on IO96B_1\n" + , __func__); + printf("%s: BIST_MEM_INIT_START Error code 0x%x\n", __func__ + , (IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & GENMASK(2, 1)) > 0x1); + return -ENOEXEC; + } + + /* Polling for the initiated memory initialization BIST status */ + start = get_timer(0); + while (!bist_success) { + io96b_mb_req(io96b_ctrl->io96b_1.io96b_csr_addr + , io96b_ctrl->io96b_1.mb_ctrl.ip_type[j] + , io96b_ctrl->io96b_1.mb_ctrl.ip_instance_id[j] + , CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_STATUS, 0 + , 0, 0, 0, 0, 0, 0, 0, &usr_resp); + + bist_success = (IOSSM_CMD_RESPONSE_DATA_SHORT + (usr_resp.cmd_resp_status) & BIT(0)); + + if (!bist_success && (get_timer(start) > TIMEOUT)) { + printf("%s: Timeout initialize memory on IO96B_1\n" + , __func__); + printf("%s: BIST_MEM_INIT_STATUS Error code 0x%x\n" + , __func__, (IOSSM_CMD_RESPONSE_DATA_SHORT + (usr_resp.cmd_resp_status) + & GENMASK(2, 1)) > 0x1); + return -ETIMEDOUT; + } + + udelay(1); + } + } + + debug("%s: Memory initialized successfully on IO96B_1\n", __func__); + break; + } + } + return 0; +} diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h new file mode 100644 index 0000000000..8c57126c3e --- /dev/null +++ b/drivers/ddr/altera/iossm_mailbox.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + */ + +#define TIMEOUT_10000MS 10000 +#define TIMEOUT TIMEOUT_10000MS +#define IOSSM_STATUS_CAL_SUCCESS BIT(0) +#define IOSSM_STATUS_CAL_FAIL BIT(1) +#define IOSSM_STATUS_CAL_BUSY BIT(2) +#define IOSSM_STATUS_COMMAND_RESPONSE_READY BIT(0) +#define IOSSM_CMD_RESPONSE_STATUS_OFFSET 0x45C +#define IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x458 +#define IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x454 +#define IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x450 +#define IOSSM_CMD_REQ_OFFSET 0x43C +#define IOSSM_CMD_PARAM_0_OFFSET 0x438 +#define IOSSM_CMD_PARAM_1_OFFSET 0x434 +#define IOSSM_CMD_PARAM_2_OFFSET 0x430 +#define IOSSM_CMD_PARAM_3_OFFSET 0x42C +#define IOSSM_CMD_PARAM_4_OFFSET 0x428 +#define IOSSM_CMD_PARAM_5_OFFSET 0x424 +#define IOSSM_CMD_PARAM_6_OFFSET 0x420 +#define IOSSM_STATUS_OFFSET 0x400 +#define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) +#define IOSSM_CMD_RESPONSE_DATA_SHORT(data) (((data) & IOSSM_CMD_RESPONSE_DATA_SHORT_MASK) >> 16) +#define MAX_IO96B_SUPPORTED 2 +#define MAX_MEM_INTERFACES_SUPPORTED 2 + +/* supported mailbox command type */ +enum iossm_mailbox_cmd_type { + CMD_NOP, + CMD_GET_SYS_INFO, + CMD_GET_MEM_INFO, + CMD_GET_MEM_CAL_INFO, + CMD_TRIG_CONTROLLER_OP, + CMD_TRIG_MEM_CAL_OP +}; + +/* supported mailbox command opcode */ +enum iossm_mailbox_cmd_opcode { + GET_MEM_INTF_INFO = 0x0001, + GET_MEM_TECHNOLOGY, + GET_MEMCLK_FREQ_KHZ, + GET_MEM_WIDTH_INFO, + ECC_ENABLE_SET = 0x0101, + ECC_ENABLE_STATUS, + ECC_INTERRUPT_STATUS, + ECC_INTERRUPT_ACK, + ECC_INTERRUPT_MASK, + ECC_WRITEBACK_ENABLE, + ECC_SCRUB_IN_PROGRESS_STATUS = 0x0201, + ECC_SCRUB_MODE_0_START, + ECC_SCRUB_MODE_1_START, + BIST_STANDARD_MODE_START = 0x0301, + BIST_RESULTS_STATUS, + BIST_MEM_INIT_START, + BIST_MEM_INIT_STATUS, + BIST_SET_DATA_PATTERN_UPPER, + BIST_SET_DATA_PATTERN_LOWER, + TRIG_MEM_CAL = 0x000a, + GET_MEM_CAL_STATUS +}; + +/* + * IOSSM mailbox required information + * + * @num_mem_interface: Number of memory interfaces instantiated + * @ip_type: IP type implemented on the IO96B + * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B + */ +struct io96b_mb_ctrl { + u32 num_mem_interface; + u32 ip_type[2]; + u32 ip_instance_id[2]; +}; + +/* + * IOSSM mailbox response outputs + * + * @cmd_resp_status: Command Interface status + * @cmd_resp_data_*: More spaces for command response + */ +struct io96b_mb_resp { + u32 cmd_resp_status; + u32 cmd_resp_data_0; + u32 cmd_resp_data_1; + u32 cmd_resp_data_2; +}; + +/* + * IO96B instance specific information + * + * @size: Memory size + * @io96b_csr_addr: IO96B instance CSR address + * @cal_status: IO96B instance calibration status + * @mb_ctrl: IOSSM mailbox required information + */ +struct io96b_instance { + u16 size; + phys_addr_t io96b_csr_addr; + bool cal_status; + struct io96b_mb_ctrl mb_ctrl; +}; + +/* + * Overall IO96B instance(s) information + * + * @num_instance: Number of instance(s) assigned to HPS + * @overall_cal_status: Overall calibration status for all IO96B instance(s) + * @ddr_type: DDR memory type + * @ecc_status: ECC enable status (false = disabled, true = enabled) + * @overall_size: Total DDR memory size + * @io96b_0: IO96B 0 instance specific information + * @io96b_1: IO96B 1 instance specific information + */ +struct io96b_info { + u8 num_instance; + bool overall_cal_status; + const char *ddr_type; + bool ecc_status; + u16 overall_size; + struct io96b_instance io96b_0; + struct io96b_instance io96b_1; +}; + +int io96b_mb_req(phys_addr_t io96b_csr_addr, u32 ip_type, u32 instance_id + , u32 usr_cmd_type, u32 usr_cmd_opcode, u32 cmd_param_0 + , u32 cmd_param_1, u32 cmd_param_2, u32 cmd_param_3, u32 cmd_param_4 + , u32 cmd_param_5, u32 cmd_param_6, u32 resp_data_len + , struct io96b_mb_resp *resp); + +/* Supported IOSSM mailbox function */ +void io96b_mb_init(struct io96b_info *io96b_ctrl); +int io96b_cal_status(phys_addr_t addr); +void init_mem_cal(struct io96b_info *io96b_ctrl); +int trig_mem_cal(struct io96b_info *io96b_ctrl); +int get_mem_technology(struct io96b_info *io96b_ctrl); +int get_mem_width_info(struct io96b_info *io96b_ctrl); +int ecc_enable_status(struct io96b_info *io96b_ctrl); +int bist_mem_init_start(struct io96b_info *io96b_ctrl); diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c new file mode 100644 index 0000000000..e8e3f258b9 --- /dev/null +++ b/drivers/ddr/altera/sdram_agilex5.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2023 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <div64.h> +#include <fdtdec.h> +#include <hang.h> +#include <log.h> +#include <ram.h> +#include <reset.h> +#include <asm/global_data.h> +#include "iossm_mailbox.h" +#include "sdram_soc64.h" +#include <wait_bit.h> +#include <asm/arch/firewall.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/io.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* MPFE NOC registers */ +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 0x58 +#define SIDEBANDMGR_FLAGOUTSET0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSET0 +#define SIDEBANDMGR_FLAGOUTSTATUS0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 + +/* Reset type */ +enum reset_type { + POR_RESET, + WARM_RESET, + COLD_RESET, + NCONFIG, + JTAG_CONFIG, + RSU_RECONFIG +}; + +static enum reset_type get_reset_type(u32 reg) +{ + return (reg & ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK) >> + ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_SHIFT; +} + +int set_mpfe_config(void) +{ + /* Set mpfe_lite_active */ + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(8)); + + debug("%s: mpfe_config: 0x%x\n", __func__, + readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG)); + + return 0; +} + +bool is_ddr_init_hang(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_POR0); + + if (reg & ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK) + return true; + + return false; +} + +void ddr_init_inprogress(bool start) +{ + if (start) + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_POR0, + ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK); + else + clrbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_POR0, + ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK); +} + +int populate_ddr_handoff(struct udevice *dev, struct io96b_info *io96b_ctrl) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + fdt_addr_t addr; + int i; + u32 len = SOC64_HANDOFF_SDRAM_LEN; + u32 handoff_table[len]; + + /* Read handoff for DDR configuration */ + socfpga_handoff_read((void *)SOC64_HANDOFF_SDRAM, handoff_table, len); + + /* Read handoff - dual port */ + plat->dualport = handoff_table[0] & BIT(0); + debug("%s: dualport from handoff: 0x%x\n", __func__, plat->dualport); + + /* Read handoff - dual EMIF */ + plat->dualemif = handoff_table[0] & BIT(1); + debug("%s: dualemif from handoff: 0x%x\n", __func__, plat->dualemif); + + if (plat->dualemif) + io96b_ctrl->num_instance = 2; + else + io96b_ctrl->num_instance = 1; + + /* Assign IO96B CSR base address if it is valid */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + addr = dev_read_addr_index(dev, i + 1); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + switch (i) { + case 0: + io96b_ctrl->io96b_0.io96b_csr_addr = addr; + debug("%s: IO96B 0x%llx CSR enabled\n", __func__ + , io96b_ctrl->io96b_0.io96b_csr_addr); + break; + case 1: + io96b_ctrl->io96b_1.io96b_csr_addr = addr; + debug("%s: IO96B 0x%llx CSR enabled\n", __func__ + , io96b_ctrl->io96b_1.io96b_csr_addr); + break; + default: + printf("%s: Invalid IO96B CSR\n", __func__); + } + } + + return 0; +} + +int config_mpfe_sideband_mgr(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + + /* Dual port setting */ + if (plat->dualport) + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(4)); + + /* Dual EMIF setting */ + if (plat->dualemif) { + set_mpfe_config(); + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(5)); + } + + debug("%s: SIDEBANDMGR_FLAGOUTSTATUS0: 0x%x\n", __func__, + readl(SIDEBANDMGR_FLAGOUTSTATUS0_REG)); + + return 0; +} + +bool hps_ocram_dbe_status(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD3); + + if (reg & ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK) + return true; + + return false; +} + +bool ddr_ecc_dbe_status(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD3); + + if (reg & ALT_SYSMGR_SCRATCH_REG_3_DDR_DBE_MASK) + return true; + + return false; +} + +int sdram_mmr_init_full(struct udevice *dev) +{ + int ret; + phys_size_t hw_size; + struct bd_info bd = {0}; + struct altera_sdram_plat *plat = dev_get_plat(dev); + struct altera_sdram_priv *priv = dev_get_priv(dev); + struct io96b_info *io96b_ctrl = malloc(sizeof(*io96b_ctrl)); + + u32 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD3); + enum reset_type reset_t = get_reset_type(reg); + bool full_mem_init = false; + + /* DDR initialization progress status tracking */ + bool is_ddr_hang_be4_rst = is_ddr_init_hang(); + + debug("DDR: SDRAM init in progress ...\n"); + ddr_init_inprogress(true); + + debug("DDR: Address MPFE 0x%llx\n", plat->mpfe_base_addr); + + /* Populating DDR handoff data */ + debug("DDR: Checking SDRAM configuration in progress ...\n"); + ret = populate_ddr_handoff(dev, io96b_ctrl); + if (ret) { + printf("DDR: Failed to populate DDR handoff\n"); + free(io96b_ctrl); + return ret; + } + + /* Configuring MPFE sideband manager registers - dual port & dual emif*/ + ret = config_mpfe_sideband_mgr(dev); + if (ret) { + printf("DDR: Failed to configure dual port dual emif\n"); + free(io96b_ctrl); + return ret; + } + + /* Ensure calibration status passing */ + init_mem_cal(io96b_ctrl); + + /* Initiate IOSSM mailbox */ + io96b_mb_init(io96b_ctrl); + + /* Need to trigger re-calibration for DDR DBE */ + if (ddr_ecc_dbe_status()) { + io96b_ctrl->io96b_0.cal_status = false; + io96b_ctrl->io96b_1.cal_status = false; + io96b_ctrl->overall_cal_status = io96b_ctrl->io96b_0.cal_status || + io96b_ctrl->io96b_1.cal_status; + } + + /* Trigger re-calibration if calibration failed */ + if (!(io96b_ctrl->overall_cal_status)) { + printf("DDR: Re-calibration in progress...\n"); + trig_mem_cal(io96b_ctrl); + } + + printf("DDR: Calibration success\n"); + + /* DDR type, DDR size and ECC status) */ + ret = get_mem_technology(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR type\n"); + free(io96b_ctrl); + return ret; + } + + ret = get_mem_width_info(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR size\n"); + free(io96b_ctrl); + return ret; + } + + hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8; + + /* Get bank configuration from devicetree */ + ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, + (phys_size_t *)&gd->ram_size, &bd); + if (ret) { + puts("DDR: Failed to decode memory node\n"); + free(io96b_ctrl); + return -ENXIO; + } + + if (gd->ram_size != hw_size) { + printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n", + gd->ram_size >> 20); + printf(" mismatch with hardware (%lld MiB).\n", + hw_size >> 20); + } + + if (gd->ram_size > hw_size) { + printf("DDR: Error: DRAM size from device tree is greater\n"); + printf(" than hardware size.\n"); + hang(); + } + + printf("%s: %lld MiB\n", io96b_ctrl->ddr_type, gd->ram_size >> 20); + + ret = ecc_enable_status(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR ECC status\n"); + free(io96b_ctrl); + return ret; + } + + /* Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC + * enabled to preserve memory content + */ + if (io96b_ctrl->ecc_status) { + full_mem_init = hps_ocram_dbe_status() | ddr_ecc_dbe_status() | + is_ddr_hang_be4_rst; + if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) { + ret = bist_mem_init_start(io96b_ctrl); + if (ret) { + printf("DDR: Failed to fully initialize DDR memory\n"); + free(io96b_ctrl); + return ret; + } + } + + printf("SDRAM-ECC: Initialized success\n"); + } + + sdram_size_check(&bd); + printf("DDR: size check success\n"); + + sdram_set_firewall(&bd); + + /* Firewall setting for MPFE CSR */ + /* IO96B0_reg */ + writel(0x1, 0x18000d00); + /* IO96B1_reg */ + writel(0x1, 0x18000d04); + /* noc_csr */ + writel(0x1, 0x18000d08); + + printf("DDR: firewall init success\n"); + + priv->info.base = bd.bi_dram[0].start; + priv->info.size = gd->ram_size; + + /* Ending DDR driver initialization success tracking */ + ddr_init_inprogress(false); + + printf("DDR: init success\n"); + + free(io96b_ctrl); + + return 0; +} diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 4716abfc9a..0fee07fcaf 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -28,6 +28,7 @@
#define PGTABLE_OFF 0x4000
+#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { return readl(plat->iomhc + reg); @@ -99,8 +100,9 @@ int emif_reset(struct altera_sdram_plat *plat) debug("DDR: %s triggered successly\n", __func__); return 0; } +#endif
-#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) int poll_hmc_clock_status(void) { return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + @@ -246,13 +248,13 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
- size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & + size *= ((phys_size_t)2 << (hmc_ecc_readl(plat, DDRIOCTRL) & DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
return size; }
-void sdram_set_firewall(struct bd_info *bd) +static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) { u32 i; phys_size_t value; @@ -288,7 +290,7 @@ void sdram_set_firewall(struct bd_info *bd) FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT + (i * 4 * sizeof(u32)));
- /* Setting non-secure MPU limit and limit extexded */ + /* Setting non-secure MPU limit and limit extended */ value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
lower = lower_32_bits(value); @@ -301,7 +303,7 @@ void sdram_set_firewall(struct bd_info *bd) FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT + (i * 4 * sizeof(u32)));
- /* Setting non-secure Non-MPU limit and limit extexded */ + /* Setting non-secure Non-MPU limit and limit extended */ FW_MPU_DDR_SCR_WRITEL(lower, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT + (i * 4 * sizeof(u32))); @@ -314,6 +316,60 @@ void sdram_set_firewall(struct bd_info *bd) } }
+static void sdram_set_firewall_f2sdram(struct bd_info *bd) +{ + u32 i; + phys_size_t value; + u32 lower, upper; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (!bd->bi_dram[i].size) + continue; + + value = bd->bi_dram[i].start; + + /* Keep first 1MB of SDRAM memory region as secure region when + * using ATF flow, where the ATF code is located. + */ + if (IS_ENABLED(CONFIG_SPL_ATF) && i == 0) + value += SZ_1M; + + /* Setting base and base extended */ + lower = lower_32_bits(value); + upper = upper_32_bits(value); + FW_F2SDRAM_DDR_SCR_WRITEL(lower, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE + + (i * 4 * sizeof(u32))); + FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT + + (i * 4 * sizeof(u32))); + + /* Setting limit and limit extended */ + value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + + lower = lower_32_bits(value); + upper = upper_32_bits(value); + + FW_F2SDRAM_DDR_SCR_WRITEL(lower, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT + + (i * 4 * sizeof(u32))); + FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT + + (i * 4 * sizeof(u32))); + + FW_F2SDRAM_DDR_SCR_WRITEL(BIT(i), FW_F2SDRAM_DDR_SCR_EN_SET); + } +} + +void sdram_set_firewall(struct bd_info *bd) +{ + sdram_set_firewall_non_f2sdram(bd); + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + sdram_set_firewall_f2sdram(bd); +#endif +} + static int altera_sdram_of_to_plat(struct udevice *dev) { struct altera_sdram_plat *plat = dev_get_plat(dev); @@ -322,7 +378,12 @@ static int altera_sdram_of_to_plat(struct udevice *dev) /* These regs info are part of DDR handoff in bitstream */ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) return 0; -#endif +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->mpfe_base_addr = addr; +#else
addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) @@ -338,15 +399,15 @@ static int altera_sdram_of_to_plat(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; plat->hmc = (void __iomem *)addr; - +#endif return 0; }
static int altera_sdram_probe(struct udevice *dev) { - int ret; struct altera_sdram_priv *priv = dev_get_priv(dev);
+ int ret; ret = reset_get_bulk(dev, &priv->resets); if (ret) { dev_err(dev, "Can't get reset: %d\n", ret); @@ -385,6 +446,7 @@ static const struct udevice_id altera_sdram_ids[] = { { .compatible = "altr,sdr-ctl-s10" }, { .compatible = "intel,sdr-ctl-agilex" }, { .compatible = "intel,sdr-ctl-n5x" }, + { .compatible = "intel,sdr-ctl-agilex5" }, { /* sentinel */ } };
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 07a0f9f2ae..c96025f8b1 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2022 Intel Corporation <www.intel.com> */
#ifndef _SDRAM_SOC64_H_ @@ -14,11 +14,20 @@ struct altera_sdram_priv { struct reset_ctl_bulk resets; };
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +struct altera_sdram_plat { + fdt_addr_t mpfe_base_addr; + bool dualport; + bool dualemif; +}; +#else + struct altera_sdram_plat { void __iomem *hmc; void __iomem *ddr_sch; void __iomem *iomhc; }; +#endif
/* ECC HMC registers */ #define DDRIOCTRL 0x8 @@ -39,6 +48,8 @@ struct altera_sdram_plat { #define RSTHANDSHAKESTAT 0x218
#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 +#define DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_MSK BIT(2) +#define DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_SHIFT 2 #define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) #define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) #define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) @@ -66,6 +77,7 @@ struct altera_sdram_plat { #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c #define CTRLCFG3 0x34 +#define CTRLCFG5 0x3c #define DRAMTIMING0 0x50 #define CALTIMING0 0x7c #define CALTIMING1 0x80 @@ -79,6 +91,9 @@ struct altera_sdram_plat { #define NIOSRESERVED1 0x114 #define NIOSRESERVED2 0x118
+#define CTRLCFG3_CFG_CTRL_CMD_RATE_QUARTER BIT(2) +#define CTRLCFG5_CFG_CTRL_RC_EN_MASK BIT(8) + #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ (((x) >> 0) & 0x1F) #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
This is for new platform enablement for agilex5. Add new clock files for new platform.Add
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex5.c | 736 +++++++++++++++++++++++++++++++ drivers/clk/altera/clk-agilex5.h | 263 +++++++++++ 3 files changed, 1000 insertions(+) create mode 100644 drivers/clk/altera/clk-agilex5.c create mode 100644 drivers/clk/altera/clk-agilex5.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index 33db092918..61ffa4179a 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += clk-agilex5.o diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c new file mode 100644 index 0000000000..05ee5f9874 --- /dev/null +++ b/drivers/clk/altera/clk-agilex5.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2023 Intel Corporation <www.intel.com> + */ + +#include <common.h> +#include <log.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/util.h> +#include <dt-bindings/clock/agilex5-clock.h> +#include <linux/bitops.h> + +#include <asm/arch/clock_manager.h> +#include <asm/system.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MPIDR_AFF1_OFFSET 8 +#define MPIDR_AFF1_MASK 0x3 +#define CORE0 1 +#define CORE1 2 +#define CORE2 3 +#define CORE3 4 + +struct socfpga_clk_plat { + void __iomem *regs; +}; + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS); + cm_wait_for_fsm(); +} + +static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS); + cm_wait_for_fsm(); +} + +/* function to write the ctrl register which requires a poll of the busy bit */ +static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_CTRL); + cm_wait_for_fsm(); +} + +#define MEMBUS_MAINPLL 0 +#define MEMBUS_PERPLL 1 +#define MEMBUS_TIMEOUT 1000 + +#define MEMBUS_CLKSLICE_REG 0x27 +#define MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG 0xb3 +#define MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG 0xe6 +#define MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG 0x03 +#define MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG 0x07 + +static const struct { + u32 reg; + u32 val; + u32 mask; +} membus_pll[] = { + { + MEMBUS_CLKSLICE_REG, + /* + * BIT[7:7] + * Enable source synchronous mode + */ + BIT(7), + BIT(7) + }, + { + MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG, + /* + * BIT[0:0] + * Sets synthcalfosc_init_centerfreq=1 to limit overshoot + * frequency during lock + */ + BIT(0), + BIT(0) + }, + { + MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG, + /* + * BIT[0:0] + * Sets synthppm_watchdogtmr_vf0=1 to give the pll more time + * to settle before lock is asserted. + */ + BIT(0), + BIT(0) + }, + { + MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG, + /* + * BIT[6:0] + * Centering duty cycle for clkslice0 output + */ + 0x4a, + GENMASK(6, 0) + }, + { + MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG, + /* + * BIT[6:0] + * Centering duty cycle for clkslice1 output + */ + 0x4a, + GENMASK(6, 0) + }, +}; + +static int membus_wait_for_req(struct socfpga_clk_plat *plat, u32 pll, + int timeout) +{ + int cnt = 0; + u32 req_status; + + if (pll == MEMBUS_MAINPLL) + req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM); + else + req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM); + + while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) { + if (pll == MEMBUS_MAINPLL) + req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM); + else + req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM); + cnt++; + } + + if (cnt >= timeout) + return -ETIMEDOUT; + + return 0; +} + +static int membus_write_pll(struct socfpga_clk_plat *plat, u32 pll, + u32 addr_offset, u32 wdat, int timeout) +{ + u32 addr; + u32 val; + + addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK); + + val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK | + (wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr); + + if (pll == MEMBUS_MAINPLL) + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM); + else + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM); + + debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr); + + return membus_wait_for_req(plat, pll, timeout); +} + +static int membus_read_pll(struct socfpga_clk_plat *plat, u32 pll, + u32 addr_offset, u32 *rdata, int timeout) +{ + u32 addr; + u32 val; + + addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK); + + val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr); + + if (pll == MEMBUS_MAINPLL) + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM); + else + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM); + + *rdata = 0; + + if (membus_wait_for_req(plat, pll, timeout)) + return -ETIMEDOUT; + + if (pll == MEMBUS_MAINPLL) + *rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT); + else + *rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT); + + debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr); + + return 0; +} + +static void membus_pll_configs(struct socfpga_clk_plat *plat, u32 pll) +{ + int i; + u32 rdata; + + for (i = 0; i < ARRAY_SIZE(membus_pll); i++) { + membus_read_pll(plat, pll, membus_pll[i].reg, + &rdata, MEMBUS_TIMEOUT); + membus_write_pll(plat, pll, membus_pll[i].reg, + ((rdata & ~membus_pll[i].mask) | membus_pll[i].val), + MEMBUS_TIMEOUT); + } +} + +static u32 calc_vocalib_pll(u32 pllm, u32 pllglob) +{ + u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib; + + mdiv = pllm & CLKMGR_PLLM_MDIV_MASK; + arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET; + drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET; + refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_REFCLKDIV_OFFSET; + mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv)); + if (!mscnt) + mscnt = 1; + hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) - + CLKMGR_VCOCALIB_HSCNT_CONST; + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | + ((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) & + CLKMGR_VCOCALIB_MSCNT_MASK); + + /* Dump all the pll calibration settings for debug purposes */ + debug("mdiv : %d\n", mdiv); + debug("arefclkdiv : %d\n", arefclkdiv); + debug("drefclkdiv : %d\n", drefclkdiv); + debug("refclkdiv : %d\n", refclkdiv); + debug("mscnt : %d\n", mscnt); + debug("hscnt : %d\n", hscnt); + debug("vcocalib : 0x%08x\n", vcocalib); + + return vcocalib; +} + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + */ +static void clk_basic_init(struct udevice *dev, + const struct cm_config * const cfg) +{ + struct socfpga_clk_plat *plat = dev_get_plat(dev); + u32 vcocalib; + + if (!cfg) + return; + + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)) { + /* Take both PLL out of reset and power up */ + CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + + cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK); + + /* Put both PLLs in bypass */ + clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL); + clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL); + + /* Take all PLLs out of bypass */ + clk_write_bypass_mainpll(plat, 0); + clk_write_bypass_perpll(plat, 0); + + /* Out of boot mode */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); + } else { +#ifdef CONFIG_SPL_BUILD + /* Always force clock manager into boot mode before any configuration */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); +#else + /* Skip clock configuration in SSBL if it's not in boot mode */ + if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE)) + return; +#endif + + /* Put both PLLs in bypass */ + clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL); + clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL); + + /* Put both PLLs in Reset and Power Down */ + CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + + /* setup main PLL dividers where calculate the vcocalib value */ + vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob); + CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK, + CLKMGR_MAINPLL_PLLGLOB); + CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK); + CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB); + CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0); + CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1); + CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2); + CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3); + CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM); + CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK); + CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV); + + /* setup peripheral PLL dividers where calculate the vcocalib value */ + vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob); + CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK, + CLKMGR_PERPLL_PLLGLOB); + CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK); + CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB); + CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0); + CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1); + CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2); + CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3); + CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM); + CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL); + CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV); + + /* Configure ping pong counters in control group */ + CM_REG_WRITEL(plat, cfg->ctl_emacactr, CLKMGR_CTL_EMACACTR); + CM_REG_WRITEL(plat, cfg->ctl_emacbctr, CLKMGR_CTL_EMACBCTR); + CM_REG_WRITEL(plat, cfg->ctl_emacptpctr, CLKMGR_CTL_EMACPTPCTR); + CM_REG_WRITEL(plat, cfg->ctl_gpiodbctr, CLKMGR_CTL_GPIODBCTR); + CM_REG_WRITEL(plat, cfg->ctl_s2fuser0ctr, CLKMGR_CTL_S2FUSER0CTR); + CM_REG_WRITEL(plat, cfg->ctl_s2fuser1ctr, CLKMGR_CTL_S2FUSER1CTR); + CM_REG_WRITEL(plat, cfg->ctl_psirefctr, CLKMGR_CTL_PSIREFCTR); + CM_REG_WRITEL(plat, cfg->ctl_usb31ctr, CLKMGR_CTL_USB31CTR); + CM_REG_WRITEL(plat, cfg->ctl_dsuctr, CLKMGR_CTL_DSUCTR); + CM_REG_WRITEL(plat, cfg->ctl_core01ctr, CLKMGR_CTL_CORE01CTR); + CM_REG_WRITEL(plat, cfg->ctl_core23ctr, CLKMGR_CTL_CORE23CTR); + CM_REG_WRITEL(plat, cfg->ctl_core2ctr, CLKMGR_CTL_CORE2CTR); + CM_REG_WRITEL(plat, cfg->ctl_core3ctr, CLKMGR_CTL_CORE3CTR); + + /* Take both PLL out of reset and power up */ + CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + + /* Membus programming for mainpll */ + membus_pll_configs(plat, MEMBUS_MAINPLL); + /* Membus programming for peripll */ + membus_pll_configs(plat, MEMBUS_PERPLL); + + /* Enable Main pll clkslices */ + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC0) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_MAINPLL_PLLC0); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC1) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_MAINPLL_PLLC1); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_MAINPLL_PLLC2); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_MAINPLL_PLLC3); + + /* Enable Periph pll clkslices */ + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC0) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_PERPLL_PLLC0); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC1) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_PERPLL_PLLC1); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_PERPLL_PLLC2); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_PERPLL_PLLC3); + + cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK); + + CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK); + CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK); + + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) | + CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK, + CLKMGR_MAINPLL_PLLGLOB); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) | + CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK, + CLKMGR_PERPLL_PLLGLOB); + + /* Take all PLLs out of bypass */ + clk_write_bypass_mainpll(plat, 0); + clk_write_bypass_perpll(plat, 0); + + /* Clear the loss of lock bits (write 1 to clear) */ + CM_REG_CLRBITS(plat, CLKMGR_INTRCLR, + CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK); + + /* Take all ping pong counters out of reset */ + CM_REG_CLRBITS(plat, CLKMGR_CTL_EXTCNTRST, + CLKMGR_CTL_EXTCNTRST_ALLCNTRST); + + /* Out of boot mode */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); + } +} + +static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat, + u32 pllglob_reg, u32 pllm_reg) +{ + u64 fref, arefdiv, mdiv, reg, vco; + + reg = CM_REG_READL(plat, pllglob_reg); + + fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >> + CLKMGR_PLLGLOB_VCO_PSRC_OFFSET; + + switch (fref) { + case CLKMGR_VCO_PSRC_EOSC1: + fref = cm_get_osc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_INTOSC: + fref = cm_get_intosc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_F2S: + fref = cm_get_fpga_clk_hz(); + break; + } + + arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET; + + mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK; + + vco = fref / arefdiv; + vco = vco * mdiv; + + return vco; +} + +static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat) +{ + return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_MAINPLL_PLLM); +} + +static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat) +{ + return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PERPLL_PLLM); +} + +static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg) +{ + u32 clksrc = CM_REG_READL(plat, reg); + + return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET; +} + +static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg, + u32 main_reg, u32 per_reg) +{ + u64 clock; + u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg); + + switch (clklsrc) { + case CLKMGR_CLKSRC_MAIN: + clock = clk_get_main_vco_clk_hz(plat); + clock /= (CM_REG_READL(plat, main_reg) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_PER: + clock = clk_get_per_vco_clk_hz(plat); + clock /= (CM_REG_READL(plat, per_reg) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + default: + return 0; + } + + return clock; +} + +static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock; + u32 ctr_reg; + u32 cpu = ((read_mpidr() >> MPIDR_AFF1_OFFSET) & MPIDR_AFF1_OFFSET); + + if (cpu > CORE1) { + ctr_reg = CLKMGR_CTL_CORE23CTR; + + clock = clk_get_clksrc_hz(plat, ctr_reg, + CLKMGR_MAINPLL_PLLC0, + CLKMGR_PERPLL_PLLC0); + } else { + ctr_reg = CLKMGR_CTL_CORE01CTR; + + clock = clk_get_clksrc_hz(plat, ctr_reg, + CLKMGR_MAINPLL_PLLC1, + CLKMGR_PERPLL_PLLC0); + } + + if (cpu == CORE3) + ctr_reg = CLKMGR_CTL_CORE3CTR; + else if (cpu == CORE2) + ctr_reg = CLKMGR_CTL_CORE2CTR; + else + ctr_reg = CLKMGR_CTL_CORE01CTR; + + clock /= 1 + (CM_REG_READL(plat, ctr_reg) & + CLKMGR_CLKCNT_MSK); + + return clock; +} + +static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat) +{ + return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK, + CLKMGR_MAINPLL_PLLC3, + CLKMGR_PERPLL_PLLC1); +} + +static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + return clock; +} + +static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4MPCLK_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l4_mp_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_SOFTPHY_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat) +{ + if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE) + return clk_get_l3_main_clk_hz(plat) / 2; + + return clk_get_l3_main_clk_hz(plat) / 4; +} + +static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) +{ + u32 ctl; + u32 ctr_reg; + u32 clock; + u32 div; + u32 reg; + + /* Get EMAC clock source */ + reg = CM_REG_READL(plat, CLKMGR_CTL_EMACACTR); + clock = (reg & CLKMGR_CTL_EMACCTR_SRC_MASK) + >> CLKMGR_CTL_EMACCTR_SRC_OFFSET; + + if (emac_id == AGILEX5_EMAC_PTP_CLK) { + ctr_reg = CLKMGR_CTL_EMACPTPCTR; + } else { + ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); + if (emac_id == AGILEX5_EMAC0_CLK) + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET; + else if (emac_id == AGILEX5_EMAC1_CLK) + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET; + else if (emac_id == AGILEX5_EMAC2_CLK) + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET; + else + return 0; + + if (ctl) { + /* EMAC B source */ + ctr_reg = CLKMGR_CTL_EMACBCTR; + } else { + /* EMAC A source */ + ctr_reg = CLKMGR_CTL_EMACACTR; + } + } + + reg = CM_REG_READL(plat, ctr_reg); + div = (reg & CLKMGR_CTL_EMACCTR_CNT_MASK) + >> CLKMGR_CTL_EMACCTR_CNT_OFFSET; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = clk_get_main_vco_clk_hz(plat); + + clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC1) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_PER: + clock = clk_get_per_vco_clk_hz(plat); + + clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + + clock /= 1 + div; + + return clock; +} + +static ulong socfpga_clk_get_rate(struct clk *clk) +{ + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + + switch (clk->id) { + case AGILEX5_MPU_CLK: + return clk_get_mpu_clk_hz(plat); + case AGILEX5_L4_MAIN_CLK: + return clk_get_l4_main_clk_hz(plat); + case AGILEX5_L4_SYS_FREE_CLK: + return clk_get_l4_sys_free_clk_hz(plat); + case AGILEX5_L4_MP_CLK: + return clk_get_l4_mp_clk_hz(plat); + case AGILEX5_L4_SP_CLK: + return clk_get_l4_sp_clk_hz(plat); + case AGILEX5_SDMMC_CLK: + case AGILEX5_NAND_CLK: + return clk_get_sdmmc_clk_hz(plat); + case AGILEX5_EMAC0_CLK: + case AGILEX5_EMAC1_CLK: + case AGILEX5_EMAC2_CLK: + case AGILEX5_EMAC_PTP_CLK: + return clk_get_emac_clk_hz(plat, clk->id); + case AGILEX5_USB_CLK: + case AGILEX5_NAND_X_CLK: + return clk_get_l4_mp_clk_hz(plat); + default: + return -ENXIO; + } +} + +static int socfpga_clk_enable(struct clk *clk) +{ + return 0; +} + +static int socfpga_clk_probe(struct udevice *dev) +{ + const struct cm_config *cm_default_cfg = cm_get_default_config(); + + clk_basic_init(dev, cm_default_cfg); + + return 0; +} + +static int socfpga_clk_of_to_plat(struct udevice *dev) +{ + struct socfpga_clk_plat *plat = dev_get_plat(dev); + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->regs = (void __iomem *)addr; + + return 0; +} + +static struct clk_ops socfpga_clk_ops = { + .enable = socfpga_clk_enable, + .get_rate = socfpga_clk_get_rate, +}; + +static const struct udevice_id socfpga_clk_match[] = { + { .compatible = "intel,agilex5-clkmgr" }, + {} +}; + +U_BOOT_DRIVER(socfpga_agilex5_clk) = { + .name = "clk-agilex5", + .id = UCLASS_CLK, + .of_match = socfpga_clk_match, + .ops = &socfpga_clk_ops, + .probe = socfpga_clk_probe, + .of_to_plat = socfpga_clk_of_to_plat, + .plat_auto = sizeof(struct socfpga_clk_plat), +}; diff --git a/drivers/clk/altera/clk-agilex5.h b/drivers/clk/altera/clk-agilex5.h new file mode 100644 index 0000000000..27124a5574 --- /dev/null +++ b/drivers/clk/altera/clk-agilex5.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + */ + +#ifndef _CLK_AGILEX5_ +#define _CLK_AGILEX5_ + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +#define CM_REG_READL(plat, reg) \ + readl((plat)->regs + (reg)) + +#define CM_REG_WRITEL(plat, data, reg) \ + writel(data, (plat)->regs + (reg)) + +#define CM_REG_CLRBITS(plat, reg, clear) \ + clrbits_le32((plat)->regs + (reg), (clear)) + +#define CM_REG_SETBITS(plat, reg, set) \ + setbits_le32((plat)->regs + (reg), (set)) + +struct cm_config { + /* main group */ + u32 main_pll_nocclk; + u32 main_pll_nocdiv; + u32 main_pll_pllglob; + u32 main_pll_fdbck; + u32 main_pll_pllc0; + u32 main_pll_pllc1; + u32 main_pll_pllc2; + u32 main_pll_pllc3; + u32 main_pll_pllm; + + /* peripheral group */ + u32 per_pll_emacctl; + u32 per_pll_gpiodiv; + u32 per_pll_pllglob; + u32 per_pll_fdbck; + u32 per_pll_pllc0; + u32 per_pll_pllc1; + u32 per_pll_pllc2; + u32 per_pll_pllc3; + u32 per_pll_pllm; + + /* control group */ + u32 ctl_emacactr; + u32 ctl_emacbctr; + u32 ctl_emacptpctr; + u32 ctl_gpiodbctr; + u32 ctl_s2fuser0ctr; + u32 ctl_s2fuser1ctr; + u32 ctl_psirefctr; + u32 ctl_usb31ctr; + u32 ctl_dsuctr; + u32 ctl_core01ctr; + u32 ctl_core23ctr; + u32 ctl_core2ctr; + u32 ctl_core3ctr; + + /* incoming clock */ + u32 hps_osc_clk_hz; + u32 fpga_clk_hz; + u32 spare[3]; +}; + +/* Clock Manager registers */ +#define CLKMGR_CTRL 0 +#define CLKMGR_STAT 4 +#define CLKMGR_TESTIOCTRL 8 +#define CLKMGR_INTRGEN 0x0c +#define CLKMGR_INTRMSK 0x10 +#define CLKMGR_INTRCLR 0x14 +#define CLKMGR_INTRSTS 0x18 +#define CLKMGR_INTRSTK 0x1c +#define CLKMGR_INTRRAW 0x20 + +/* Clock Manager Main PPL group registers */ +#define CLKMGR_MAINPLL_EN 0x24 +#define CLKMGR_MAINPLL_ENS 0x28 +#define CLKMGR_MAINPLL_ENR 0x2c +#define CLKMGR_MAINPLL_BYPASS 0x30 +#define CLKMGR_MAINPLL_BYPASSS 0x34 +#define CLKMGR_MAINPLL_BYPASSR 0x38 +#define CLKMGR_MAINPLL_NOCCLK 0x40 +#define CLKMGR_MAINPLL_NOCDIV 0x44 +#define CLKMGR_MAINPLL_PLLGLOB 0x48 +#define CLKMGR_MAINPLL_FDBCK 0x4c +#define CLKMGR_MAINPLL_MEM 0x50 +#define CLKMGR_MAINPLL_MEMSTAT 0x54 +#define CLKMGR_MAINPLL_VCOCALIB 0x58 +#define CLKMGR_MAINPLL_PLLC0 0x5c +#define CLKMGR_MAINPLL_PLLC1 0x60 +#define CLKMGR_MAINPLL_PLLC2 0x64 +#define CLKMGR_MAINPLL_PLLC3 0x68 +#define CLKMGR_MAINPLL_PLLM 0x6c +#define CLKMGR_MAINPLL_FHOP 0x70 +#define CLKMGR_MAINPLL_SSC 0x74 +#define CLKMGR_MAINPLL_LOSTLOCK 0x78 + +/* Clock Manager Peripheral PPL group registers */ +#define CLKMGR_PERPLL_EN 0x7c +#define CLKMGR_PERPLL_ENS 0x80 +#define CLKMGR_PERPLL_ENR 0x84 +#define CLKMGR_PERPLL_BYPASS 0x88 +#define CLKMGR_PERPLL_BYPASSS 0x8c +#define CLKMGR_PERPLL_BYPASSR 0x90 +#define CLKMGR_PERPLL_EMACCTL 0x94 +#define CLKMGR_PERPLL_GPIODIV 0x98 +#define CLKMGR_PERPLL_PLLGLOB 0x9c +#define CLKMGR_PERPLL_FDBCK 0xa0 +#define CLKMGR_PERPLL_MEM 0xa4 +#define CLKMGR_PERPLL_MEMSTAT 0xa8 +#define CLKMGR_PERPLL_VCOCALIB 0xac +#define CLKMGR_PERPLL_PLLC0 0xb0 +#define CLKMGR_PERPLL_PLLC1 0xb4 +#define CLKMGR_PERPLL_PLLC2 0xb8 +#define CLKMGR_PERPLL_PLLC3 0xbc +#define CLKMGR_PERPLL_PLLM 0xc0 +#define CLKMGR_PERPLL_FHOP 0xc4 +#define CLKMGR_PERPLL_SSC 0xc8 +#define CLKMGR_PERPLL_LOSTLOCK 0xcc + +/* Clock Manager Control group registers */ +#define CLKMGR_CTL_JTAG 0xd0 +#define CLKMGR_CTL_EMACACTR 0xd4 +#define CLKMGR_CTL_EMACBCTR 0xd8 +#define CLKMGR_CTL_EMACPTPCTR 0xdc +#define CLKMGR_CTL_GPIODBCTR 0xe0 +#define CLKMGR_CTL_S2FUSER0CTR 0xe8 +#define CLKMGR_CTL_S2FUSER1CTR 0xec +#define CLKMGR_CTL_PSIREFCTR 0xf0 +#define CLKMGR_CTL_EXTCNTRST 0xf4 +#define CLKMGR_CTL_USB31CTR 0xf8 +#define CLKMGR_CTL_DSUCTR 0xfc +#define CLKMGR_CTL_CORE01CTR 0x100 +#define CLKMGR_CTL_CORE23CTR 0x104 +#define CLKMGR_CTL_CORE2CTR 0x108 +#define CLKMGR_CTL_CORE3CTR 0x10C + +#define CLKMGR_CTRL_BOOTMODE BIT(0) + +#define CLKMGR_STAT_BUSY BIT(0) +#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8) +#define CLKMGR_STAT_MAIN_TRANS BIT(9) +#define CLKMGR_STAT_PERPLL_LOCKED BIT(16) +#define CLKMGR_STAT_PERF_TRANS BIT(17) +#define CLKMGR_STAT_BOOTMODE BIT(24) +#define CLKMGR_STAT_BOOTCLKSRC BIT(25) + +#define CLKMGR_STAT_ALLPLL_LOCKED_MASK \ + (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED) + +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008 + +#define CLKMGR_CLKSRC_MASK GENMASK(18, 16) +#define CLKMGR_CLKSRC_OFFSET 16 +#define CLKMGR_CLKSRC_MAIN 0 +#define CLKMGR_CLKSRC_PER 1 +#define CLKMGR_CLKSRC_OSC1 2 +#define CLKMGR_CLKSRC_INTOSC 3 +#define CLKMGR_CLKSRC_FPGA 4 +#define CLKMGR_CLKCNT_MSK GENMASK(10, 0) + +#define CLKMGR_BYPASS_MAINPLL_ALL 0xf6 +#define CLKMGR_BYPASS_PERPLL_ALL 0xef + +#define CLKMGR_NOCDIV_SOFTPHY_DIV_ONE 0 +#define CLKMGR_NOCDIV_SOFTPHY_DIV_TWO 1 +#define CLKMGR_NOCDIV_SOFTPHY_DIV_FOUR 2 +#define CLKMGR_NOCDIV_L4SYSFREECLK_OFFSET 0 +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 4 +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 6 +#define CLKMGR_NOCDIV_SOFTPHY_OFFSET 16 +#define CLKMGR_NOCDIV_CCU_OFFSET 18 +#define CLKMGR_NOCDIV_MPUPERIPH_OFFSET 20 +#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24 +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 +#define CLKMGR_NOCDIV_DIVIDER_MASK 0x3 + +#define CLKMGR_PLLGLOB_PD_MASK BIT(0) +#define CLKMGR_PLLGLOB_RST_MASK BIT(1) +#define CLKMGR_PLLGLOB_AREFCLKDIV_MASK GENMASK(11, 8) +#define CLKMGR_PLLGLOB_DREFCLKDIV_MASK GENMASK(13, 12) +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK GENMASK(13, 8) +#define CLKMGR_PLLGLOB_MODCLKDIV_MASK GENMASK(24, 27) +#define CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET 8 +#define CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET 12 +#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 +#define CLKMGR_PLLGLOB_MODCLKDIV_OFFSET 24 +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16) +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 +#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29) + +#define CLKMGR_VCO_PSRC_EOSC1 0 +#define CLKMGR_VCO_PSRC_INTOSC 1 +#define CLKMGR_VCO_PSRC_F2S 2 + +#define CLKMGR_MEM_REQ_SET_MSK BIT(24) +#define CLKMGR_MEM_WR_SET_MSK BIT(25) +#define CLKMGR_MEM_ERR_MSK BIT(26) +#define CLKMGR_MEM_WDAT_LSB_OFFSET 16 +#define CLKMGR_MEM_ADDR_MASK GENMASK(15, 0) +#define CLKMGR_MEM_ADDR_START 0x00004000 + +#define CLKMGR_PLLCX_EN_SET_MSK BIT(27) +#define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28) + +#define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16) +#define CLKMGR_VCOCALIB_MSCNT_OFFSET 16 +#define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0) +#define CLKMGR_VCOCALIB_MSCNT_CONST 100 +#define CLKMGR_VCOCALIB_HSCNT_CONST 4 + +#define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0) + +#define CLKMGR_LOSTLOCK_SET_MASK BIT(0) + +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28) + +#define CLKMGR_CTL_EMACCTR_SRC_OFFSET 16 +#define CLKMGR_CTL_EMACCTR_SRC_MASK GENMASK(18, 16) +#define CLKMGR_CTL_EMACCTR_CNT_OFFSET 0 +#define CLKMGR_CTL_EMACCTR_CNT_MASK GENMASK(10, 0) + +#define CLKMGR_CTL_EXTCNTRST_EMACACNTRST BIT(0) +#define CLKMGR_CTL_EXTCNTRST_EMACBCNTRST BIT(1) +#define CLKMGR_CTL_EXTCNTRST_EMACPTPCNTRST BIT(2) +#define CLKMGR_CTL_EXTCNTRST_GPIODBCNTRST BIT(3) +#define CLKMGR_CTL_EXTCNTRST_S2FUSER0CNTRST BIT(5) +#define CLKMGR_CTL_EXTCNTRST_S2FUSER1CNTRST BIT(6) +#define CLKMGR_CTL_EXTCNTRST_PSIREFCNTRST BIT(7) +#define CLKMGR_CTL_EXTCNTRST_USB31REFCNTRST BIT(8) +#define CLKMGR_CTL_EXTCNTRST_DSUCNTRST BIT(10) +#define CLKMGR_CTL_EXTCNTRST_CORE01CNTRST BIT(11) +#define CLKMGR_CTL_EXTCNTRST_CORE2CNTRST BIT(12) +#define CLKMGR_CTL_EXTCNTRST_CORE3CNTRST BIT(13) +#define CLKMGR_CTL_EXTCNTRST_ALLCNTRST \ + (CLKMGR_CTL_EXTCNTRST_EMACACNTRST | \ + CLKMGR_CTL_EXTCNTRST_EMACBCNTRST | \ + CLKMGR_CTL_EXTCNTRST_EMACPTPCNTRST | \ + CLKMGR_CTL_EXTCNTRST_GPIODBCNTRST | \ + CLKMGR_CTL_EXTCNTRST_S2FUSER0CNTRST | \ + CLKMGR_CTL_EXTCNTRST_S2FUSER1CNTRST | \ + CLKMGR_CTL_EXTCNTRST_PSIREFCNTRST | \ + CLKMGR_CTL_EXTCNTRST_USB31REFCNTRST | \ + CLKMGR_CTL_EXTCNTRST_DSUCNTRST | \ + CLKMGR_CTL_EXTCNTRST_CORE01CNTRST | \ + CLKMGR_CTL_EXTCNTRST_CORE2CNTRST | \ + CLKMGR_CTL_EXTCNTRST_CORE3CNTRST) +#endif /* _CLK_AGILEX5_ */
This is for new platform enablement for agilex5. Update secure registers, Kconfig and makefile for new platform.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/misc/Kconfig | 9 +++ drivers/misc/Makefile | 1 + drivers/misc/socfpga_secreg.c | 116 ++++++++++++++++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 drivers/misc/socfpga_secreg.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 04460f1acb..3b6f5314ff 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -666,4 +666,13 @@ config SL28CPLD the base driver which provides common access methods for the sub-drivers.
+config SPL_SOCFPGA_SEC_REG + bool "Enable register setting from device tree in SPL" + depends on SPL + help + Enable register setting from device tree in SPL, which require + high privilege access like firewall registers. This also + provides user a clean interface and all register settings are + centralized in one place, device tree. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 52aed09602..441c03509f 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -88,3 +88,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o +obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_secreg.o diff --git a/drivers/misc/socfpga_secreg.c b/drivers/misc/socfpga_secreg.c new file mode 100644 index 0000000000..3f3ba8b0c1 --- /dev/null +++ b/drivers/misc/socfpga_secreg.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2023 Intel Corporation <www.intel.com> + */ + +#include <asm/io.h> +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <linux/sizes.h> + +#define NUMBER_OF_ELEMENTS 3 + +static int socfpga_secreg_probe(struct udevice *dev) +{ + const fdt32_t *list; + fdt_addr_t offset, base; + fdt_val_t val, read_val, mask, set_mask; + int size, i; + u32 blk_sz, reg; + ofnode node; + const char *name = NULL; + + debug("%s(dev=%p)\n", __func__, dev); + + if (!dev_has_ofnode(dev)) + return 0; + + dev_for_each_subnode(node, dev) { + name = ofnode_get_name(node); + if (!name) + return -EINVAL; + + if (ofnode_read_u32_index(node, "reg", 1, &blk_sz)) + return -EINVAL; + + base = ofnode_get_addr(node); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + debug("%s(node_offset 0x%lx node_name %s ", __func__, + node.of_offset, name); + debug("node addr 0x%llx blk sz 0x%x)\n", base, blk_sz); + + list = ofnode_read_prop(node, "intel,offset-settings", &size); + if (!list) + return -EINVAL; + + debug("%s(intel,offset-settings property size=%x)\n", __func__, + size); + size /= sizeof(*list) * NUMBER_OF_ELEMENTS; + + /* + * First element: offset + * Second element: val + * Third element: mask + */ + for (i = 0; i < size; i++) { + offset = fdt32_to_cpu(*list++); + val = fdt32_to_cpu(*list++); + + /* Reads the masking bit value from the list */ + mask = fdt32_to_cpu(*list++); + + /* + * Reads out the offsets, value and masking bits + * Ex: <0x00000000 0x00000230 0xffffffff> + */ + debug("%s(intel,offset-settings 0x%llx : 0x%llx : 0x%llx)\n", + __func__, offset, val, mask); + + if (blk_sz < offset + SZ_4) { + printf("%s: Overflow as offset 0x%llx or reg", + __func__, offset); + printf(" write is more than block size 0x%x\n", + blk_sz); + return -EINVAL; + } + + if (mask != 0) { + if (mask == 0xffffffff) { + reg = base + offset; + writel(val, (uintptr_t)reg); + } else { + /* Mask the value with the masking bits */ + set_mask = val & mask; + + reg = base + offset; + + /* Clears and sets specific bits in the register */ + clrsetbits_le32((uintptr_t)reg, mask, set_mask); + } + } + + read_val = readl((uintptr_t)reg); + + /* Reads out the register, masked value and the read value */ + debug("%s(reg 0x%x = wr : 0x%llx rd : 0x%llx)\n", + __func__, reg, set_mask, read_val); + } + } + + return 0; +}; + +static const struct udevice_id socfpga_secreg_ids[] = { + {.compatible = "intel,socfpga-secreg"}, + { } +}; + +U_BOOT_DRIVER(socfpga_secreg) = { + .name = "socfpga-secreg", + .id = UCLASS_NOP, + .of_match = socfpga_secreg_ids, + .probe = socfpga_secreg_probe, +};
This is for new platform enablement for agilex5. Add mmc and cadence host driver for new platform.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/mmc/mmc.c | 27 +++--- drivers/mmc/sdhci-cadence.c | 164 ++++++++++++++++++++++++++++++++---- 2 files changed, 160 insertions(+), 31 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 1af6af82e6..88c674d44f 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -26,6 +26,7 @@ #include <div64.h> #include "mmc_private.h"
+#define TIMEOUT_TEN_MS 10 #define DEFAULT_CMD6_TIMEOUT_MS 500
static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); @@ -247,7 +248,7 @@ static int mmc_send_cmd_retry(struct mmc *mmc, struct mmc_cmd *cmd, static int mmc_send_cmd_quirks(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data, u32 quirk, uint retries) { - if (IS_ENABLED(CONFIG_MMC_QUIRKS) && mmc->quirks & quirk) + if (CONFIG_IS_ENABLED(MMC_QUIRKS) && mmc->quirks & quirk) return mmc_send_cmd_retry(mmc, cmd, data, retries); else return mmc_send_cmd(mmc, cmd, data); @@ -597,6 +598,11 @@ static int sd_send_op_cond(struct mmc *mmc, bool uhs_en) int err; struct mmc_cmd cmd;
+ /* lower timeout, to speed up mmc init since both uses same flow */ + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU) || + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS)) + timeout = TIMEOUT_TEN_MS; + while (1) { cmd.cmdidx = MMC_CMD_APP_CMD; cmd.resp_type = MMC_RSP_R1; @@ -635,7 +641,7 @@ static int sd_send_op_cond(struct mmc *mmc, bool uhs_en) break;
if (timeout-- <= 0) - return -EOPNOTSUPP; + return -ETIMEDOUT;
udelay(1000); } @@ -2432,9 +2438,6 @@ static int mmc_startup_v4(struct mmc *mmc)
mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
- mmc->can_trim = - !!(ext_csd[EXT_CSD_SEC_FEATURE] & EXT_CSD_SEC_FEATURE_TRIM_EN); - return 0; error: if (mmc->ext_csd) { @@ -3130,10 +3133,9 @@ int mmc_init_device(int num) #endif
#ifdef CONFIG_CMD_BKOPS_ENABLE -int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable) +int mmc_set_bkops_enable(struct mmc *mmc) { int err; - u32 bit = autobkops ? BIT(1) : BIT(0); ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
err = mmc_send_ext_csd(mmc, ext_csd); @@ -3147,21 +3149,18 @@ int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable) return -EMEDIUMTYPE; }
- if (enable && (ext_csd[EXT_CSD_BKOPS_EN] & bit)) { + if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) { puts("Background operations already enabled\n"); return 0; }
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, - enable ? bit : 0); + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1); if (err) { - printf("Failed to %sable manual background operations\n", - enable ? "en" : "dis"); + puts("Failed to enable manual background operations\n"); return err; }
- printf("%sabled %s background operations\n", - enable ? "En" : "Dis", autobkops ? "auto" : "manual"); + puts("Enabled manual background operations\n");
return 0; } diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 327a05ad11..4154fd33da 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -5,7 +5,10 @@ */
#include <common.h> +#include <clk.h> #include <dm.h> +#include <generic-phy.h> +#include <asm/arch/clock_manager.h> #include <asm/global_data.h> #include <dm/device_compat.h> #include <linux/bitfield.h> @@ -16,10 +19,15 @@ #include <linux/sizes.h> #include <linux/libfdt.h> #include <mmc.h> +#include <reset-uclass.h> #include <sdhci.h>
+/* General define */ +#define SD_MIN_CLK 400000 + /* HRS - Host Register Set (specific to Cadence) */ #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ +#define SDHCI_CDNS_HRS05 0x14 /* PHY data access port */ #define SDHCI_CDNS_HRS04_ACK BIT(26) #define SDHCI_CDNS_HRS04_RD BIT(25) #define SDHCI_CDNS_HRS04_WR BIT(24) @@ -66,6 +74,16 @@ struct sdhci_cdns_plat { struct mmc_config cfg; struct mmc mmc; void __iomem *hrs_addr; + struct udevice *udev; + struct phy phy_dev; + bool phy_enabled; + struct reset_ctl softreset_ctl; +}; + +/* socfpga implementation specific driver private data */ +struct sdhci_socfpga_priv_data { + struct sdhci_host host; + struct phy phy; };
struct sdhci_cdns_phy_cfg { @@ -94,25 +112,45 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, u32 tmp; int ret;
- tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | - FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + if (plat->phy_enabled) { + /* retrieve reg. addr */ + tmp = FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
- tmp |= SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + ret = writel(tmp, reg); + debug("%s: register = 0x%08x\n", __func__, readl(reg));
- ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10); - if (ret) - return ret; + /* read existing value, mask it */ + reg = plat->hrs_addr + SDHCI_CDNS_HRS05; + tmp = readl(reg); + debug("%s: register = 0x%08x\n", __func__, readl(reg));
- tmp &= ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + tmp &= ~data; + tmp |= data; + + /* write operation */ + ret = writel(tmp, reg); + debug("%s: register = 0x%08x\n", __func__, readl(reg)); + } else { + tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | + FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); + writel(tmp, reg); + + tmp |= SDHCI_CDNS_HRS04_WR; + writel(tmp, reg); + + ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10); + if (ret) + return ret; + + tmp &= ~SDHCI_CDNS_HRS04_WR; + writel(tmp, reg); + }
return 0; }
static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat, - const void *fdt, int nodeoffset) + const void *fdt, int nodeoffset) { const fdt32_t *prop; int ret, i; @@ -126,6 +164,7 @@ static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat, ret = sdhci_cdns_write_phy_reg(plat, sdhci_cdns_phy_cfgs[i].addr, fdt32_to_cpu(*prop)); + if (ret) return ret; } @@ -162,7 +201,14 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host *host) tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06); tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); + writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06); + debug("%s: register = 0x%x\n", __func__, + readl(plat->hrs_addr + SDHCI_CDNS_HRS06)); + + /* program phy based on generated settings, input through device tree */ + if (plat->phy_enabled) + generic_phy_configure(&plat->phy_dev, NULL); }
static const struct sdhci_ops sdhci_cdns_ops = { @@ -192,6 +238,8 @@ static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, tmp |= SDHCI_CDNS_HRS06_TUNE_UP; writel(tmp, reg);
+ debug("%s: register = 0x%08x\n", __func__, readl(reg)); + ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), 1); if (ret) @@ -252,15 +300,49 @@ static int sdhci_cdns_bind(struct udevice *dev) return sdhci_bind(dev, &plat->mmc, &plat->cfg); }
+static int socfpga_sdhci_get_clk_rate(struct udevice *dev) +{ + struct sdhci_socfpga_priv_data *priv = dev_get_priv(dev); + struct sdhci_host *host = &priv->host; + +#if (IS_ENABLED(CONFIG_CLK)) + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, 1, &clk); + if (ret) + return ret; + + host->max_clk = clk_get_rate(&clk); + + clk_free(&clk); +#else + /* Fixed clock divide by 4 which due to the SDMMC wrapper */ + host->max_clk = cm_get_mmc_controller_clk_hz(); +#endif + + if (!host->max_clk) { + debug("SDHCI: MMC clock is zero!"); + return -EINVAL; + } + debug("max_clk: %d\n", host->max_clk); + + return 0; +} + static int sdhci_cdns_probe(struct udevice *dev) { DECLARE_GLOBAL_DATA_PTR; struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_cdns_plat *plat = dev_get_plat(dev); - struct sdhci_host *host = dev_get_priv(dev); + struct sdhci_socfpga_priv_data *priv = dev_get_priv(dev); + struct sdhci_host *host = &priv->host; + const char *phy_name = dev_read_string(dev, "phy-names"); fdt_addr_t base; int ret;
+ plat->phy_enabled = false; + base = dev_read_addr(dev); if (base == FDT_ADDR_T_NONE) return -EINVAL; @@ -269,6 +351,43 @@ static int sdhci_cdns_probe(struct udevice *dev) if (!plat->hrs_addr) return -ENOMEM;
+ if (!phy_name) + return -EINVAL; + + /* get SDMMC softreset */ + ret = reset_get_by_name(dev, "reset", &plat->softreset_ctl); + if (ret) + pr_err("can't get soft reset for %s (%d)", dev->name, ret); + + /* assert & deassert softreset */ + ret = reset_assert(&plat->softreset_ctl); + if (ret < 0) { + pr_err("SDMMC soft reset deassert failed: %d", ret); + return ret; + } + + ret = reset_deassert(&plat->softreset_ctl); + if (ret < 0) { + pr_err("SDMMC soft reset deassert failed: %d", ret); + return ret; + } + + /* probe ComboPHY */ + ret = generic_phy_get_by_name(dev, "combo-phy", &plat->phy_dev); + if (ret) { + printf("ComboPHY probe failed: %d\n", ret); + return ret; + } + debug("ComboPHY probe success\n"); + + ret = generic_phy_init(&plat->phy_dev); + if (ret) { + printf("ComboPHY init failed: %d\n", ret); + return ret; + } + debug("ComboPHY init success\n"); + + plat->phy_enabled = true; host->name = dev->name; host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE; host->ops = &sdhci_cdns_ops; @@ -282,18 +401,29 @@ static int sdhci_cdns_probe(struct udevice *dev) if (ret) return ret;
- ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev)); + /* get max clk */ + ret = socfpga_sdhci_get_clk_rate(dev); if (ret) return ret;
- host->mmc = &plat->mmc; - host->mmc->dev = dev; - ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); + ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev)); if (ret) return ret;
+ host->mmc = &plat->mmc; upriv->mmc = &plat->mmc; host->mmc->priv = host; + host->mmc->dev = dev; + +#if (IS_ENABLED(CONFIG_BLK)) + ret = sdhci_setup_cfg(&plat->cfg, host, host->max_clk, SD_MIN_CLK); + if (ret) + return ret; +#else + ret = add_sdhci(host, host->max_clk, SD_MIN_CLK); + if (ret) + return ret; +#endif
return sdhci_probe(dev); } @@ -310,7 +440,7 @@ U_BOOT_DRIVER(sdhci_cdns) = { .of_match = sdhci_cdns_match, .bind = sdhci_cdns_bind, .probe = sdhci_cdns_probe, - .priv_auto = sizeof(struct sdhci_host), + .priv_auto = sizeof(struct sdhci_socfpga_priv_data), .plat_auto = sizeof(struct sdhci_cdns_plat), .ops = &sdhci_cdns_mmc_ops, };
This is for new platform enablement for agilex5. Add combo phy driver for new platform.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/phy/cadence/Kconfig | 9 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-combophy.c | 855 +++++++++++++++++++++ 3 files changed, 865 insertions(+) create mode 100644 drivers/phy/cadence/phy-cadence-combophy.c
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 549ddbf504..61d1b36be2 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -1,3 +1,12 @@ +config PHY_CADENCE_COMBOPHY + tristate "Cadence ComboPhy PHY Driver" + depends on MMC_SDHCI_CADENCE + help + Enable this to support the Cadence ComboPhy PHY driver + A single module that encapsulates all functionality required to interface + to external NAND Flash, eMMC devices, and SD cards for command and data + transfer. + config PHY_CADENCE_SIERRA tristate "Cadence Sierra PHY Driver" depends on DM_RESET diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile index af63b32d9f..3092b9f3b8 100644 --- a/drivers/phy/cadence/Makefile +++ b/drivers/phy/cadence/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_$(SPL_)PHY_CADENCE_SIERRA) += phy-cadence-sierra.o obj-$(CONFIG_$(SPL_)PHY_CADENCE_TORRENT) += phy-cadence-torrent.o +obj-$(CONFIG_PHY_CADENCE_COMBOPHY) += phy-cadence-combophy.o diff --git a/drivers/phy/cadence/phy-cadence-combophy.c b/drivers/phy/cadence/phy-cadence-combophy.c new file mode 100644 index 0000000000..c49c45e5a0 --- /dev/null +++ b/drivers/phy/cadence/phy-cadence-combophy.c @@ -0,0 +1,855 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cadence COMBOPHY PHY Driver + * + * Based on the linux driver provided by Cadence Sierra + * + * Copyright (c) 2022 - 2023 Intel Corporation + * Author: Lee, Kah Jing kah.jing.lee@intel.com + * + */ + +#include <clk.h> +#include <common.h> +#include <generic-phy.h> +#include <reset.h> +#include <reset-uclass.h> +#include <wait_bit.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <dm/devres.h> +#include <dm/lists.h> +#include <dm/read.h> +#include <dm/uclass.h> +#include <dt-bindings/phy/phy.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h> + +/* PHY register offsets */ +/* General define */ +#define BIT_ZERO 0 +#define BIT_ONE 1 +#define SD_HOST_CLK 200000000 + +/* SDIO Card UHS-I modes */ +#define SDIO_MODE_SDR12 0 +#define SDIO_MODE_SDR25 1 +#define SDIO_MODE_SDR50 2 +#define SDIO_MODE_SDR104 3 +#define SDIO_MODE_DDR50 4 +#define SD_MODE_HS 5 + +/* eMMC modes */ +#define eMMC_MODE_SDR 0 +#define eMMC_MODE_HS 1 +#define eMMC_MODE_HS200 2 +#define eMMC_MODE_HS400 3 +/* SW_RESET_REG */ +#define SDHCI_CDNS_HRS00 0x00 +#define SDHCI_CDNS_HRS00_SWR BIT(0) +/* PHY access port */ +#define SDHCI_CDNS_HRS04 0x10 +#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0) +/* PHY data access port */ +#define SDHCI_CDNS_HRS05 0x14 +/* eMMC control registers */ +#define SDHCI_CDNS_HRS06 0x18 + +#define READ_OP 0 +#define WRITE_OP 1 +#define READ_WRITE_OP 2 +#define POLLING_OP 3 +#define READ_PHY_OP 4 +#define READ_WRITE_PHY_OP 5 + +#define PHY_TYPE_NAND 0 +#define PHY_TYPE_SDMMC 1 +#define PHY_REG_LEN 15 +/* IO_DELAY_INFO_REG */ +#define SDHCI_CDNS_HRS07 0x1c +#define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16) +#define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0) +/* TODO: check DV dfi_init val=9 */ +#define SDHCI_CDNS_HRS07_RW_COMPENSATE_DATA 0x9 +/* TODO: check DV dfi_init val=8; DDR Mode */ +#define SDHCI_CDNS_HRS07_RW_COMPENSATE_DATA_DDR 0x8 +#define SDHCI_CDNS_HRS07_IDELAY_VAL_DATA 0x0 +/* PHY reset port */ +#define SDHCI_CDNS_HRS09 0x24 +#define SDHCI_CDNS_HRS09_PHY_SW_RESET BIT(0) +#define SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE BIT(1) +#define SDHCI_CDNS_HRS09_EXTENDED_RD_MODE BIT(2) +#define SDHCI_CDNS_HRS09_EXTENDED_WR_MODE BIT(3) +#define SDHCI_CDNS_HRS09_RDCMD_EN BIT(15) +#define SDHCI_CDNS_HRS09_RDDATA_EN BIT(16) + +/* PHY reset port */ +#define SDHCI_CDNS_HRS10 0x28 +#define SDHCI_CDNS_HRS10_HCSDCLKADJ GENMASK(19, 16) +#define SDHCI_CDNS_HRS10_HCSDCLKADJ_DATA 0x0 +/* HCSDCLKADJ DATA; DDR Mode */ +#define SDHCI_CDNS_HRS10_HCSDCLKADJ_DATA_DDR 0x2 + +/* CMD_DATA_OUTPUT */ +#define SDHCI_CDNS_HRS16 0x40 +#define SDHCI_CDNS_HRS16_WRDATA1_SDCLK_DLY GENMASK(31, 28) +#define SDHCI_CDNS_HRS16_WRDATA0_SDCLK_DLY GENMASK(27, 24) +#define SDHCI_CDNS_HRS16_WRCMD1_SDCLK_DLY GENMASK(23, 20) +#define SDHCI_CDNS_HRS16_WRCMD0_SDCLK_DLY GENMASK(19, 16) +#define SDHCI_CDNS_HRS16_WRDATA1_DLY GENMASK(15, 12) +#define SDHCI_CDNS_HRS16_WRDATA0_DLY GENMASK(11, 8) +#define SDHCI_CDNS_HRS16_WRCMD1_DLY GENMASK(7, 4) +#define SDHCI_CDNS_HRS16_WRCMD0_DLY GENMASK(3, 0) +#define SDHCI_CDNS_HRS16_WRDATA1_SDCLK_DLY_DATA 0x0 +#define SDHCI_CDNS_HRS16_WRDATA1_SDCLK_DLY_DATA_DDR 0x1 +#define SDHCI_CDNS_HRS16_WRDATA0_SDCLK_DLY_DATA 0x0 +#define SDHCI_CDNS_HRS16_WRDATA0_SDCLK_DLY_DATA_DDR 0x1 +#define SDHCI_CDNS_HRS16_WRCMD1_SDCLK_DLY_DATA 0x0 +#define SDHCI_CDNS_HRS16_WRCMD0_SDCLK_DLY_DATA 0x0 +#define SDHCI_CDNS_HRS16_WRDATA1_DLY_DATA 0x0 +/* TODO: check DV dfi_init val=1 */ +#define SDHCI_CDNS_HRS16_WRDATA0_DLY_DATA 0x1 +#define SDHCI_CDNS_HRS16_WRCMD1_DLY_DATA 0x0 +/* TODO: check DV dfi_init val=1 */ +#define SDHCI_CDNS_HRS16_WRCMD0_DLY_DATA 0x1 + +/* SRS - Slot Register Set (SDHCI-compatible) */ +#define SDHCI_CDNS_SRS_BASE 0x200 +#define SDHCI_CDNS_SRS00 0x200 +#define SDHCI_CDNS_SRS01 0x204 +#define SDHCI_CDNS_SRS02 0x208 +#define SDHCI_CDNS_SRS03 0x20c +#define SDHCI_CDNS_SRS04 0x210 +#define SDHCI_CDNS_SRS08 0x220 +#define SDHCI_CDNS_SRS09 0x224 +#define SDHCI_CDNS_SRS09_CI BIT(16) +#define SDHCI_CDNS_SRS10 0x228 +#define SDHCI_CDNS_SRS10_VOLT_ON FIELD_PREP(GENMASK(11, 9), BIT_ONE)\ + | FIELD_PREP(BIT(8), BIT_ONE) | FIELD_PREP(BIT(0), BIT_ZERO) +#define SDHCI_CDNS_SRS10_VOLT_OFF FIELD_PREP(GENMASK(11, 9), BIT_ONE)\ + | FIELD_PREP(BIT(8), BIT_ZERO) + +#define SDHCI_CDNS_SRS11 0x22c +#define SDHCI_CDNS_SRS11_RST 0x0 +#define SDHCI_CDNS_SRS12 0x230 +#define SDHCI_CDNS_SRS13 0x234 +#define SDHCI_CDNS_SRS13_DATA 0xffffffff +#define SDHCI_CDNS_SRS14 0x238 +#define SDHCI_CDNS_SRS15 0x23c + +/* PHY register values */ +#define PHY_DQ_TIMING_REG 0x2000 +#define PHY_DQS_TIMING_REG 0x2004 +#define PHY_GATE_LPBK_CTRL_REG 0x2008 +#define PHY_DLL_MASTER_CTRL_REG 0x200C +#define PHY_DLL_SLAVE_CTRL_REG 0x2010 +#define PHY_CTRL_REG 0x2080 +#define USE_EXT_LPBK_DQS BIT(22) +#define USE_LPBK_DQS BIT(21) +#define USE_PHONY_DQS BIT(20) +#define USE_PHONY_DQS_CMD BIT(19) +#define SYNC_METHOD BIT(31) +#define SW_HALF_CYCLE_SHIFT BIT(28) +#define RD_DEL_SEL GENMASK(24, 19) +#define RD_DEL_SEL_DATA 0x34 +#define GATE_CFG_ALWAYS_ON BIT(6) +#define UNDERRUN_SUPPRESS BIT(18) +#define PARAM_DLL_BYPASS_MODE BIT(23) +#define PARAM_PHASE_DETECT_SEL GENMASK(22, 20) +#define PARAM_DLL_START_POINT GENMASK(7, 0) +#define PARAM_PHASE_DETECT_SEL_DATA 0x2 +#define PARAM_DLL_START_POINT_DATA 0x4 +#define PARAM_DLL_START_POINT_DATA_SDR50 254 + +#define READ_DQS_CMD_DELAY GENMASK(31, 24) +#define CLK_WRDQS_DELAY GENMASK(23, 16) +#define CLK_WR_DELAY GENMASK(15, 8) +#define READ_DQS_DELAY GENMASK(7, 0) +#define READ_DQS_CMD_DELAY_DATA 0x0 +#define CLK_WRDQS_DELAY_DATA 0xca +#define CLK_WR_DELAY_DATA 0xca +#define READ_DQS_DELAY_DATA 0x0 + +#define PHONY_DQS_TIMING GENMASK(9, 4) +#define PHONY_DQS_TIMING_DATA 0x0 + +#define IO_MASK_ALWAYS_ON BIT(31) +#define IO_MASK_END GENMASK(29, 27) +#define IO_MASK_START GENMASK(26, 24) +#define DATA_SELECT_OE_END GENMASK(2, 0) +/* TODO: check DV dfi_init val=0 */ +#define IO_MASK_END_DATA 0x5 +/* TODO: check DV dfi_init val=2; DDR Mode */ +#define IO_MASK_END_DATA_DDR 0x2 +#define IO_MASK_START_DATA 0x0 +#define DATA_SELECT_OE_END_DATA 0x1 + +/* rstmgr settings */ +#define COMBOPHY_RST BIT(6) +#define SDMMC_RST BIT(7) + +struct cdns_combophy_reg_pairs { + u32 reg; + u32 val; + u32 op; +}; + +struct sdhci_cdns_phy_param { + u32 addr; + u32 data; + u32 offset; +}; + +struct sdhci_cdns_phy_cfg { + const char *property; + u32 addr; + u32 offset; +}; + +struct cdns_combophy_plat { + u32 phy_type; + void __iomem *hrs_addr; + u32 nr_phy_params; + struct sdhci_cdns_phy_param *phy_params; + struct reset_ctl softreset_ctl; +}; + +struct cdns_combophy_phy { + struct udevice *dev; + void *base; +}; + +struct cdns_combophy_data { + u32 speed_mode; + struct cdns_combophy_reg_pairs *cdns_phy_regs; +}; + +static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { + { "cdns,phy-use-ext-lpbk-dqs", PHY_DQS_TIMING_REG, 22,}, + { "cdns,phy-use-lpbk-dqs", PHY_DQS_TIMING_REG, 21,}, + { "cdns,phy-use-phony-dqs", PHY_DQS_TIMING_REG, 20,}, + { "cdns,phy-use-phony-dqs-cmd", PHY_DQS_TIMING_REG, 19,}, + { "cdns,phy-io-mask-always-on", PHY_DQ_TIMING_REG, 31,}, + { "cdns,phy-io-mask-end", PHY_DQ_TIMING_REG, 27,}, + { "cdns,phy-io-mask-start", PHY_DQ_TIMING_REG, 24,}, + { "cdns,phy-data-select-oe-end", PHY_DQ_TIMING_REG, 0,}, + { "cdns,phy-sync-method", PHY_GATE_LPBK_CTRL_REG, 31,}, + { "cdns,phy-sw-half-cycle-shift", PHY_GATE_LPBK_CTRL_REG, 28,}, + { "cdns,phy-rd-del-sel", PHY_GATE_LPBK_CTRL_REG, 19,}, + { "cdns,phy-underrun-suppress", PHY_GATE_LPBK_CTRL_REG, 18,}, + { "cdns,phy-gate-cfg-always-on", PHY_GATE_LPBK_CTRL_REG, 6,}, + { "cdns,phy-param-dll-bypass-mode", PHY_DLL_MASTER_CTRL_REG, 23,}, + { "cdns,phy-param-phase-detect-sel", PHY_DLL_MASTER_CTRL_REG, 20,}, + { "cdns,phy-param-dll-start-point", PHY_DLL_MASTER_CTRL_REG, 0,}, + { "cdns,phy-read-dqs-cmd-delay", PHY_DLL_SLAVE_CTRL_REG, 24,}, + { "cdns,phy-clk-wrdqs-delay", PHY_DLL_SLAVE_CTRL_REG, 16,}, + { "cdns,phy-clk-wr-delay", PHY_DLL_SLAVE_CTRL_REG, 8,}, + { "cdns,phy-read-dqs-delay", PHY_DLL_SLAVE_CTRL_REG, 0,}, + { "cdns,phy-phony-dqs-timing", PHY_CTRL_REG, 4,}, + { "cdns,hrs09-rddata-en", SDHCI_CDNS_HRS09, 16,}, + { "cdns,hrs09-rdcmd-en", SDHCI_CDNS_HRS09, 15,}, + { "cdns,hrs09-extended-wr-mode", SDHCI_CDNS_HRS09, 3,}, + { "cdns,hrs09-extended-rd-mode", SDHCI_CDNS_HRS09, 2,}, + { "cdns,hrs10-hcsdclkadj", SDHCI_CDNS_HRS10, 16,}, + { "cdns,hrs16-wrdata1-sdclk-dly", SDHCI_CDNS_HRS16, 28,}, + { "cdns,hrs16-wrdata0-sdclk-dly", SDHCI_CDNS_HRS16, 24,}, + { "cdns,hrs16-wrcmd1-sdclk-dly", SDHCI_CDNS_HRS16, 20,}, + { "cdns,hrs16-wrcmd0-sdclk-dly", SDHCI_CDNS_HRS16, 16,}, + { "cdns,hrs16-wrdata1-dly", SDHCI_CDNS_HRS16, 12,}, + { "cdns,hrs16-wrdata0-dly", SDHCI_CDNS_HRS16, 8,}, + { "cdns,hrs16-wrcmd1-dly", SDHCI_CDNS_HRS16, 4,}, + { "cdns,hrs16-wrcmd0-dly", SDHCI_CDNS_HRS16, 0,}, + { "cdns,hrs07-rw-compensate", SDHCI_CDNS_HRS07, 16,}, + { "cdns,hrs07-idelay-val", SDHCI_CDNS_HRS07, 0,} +}; + +static u32 sdhci_cdns_phy_param_count(struct cdns_combophy_plat *plat, + const void *fdt, int nodeoffset) +{ + const fdt32_t *prop; + int i; + u32 count = 0; + + for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) { + prop = fdt_getprop(fdt, nodeoffset, + sdhci_cdns_phy_cfgs[i].property, NULL); + if (!prop) + continue; + + count++; + } + + debug("%s: count:%d\n", __func__, count); + return count; +} + +static void sdhci_cdns_phy_param_parse(struct cdns_combophy_plat *plat, + const void *fdt, int nodeoffset) +{ + struct sdhci_cdns_phy_param *p = plat->phy_params; + const fdt32_t *prop; + int i; + + for (i = 0; i < plat->nr_phy_params; i++) { + prop = fdt_getprop(fdt, nodeoffset, + sdhci_cdns_phy_cfgs[i].property, NULL); + if (!prop) + continue; + + p->addr = sdhci_cdns_phy_cfgs[i].addr; + p->data = fdt32_to_cpu(*prop); + p->offset = sdhci_cdns_phy_cfgs[i].offset; + debug("%s: p->addr: %02x, p->data: %02x, p->offset: %02x\n", + __func__, p->addr, p->data, p->offset); + p++; + } +} + +static u32 sdhci_cdns_dfi_phy_val(struct cdns_combophy_plat *plat, u32 reg) +{ + int i; + u32 tmp = 0; + + for (i = 0; i < plat->nr_phy_params; i++) { + if (plat->phy_params[i].addr == reg) { + tmp |= plat->phy_params[i].data << plat->phy_params[i].offset; + debug("%s: p->addr: %02x, p->data: %02x, p->offset: %02x\n", + __func__, plat->phy_params[i].addr, plat->phy_params[i].data, + plat->phy_params[i].offset); + } + } + + debug("%s: reg value:%08x\n", __func__, tmp); + return tmp; +} + +static int sdhci_cdns_write_phy_reg_mask(u32 addr, u32 data, u32 mask, + void __iomem *hrs_addr) +{ + void __iomem *reg = hrs_addr + SDHCI_CDNS_HRS04; + u32 tmp; + + tmp = addr; + + /* get PHY address */ + writel(tmp, reg); + debug("%s: register = 0x%08x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS04)); + + /* read current PHY register value, before write */ + reg = hrs_addr + SDHCI_CDNS_HRS05; + tmp = readl(reg); + debug("%s: register = 0x%08x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS05)); + tmp &= ~mask; + tmp |= data; + + /* write operation */ + writel(tmp, reg); + debug("%s: register = 0x%08x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS05)); + + return 0; +} + +static u32 sdhci_cdns_read_phy_reg(u32 addr, void __iomem *hrs_addr) +{ + void __iomem *reg = hrs_addr + SDHCI_CDNS_HRS04; + u32 tmp; + + tmp = addr; + + /* get PHY address */ + writel(tmp, reg); + debug("%s: register = 0x%08x\n", __func__, readl(reg)); + + /* read current PHY register value, before write */ + reg = hrs_addr + SDHCI_CDNS_HRS05; + tmp = readl(reg); + debug("%s: register = 0x%08x\n", __func__, readl(reg)); + + return tmp; +} + +/* initialize clock */ +static void sdhci_set_clk(u32 freq_khz, void __iomem *hrs_addr) +{ + void __iomem *reg = hrs_addr + SDHCI_CDNS_SRS11; + + /* calculate the value to set */ + u32 sdclkfs = (SD_HOST_CLK / 2000) / freq_khz; + u32 dtcvval = 0xe; + + /* disable SDCE */ + writel(0, reg); + debug("Disable SDCE\n"); + + /* Enable ICE (internal clock enable) */ + writel(dtcvval << 16 | sdclkfs << 8 | 1 << 0, reg); + debug("Enable ICE: SRS11: %08x\n", readl(reg)); + + reg = hrs_addr + SDHCI_CDNS_SRS11; + /* Wait for ICS (internal clock stable) */ + /* polling for ICS = 1 */ + wait_for_bit_le32(reg, BIT(1), true, 10, false); + + reg = hrs_addr + SDHCI_CDNS_HRS09; + /* Enable DLL reset */ + writel(readl(reg) & ~0x00000001, reg); + debug("Enable DLL reset\n"); + + /* Set extended_wr_mode */ + writel((readl(reg) & 0xFFFFFFF7) | + ((sdclkfs > 0 ? 1 << 3 : 0 << 3)), reg); + debug("Set extended_wr_mode\n"); + + /* Release DLL reset */ + writel(readl(reg) | BIT(0), reg); + writel(readl(reg) | 3 << 15, reg); + debug("Release DLL reset\n"); + + /* polling for phy_init = 1 */ + wait_for_bit_le32(reg, BIT(1), true, 10, false); + + debug("PHY init complete\n"); + + reg = hrs_addr + SDHCI_CDNS_SRS11; + writel(dtcvval << 16 | sdclkfs << 8 | 1 << 0 | 1 << 2, reg); + debug("SD clock enabled\n"); +} + +static int sdhci_cdns_detect_card(void __iomem *hrs_addr) +{ + u32 tmp; + void __iomem *reg = hrs_addr + SDHCI_CDNS_SRS09; + + /* step 1, polling for sdcard */ + /* polling for SRS9.CI = 1 */ + wait_for_bit_le32(reg, SDHCI_CDNS_SRS09_CI, true, 10, false); + + debug("SDcard detected\n"); + + debug("ON voltage\n"); + tmp = SDHCI_CDNS_SRS10_VOLT_ON; + reg = hrs_addr + SDHCI_CDNS_SRS10; + writel(tmp, reg); + + debug("OFF Voltage\n"); + tmp = SDHCI_CDNS_SRS10_VOLT_OFF; + writel(tmp, reg); + + debug("ON voltage\n"); + tmp = SDHCI_CDNS_SRS10_VOLT_ON; + reg = hrs_addr + SDHCI_CDNS_SRS10; + writel(tmp, reg); + + /* sdhci_set_clk - 100000 */ + debug("SD clock\n"); + sdhci_set_clk(100000, hrs_addr); + + /* set SRS13 */ + tmp = SDHCI_CDNS_SRS13_DATA; + reg = hrs_addr + SDHCI_CDNS_SRS13; + writel(tmp, reg); + debug("SRS13: %08x\n", readl(reg)); + + return 0; +} + +static int sdhci_cdns_combophy_phy_prog(void __iomem *hrs_addr) +{ + u32 ret, tmp; + u32 mask = 0x0; + + /* step 1, switch on SW_RESET */ + tmp = SDHCI_CDNS_HRS00_SWR; + writel(tmp, hrs_addr); + /* polling for HRS0.0 (SWR) = 0 */ + wait_for_bit_le32(hrs_addr, SDHCI_CDNS_HRS00_SWR, false, 10, false); + debug("SW reset\n"); + + /* switch on DLL_RESET */ + tmp = readl(hrs_addr + SDHCI_CDNS_HRS09); + tmp &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET; + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, BIT_ZERO); + + writel(tmp, hrs_addr + SDHCI_CDNS_HRS09); + debug("PHY_SW_RESET: 0x%08x\n", readl(hrs_addr + SDHCI_CDNS_HRS09)); + + /* program PHY_DQS_TIMING_REG */ + tmp = FIELD_PREP(USE_EXT_LPBK_DQS, BIT_ONE) | + FIELD_PREP(USE_LPBK_DQS, BIT_ONE) | + FIELD_PREP(USE_PHONY_DQS, BIT_ONE) | + FIELD_PREP(USE_PHONY_DQS_CMD, BIT_ONE); + ret = sdhci_cdns_write_phy_reg_mask(PHY_DQS_TIMING_REG, tmp, tmp, hrs_addr); + + /* program PHY_GATE_LPBK_CTRL_REG */ + tmp = FIELD_PREP(SYNC_METHOD, BIT_ONE) | + FIELD_PREP(SW_HALF_CYCLE_SHIFT, BIT_ZERO) | + FIELD_PREP(RD_DEL_SEL, RD_DEL_SEL_DATA) | + FIELD_PREP(UNDERRUN_SUPPRESS, BIT_ONE) | + FIELD_PREP(GATE_CFG_ALWAYS_ON, BIT_ONE); + mask = SYNC_METHOD | SW_HALF_CYCLE_SHIFT | RD_DEL_SEL | UNDERRUN_SUPPRESS | + GATE_CFG_ALWAYS_ON; + ret = sdhci_cdns_write_phy_reg_mask(PHY_GATE_LPBK_CTRL_REG, tmp, mask, + hrs_addr); + + /* program PHY_DLL_MASTER_CTRL_REG */ + tmp = FIELD_PREP(PARAM_DLL_BYPASS_MODE, BIT_ONE) | + FIELD_PREP(PARAM_PHASE_DETECT_SEL, PARAM_PHASE_DETECT_SEL_DATA) | + FIELD_PREP(PARAM_DLL_START_POINT, PARAM_DLL_START_POINT_DATA); + mask = PARAM_DLL_BYPASS_MODE | PARAM_PHASE_DETECT_SEL | + PARAM_DLL_START_POINT; + ret = sdhci_cdns_write_phy_reg_mask(PHY_DLL_MASTER_CTRL_REG, tmp, mask, + hrs_addr); + + /* program PHY_DLL_SLAVE_CTRL_REG */ + tmp = FIELD_PREP(READ_DQS_CMD_DELAY, READ_DQS_CMD_DELAY_DATA) | + FIELD_PREP(CLK_WRDQS_DELAY, CLK_WRDQS_DELAY_DATA) | + FIELD_PREP(CLK_WR_DELAY, CLK_WR_DELAY_DATA) | + FIELD_PREP(READ_DQS_DELAY, READ_DQS_DELAY_DATA); + mask = READ_DQS_CMD_DELAY | CLK_WRDQS_DELAY | CLK_WR_DELAY | READ_DQS_DELAY; + ret = sdhci_cdns_write_phy_reg_mask(PHY_DLL_SLAVE_CTRL_REG, tmp, mask, + hrs_addr); + + /* program PHY_CTRL_REG */ + tmp = FIELD_PREP(PHONY_DQS_TIMING, PHONY_DQS_TIMING_DATA); + mask = PHONY_DQS_TIMING; + ret = sdhci_cdns_write_phy_reg_mask(PHY_CTRL_REG, tmp, mask, hrs_addr); + + /* switch off DLL_RESET */ + tmp = readl(hrs_addr + SDHCI_CDNS_HRS09); + tmp &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET; + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, BIT_ONE); + + writel(tmp, hrs_addr + SDHCI_CDNS_HRS09); + + /* polling for PHY_INIT_COMPLETE bit */ + wait_for_bit_le32(hrs_addr + SDHCI_CDNS_HRS09, + SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE, true, 10, false); + + /* program PHY_DQ_TIMING_REG */ + tmp = sdhci_cdns_read_phy_reg(PHY_DQ_TIMING_REG, hrs_addr) & 0x07FFFF8; + tmp |= FIELD_PREP(IO_MASK_ALWAYS_ON, BIT_ZERO) | + FIELD_PREP(IO_MASK_END, IO_MASK_END_DATA) | + FIELD_PREP(IO_MASK_START, IO_MASK_START_DATA) | + FIELD_PREP(DATA_SELECT_OE_END, DATA_SELECT_OE_END_DATA); + mask = IO_MASK_ALWAYS_ON | IO_MASK_END | IO_MASK_START | DATA_SELECT_OE_END; + ret = sdhci_cdns_write_phy_reg_mask(PHY_DQ_TIMING_REG, tmp, mask, hrs_addr); + + /* program HRS09, register 42 */ + tmp = readl(hrs_addr + SDHCI_CDNS_HRS09) & 0xFFFE7FF3; + tmp &= ~(SDHCI_CDNS_HRS09_RDDATA_EN | + SDHCI_CDNS_HRS09_RDCMD_EN | + SDHCI_CDNS_HRS09_EXTENDED_WR_MODE | + SDHCI_CDNS_HRS09_EXTENDED_RD_MODE); + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_RDDATA_EN, BIT_ONE) | + FIELD_PREP(SDHCI_CDNS_HRS09_RDCMD_EN, BIT_ONE) | + FIELD_PREP(SDHCI_CDNS_HRS09_EXTENDED_WR_MODE, BIT_ONE) | + FIELD_PREP(SDHCI_CDNS_HRS09_EXTENDED_RD_MODE, BIT_ONE); + + writel(tmp, hrs_addr + SDHCI_CDNS_HRS09); + debug("%s: register = 0x%x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS09)); + + /* program HRS10, register 43 */ + tmp = readl(hrs_addr + SDHCI_CDNS_HRS10) & 0xFFF0FFFF; + tmp &= ~SDHCI_CDNS_HRS10_HCSDCLKADJ; + tmp |= FIELD_PREP(SDHCI_CDNS_HRS10_HCSDCLKADJ, + SDHCI_CDNS_HRS10_HCSDCLKADJ_DATA); + + writel(tmp, hrs_addr + SDHCI_CDNS_HRS10); + debug("%s: register = 0x%x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS10)); + + /* program HRS16, register 48 */ + tmp = readl(hrs_addr + SDHCI_CDNS_HRS16); + tmp &= ~(SDHCI_CDNS_HRS16_WRDATA1_SDCLK_DLY | + SDHCI_CDNS_HRS16_WRDATA0_SDCLK_DLY | + SDHCI_CDNS_HRS16_WRCMD1_SDCLK_DLY | + SDHCI_CDNS_HRS16_WRDATA1_DLY | + SDHCI_CDNS_HRS16_WRDATA0_DLY | + SDHCI_CDNS_HRS16_WRCMD1_DLY | + SDHCI_CDNS_HRS16_WRCMD0_DLY); + tmp |= FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA1_SDCLK_DLY, + SDHCI_CDNS_HRS16_WRDATA1_SDCLK_DLY_DATA) | + FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA0_SDCLK_DLY, + SDHCI_CDNS_HRS16_WRDATA0_SDCLK_DLY_DATA) | + FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD1_SDCLK_DLY, + SDHCI_CDNS_HRS16_WRCMD1_SDCLK_DLY_DATA) | + FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD0_SDCLK_DLY, + SDHCI_CDNS_HRS16_WRCMD0_SDCLK_DLY_DATA) | + FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA1_DLY, + SDHCI_CDNS_HRS16_WRDATA1_DLY_DATA) | + FIELD_PREP(SDHCI_CDNS_HRS16_WRDATA0_DLY, + SDHCI_CDNS_HRS16_WRDATA0_DLY_DATA) | + FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD1_DLY, + SDHCI_CDNS_HRS16_WRCMD1_DLY_DATA) | + FIELD_PREP(SDHCI_CDNS_HRS16_WRCMD0_DLY, + SDHCI_CDNS_HRS16_WRCMD0_DLY_DATA); + + writel(tmp, hrs_addr + SDHCI_CDNS_HRS16); + debug("%s: register = 0x%x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS16)); + + /* program HRS07, register 40 */ + tmp = readl(hrs_addr + SDHCI_CDNS_HRS07); + tmp &= ~(SDHCI_CDNS_HRS07_RW_COMPENSATE | + SDHCI_CDNS_HRS07_IDELAY_VAL); + tmp |= FIELD_PREP(SDHCI_CDNS_HRS07_RW_COMPENSATE, + SDHCI_CDNS_HRS07_RW_COMPENSATE_DATA) | + FIELD_PREP(SDHCI_CDNS_HRS07_IDELAY_VAL, + SDHCI_CDNS_HRS07_IDELAY_VAL_DATA); + writel(tmp, hrs_addr + SDHCI_CDNS_HRS07); + debug("%s: register = 0x%x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS07)); + /* end of combophy init */ + + /* initialize sdcard/eMMC & set clock*/ + ret = sdhci_cdns_detect_card(hrs_addr); + debug("eMMC Mode: 0x%08x\n", readl(hrs_addr + SDHCI_CDNS_HRS06)); + + return 0; +} + +static int cdns_combophy_phy_init(struct phy *gphy) +{ + u32 tmp; + int ret; + struct cdns_combophy_plat *plat = dev_get_plat(gphy->dev); + +#if (IS_ENABLED(CONFIG_SPL_BUILD)) + /* assert & deassert softreset */ + ret = reset_assert(&plat->softreset_ctl); + if (ret < 0) { + pr_err("COMBOPHY soft reset deassert failed: %d", ret); + return ret; + } + + ret = reset_deassert(&plat->softreset_ctl); + if (ret < 0) { + pr_err("COMBOPHY soft reset deassert failed: %d", ret); + return ret; + } +#endif + + if (plat->phy_type == PHY_TYPE_SDMMC) { + tmp = SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC; + +#if (IS_ENABLED(CONFIG_SPL_BUILD)) +#if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)) + /* OCRAM FW - allow non secure sdmmc */ + writel(NON_SECURE_ACCESS, OCRAM_SECURE_REGION1_REG); +#endif + /* configure DFI_SEL for SDMMC */ + writel(tmp, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_COMBOPHY_DFISEL); + debug("DFISEL: %08x\nSDMMC_USEFPGA: %08x\n", + readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_COMBOPHY_DFISEL), + readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC_USEFPGA)); + debug("clkmgr.mainpllgrp.en: 0x%08x\nclkmgr.mainpllgrp.ens: 0x%08x\n", + readl(socfpga_get_clkmgr_addr() + CLKMGR_MAINPLL_EN), + readl(socfpga_get_clkmgr_addr() + CLKMGR_MAINPLL_ENS)); + debug("clkmgr.perpllgrp.en: 0x%08x\nclkmgr.perpllgrp.ens: 0x%08x\n", + readl(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN), + readl(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_ENS)); + + /* configure default base clkmgr clock - 200MHz */ + writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_MAINPLL_NOCDIV) + & 0xfffcffff) | + (CLKMGR_NOCDIV_SOFTPHY_DIV_ONE << CLKMGR_NOCDIV_SOFTPHY_OFFSET), + socfpga_get_clkmgr_addr() + CLKMGR_MAINPLL_NOCDIV); + + debug("clkmgr.nocdiv: 0x%08x\n", + readl(socfpga_get_clkmgr_addr() + CLKMGR_MAINPLL_NOCDIV)); + + /* enable DDR secure zone access for SDMMC */ + writel(SECURE_TRANS_SET, SECURE_TRANS_REG); +#endif + + /* TODO: add speed-mode checking in device tree */ + ret = sdhci_cdns_combophy_phy_prog(plat->hrs_addr); + + } else if (plat->phy_type == PHY_TYPE_NAND) { + /* configure DFI_SEL for NAND */ + } else { + return -EINVAL; + } + + return 0; +} + +static int cdns_combophy_phy_on(struct phy *gphy) +{ + return 0; +} + +static int cdns_combophy_phy_configure(struct phy *gphy, void *params) +{ + u32 ret, tmp; + u32 mask = 0x0; + struct cdns_combophy_plat *plat = dev_get_plat(gphy->dev); + void __iomem *hrs_addr = plat->hrs_addr; + + /* switch on DLL_RESET */ + tmp = readl(hrs_addr + SDHCI_CDNS_HRS09); + tmp &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET; + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, BIT_ZERO); + + writel(tmp, hrs_addr + SDHCI_CDNS_HRS09); + debug("PHY_SW_RESET: 0x%08x\n", readl(hrs_addr + SDHCI_CDNS_HRS09)); + + /* program PHY_DQS_TIMING_REG */ + tmp = sdhci_cdns_dfi_phy_val(plat, PHY_DQS_TIMING_REG); + ret = sdhci_cdns_write_phy_reg_mask(PHY_DQS_TIMING_REG, tmp, tmp, hrs_addr); + + /* program PHY_GATE_LPBK_CTRL_REG */ + tmp = sdhci_cdns_dfi_phy_val(plat, PHY_GATE_LPBK_CTRL_REG); + mask = SYNC_METHOD | SW_HALF_CYCLE_SHIFT | RD_DEL_SEL | UNDERRUN_SUPPRESS | + GATE_CFG_ALWAYS_ON; + ret = sdhci_cdns_write_phy_reg_mask(PHY_GATE_LPBK_CTRL_REG, tmp, mask, + hrs_addr); + + /* program PHY_DLL_MASTER_CTRL_REG */ + tmp = sdhci_cdns_dfi_phy_val(plat, PHY_DLL_MASTER_CTRL_REG); + mask = PARAM_DLL_BYPASS_MODE | PARAM_PHASE_DETECT_SEL | + PARAM_DLL_START_POINT; + ret = sdhci_cdns_write_phy_reg_mask(PHY_DLL_MASTER_CTRL_REG, tmp, mask, + hrs_addr); + + /* program PHY_DLL_SLAVE_CTRL_REG */ + tmp = sdhci_cdns_dfi_phy_val(plat, PHY_DLL_SLAVE_CTRL_REG); + mask = READ_DQS_CMD_DELAY | CLK_WRDQS_DELAY | CLK_WR_DELAY | READ_DQS_DELAY; + ret = sdhci_cdns_write_phy_reg_mask(PHY_DLL_SLAVE_CTRL_REG, tmp, mask, + hrs_addr); + + /* program PHY_CTRL_REG */ + debug("%s: Skip PHY_CTRL_REG - PHONY_DQS_TIMING field\n", __func__); + + /* switch off DLL_RESET */ + tmp = readl(hrs_addr + SDHCI_CDNS_HRS09); + tmp &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET; + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, BIT_ONE); + + writel(tmp, hrs_addr + SDHCI_CDNS_HRS09); + + /* polling for PHY_INIT_COMPLETE bit */ + wait_for_bit_le32(hrs_addr + SDHCI_CDNS_HRS09, + SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE, true, 10, false); + + /* program PHY_DQ_TIMING_REG */ + tmp = sdhci_cdns_read_phy_reg(PHY_DQ_TIMING_REG, hrs_addr) & 0x07FFFF8; + tmp |= sdhci_cdns_dfi_phy_val(plat, PHY_DQ_TIMING_REG); + mask = IO_MASK_ALWAYS_ON | IO_MASK_END | IO_MASK_START | DATA_SELECT_OE_END; + ret = sdhci_cdns_write_phy_reg_mask(PHY_DQ_TIMING_REG, tmp, mask, hrs_addr); + + /* program HRS09, register 42 */ + tmp = readl(hrs_addr + SDHCI_CDNS_HRS09) & 0xFFFE7FF3; + tmp |= sdhci_cdns_dfi_phy_val(plat, SDHCI_CDNS_HRS09); + writel(tmp, hrs_addr + SDHCI_CDNS_HRS09); + debug("%s: register = 0x%x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS09)); + + /* program HRS10, register 43 */ + tmp = readl(hrs_addr + SDHCI_CDNS_HRS10) & 0xFFF0FFFF; + tmp |= sdhci_cdns_dfi_phy_val(plat, SDHCI_CDNS_HRS10); + writel(tmp, hrs_addr + SDHCI_CDNS_HRS10); + debug("%s: register = 0x%x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS10)); + + /* program HRS16, register 48 */ + tmp = sdhci_cdns_dfi_phy_val(plat, SDHCI_CDNS_HRS16); + writel(tmp, hrs_addr + SDHCI_CDNS_HRS16); + debug("%s: register = 0x%x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS16)); + + /* program HRS07, register 40 */ + tmp = sdhci_cdns_dfi_phy_val(plat, SDHCI_CDNS_HRS07); + writel(tmp, hrs_addr + SDHCI_CDNS_HRS07); + debug("%s: register = 0x%x\n", __func__, readl(hrs_addr + + SDHCI_CDNS_HRS07)); + /* end of combophy init */ + + /* initialize sdcard/eMMC & set clock*/ + ret = sdhci_cdns_detect_card(hrs_addr); + debug("eMMC Mode: 0x%08x\n", readl(hrs_addr + SDHCI_CDNS_HRS06)); + + return 0; +} + +static int cdns_combophy_phy_off(struct phy *gphy) +{ + return 0; +} + +static int cdns_combophy_phy_reset(struct phy *gphy) +{ + return 0; +}; + +static const struct phy_ops ops = { + .configure = cdns_combophy_phy_configure, + .init = cdns_combophy_phy_init, + .power_on = cdns_combophy_phy_on, + .power_off = cdns_combophy_phy_off, + .reset = cdns_combophy_phy_reset, +}; + +static int cdns_combophy_phy_probe(struct udevice *dev) +{ + struct cdns_combophy_plat *plat = dev_get_plat(dev); + u32 nr_phy_params; + int ret = 0; + + plat->phy_type = dev_read_u32_default(dev, "phy-type", 0); + plat->hrs_addr = dev_remap_addr_index(dev, 0); + + /* get softreset reset */ + ret = reset_get_by_name(dev, "reset", &plat->softreset_ctl); + if (ret) + pr_err("can't get soft reset for %s (%d)", dev->name, ret); + + nr_phy_params = sdhci_cdns_phy_param_count(plat, gd->fdt_blob, + dev_of_offset(dev)); + if (!nr_phy_params) + return ret; + + plat->phy_params = kcalloc(nr_phy_params, sizeof(*plat->phy_params), + GFP_KERNEL); + if (!plat->phy_params) + return -ENOMEM; + + plat->nr_phy_params = nr_phy_params; + sdhci_cdns_phy_param_parse(plat, gd->fdt_blob, dev_of_offset(dev)); + + debug("%s: ComboPHY probed\n", __func__); + + return ret; +} + +static int cdns_combophy_phy_remove(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id cdns_combophy_id_table[] = { + { .compatible = "cdns,combophy" }, + {} +}; + +U_BOOT_DRIVER(combophy_phy_provider) = { + .name = "combophy", + .id = UCLASS_PHY, + .of_match = cdns_combophy_id_table, + .probe = cdns_combophy_phy_probe, + .remove = cdns_combophy_phy_remove, + .ops = &ops, + .priv_auto = sizeof(struct cdns_combophy_phy), + .plat_auto = sizeof(struct cdns_combophy_plat), +};
This is for new platform enablement for agilex5. Add reset driver for new platform.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/reset/reset-socfpga.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 6e3f03e248..8b35f0685d 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -24,9 +24,18 @@ #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> - -#define BANK_INCREMENT 4 -#define NR_BANKS 8 +#include <asm/arch/reset_manager.h> + +#define BANK_INCREMENT 4 +#define NR_BANKS 8 +#define RSTMGR_PER0MODRST_USB31 BIT(4) +#define RSTMGR_PER0MODRST_NAND BIT(5) +#define RSTMGR_PER0MODRST_DMA BIT(16) +#define RSTMGR_PER0MODRST_DMAIF GENMASK(31, 24) +#define RSTMGR_PER0MODRST_USB31_NAND_DMA_DEASSERT RSTMGR_PER0MODRST_USB31 \ + | RSTMGR_PER0MODRST_NAND \ + | RSTMGR_PER0MODRST_DMA \ + | RSTMGR_PER0MODRST_DMAIF
struct socfpga_reset_data { void __iomem *modrst_base; @@ -112,9 +121,22 @@ static int socfpga_reset_remove(struct udevice *dev) { struct socfpga_reset_data *data = dev_get_priv(dev);
+/* + * TODO: This is temporary solution for NAND/DMA/USB3.1 deaasert. + * When NAND/DMA/USB3.1 driver is ready, the deassert shall be done + * from NAND/DMA/USB3.1 driver. + */ +#if defined(CONFIG_TARGET_SOCFPGA_AGILEX5) + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST, + RSTMGR_PER0MODRST_USB31_NAND_DMA_DEASSERT); +#endif + if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + writel(0, data->modrst_base + 8); +#endif }
return 0;
This is for new platform enablement for agilex5. Add cold, warm reset logic for new platform.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/sysreset/Kconfig | 7 ++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_socfpga_agilex5.c | 44 +++++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 03f7fdd597..850191eeed 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -137,6 +137,13 @@ config SYSRESET_SOCFPGA_SOC64 This enables the system reset driver support for Intel SOCFPGA SoC64 SoCs.
+config SYSRESET_SOCFPGA_AGILEX5 + bool "Enable support for Intel SOCFPGA AGILEX5 device" + depends on ARCH_SOCFPGA && TARGET_SOCFPGA_AGILEX5 + help + This enables the system reset driver support for Intel SOCFPGA + AGILEX5 device. + config SYSRESET_TI_SCI bool "TI System Control Interface (TI SCI) system reset driver" depends on TI_SCI_PROTOCOL diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 40c876764a..6631a71db6 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o +obj-$(CONFIG_SYSRESET_SOCFPGA_AGILEX5) += sysreset_socfpga_agilex5.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o diff --git a/drivers/sysreset/sysreset_socfpga_agilex5.c b/drivers/sysreset/sysreset_socfpga_agilex5.c new file mode 100644 index 0000000000..7b05ffd269 --- /dev/null +++ b/drivers/sysreset/sysreset_socfpga_agilex5.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/arch/reset_manager.h> +#include <asm/system.h> + +static int socfpga_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + const char *reset = env_get("reset"); + + if (reset && !strcmp(reset, "warm")) { + /* request a warm reset */ + puts("Do warm reset now...\n"); + + /* doing architecture system reset */ + psci_system_reset2(0, 0); + } else { + puts("Issuing cold reset REBOOT_HPS\n"); + psci_system_reset(); + } +#endif + + return -EINPROGRESS; +} + +static struct sysreset_ops socfpga_sysreset = { + .request = socfpga_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_socfpga) = { + .id = UCLASS_SYSRESET, + .name = "socfpga_sysreset", + .ops = &socfpga_sysreset, +};
This is for new platform enablement for agilex5. Update watchdog timeout timer for new platform.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 646663528a..18d2e33e09 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -28,7 +28,7 @@ config WATCHDOG_TIMEOUT_MSECS int "Watchdog timeout in msec" default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6 default 128000 if ARCH_MX7 || ARCH_VF610 - default 30000 if ARCH_SOCFPGA + default 10000 if ARCH_SOCFPGA default 16000 if ARCH_SUNXI default 5376 if ULP_WATCHDOG default 15000 if ARCH_BCM283X
This is for new platform enablement for agilex5. Add in new configuration that needed to boot new platform.
Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/mach-socfpga/Kconfig | 55 +++++ configs/socfpga_agilex5_defconfig | 2 + configs/socfpga_agilex5_legacy_defconfig | 2 + include/configs/socfpga_agilex5_socdk.h | 12 + include/configs/socfpga_soc64_common.h | 214 +++++++++++++++++- include/dt-bindings/clock/agilex5-clock.h | 71 ++++++ include/dt-bindings/reset/altr,rst-mgr-agx5.h | 82 +++++++ 7 files changed, 428 insertions(+), 10 deletions(-) create mode 100644 include/configs/socfpga_agilex5_socdk.h create mode 100644 include/dt-bindings/clock/agilex5-clock.h create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 562c3796ec..a35928ef47 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -3,6 +3,10 @@ if ARCH_SOCFPGA config ERR_PTR_OFFSET default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
+config MEM_RESERVE_SECURE + int + default 0 + config NR_DRAM_BANKS default 1
@@ -33,6 +37,37 @@ config SPL_STACK_R_ADDR config SPL_SYS_MALLOC_F_LEN default 0x800 if TARGET_SOCFPGA_GEN5
+config SYS_CACHELINE_SIZE + default 64 + +config SYS_INIT_RAM_ADDR + bool + default 0xFFE00000 if TARGET_SOCFPGA_AGILEX + default 0x0 if TARGET_SOCFPGA_AGILEX5 + default 0xFFE00000 if TARGET_SOCFPGA_N5X + default 0xFFE00000 if TARGET_SOCFPGA_STRATIX10 + +config SYS_INIT_RAM_SIZE + bool + default 0x40000 if TARGET_SOCFPGA_AGILEX + default 0x80000 if TARGET_SOCFPGA_AGILEX5 + default 0x40000 if TARGET_SOCFPGA_N5X + default 0x40000 if TARGET_SOCFPGA_STRATIX10 + +config SYS_MAX_NAND_DEVICE + default 1 + +config SYS_NAND_ONFI_DETECTION + default 1 + +config SYS_NAND_U_BOOT_SIZE + int + default 1048576 + +config SYS_NAND_U_BOOT_DST + bool + default CONFIG_TEXT_BASE if TARGET_SOCFPGA_SOC64 + config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE default 0xa2
@@ -40,6 +75,16 @@ config SYS_MALLOC_F_LEN default 0x2000 if TARGET_SOCFPGA_ARRIA10 default 0x2000 if TARGET_SOCFPGA_GEN5
+config SYS_NS16550_MEM32 + default y if TARGET_SOCFPGA_SOC64 + +config SYS_SDRAM_BASE + bool + default 0x0 if TARGET_SOCFPGA_AGILEX + default 0x80000000 if TARGET_SOCFPGA_AGILEX5 + default 0x0 if TARGET_SOCFPGA_N5X + default 0x0 if TARGET_SOCFPGA_STRATIX10 + config TEXT_BASE default 0x01000040 if TARGET_SOCFPGA_ARRIA10 default 0x01000040 if TARGET_SOCFPGA_GEN5 @@ -59,29 +104,35 @@ config TARGET_SOCFPGA_AGILEX select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select CLK + select CONFIG_BOOTFILE if SPL_ATF select FPGA_INTEL_SDM_MAILBOX select GICV2 select NCORE_CACHE select SPL_CLK if SPL + select SYS_SDRAM_BASE select TARGET_SOCFPGA_SOC64
config TARGET_SOCFPGA_AGILEX5 bool select BINMAN if SPL_ATF select CLK + select CONFIG_BOOTFILE if SPL_ATF select FPGA_INTEL_SDM_MAILBOX select GICV3 select NCORE_CACHE select SPL_CLK if SPL + select SYS_SDRAM_BASE select TARGET_SOCFPGA_SOC64
config TARGET_SOCFPGA_AGILEX5_EMU bool "Enable build that bootable only on Agilex5 Emulator" + select TARGET_SOCFPGA_AGILEX5 help This is to use for Agilex5 Emulator.
config TARGET_SOCFPGA_AGILEX5_SIMICS bool "Enable build that bootable only on Agilex5 Simics platform" + select TARGET_SOCFPGA_AGILEX5 help This is to use for Agilex5 Simics.
@@ -127,10 +178,12 @@ config TARGET_SOCFPGA_N5X select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select CLK + select CONFIG_BOOTFILE if SPL_ATF select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE select SPL_ALTERA_SDRAM select SPL_CLK if SPL + select SYS_SDRAM_BASE select TARGET_SOCFPGA_SOC64
config TARGET_SOCFPGA_N5X_SOCDK @@ -145,7 +198,9 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select BINMAN if SPL_ATF + select CONFIG_BOOTFILE if SPL_ATF select FPGA_INTEL_SDM_MAILBOX + select SYS_SDRAM_BASE select TARGET_SOCFPGA_SOC64
choice diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 6a90fa0b27..8e5c7e6f70 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -50,6 +50,8 @@ CONFIG_CMD_FAT=y CONFIG_DOS_PARTITION=y CONFIG_SPL_DOS_PARTITION=y CONFIG_SPL_SYS_DISABLE_DCACHE_OPS=y +CONFIG_USE_BOOTFILE=y +CONFIG_BOOTFILE="kernel.itb" CONFIG_CMD_MTD=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_NAND_LOCK_UNLOCK=y diff --git a/configs/socfpga_agilex5_legacy_defconfig b/configs/socfpga_agilex5_legacy_defconfig index cede11c880..054f785b6e 100644 --- a/configs/socfpga_agilex5_legacy_defconfig +++ b/configs/socfpga_agilex5_legacy_defconfig @@ -45,6 +45,8 @@ CONFIG_MMC_SDHCI_CADENCE=y CONFIG_CMD_FAT=y CONFIG_DOS_PARTITION=y CONFIG_SPL_DOS_PARTITION=y +CONFIG_USE_BOOTFILE=y +CONFIG_BOOTFILE="kernel.itb" CONFIG_CMD_MTD=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_NAND_LOCK_UNLOCK=y diff --git a/include/configs/socfpga_agilex5_socdk.h b/include/configs/socfpga_agilex5_socdk.h new file mode 100644 index 0000000000..ad2b5632d1 --- /dev/null +++ b/include/configs/socfpga_agilex5_socdk.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + * + */ + +#ifndef __CONFIG_SOCFGPA_AGILEX5_H__ +#define __CONFIG_SOCFGPA_AGILEX5_H__ + +#include <configs/socfpga_soc64_common.h> + +#endif /* __CONFIG_SOCFGPA_AGILEX5_H__ */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 66ecb168a0..04466dc8ac 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2023 Intel Corporation <www.intel.com> * */
@@ -18,25 +18,185 @@ #define CPU_RELEASE_ADDR 0xFFD12210
/* - * U-Boot console configurations + * sysmgr.boot_scratch_cold6 & 7 (64bit) will be used by master CPU to + * store its VBAR_EL3 value. Other slave CPUs will read from this + * location and update their VBAR_EL3 respectively + */ +#define VBAR_EL3_BASE_ADDR 0xFFD12218 +/* + * Share sysmgr.boot_scratch_cold6 & 7 (64bit) with VBAR_LE3_BASE_ADDR + * Indicate L2 reset is done. HPS should trigger warm reset via RMR_EL3. + */ +#define L2_RESET_DONE_REG 0xFFD12218 + +/* + * sysmgr.boot_scratch_cold8 bit 19 (1bit) will be used to check whether CPU0 + * is being powered off/on from kernel */ +#define BOOT_SCRATCH_COLD8 0xFFD12220
-/* Extend size of kernel image for uncompression */ +/* Magic word to indicate L2 reset is completed */ +#define L2_RESET_DONE_STATUS 0x1228E5E7 + +/* + * U-Boot console configurations + */
/* * U-Boot run time memory configurations */ -#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 -#define CFG_SYS_INIT_RAM_SIZE 0x40000
/* * U-Boot environment configurations */
+/* + * NAND support + */ + /* * Environment variable */ + +#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS) +#if IS_ENABLED(CONFIG_CMD_MMC) +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if IS_ENABLED(CONFIG_CMD_SF) +#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +#define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=sf probe && " \ + "ubi part root && ubi readvol ${scriptaddr} script && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo QSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#if IS_ENABLED(CONFIG_CMD_NAND) +# define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand, na) +#else +# define BOOT_TARGET_DEVICES_NAND(func) +#endif + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_nand=ubi part root && " \ + "ubi readvol ${scriptaddr} script && " \ + "echo NAND: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo NAND: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + "nand " + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) +#else +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_NAND(func) +#endif + +#include <config_distro_bootcmd.h> + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + +#define CFG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x86000000\0" \ + "qspiscriptaddr=0x02110000\0" \ + "scriptsize=0x00010000\0" \ + "qspibootimageaddr=0x02120000\0" \ + "bootimagesize=0x03200000\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@108d2000 status okay;" \ + "if fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ + "scriptaddr=0x81000000\0" \ + "scriptfile=boot.scr\0" \ + "nandroot=ubi0:rootfs\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "rsu_status=rsu dtb; rsu display_dcmf_version; "\ + "rsu display_dcmf_status; rsu display_max_retry\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " \ + BOOTENV + +#else + +#define CFG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x2000000\0" \ + "fdt_addr_r=0x6000000\0" \ + "qspiscriptaddr=0x02110000\0" \ + "scriptsize=0x00010000\0" \ + "qspibootimageaddr=0x02120000\0" \ + "bootimagesize=0x03200000\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@ff8d2000 status okay;" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ + "scriptaddr=0x05FF0000\0" \ + "scriptfile=boot.scr\0" \ + "nandroot=ubi0:rootfs\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "rsu_status=rsu dtb; rsu display_dcmf_version; "\ + "rsu display_dcmf_status; rsu display_max_retry\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " \ + BOOTENV +#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/ + +#else + #define CFG_EXTRA_ENV_SETTINGS \ + "kernel_comp_addr_r=0x9000000\0" \ + "kernel_comp_size=0x01000000\0" \ + "qspibootimageaddr=0x020E0000\0" \ + "qspifdtaddr=0x020D0000\0" \ + "bootimagesize=0x01F00000\0" \ + "fdtimagesize=0x00010000\0" \ + "qspiload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \ + "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \ + "qspiboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;booti ${loadaddr} - ${fdt_addr}\0" \ + "qspifitload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize}\0" \ + "qspifitboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;bootm ${loadaddr}\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ @@ -53,30 +213,64 @@ "bootm ${loadaddr}\0" \ "mmcfitload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "linux_qspi_enable=if sf probe; then " \ "echo Enabling QSPI at Linux DTB...;" \ "fdt addr ${fdt_addr}; fdt resize;" \ "fdt set /soc/spi@ff8d2000 status okay;" \ - "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ - " ${qspi_clock}; fi; \0" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ "scriptaddr=0x02100000\0" \ "scriptfile=u-boot.scr\0" \ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ - "then source ${scriptaddr}; fi\0" \ - "socfpga_legacy_reset_compat=1\0" + "then source ${scriptaddr}:script; fi\0" \ + "nandroot=ubi0:rootfs\0" \ + "nandload=ubi part root; ubi readvol ${loadaddr} kernel; ubi readvol ${fdt_addr} dtb\0" \ + "nandboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1; " \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "nandfitboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1; " \ + "bootm ${loadaddr}\0" \ + "nandfitload=ubi part root; ubi readvol ${loadaddr} kernel\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "rsu_status=rsu dtb; rsu display_dcmf_version; "\ + "rsu display_dcmf_status; rsu display_max_retry\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " +#endif /*#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)*/
/* * External memory configurations */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) +#else #define PHYS_SDRAM_1 0x0 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) -#define CFG_SYS_SDRAM_BASE 0 +#endif
/* * Serial / UART configurations */ #define CFG_SYS_NS16550_CLK 100000000
+/* + * Timer & watchdog configurations + */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS) +#define COUNTER_FREQUENCY 80000000 +#else +#define COUNTER_FREQUENCY 400000000 +#endif + /* * SDMMC configurations */ diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h new file mode 100644 index 0000000000..2691084653 --- /dev/null +++ b/include/dt-bindings/clock/agilex5-clock.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019-2022, Intel Corporation + */ + +#ifndef __AGILEX5_CLOCK_H +#define __AGILEX5_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX5_OSC1 0 +#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX5_CB_INTOSC_LS_CLK 2 +#define AGILEX5_L4_SYS_FREE_CLK 3 +#define AGILEX5_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX5_MAIN_PLL_CLK 5 +#define AGILEX5_MAIN_PLL_C0_CLK 6 +#define AGILEX5_MAIN_PLL_C1_CLK 7 +#define AGILEX5_MAIN_PLL_C2_CLK 8 +#define AGILEX5_MAIN_PLL_C3_CLK 9 +#define AGILEX5_PERIPH_PLL_CLK 10 +#define AGILEX5_PERIPH_PLL_C0_CLK 11 +#define AGILEX5_PERIPH_PLL_C1_CLK 12 +#define AGILEX5_PERIPH_PLL_C2_CLK 13 +#define AGILEX5_PERIPH_PLL_C3_CLK 14 +#define AGILEX5_MPU_FREE_CLK 15 +#define AGILEX5_MPU_CCU_CLK 16 +#define AGILEX5_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX5_L3_MAIN_FREE_CLK 18 +#define AGILEX5_NOC_FREE_CLK 19 +#define AGILEX5_S2F_USR0_CLK 20 +#define AGILEX5_NOC_CLK 21 +#define AGILEX5_EMAC_A_FREE_CLK 22 +#define AGILEX5_EMAC_B_FREE_CLK 23 +#define AGILEX5_EMAC_PTP_FREE_CLK 24 +#define AGILEX5_GPIO_DB_FREE_CLK 25 +#define AGILEX5_SDMMC_FREE_CLK 26 +#define AGILEX5_S2F_USER0_FREE_CLK 27 +#define AGILEX5_S2F_USER1_FREE_CLK 28 +#define AGILEX5_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX5_MPU_CLK 30 +#define AGILEX5_MPU_PERIPH_CLK 31 +#define AGILEX5_L4_MAIN_CLK 32 +#define AGILEX5_L4_MP_CLK 33 +#define AGILEX5_L4_SP_CLK 34 +#define AGILEX5_CS_AT_CLK 35 +#define AGILEX5_CS_TRACE_CLK 36 +#define AGILEX5_CS_PDBG_CLK 37 +#define AGILEX5_CS_TIMER_CLK 38 +#define AGILEX5_S2F_USER0_CLK 39 +#define AGILEX5_EMAC0_CLK 40 +#define AGILEX5_EMAC1_CLK 41 +#define AGILEX5_EMAC2_CLK 42 +#define AGILEX5_EMAC_PTP_CLK 43 +#define AGILEX5_GPIO_DB_CLK 44 +#define AGILEX5_NAND_CLK 45 +#define AGILEX5_PSI_REF_CLK 46 +#define AGILEX5_S2F_USER1_CLK 47 +#define AGILEX5_SDMMC_CLK 48 +#define AGILEX5_SPI_M_CLK 49 +#define AGILEX5_USB_CLK 50 +#define AGILEX5_NAND_X_CLK 51 +#define AGILEX5_NAND_ECC_CLK 52 +#define AGILEX5_NUM_CLKS 53 + +#endif /* __AGILEX5_CLOCK_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-agx5.h b/include/dt-bindings/reset/altr,rst-mgr-agx5.h new file mode 100644 index 0000000000..601093eaba --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-agx5.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2023 Intel Corporation. All rights reserved + * Copyright (C) 2016 Altera Corporation. All rights reserved + * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H + +/* PER0MODRST */ +#define EMAC0_RESET 0 +#define EMAC1_RESET 1 +#define EMAC2_RESET 2 +#define USB0_RESET 3 +#define USB1_RESET 4 +#define NAND_RESET 5 +#define COMBOPHY_RESET 6 +#define SDMMC_RESET 7 +#define EMAC0_OCP_RESET 8 +#define EMAC1_OCP_RESET 9 +#define EMAC2_OCP_RESET 10 +#define USB0_OCP_RESET 11 +#define USB1_OCP_RESET 12 +#define NAND_OCP_RESET 13 +/* 14 is empty */ +#define SDMMC_OCP_RESET 15 +#define DMA_RESET 16 +#define SPIM0_RESET 17 +#define SPIM1_RESET 18 +#define SPIS0_RESET 19 +#define SPIS1_RESET 20 +#define DMA_OCP_RESET 21 +#define EMAC_PTP_RESET 22 +/* 23 is empty*/ +#define DMAIF0_RESET 24 +#define DMAIF1_RESET 25 +#define DMAIF2_RESET 26 +#define DMAIF3_RESET 27 +#define DMAIF4_RESET 28 +#define DMAIF5_RESET 29 +#define DMAIF6_RESET 30 +#define DMAIF7_RESET 31 + +/* PER1MODRST */ +#define WATCHDOG0_RESET 32 +#define WATCHDOG1_RESET 33 +#define WATCHDOG2_RESET 34 +#define WATCHDOG3_RESET 35 +#define L4SYSTIMER0_RESET 36 +#define L4SYSTIMER1_RESET 37 +#define SPTIMER0_RESET 38 +#define SPTIMER1_RESET 39 +#define I2C0_RESET 40 +#define I2C1_RESET 41 +#define I2C2_RESET 42 +#define I2C3_RESET 43 +#define I2C4_RESET 44 +#define I3C0_RESET 45 +#define I3C1_RESET 46 +/* 47 is empty */ +#define UART0_RESET 48 +#define UART1_RESET 49 +/* 50-55 is empty */ +#define GPIO0_RESET 56 +#define GPIO1_RESET 57 +#define WATCHDOG4_RESET 58 +/* 59-63 is empty */ + +/* BRGMODRST */ +#define SOC2FPGA_RESET 64 +#define LWHPS2FPGA_RESET 65 +#define FPGA2SOC_RESET 66 +#define F2SSDRAM_RESET 67 +/* 68-69 is empty */ +#define DDRSCH_RESET 70 +/* 71-95 is empty */ + +/* DBGMODRST */ +#define DBG_RESET 192 + +#endif
From: Sieu Mun Tang sieu.mun.tang@intel.com
This is for new platform enablement for agilex5. Update binman tool for new platform.
Signed-off-by: Sieu Mun Tang sieu.mun.tang@intel.com --- tools/binman/control.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tools/binman/control.py b/tools/binman/control.py index 68597c4e77..51e94c9e65 100644 --- a/tools/binman/control.py +++ b/tools/binman/control.py @@ -7,11 +7,11 @@
from collections import OrderedDict import glob -try: - import importlib.resources -except ImportError: +#try: +# import importlib.resources +#except ImportError: # for Python 3.6 - import importlib_resources +# import importlib_resources import os import pkg_resources import re
participants (3)
-
Chee, Tien Fong -
Jit Loon Lim -
Lim, Jit Loon