[U-Boot] [PATCH 0/5] Add Marvell New Soc Support ARMADA100
This patch series adds basic ARMADA100 support, with minimal drivers (UART, MFP) support and Aspenite-DB board support for simple boot
Prafulla WADASKAR (3): arm: Add Support for Marvell ARMADA 100 Familiy SoCs. Serial: Add UART support for Marvell ARMADA 100 SoCs. Armada100: Add Board Support for Marvell Aspenite-DB
Prafulla Wadaskar (2): gpio: Add Multu-Function-Pin configuration driver for Marvell SoCs add mfp configuration support for ARMADA100
MAINTAINERS | 1 + MAKEALL | 1 + arch/arm/cpu/arm926ejs/armada100/Makefile | 46 +++++ arch/arm/cpu/arm926ejs/armada100/cpu.c | 92 ++++++++++ arch/arm/cpu/arm926ejs/armada100/dram.c | 122 +++++++++++++ arch/arm/cpu/arm926ejs/armada100/timer.c | 199 +++++++++++++++++++++ arch/arm/include/asm/arch-armada100/armada100.h | 120 +++++++++++++ arch/arm/include/asm/arch-armada100/cpu.h | 53 ++++++ arch/arm/include/asm/arch-armada100/mfp.h | 218 +++++++++++++++++++++++ board/Marvell/aspenite/Makefile | 52 ++++++ board/Marvell/aspenite/aspenite.c | 53 ++++++ board/Marvell/aspenite/config.mk | 26 +++ boards.cfg | 1 + drivers/gpio/Makefile | 1 + drivers/gpio/mfp.c | 105 +++++++++++ drivers/serial/ns16550.c | 16 ++ drivers/serial/serial.c | 3 + include/configs/aspenite.h | 133 ++++++++++++++ include/mfp.h | 97 ++++++++++ 19 files changed, 1339 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile create mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c create mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c create mode 100644 arch/arm/include/asm/arch-armada100/armada100.h create mode 100644 arch/arm/include/asm/arch-armada100/cpu.h create mode 100755 arch/arm/include/asm/arch-armada100/mfp.h create mode 100644 board/Marvell/aspenite/Makefile create mode 100644 board/Marvell/aspenite/aspenite.c create mode 100644 board/Marvell/aspenite/config.mk create mode 100644 drivers/gpio/mfp.c create mode 100644 include/configs/aspenite.h create mode 100644 include/mfp.h
From: Prafulla WADASKAR prafulla@marvell.com
ARMADA 100 Family processors are highly integrated SoCs based on Sheeva_88SV331x-v5 PJ1 cpu core. Ref: http://www.marvell.com/products/processors/applications/armada_100
SoC versions Supported: 1) ARMADA168/88AP168 (Aspen P) 2) ARMADA166/88AP166 (Aspen M) 3) ARMADA162/88AP162 (Aspen L)
Contributors: Eric Miao eric.y.miao@marvell.com Lei Wen leiwen@marvell.com Mahavir Jain mjain@marvell.com
Signed-off-by: Mahavir Jain mjain@marvell.com Signed-off-by: Prafulla Wadaskar prafulla@marvell.com --- arch/arm/cpu/arm926ejs/armada100/Makefile | 46 ++++++ arch/arm/cpu/arm926ejs/armada100/cpu.c | 92 +++++++++++ arch/arm/cpu/arm926ejs/armada100/dram.c | 122 ++++++++++++++ arch/arm/cpu/arm926ejs/armada100/timer.c | 199 +++++++++++++++++++++++ arch/arm/include/asm/arch-armada100/armada100.h | 120 ++++++++++++++ arch/arm/include/asm/arch-armada100/cpu.h | 53 ++++++ 6 files changed, 632 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile create mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c create mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c create mode 100644 arch/arm/include/asm/arch-armada100/armada100.h create mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile new file mode 100644 index 0000000..6403bf4 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/armada100/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2010 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y = cpu.o timer.o dram.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c new file mode 100644 index 0000000..62aa175 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * Contributor: Mahavir Jain mjain@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/arch/armada100.h> +#include <asm/io.h> + +#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) +#define SET_MRVL_ID (1<<8) +#define L2C_RAM_SEL (1<<4) + +int arch_cpu_init(void) +{ + u32 val; + struct armd1cpu_registers *cpuregs = + (struct armd1cpu_registers *) ARMD1_CPU_BASE; + + struct armd1apb1_registers *apb1clkres = + (struct armd1apb1_registers *) ARMD1_APBC1_BASE; + + struct armd1mpmu_registers *mpmu = + (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; + + /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */ + val = readl(&cpuregs->cpu_conf); + val = val | SET_MRVL_ID; + writel(val, &cpuregs->cpu_conf); + + /* Enable Clocks for all hardware units */ + writel(0xFFFFFFFF, &mpmu->acgr); + + /* Turn on AIB and AIB-APB Functional clock */ + writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib); + + /* ensure L2 cache is not mapped as SRAM */ + val = readl(&cpuregs->cpu_conf); + val = val & ~(L2C_RAM_SEL); + writel(val, &cpuregs->cpu_conf); + + /* Enable GPIO clock */ + writel(APBC_APBCLK, &apb1clkres->gpio); + + /* + * Enable Functional and APB clock at 14.7456MHz + * for configured UART console + */ +#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE) + writel(UARTCLK14745KHZ, &apb1clkres->uart3); +#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE) + writel(UARTCLK14745KHZ, &apb1clkres->uart2); +#else + writel(UARTCLK14745KHZ, &apb1clkres->uart1); +#endif + icache_enable(); + + return 0; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + u32 id; + struct armd1cpu_registers *cpuregs = + (struct armd1cpu_registers *) ARMD1_CPU_BASE; + + id = readl(&cpuregs->chip_id); + printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10)); + return 0; +} +#endif diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c new file mode 100644 index 0000000..4422f74 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/armada100/dram.c @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com, + * Contributor: Mahavir Jain mjain@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/arch/armada100.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * ARMADA100 DRAM controller supports upto 8 banks + * for chip select 0 and 1 + */ + +/* + * DDR Memory Control Registers + * Refer Datasheet Appendix A.17 + */ +struct armd1ddr_map_registers { + u32 cs; /* Memory Address Map Register -CS */ + u32 pad[3]; +}; + +struct armd1ddr_registers { + u8 pad[0x100 - 0x000 -4]; + struct armd1ddr_map_registers mmap[2]; +}; + +/* + * armd1_sdram_base - reads SDRAM Base Address Register + */ +u32 armd1_sdram_base(int chip_sel) +{ + struct armd1ddr_registers *ddr_regs = + (struct armd1ddr_registers *)ARMD1_DRAM_BASE; + u32 result = 0; + u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); + + if (!CS_valid) + return 0; + + result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; + return result; +} + +/* + * armd1_sdram_size - reads SDRAM size + */ +u32 armd1_sdram_size(int chip_sel) +{ + struct armd1ddr_registers *ddr_regs = + (struct armd1ddr_registers *)ARMD1_DRAM_BASE; + u32 result = 0; + u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); + + if (!CS_valid) + return 0; + + result = readl(&ddr_regs->mmap[chip_sel].cs); + result = (result >> 16) & 0xF; + if (result < 0x7) { + printf("Unknown DRAM Size\n"); + return -1; + } else { + return ((0x8 << (result - 0x7)) * 1024 * 1024); + } +} + +#ifndef CONFIG_SYS_BOARD_DRAM_INIT +int dram_init(void) +{ + int i; + + gd->ram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = armd1_sdram_base(i); + gd->bd->bi_dram[i].size = armd1_sdram_size(i); + /* + * It is assumed that all memory banks are consecutive + * and without gaps. + * If the gap is found, ram_size will be reported for + * consecutive memory only + */ + if (gd->bd->bi_dram[i].start != gd->ram_size) + break; + + gd->ram_size += gd->bd->bi_dram[i].size; + + } + return 0; +} + +/* + * If this function is not defined here, + * board.c alters dram bank zero configuration defined above. + */ +void dram_init_banksize(void) +{ + dram_init(); +} +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c new file mode 100644 index 0000000..b9ef8af --- /dev/null +++ b/arch/arm/cpu/arm926ejs/armada100/timer.c @@ -0,0 +1,199 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * Contributor: Mahavir Jain mjain@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/arch/armada100.h> + +/* + * Timer registers + * Refer Section A.6 in Datasheet + */ +struct armd1tmr_registers { + u32 clk_ctrl; /* Timer clk control reg */ + u32 match[9]; /* Timer match registers */ + u32 count[3]; /* Timer count registers */ + u32 status[3]; + u32 ie[3]; + u32 preload[3]; /* Timer preload value */ + u32 preload_ctrl[3]; + u32 wdt_match_en; + u32 wdt_match_r; + u32 wdt_val; + u32 wdt_sts; + u32 icr[3]; + u32 wdt_icr; + u32 cer; /* Timer count enable reg */ + u32 cmr; + u32 ilr[3]; + u32 wcr; + u32 wfar; + u32 wsar; + u32 cvwr; +}; + +struct armd1tmr_registers *armd1timers = + (struct armd1tmr_registers *) ARMD1_TIMER_BASE; + +#define TIMER 0 /* Use TIMER 0 */ +/* Each timer has 3 match registers */ +#define MATCH_CMP(x) ((3 * TIMER) + x) +#define TIMER_LOAD_VAL 0xffffffff + +/* For preventing risk of instability in reading counter value, + * first set read request to register cvwr and then read same + * register after it captures counter value. + */ +#define COUNT_RD_REQ 0x1 +#define READ_TIMER ({volatile int loop=100; \ + writel(COUNT_RD_REQ, &armd1timers->cvwr); \ + while (loop--); \ + readl(&armd1timers->cvwr);}) +static ulong timestamp; +static ulong lastdec; + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER; + + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + /* we have an overflow ... */ + timestamp += now + TIMER_LOAD_VAL - lastdec; + } + lastdec = now; + + return timestamp; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - + base); +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void __udelay(unsigned long usec) +{ + ulong delayticks; + ulong endtime; + + delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); + endtime = get_timer_masked() + delayticks; + + while (get_timer_masked() < endtime); +} + +/* + * init the Timer + */ +int timer_init(void) +{ + struct armd1apb1_registers *apb1clkres = + (struct armd1apb1_registers *) ARMD1_APBC1_BASE; + + /* Enable Timer clock at 3.25 MHZ */ + writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); + + /* load value into timer */ + writel(0x0, &armd1timers->clk_ctrl); + /* Use Timer 0 Match Resiger 0 */ + writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]); + /* Preload value is 0 */ + writel(0x0, &armd1timers->preload[TIMER]); + /* Enable match comparator 0 for Timer 0 */ + writel(0x1, &armd1timers->preload_ctrl[TIMER]); + + /* Enable timer 0 */ + writel(0x1, &armd1timers->cer); + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +#define MPMU_APRR_WDTR (1<<4) +#define TMR_WFAR 0xbaba /* WDT Register First key */ +#define TMP_WSAR 0xeb10 /* WDT Register Second key */ + +/* + * This function uses internal Watchdog Timer + * based reset mechanism. + * Steps to write watchdog registers (protected access) + * 1. Write key value to TMR_WFAR reg. + * 2. Write key value to TMP_WSAR reg. + * 3. Perform write operation. + */ +void reset_cpu (unsigned long ignored) +{ + struct armd1mpmu_registers *mpmu = + (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; + u32 val; + + /* negate hardware reset to the WDT after system reset */ + val = readl(&mpmu->aprr); + val = val | MPMU_APRR_WDTR; + writel(val, &mpmu->aprr); + + /* reset/enable WDT clock */ + writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr); + readl(&mpmu->wdtpcr); + writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); + readl(&mpmu->wdtpcr); + + /* clear previous WDT status */ + writel(TMR_WFAR, &armd1timers->wfar); + writel(TMP_WSAR, &armd1timers->wsar); + writel(0, &armd1timers->wdt_sts); + + /* set match counter */ + writel(TMR_WFAR, &armd1timers->wfar); + writel(TMP_WSAR, &armd1timers->wsar); + writel(0xf, &armd1timers->wdt_match_r); + + /* enable WDT reset */ + writel(TMR_WFAR, &armd1timers->wfar); + writel(TMP_WSAR, &armd1timers->wsar); + writel(0x3, &armd1timers->wdt_match_en); + + while(1); +} diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h new file mode 100644 index 0000000..5286eeb --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * Contributor: Mahavir Jain mjain@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_ARMADA100_H +#define _ASM_ARCH_ARMADA100_H + +#ifndef __ASSEMBLY__ +#include <asm/types.h> +#include <asm/io.h> +#endif /* __ASSEMBLY__ */ + +#if defined (CONFIG_ARMADA100) +#include <asm/arch/cpu.h> + +/* Common APB clock register bit definitions */ +#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ +#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ +#define APBC_RST (1<<2) /* Reset Generation */ +/* Functional Clock Selection Mask */ +#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) + +/* Register Base Addresses */ +#define ARMD1_DRAM_BASE 0xB0000000 +#define ARMD1_TIMER_BASE 0xD4014000 +#define ARMD1_APBC1_BASE 0xD4015000 +#define ARMD1_APBC2_BASE 0xD4015800 +#define ARMD1_UART1_BASE 0xD4017000 +#define ARMD1_UART2_BASE 0xD4018000 +#define ARMD1_GPIO_BASE 0xD4019000 +#define ARMD1_SSP1_BASE 0xD401B000 +#define ARMD1_SSP2_BASE 0xD401C000 +#define ARMD1_MFPR_BASE 0xD401E000 +#define ARMD1_SSP3_BASE 0xD401F000 +#define ARMD1_SSP4_BASE 0xD4020000 +#define ARMD1_SSP5_BASE 0xD4021000 +#define ARMD1_UART3_BASE 0xD4026000 +#define ARMD1_MPMU_BASE 0xD4050000 +#define ARMD1_APMU_BASE 0xD4282800 +#define ARMD1_CPU_BASE 0xD4282C00 + +/* + * Main Power Management (MPMU) Registers + * Refer Datasheet Appendix A.8 + */ +struct armd1mpmu_registers { + u32 pad0; + u32 fccr; /*0x0008*/ + u32 pocr; /*0x000c*/ + u32 posr; /*0x0010*/ + u32 succr; /*0x0014*/ + u8 pad1[0x030 - 0x014 - 4]; + u32 gpcr; /*0x0030*/ + u8 pad2[0x200 - 0x030 - 4]; + u32 wdtpcr; /*0x0200*/ + u8 pad3[0x1000 - 0x200 - 4]; + u32 apcr; /*0x1000*/ + u32 apsr; /*0x1004*/ + u8 pad4[0x1020 - 0x1004 - 4]; + u32 aprr; /*0x1020*/ + u32 acgr; /*0x1024*/ + u32 arsr; /*0x1028*/ +}; + +/* + * APB1 Clock Reset/Control Registers + * Refer Datasheet Appendix A.10 + */ +struct armd1apb1_registers { + u32 uart1; /*0x000*/ + u32 uart2; /*0x004*/ + u32 gpio; /*0x008*/ + u32 pwm1; /*0x00c*/ + u32 pwm2; /*0x010*/ + u32 pwm3; /*0x014*/ + u32 pwm4; /*0x018*/ + u8 pad0[0x028 - 0x018 - 4]; + u32 rtc; /*0x028*/ + u32 twsi0; /*0x02c*/ + u32 kpc; /*0x030*/ + u32 timers; /*0x034*/ + u32 aib; /*0x03c*/ + u32 sw_jtag; /*0x040*/ + u32 timer1; /*0x044*/ + u32 onewire; /*0x048*/ + u32 pad1; + u32 asfar; /*0x050 AIB Secure First Access Reg*/ + u32 assar; /*0x054 AIB Secure Second Access Reg*/ + u8 pad2[0x06c - 0x054 - 4]; + u32 twsi1; /*0x06c*/ + u32 uart3; /*0x070*/ + u8 pad3[0x07c - 0x070 - 4]; + u32 timer2; /*0x07C*/ + u32 pad4; + u32 ac97; /*0x084*/ +}; + +#endif /* CONFIG_ARMADA100 */ +#endif /* _ASM_ARCH_ARMADA100_H */ diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h new file mode 100644 index 0000000..0518a6a --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/cpu.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com, Contributor: Mahavir Jain mjain@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ARMADA100CPU_H +#define _ARMADA100CPU_H + +#include <asm/io.h> +#include <asm/system.h> + +/* + * CPU Interface Registers + * Refer Datasheet Appendix A.2 + */ +struct armd1cpu_registers { + u32 chip_id; /* Chip Id Reg */ + u32 pad; + u32 cpu_conf; /* CPU Conf Reg */ + u32 pad1; + u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ + u32 pad2; + u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ + u32 mcb_conf; /* MCB Conf Reg */ + u32 sys_boot_ctl; /* Sytem Boot Control */ +}; + +/* + * Functions + */ +u32 armd1_sdram_base(int); +u32 armd1_sdram_size(int); + +#endif /* _ARMADA100CPU_H */
From: Prafulla WADASKAR prafulla@marvell.com
ARMADA 100 SoCs has NS16550 compatible UART peripheral This patch enables the same for ARMADA100 platforms
Signed-off-by: Mahavir Jain mjain@marvell.com Signed-off-by: Prafulla WADASKAR prafulla@marvell.com --- drivers/serial/ns16550.c | 16 ++++++++++++++++ drivers/serial/serial.c | 3 +++ 2 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 32f24de..e57ed1f 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -26,7 +26,15 @@
void NS16550_init (NS16550_t com_port, int baud_divisor) { +#ifdef CONFIG_ARMADA100 + /* + * For ARMADA 100 Based Processors bit 6 in IER register + * represents UART Unit Enable bit. + */ + serial_out((1 << 6), &com_port->ier); +#else serial_out(0x00, &com_port->ier); +#endif #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif @@ -52,7 +60,15 @@ void NS16550_init (NS16550_t com_port, int baud_divisor) #ifndef CONFIG_NS16550_MIN_FUNCTIONS void NS16550_reinit (NS16550_t com_port, int baud_divisor) { +#ifdef CONFIG_ARMADA100 + /* + * For ARMADA 100 Based Processors bit 6 in IER register + * represents UART Unit Enable bit. + */ + serial_out((1 << 6), &com_port->ier); +#else serial_out(0x00, &com_port->ier); +#endif serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); serial_out(0, &com_port->dll); serial_out(0, &com_port->dlm); diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 1073ac0..f9a964e 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -33,6 +33,9 @@ #ifdef CONFIG_ORION5X #include <asm/arch/orion5x.h> #endif +#ifdef CONFIG_ARMADA100 +#include <asm/arch/armada100.h> +#endif
#if defined (CONFIG_SERIAL_MULTI) #include <serial.h>
Hi Prafulla,
On Wednesday 27 October 2010 15:53:21 Prafulla Wadaskar wrote:
ARMADA 100 SoCs has NS16550 compatible UART peripheral This patch enables the same for ARMADA100 platforms
Signed-off-by: Mahavir Jain mjain@marvell.com Signed-off-by: Prafulla WADASKAR prafulla@marvell.com
drivers/serial/ns16550.c | 16 ++++++++++++++++ drivers/serial/serial.c | 3 +++ 2 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 32f24de..e57ed1f 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -26,7 +26,15 @@
void NS16550_init (NS16550_t com_port, int baud_divisor) { +#ifdef CONFIG_ARMADA100
- /*
* For ARMADA 100 Based Processors bit 6 in IER register* represents UART Unit Enable bit.*/- serial_out((1 << 6), &com_port->ier);
+#else serial_out(0x00, &com_port->ier); +#endif
These board/platform specific driver additions are really ugly. A better way to do this would be something like this:
Add this to your board/platform header:
#define CONFIG_SYS_NS16550_IER (1 << 6)
And then to ns16550.c or even ns16550.h:
#ifndef CONFIG_SYS_NS16550_IER #define CONFIG_SYS_NS16550_IER 0x00 #endif
This macro can now be used unconditionally when initializing this "ier" register:
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
-----Original Message----- From: Stefan Roese [mailto:sr@denx.de] Sent: Wednesday, October 27, 2010 3:24 PM To: u-boot@lists.denx.de; Prabhanjan Sarnaik Cc: Prafulla Wadaskar; Manas Saksena; Lei Wen; Eric Miao Subject: Re: [U-Boot] [PATCH 2/5] Serial: Add UART support for Marvell ARMADA 100 SoCs.
Hi Prafulla,
On Wednesday 27 October 2010 15:53:21 Prafulla Wadaskar wrote:
ARMADA 100 SoCs has NS16550 compatible UART peripheral This patch enables the same for ARMADA100 platforms
Signed-off-by: Mahavir Jain mjain@marvell.com Signed-off-by: Prafulla WADASKAR prafulla@marvell.com
drivers/serial/ns16550.c | 16 ++++++++++++++++ drivers/serial/serial.c | 3 +++ 2 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 32f24de..e57ed1f 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -26,7 +26,15 @@
void NS16550_init (NS16550_t com_port, int baud_divisor) { +#ifdef CONFIG_ARMADA100
- /*
* For ARMADA 100 Based Processors bit 6 in IER register* represents UART Unit Enable bit.*/- serial_out((1 << 6), &com_port->ier);
+#else serial_out(0x00, &com_port->ier); +#endif
These board/platform specific driver additions are really ugly. A better way to do this would be something like this:
Add this to your board/platform header:
#define CONFIG_SYS_NS16550_IER (1 << 6)
And then to ns16550.c or even ns16550.h:
#ifndef CONFIG_SYS_NS16550_IER #define CONFIG_SYS_NS16550_IER 0x00 #endif
This macro can now be used unconditionally when initializing this "ier" register:
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
Thanks... I will do it for next version post.
Regards.. Prafulla . .
Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers For ex. ARMADA100.
These registers are programmed to expose the specific functionality associated with respective SoC Pins
This driver provides configuration APIs, using them, configuration need to be done in board specific code
for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality
int board_early_init_f(void) { u32 mfp_cfg[] = { /* Console on UART1 */ MFP107_UART1_RXD, MFP108_UART1_TXD, MFP_EOC /*End of configureation*/ }; /* configure MFP's */ mfp_config(mfp_cfg); return 0; }
Signed-off-by: Prafulla Wadaskar prafulla@marvell.com --- drivers/gpio/Makefile | 1 + drivers/gpio/mfp.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++ include/mfp.h | 97 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 203 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/mfp.c create mode 100644 include/mfp.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index a0f4552..7590b22 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libgpio.a
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +COBJS-$(CONFIG_MFP) += mfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_S5P) += s5p_gpio.o diff --git a/drivers/gpio/mfp.c b/drivers/gpio/mfp.c new file mode 100644 index 0000000..a0278db --- /dev/null +++ b/drivers/gpio/mfp.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <mfp.h> +#include <asm/arch/mfp.h> +#ifdef CONFIG_ARMADA100 +#include <asm/arch/armada100.h> +#define MFPR_BASE ARMD1_MFPR_BASE; +#else +#error Unsupported SoC... +#endif + +/* + * mfp_config + * + * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin + * configuration registers to configure each GPIO/Function pin on the + * SoC. + * + * This function reads the array of values for + * MFPR_X registers and programms them into respective + * Multi-Function Pin registers. + * It supports - Alternate Function Selection programming. + * + * Whereas, + * The Configureation value is constructed using ARMD_MFP() + * array consists of 32bit values as- + * Bits 31-16 : Mfp instance number (i.e. MFPR no. to be programmed) + * Bits 15-13 : PULL_UP/PULL_DOWN selection + * Bits 11:10 : Pin Driver strength + * Bits 6-4 : Edge detection configuration + * Bits 2-0 : Alternate Function Selection + * + * For more details please refer respective Product Software Manual + */ +void mfp_config(u32 *mfp_cfgs) +{ + u32 *p_mfpr = NULL; + u32 val, cfg_val, mfpr_no; + + do { + cfg_val = *mfp_cfgs++; + /* exit if End of configuration table detected */ + if (cfg_val == MFP_EOC) + break; + /* abstract mfpr tobe programmed from configuration value */ + mfpr_no = (cfg_val & MFP_PINNO_MASK) >> 16; + BUG_ON(mfpr_no >= MFP_PIN_MAX); + + /* the offset address are divided in three regions and not + * consecutive, this corrects the same (Ref: Specs: A1.1) */ + p_mfpr = (u32 *)MFPR_BASE; + if ( mfpr_no < 37) + p_mfpr += (0x004c / 4) + mfpr_no; + else if ( mfpr_no >= 56) + p_mfpr += (0x00e0 / 4) + (mfpr_no - 56); + else + p_mfpr += (mfpr_no - 37); + /*p_mfpr contains address of register to be programmed */ + + val = readl(p_mfpr) & ~MFP_AF_MASK; + /* Abstract and program Afternate-Function Selection from cfg_val */ + if (cfg_val & MFP_CFG_AF) + val |= cfg_val & MFP_AF_MASK; + /* Abstract and program Edge configuration from cfg_val */ + if (cfg_val & MFP_CFG_EDGE) + val |= cfg_val & MFP_LPM_EDGE_MASK; + /* Abstract and program Drive configuration from cfg_val */ + if (cfg_val & MFP_CFG_DRIVE) + val |= cfg_val & MFP_DRIVE_MASK; + /* Abstract and program Pullup/down configuration from cfg_val */ + if (cfg_val & MFP_CFG_PULL) + val |= cfg_val & MFP_PULL_MASK; + + writel(val, p_mfpr); + } while (1); + /* + * perform a read-back of any MFPR register to make sure the + * previous writings are finished + */ + readl(p_mfpr); +} diff --git a/include/mfp.h b/include/mfp.h new file mode 100644 index 0000000..a82dffb --- /dev/null +++ b/include/mfp.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MFP_H +#define __MFP_H + +/* + * Header file for MultiFunctionPin (MFP) Configururation framework + * + * Processors Supported: + * 1. Marvell ARMADA100 Processors + * + * processor to be supported should be added here + */ + +#define MFP_EOC 0xffffffff /* flag to indicate end-of-configuration */ + +/* + * Possible MFP configuration is represented by a 32-bit unsigned integer + * + * bit 0.. 2 - Alternate Function Selection + * bit 4.. 6 - Edge Detection + * bit 7.. 9 - Type of configuration + * bit 10..11 - Drive Strength + * bit 13..15 - Run Mode Pull State + * bit 16..31 - Used to hold MFP number to be configured + * + * to facilitate the definition, the following macros are provided + */ + +#define MFP_AF0 (0x0 << 0) +#define MFP_AF1 (0x1 << 0) +#define MFP_AF2 (0x2 << 0) +#define MFP_AF3 (0x3 << 0) +#define MFP_AF4 (0x4 << 0) +#define MFP_AF5 (0x5 << 0) +#define MFP_AF6 (0x6 << 0) +#define MFP_AF7 (0x7 << 0) +#define MFP_AF_MASK (0x7 << 0) + +#define MFP_LPM_EDGE_NONE (0x0 << 4) +#define MFP_LPM_EDGE_RISE (0x1 << 4) +#define MFP_LPM_EDGE_FALL (0x2 << 4) +#define MFP_LPM_EDGE_BOTH (0x3 << 4) +#define MFP_LPM_EDGE_MASK (0x3 << 4) + +/* unused bits are used to identify config type */ +#define MFP_CFG_AF (0x1 << 7) +#define MFP_CFG_DRIVE (0x1 << 8) +#define MFP_CFG_EDGE (0x1 << 9) +#define MFP_CFG_PULL (0x1 << 3) + +#define MFP_DRIVE_VERY_SLOW (0x0 << 10) +#define MFP_DRIVE_SLOW (0x1 << 10) +#define MFP_DRIVE_MEDIUM (0x2 << 10) +#define MFP_DRIVE_FAST (0x3 << 10) +#define MFP_DRIVE_MASK (0x3 << 10) + +#define MFP_PULL_NONE (0x0 << 13) +#define MFP_PULL_LOW (0x1 << 13) +#define MFP_PULL_HIGH (0x2 << 13) +#define MFP_PULL_BOTH (0x3 << 13) +#define MFP_PULL_FLOAT (0x4 << 13) +#define MFP_PULL_MASK (0x7 << 13) + +#define MFP_PINNO_MASK (0xffff << 16) + +#define MFP_AF(af) (MFP_CFG_AF | MFP_AF##af) +#define MFP_DRIVE(drv) (MFP_CFG_DRIVE | MFP_DRIVE_##drv) +#define MFP_EDGE(edge) (MFP_CFG_EDGE | MFP_LPM_EDGE_##edge) +#define MFP_PULL(pull) (MFP_CFG_PULL | MFP_PULL_##pull) +#define MFP(pin) (MFP_PINNO_MASK & (pin << 16)) + +void mfp_config(u32 *mfp_cfgs); + +#endif /* __MFP_H */
This patch adds the support MFP support for Marvell ARMADA100 SoCs
Signed-off-by: Prafulla Wadaskar prafulla@marvell.com --- arch/arm/include/asm/arch-armada100/mfp.h | 218 +++++++++++++++++++++++++++++ 1 files changed, 218 insertions(+), 0 deletions(-) create mode 100755 arch/arm/include/asm/arch-armada100/mfp.h
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h new file mode 100755 index 0000000..eddcef7 --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -0,0 +1,218 @@ +/* + * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h + * (C) Copyright 2007 + * Marvell Semiconductor <www.marvell.com> + * 2007-08-21: eric miao eric.miao@marvell.com + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * Contributor: Mahavir Jain mjain@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ARMADA100_MFP_H +#define __ARMADA100_MFP_H + +/* By default Pin Drive is set to medium */ +#define MFPD(x) MFP(x) | MFP_DRIVE(MEDIUM) + +/* GPIOs */ +#define GPIOAF(x) (if (x <= 15) ? 5 : \ + if (x == 16) ? 0 : \ + if (x == 17) ? 5 : \ + if (x == 18) ? 0 : \ + if (x == 19) ? 5 : \ + if (x == 20) ? 0 : \ + if (x <= 25) ? 5 : \ + if (x == 26) ? 0 : \ + if (x == 33) ? 5 : 0) + +#define MFP_GPIO(x) MFPD(x) | MFP_AF(GPIOAF(x)) + +/* UART2 */ +#define MFP47_UART2_RXD MFPD(47) | MFP_AF(6) +#define MFP48_UART2_TXD MFPD(48) | MFP_AF(6) +#define MFP88_UART2_RXD MFPD(88) | MFP_AF(2) +#define MFP89_UART2_TXD MFPD(89) | MFP_AF(2) + +/* UART3 */ +#define GPIO8_UART3_RXD MFPD(8) | MFP_AF(2) +#define GPIO9_UART3_TXD MFPD(9) | MFP_AF(2) + +/* MFU */ +#define MFP86_TX_CLK MFPD(86) | MFP_AF(5) +#define MFP87_TX_EN MFPD(87) | MFP_AF(5) +#define MFP88_TX_DQ3 MFPD(88) | MFP_AF(5) +#define MFP89_TX_DQ2 MFPD(89) | MFP_AF(5) +#define MFP90_TX_DQ1 MFPD(90) | MFP_AF(5) +#define MFP91_TX_DQ0 MFPD(91) | MFP_AF(5) +#define MFP92_MII_CRS MFPD(92) | MFP_AF(5) +#define MFP93_MII_COL MFPD(93) | MFP_AF(5) +#define MFP94_RX_CLK MFPD(94) | MFP_AF(5) +#define MFP95_RX_ER MFPD(95) | MFP_AF(5) +#define MFP96_RX_DQ3 MFPD(96) | MFP_AF(5) +#define MFP97_RX_DQ2 MFPD(97) | MFP_AF(5) +#define MFP98_RX_DQ1 MFPD(98) | MFP_AF(5) +#define MFP99_RX_DQ0 MFPD(99) | MFP_AF(5) +#define MFP100_MII_MDC MFPD(100) | MFP_AF(5) +#define MFP101_MII_MDIO MFPD(101) | MFP_AF(5) +#define MFP103_RX_DV MFPD(103) | MFP_AF(5) + +/* SSP2*/ +#define MFP107_SPI_NOR_RXD MFPD(107) | MFP_AF(4) +#define MFP108_SPI_NOR_TXD MFPD(108) | MFP_AF(4) +#define MFP109_SPI_NOR_SYSCLK MFPD(109) | MFP_AF(4) +#define MFP111_SPI_NOR_CLK MFPD(111) | MFP_AF(4) + +/* DFI */ +#define MFP0_DFI_D15 MFPD(0) | MFP_AF(0) +#define MFP1_DFI_D14 MFPD(1) | MFP_AF(0) +#define MFP2_DFI_D13 MFPD(2) | MFP_AF(0) +#define MFP3_DFI_D12 MFPD(3) | MFP_AF(0) +#define MFP4_DFI_D11 MFPD(4) | MFP_AF(0) +#define MFP5_DFI_D10 MFPD(5) | MFP_AF(0) +#define MFP6_DFI_D9 MFPD(6) | MFP_AF(0) +#define MFP7_DFI_D8 MFPD(7) | MFP_AF(0) +#define MFP8_DFI_D7 MFPD(8) | MFP_AF(0) +#define MFP9_DFI_D6 MFPD(9) | MFP_AF(0) +#define MFP10_DFI_D5 MFPD(10) | MFP_AF(0) +#define MFP11_DFI_D4 MFPD(11) | MFP_AF(0) +#define MFP12_DFI_D3 MFPD(12) | MFP_AF(0) +#define MFP13_DFI_D2 MFPD(13) | MFP_AF(0) +#define MFP14_DFI_D1 MFPD(14) | MFP_AF(0) +#define MFP15_DFI_D0 MFPD(15) | MFP_AF(0) + +#define MFP30_DFI_ADDR0 MFPD(30) | MFP_AF(0) +#define MFP31_DFI_ADDR1 MFPD(31) | MFP_AF(0) +#define MFP32_DFI_ADDR2 MFPD(32) | MFP_AF(0) +#define MFP33_DFI_ADDR3 MFPD(33) | MFP_AF(0) + +/* NAND */ +#define MFP16_ND_nCS0 MFPD(16) | MFP_AF(1) +#define MFP17_ND_nWE MFPD(17) | MFP_AF(0) +#define MFP21_ND_ALE MFPD(21) | MFP_AF(0) +#define MFP22_ND_CLE MFPD(22) | MFP_AF(0) +#define MFP24_ND_nRE MFPD(24) | MFP_AF(0) +#define MFP26_ND_RnB1 MFPD(26) | MFP_AF(1) +#define MFP27_ND_RnB2 MFPD(27) | MFP_AF(1) + +/* Static Memory Controller */ +#define MFP18_SMC_nCS0 MFPD(18) | MFP_AF(3) +#define MFP18_SMC_nCS1 MFPD(18) | MFP_AF(2) +#define MFP16_SMC_nCS0 MFPD(16) | MFP_AF(2) +#define MFP16_SMC_nCS1 MFPD(16) | MFP_AF(3) +#define MFP19_SMC_nCS0 MFPD(19) | MFP_AF(0) +#define MFP20_SMC_nCS1 MFPD(20) | MFP_AF(2) +#define MFP23_SMC_nLUA MFPD(23) | MFP_AF(0) +#define MFP25_SMC_nLLA MFPD(25) | MFP_AF(0) +#define MFP27_SMC_IRQ MFPD(27) | MFP_AF(0) +#define MFP28_SMC_RDY MFPD(28) | MFP_AF(0) +#define MFP29_SMC_SCLK MFPD(29) | MFP_AF(0) +#define MFP34_SMC_nCS1 MFPD(34) | MFP_AF(2) +#define MFP35_SMC_BE1 MFPD(35) | MFP_AF(2) +#define MFP36_SMC_BE2 MFPD(36) | MFP_AF(2) + +/* Compact Flash */ +#define MFP19_CF_nCE1 MFPD(19) | MFP_AF(3) +#define MFP20_CF_nCE2 MFPD(20) | MFP_AF(3) +#define MFP23_CF_nALE MFPD(23) | MFP_AF(3) +#define MFP25_CF_nRESET MFPD(25) | MFP_AF(3) +#define MFP28_CF_RDY MFPD(28) | MFP_AF(3) +#define MFP29_CF_STSCH MFPD(29) | MFP_AF(3) +#define MFP30_CF_nREG MFPD(30) | MFP_AF(3) +#define MFP31_CF_nIOIS16 MFPD(31) | MFP_AF(3) +#define MFP32_CF_nCD1 MFPD(32) | MFP_AF(3) +#define MFP33_CF_nCD2 MFPD(33) | MFP_AF(3) + +/* UART1 */ +#define MFP107_UART1_TXD MFP(107) | MFP_AF(1) | MFP_DRIVE(FAST) +#define MFP107_UART1_RXD MFP(107) | MFP_AF(2) | MFP_DRIVE(FAST) +#define MFP108_UART1_RXD MFP(108) | MFP_AF(1) | MFP_DRIVE(FAST) +#define MFP108_UART1_TXD MFP(108) | MFP_AF(2) | MFP_DRIVE(FAST) +#define MFP109_UART1_CTS MFPD(109) | MFP_AF(1) +#define MFP109_UART1_RTS MFPD(109) | MFP_AF(2) +#define MFP110_UART1_RTS MFPD(110) | MFP_AF(1) +#define MFP110_UART1_CTS MFPD(110) | MFP_AF(2) +#define MFP111_UART1_RI MFPD(111) | MFP_AF(1) +#define MFP111_UART1_DSR MFPD(111) | MFP_AF(2) +#define MFP112_UART1_DTR MFPD(111) | MFP_AF(1) +#define MFP112_UART1_DCD MFPD(112) | MFP_AF(2) + +/* MMC1 */ +#define MFP37_MMC1_DAT7 MFPD(37) | MFP_AF(1) +#define MFP38_MMC1_DAT6 MFPD(38) | MFP_AF(1) +#define MFP54_MMC1_DAT5 MFPD(54) | MFP_AF(1) +#define MFP48_MMC1_DAT4 MFPD(48) | MFP_AF(1) +#define MFP51_MMC1_DAT3 MFPD(51) | MFP_AF(1) +#define MFP52_MMC1_DAT2 MFPD(52) | MFP_AF(1) +#define MFP40_MMC1_DAT1 MFPD(40) | MFP_AF(1) +#define MFP41_MMC1_DAT0 MFPD(41) | MFP_AF(1) +#define MFP49_MMC1_CMD MFPD(49) | MFP_AF(1) +#define MFP43_MMC1_CLK MFPD(43) | MFP_AF(1) +#define MFP53_MMC1_CD MFPD(53) | MFP_AF(1) +#define MFP46_MMC1_WP MFPD(46) | MFP_AF(1) + +/* LCD */ +#define MFP84_LCD_CS MFPD(84) | MFP_AF(1) +#define MFP60_LCD_DD0 MFPD(60) | MFP_AF(1) +#define MFP61_LCD_DD1 MFPD(61) | MFP_AF(1) +#define MFP70_LCD_DD10 MFPD(70) | MFP_AF(1) +#define MFP71_LCD_DD11 MFPD(71) | MFP_AF(1) +#define MFP72_LCD_DD12 MFPD(72) | MFP_AF(1) +#define MFP73_LCD_DD13 MFPD(73) | MFP_AF(1) +#define MFP74_LCD_DD14 MFPD(74) | MFP_AF(1) +#define MFP75_LCD_DD15 MFPD(75) | MFP_AF(1) +#define MFP76_LCD_DD16 MFPD(76) | MFP_AF(1) +#define MFP77_LCD_DD17 MFPD(77) | MFP_AF(1) +#define MFP78_LCD_DD18 MFPD(78) | MFP_AF(1) +#define MFP79_LCD_DD19 MFPD(79) | MFP_AF(1) +#define MFP62_LCD_DD2 MFPD(62) | MFP_AF(1) +#define MFP80_LCD_DD20 MFPD(80) | MFP_AF(1) +#define MFP81_LCD_DD21 MFPD(81) | MFP_AF(1) +#define MFP82_LCD_DD22 MFPD(82) | MFP_AF(1) +#define MFP83_LCD_DD23 MFPD(83) | MFP_AF(1) +#define MFP63_LCD_DD3 MFPD(63) | MFP_AF(1) +#define MFP64_LCD_DD4 MFPD(64) | MFP_AF(1) +#define MFP65_LCD_DD5 MFPD(65) | MFP_AF(1) +#define MFP66_LCD_DD6 MFPD(66) | MFP_AF(1) +#define MFP67_LCD_DD7 MFPD(67) | MFP_AF(1) +#define MFP68_LCD_DD8 MFPD(68) | MFP_AF(1) +#define MFP69_LCD_DD9 MFPD(69) | MFP_AF(1) +#define MFP59_LCD_DENA_BIAS MFPD(59) | MFP_AF(1) +#define MFP56_LCD_FCLK_RD MFPD(56) | MFP_AF(1) +#define MFP57_LCD_LCLK_A0 MFPD(57) | MFP_AF(1) +#define MFP58_LCD_PCLK_WR MFPD(58) | MFP_AF(1) +#define MFP85_LCD_VSYNC MFPD(85) | MFP_AF(1) + +/* I2C */ +#define MFP105_CI2C_SDA MFPD(105) | MFP_AF(1) +#define MFP106_CI2C_SCL MFPD(106) | MFP_AF(1) + +/* I2S */ +#define MFP113_I2S_MCLK MFPD(113), MFP_AF(6) +#define MFP114_I2S_FRM MFPD(114), MFP_AF(1) +#define MFP115_I2S_BCLK MFPD(115), MFP_AF(1) +#define MFP116_I2S_RXD MFPD(116), MFP_AF(2) +#define MFP117_I2S_TXD MFPD(117), MFP_AF(2) + +#define MFP_PIN_MAX 117 + +#endif /* __ARMADA100_MFP_H */
From: Prafulla WADASKAR prafulla@marvell.com
Aspenite is a Development Board for ASPEN/ARMADA168 (88AP168) Processor upto 1.2GHz with * Parallel 1Gb x8 DDR2-1066 MHz * 16 Mb x16 NOR, 4Gb x8 SLC NAND, footprint for SPI NOR * Footprints for eMMC/eSD NAND & MMC x8 card * 4-in-1 card reader (xD, MMC/SD/MS Pro), CF True IDE socket * SEAF memory board, subset of PISMO2 With Peripherals: * 4.3” WVGA 24-bit LCD * Audio codecs (AC97 & I2S), TSI * VGA camera * Video in via 3 RCA jacks, and HDMI type C out * Marvell 88W8688 802.11bg/BT module * GPS RF IC * Dual analog mics & speakers, headset jack, LED, ambient light sensor * USB2.0 HS host (A), OTG (micro AB) * FE PHY, PCIE Mini Card slot * GPIO, GPIO expander with DIP switches for easier selection UART serial over USB, CIR
This patch adds basic board support with DRAM and UART functionality The patch is tested for boot from DRAM using XDB
Signed-off-by: Mahavir Jain mjain@marvell.com Signed-off-by: Prafulla Wadaskar prafulla@marvell.com --- MAINTAINERS | 1 + MAKEALL | 1 + board/Marvell/aspenite/Makefile | 52 ++++++++++++++ board/Marvell/aspenite/aspenite.c | 53 +++++++++++++++ board/Marvell/aspenite/config.mk | 26 +++++++ boards.cfg | 1 + include/configs/aspenite.h | 133 +++++++++++++++++++++++++++++++++++++ 7 files changed, 267 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/aspenite/Makefile create mode 100644 board/Marvell/aspenite/aspenite.c create mode 100644 board/Marvell/aspenite/config.mk create mode 100644 include/configs/aspenite.h
diff --git a/MAINTAINERS b/MAINTAINERS index 2f61776..ea4121b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -831,6 +831,7 @@ Matt Waddel matt.waddel@linaro.org
Prafulla Wadaskar prafulla@marvell.com
+ aspenite ARM926EJS (ARMADA100 88AP168 SoC) mv88f6281gtw_ge ARM926EJS (Kirkwood SoC) rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) diff --git a/MAKEALL b/MAKEALL index 51312dd..345aa3a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -320,6 +320,7 @@ LIST_ARM9=" \ ap926ejs \ ap946es \ ap966 \ + aspenite \ cp920t \ cp922_XA10 \ cp926ejs \ diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile new file mode 100644 index 0000000..7ec7727 --- /dev/null +++ b/board/Marvell/aspenite/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2010 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# Contributor: Mahavir Jain mjain@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := aspenite.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c new file mode 100644 index 0000000..e7bc3eb --- /dev/null +++ b/board/Marvell/aspenite/aspenite.c @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * Contributor: Mahavir Jain mjain@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <mfp.h> +#include <asm/arch/mfp.h> +#include <asm/arch/armada100.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + u32 mfp_cfg[] = { + /* Enable Console on UART1 */ + MFP107_UART1_RXD, + MFP108_UART1_TXD, + MFP_EOC /*End of configureation*/ + }; + /* configure MFP's */ + mfp_config(mfp_cfg); + return 0; +} + +int board_init(void) +{ + /* arch number of Board */ + gd->bd->bi_arch_number = MACH_TYPE_ASPENITE; + /* adress of boot parameters */ + gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; + return 0; +} diff --git a/board/Marvell/aspenite/config.mk b/board/Marvell/aspenite/config.mk new file mode 100644 index 0000000..8c91984 --- /dev/null +++ b/board/Marvell/aspenite/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2010 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# Contributor: Mahavir Jain mjain@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +CONFIG_SYS_TEXT_BASE = 0x0600000 diff --git a/boards.cfg b/boards.cfg index 0f3292f..82bdd19 100644 --- a/boards.cfg +++ b/boards.cfg @@ -373,6 +373,7 @@ davinci_sffsdr arm arm926ejs sffsdr davinci davinci davinci_sonata arm arm926ejs sonata davinci davinci da830evm arm arm926ejs da8xxevm davinci davinci da850evm arm arm926ejs da8xxevm davinci davinci +aspenite arm arm926ejs - Marvell armada100 guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood openrd_base arm arm926ejs - Marvell kirkwood diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h new file mode 100644 index 0000000..30b083c --- /dev/null +++ b/include/configs/aspenite.h @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * Contributor: Mahavir Jain mjain@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __CONFIG_ASPENITE_H +#define __CONFIG_ASPENITE_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nMarvell-Aspenite DB" + +/* + * High Level Configuration Options + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ +#define CONFIG_ARMADA100 1 /* SOC Family Name */ +#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ +#define CONFIG_MACH_ASPENITE /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_BOARD_EARLY_INIT_F /* Do mfp config in board_init_f */ +#define CONFIG_MFP /* Enable MFP driver */ + +/* + * CLKs configuration + */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK 14745600 +#define CONFIG_SYS_NS16550_COM1 ARMD1_UART1_BASE +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_SERIAL + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ +#define CONFIG_CONS_INDEX 1 /*Console on UART3 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400, 460800, 921600 } +/* auto boot */ +#define CONFIG_BOOTDELAY 3 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ +#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_NET + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#define CONFIG_ENV_SIZE 0x20000 /* 64k */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1 MiB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ + +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* + * There is no internal RAM in ARMADA100, using DRAM + * TBD: dcache to be used for this + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) + +#define CONFIG_STACKSIZE 0x00100000 /* _1M regular stack */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load address */ +#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8 MB */ +#define CONFIG_SYS_MEMTEST_END 0x00FFFFFF /* 15 MB- 1 */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +#endif /* __CONFIG_ASPENITE_H */
Dear Prafulla Wadaskar,
In message 1288187604-3371-6-git-send-email-prafulla@marvell.com you wrote: ...
MAINTAINERS | 1 + MAKEALL | 1 + board/Marvell/aspenite/Makefile | 52 ++++++++++++++ board/Marvell/aspenite/aspenite.c | 53 +++++++++++++++ board/Marvell/aspenite/config.mk | 26 +++++++ boards.cfg | 1 + include/configs/aspenite.h | 133 +++++++++++++++++++++++++++++++++++++ 7 files changed, 267 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/aspenite/Makefile create mode 100644 board/Marvell/aspenite/aspenite.c create mode 100644 board/Marvell/aspenite/config.mk create mode 100644 include/configs/aspenite.h
Please don't create a config.mk file any more (move CONFIG_SYS_TEXT_BASE setting to board config file), and please also do not create an entry to MAKEALL (gets auto-generated from boards.cfg).
Thanks.
Best regards,
Wolfgang Denk
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Wednesday, October 27, 2010 11:59 PM To: Prafulla Wadaskar Cc: u-boot@lists.denx.de; Manas Saksena; Lei Wen; Yu Tang; Eric Miao; Ashish Karkare; Kiran Vedere; Prabhanjan Sarnaik Subject: Re: [U-Boot] [PATCH 5/5] Armada100: Add Board Support for Marvell Aspenite-DB
Dear Prafulla Wadaskar,
In message 1288187604-3371-6-git-send-email-prafulla@marvell.com you wrote: ...
MAINTAINERS | 1 + MAKEALL | 1 + board/Marvell/aspenite/Makefile | 52 ++++++++++++++ board/Marvell/aspenite/aspenite.c | 53 +++++++++++++++ board/Marvell/aspenite/config.mk | 26 +++++++ boards.cfg | 1 + include/configs/aspenite.h | 133
+++++++++++++++++++++++++++++++++++++
7 files changed, 267 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/aspenite/Makefile create mode 100644 board/Marvell/aspenite/aspenite.c create mode 100644 board/Marvell/aspenite/config.mk create mode 100644 include/configs/aspenite.h
Please don't create a config.mk file any more (move CONFIG_SYS_TEXT_BASE setting to board config file), and please also do not create an entry to MAKEALL (gets auto-generated from boards.cfg).
Hi Wolfgang
Entry in boards.cfg already done, I am sorry for config.mk, I will change it.
Thanks Regards... Prafulla . .
Dear Prafulla Wadaskar,
In message 1288187604-3371-5-git-send-email-prafulla@marvell.com you wrote:
This patch adds the support MFP support for Marvell ARMADA100 SoCs
Signed-off-by: Prafulla Wadaskar prafulla@marvell.com
There is a typo in the Subject: please s/Fnction/Function/
[No need to repost beause of this; this can be fixed when the patch gets comitted.]
Best regards,
Wolfgang Denk
participants (3)
-
Prafulla Wadaskar -
Stefan Roese -
Wolfgang Denk