Synchronize RZ/G2M SoC DTs with mainline Linux 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4")

Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- arch/arm/dts/r8a774a1.dtsi | 10 +- include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 96 +++++++++---------- include/dt-bindings/power/r8a774a1-sysc.h | 2 - 3 files changed, 51 insertions(+), 57 deletions(-)

diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi index a603d94797..8e80f50132 100644 --- a/arch/arm/dts/r8a774a1.dtsi +++ b/arch/arm/dts/r8a774a1.dtsi @@ -10,6 +10,8 @@ #include <dt-bindings/clock/r8a774a1-cpg-mssr.h> #include <dt-bindings/power/r8a774a1-sysc.h>

+#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 + / { compatible = "renesas,r8a774a1"; #address-cells = <2>; @@ -2250,7 +2252,7 @@ status = "disabled"; };

- sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; @@ -2262,7 +2264,7 @@ status = "disabled"; };

- sdhi1: sd@ee120000 { + sdhi1: mmc@ee120000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; @@ -2274,7 +2276,7 @@ status = "disabled"; };

- sdhi2: sd@ee140000 { + sdhi2: mmc@ee140000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; @@ -2286,7 +2288,7 @@ status = "disabled"; };

- sdhi3: sd@ee160000 { + sdhi3: mmc@ee160000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h index ac3fde148c..67bf8cdf49 100644 --- a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h @@ -10,56 +10,50 @@ /* r8a774a1 CPG Core Clocks */ #define R8A774A1_CLK_Z 0 #define R8A774A1_CLK_Z2 1 -#define R8A774A1_CLK_ZR 2 -#define R8A774A1_CLK_ZG 3 -#define R8A774A1_CLK_ZTR 4 -#define R8A774A1_CLK_ZTRD2 5 -#define R8A774A1_CLK_ZT 6 -#define R8A774A1_CLK_ZX 7 -#define R8A774A1_CLK_S0D1 8 -#define R8A774A1_CLK_S0D2 9 -#define R8A774A1_CLK_S0D3 10 -#define R8A774A1_CLK_S0D4 11 -#define R8A774A1_CLK_S0D6 12 -#define R8A774A1_CLK_S0D8 13 -#define R8A774A1_CLK_S0D12 14 -#define R8A774A1_CLK_S1D1 15 -#define R8A774A1_CLK_S1D2 16 -#define R8A774A1_CLK_S1D4 17 -#define R8A774A1_CLK_S2D1 18 -#define R8A774A1_CLK_S2D2 19 -#define R8A774A1_CLK_S2D4 20 -#define R8A774A1_CLK_S3D1 21 -#define R8A774A1_CLK_S3D2 22 -#define R8A774A1_CLK_S3D4 23 -#define R8A774A1_CLK_LB 24 -#define R8A774A1_CLK_CL 25 -#define R8A774A1_CLK_ZB3 26 -#define R8A774A1_CLK_ZB3D2 27 -#define R8A774A1_CLK_ZB3D4 28 -#define R8A774A1_CLK_CR 29 -#define R8A774A1_CLK_CRD2 30 -#define R8A774A1_CLK_SD0H 31 -#define R8A774A1_CLK_SD0 32 -#define R8A774A1_CLK_SD1H 33 -#define R8A774A1_CLK_SD1 34 -#define R8A774A1_CLK_SD2H 35 -#define R8A774A1_CLK_SD2 36 -#define R8A774A1_CLK_SD3H 37 -#define R8A774A1_CLK_SD3 38 -#define R8A774A1_CLK_SSP2 39 -#define R8A774A1_CLK_SSP1 40 -#define R8A774A1_CLK_SSPRS 41 -#define R8A774A1_CLK_RPC 42 -#define R8A774A1_CLK_RPCD2 43 -#define R8A774A1_CLK_MSO 44 -#define R8A774A1_CLK_CANFD 45 -#define R8A774A1_CLK_HDMI 46 -#define R8A774A1_CLK_CSI0 47 -#define R8A774A1_CLK_CSIREF 48 -#define R8A774A1_CLK_CP 49 -#define R8A774A1_CLK_CPEX 50 -#define R8A774A1_CLK_R 51 -#define R8A774A1_CLK_OSC 52 +#define R8A774A1_CLK_ZG 2 +#define R8A774A1_CLK_ZTR 3 +#define R8A774A1_CLK_ZTRD2 4 +#define R8A774A1_CLK_ZT 5 +#define R8A774A1_CLK_ZX 6 +#define R8A774A1_CLK_S0D1 7 +#define R8A774A1_CLK_S0D2 8 +#define R8A774A1_CLK_S0D3 9 +#define R8A774A1_CLK_S0D4 10 +#define R8A774A1_CLK_S0D6 11 +#define R8A774A1_CLK_S0D8 12 +#define R8A774A1_CLK_S0D12 13 +#define R8A774A1_CLK_S1D2 14 +#define R8A774A1_CLK_S1D4 15 +#define R8A774A1_CLK_S2D1 16 +#define R8A774A1_CLK_S2D2 17 +#define R8A774A1_CLK_S2D4 18 +#define R8A774A1_CLK_S3D1 19 +#define R8A774A1_CLK_S3D2 20 +#define R8A774A1_CLK_S3D4 21 +#define R8A774A1_CLK_LB 22 +#define R8A774A1_CLK_CL 23 +#define R8A774A1_CLK_ZB3 24 +#define R8A774A1_CLK_ZB3D2 25 +#define R8A774A1_CLK_ZB3D4 26 +#define R8A774A1_CLK_CR 27 +#define R8A774A1_CLK_CRD2 28 +#define R8A774A1_CLK_SD0H 29 +#define R8A774A1_CLK_SD0 30 +#define R8A774A1_CLK_SD1H 31 +#define R8A774A1_CLK_SD1 32 +#define R8A774A1_CLK_SD2H 33 +#define R8A774A1_CLK_SD2 34 +#define R8A774A1_CLK_SD3H 35 +#define R8A774A1_CLK_SD3 36 +#define R8A774A1_CLK_RPC 37 +#define R8A774A1_CLK_RPCD2 38 +#define R8A774A1_CLK_MSO 39 +#define R8A774A1_CLK_HDMI 40 +#define R8A774A1_CLK_CSI0 41 +#define R8A774A1_CLK_CP 42 +#define R8A774A1_CLK_CPEX 43 +#define R8A774A1_CLK_R 44 +#define R8A774A1_CLK_OSC 45 +#define R8A774A1_CLK_CANFD 46

#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h index d84ea0eb12..d35183557c 100644 --- a/include/dt-bindings/power/r8a774a1-sysc.h +++ b/include/dt-bindings/power/r8a774a1-sysc.h @@ -18,12 +18,10 @@ #define R8A774A1_PD_CA53_CPU2 7 #define R8A774A1_PD_CA53_CPU3 8 #define R8A774A1_PD_CA57_SCU 12 -#define R8A774A1_PD_CR7 13 #define R8A774A1_PD_A3VC 14 #define R8A774A1_PD_3DG_A 17 #define R8A774A1_PD_3DG_B 18 #define R8A774A1_PD_CA53_SCU 21 -#define R8A774A1_PD_A3IR 24 #define R8A774A1_PD_A2VC0 25 #define R8A774A1_PD_A2VC1 26

The HiHope RZ/G2M board from HopeRun consists of main board (HopeRun HiHope RZ/G2M main board) and sub board(HopeRun HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M main board.

DTS files apart from r8a774a1-hihope-rzg2m-u-boot.dts and r8a774a1-u-boot.dtsi have been imported from Linux kernel 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4")

This patch adds the required board support to boot HopeRun HiHope RZ/G2M board.

Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/hihope-common.dtsi | 377 ++++++++++++++++++ arch/arm/dts/hihope-rev4.dtsi | 124 ++++++ arch/arm/dts/hihope-rzg2-ex.dtsi | 93 +++++ arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts | 21 + arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts | 9 + arch/arm/dts/r8a774a1-hihope-rzg2m.dts | 37 ++ arch/arm/dts/r8a774a1-u-boot.dtsi | 55 +++ arch/arm/mach-rmobile/Kconfig.64 | 14 + board/hoperun/hihope-rzg2/Kconfig | 15 + board/hoperun/hihope-rzg2/MAINTAINERS | 6 + board/hoperun/hihope-rzg2/Makefile | 9 + board/hoperun/hihope-rzg2/hihope-rzg2.c | 177 ++++++++ configs/hihope_rzg2_defconfig | 73 ++++ include/configs/hihope-rzg2.h | 20 + 15 files changed, 1031 insertions(+) create mode 100644 arch/arm/dts/hihope-common.dtsi create mode 100644 arch/arm/dts/hihope-rev4.dtsi create mode 100644 arch/arm/dts/hihope-rzg2-ex.dtsi create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m.dts create mode 100644 arch/arm/dts/r8a774a1-u-boot.dtsi create mode 100644 board/hoperun/hihope-rzg2/Kconfig create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS create mode 100644 board/hoperun/hihope-rzg2/Makefile create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c create mode 100644 configs/hihope_rzg2_defconfig create mode 100644 include/configs/hihope-rzg2.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f8f529435b..ce7b561fcb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -784,6 +784,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \

dtb-$(CONFIG_RCAR_GEN3) += \ r8a774a1-beacon-rzg2m-kit.dtb \ + r8a774a1-hihope-rzg2m-u-boot.dtb \ r8a77950-ulcb-u-boot.dtb \ r8a77950-salvator-x-u-boot.dtb \ r8a77960-ulcb-u-boot.dtb \ diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi new file mode 100644 index 0000000000..51eb74fbe9 --- /dev/null +++ b/arch/arm/dts/hihope-common.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and + * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &scif2; + serial1 = &hscif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + hdmi0-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con: endpoint { + remote-endpoint = <&rcar_dw_hdmi0_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; + + led2 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; + + led3 { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + led4 { + gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sound_card: sound { + compatible = "audio-graph-card"; + + label = "rcar-sound"; + + dais = <&rsnd_port>; + }; + + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + x302_clk: x302-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33000000>; + }; + + x304_clk: x304-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&du { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&gpio6 { + usb1-reset { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-low; + line-name = "usb1-reset"; + }; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint>; + }; + }; + }; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + versaclock5: clock-generator@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x304_clk>; + clock-names = "xin"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; + function = "sdhi3"; + power-source = <1800>; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + mux { + groups = "usb1"; + function = "usb1"; + }; + + ovc { + pins = "GP_6_27"; + bias-pull-up; + }; + }; + + usb30_pins: usb30 { + groups = "usb30"; + function = "usb30"; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&reg_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi2 { + status = "okay"; + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&reg_3p3v>; + vqmmc-supply = <&reg_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&usb_extal_clk { + clock-frequency = <50000000>; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&vbus0_usb2>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb3_peri0 { + phys = <&usb3_phy0>; + phy-names = "usb"; + + companion = <&xhci0>; + + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3s0_clk { + clock-frequency = <100000000>; +}; + +&xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/dts/hihope-rev4.dtsi b/arch/arm/dts/hihope-rev4.dtsi new file mode 100644 index 0000000000..3046c07a28 --- /dev/null +++ b/arch/arm/dts/hihope-rev4.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and + * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include "hihope-common.dtsi" + +/ { + audio_clkout: audio-clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2000/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + wlan_en_reg: regulator-wlan_en { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <70000>; + + gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + x1801_clk: x1801-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&hscif0 { + bluetooth { + compatible = "ti,wl1837-st"; + enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + status = "okay"; + + cs2000: clk_multiplier@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x1801_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&pfc { + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a"; + function = "audio_clk"; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <12288000 11289600>; + + /* update <audio_clk_b> to <cs2000> */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, + <&cpg CPG_CORE CPG_AUDIO_CLK_I>; + + rsnd_port: port { + rsnd_endpoint: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint>; + frame-master = <&rsnd_endpoint>; + + playback = <&ssi2>; + }; + }; +}; diff --git a/arch/arm/dts/hihope-rzg2-ex.dtsi b/arch/arm/dts/hihope-rzg2-ex.dtsi new file mode 100644 index 0000000000..6233069282 --- /dev/null +++ b/arch/arm/dts/hihope-rzg2-ex.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/ { + aliases { + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pciec0 { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + can0_pins: can0 { + groups = "can0_data_a"; + function = "can0"; + }; + + can1_pins: can1 { + groups = "can1_data"; + function = "can1"; + }; + + pwm0_pins: pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts new file mode 100644 index 0000000000..a5ca86196a --- /dev/null +++ b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to + * sub board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a774a1-hihope-rzg2m.dts" +#include "hihope-rzg2-ex.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2M with sub board"; + compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", + "renesas,r8a774a1"; +}; + +/* SW43 should be OFF, if in ON state SATA port will be activated */ +&pciec1 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts new file mode 100644 index 0000000000..e5872ee68c --- /dev/null +++ b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Hihope RZ/G2M board + * + * Copyright (C) 2020 Renesas Electronics Corporation + */ + +#include "r8a774a1-hihope-rzg2m-ex.dts" +#include "r8a774a1-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m.dts new file mode 100644 index 0000000000..25ae255de0 --- /dev/null +++ b/arch/arm/dts/r8a774a1-hihope-rzg2m.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774a1.dtsi" +#include "hihope-rev4.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2M main board based on r8a774a1"; + compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", + "dclkin.0", "dclkin.1", "dclkin.2"; +}; diff --git a/arch/arm/dts/r8a774a1-u-boot.dtsi b/arch/arm/dts/r8a774a1-u-boot.dtsi new file mode 100644 index 0000000000..86be1af351 --- /dev/null +++ b/arch/arm/dts/r8a774a1-u-boot.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot on RZ/G2 R8A774A1 SoC + * + * Copyright (C) 2020 Renesas Electronics Corporation + */ + +#include "r8a779x-u-boot.dtsi" + +&extalr_clk { + u-boot,dm-pre-reloc; +}; + +/delete-node/ &audma0; +/delete-node/ &audma1; +/delete-node/ &can0; +/delete-node/ &can1; +/delete-node/ &canfd; +/delete-node/ &csi20; +/delete-node/ &csi40; +/delete-node/ &du; +/delete-node/ &fcpf0; +/delete-node/ &fcpvb0; +/delete-node/ &fcpvd0; +/delete-node/ &fcpvd1; +/delete-node/ &fcpvd2; +/delete-node/ &fcpvi0; +/delete-node/ &hdmi0; +/delete-node/ &lvds0; +/delete-node/ &rcar_sound; +/delete-node/ &sdhi2; +/delete-node/ &sound_card; +/delete-node/ &vin0; +/delete-node/ &vin1; +/delete-node/ &vin2; +/delete-node/ &vin3; +/delete-node/ &vin4; +/delete-node/ &vin5; +/delete-node/ &vin6; +/delete-node/ &vin7; +/delete-node/ &vspb; +/delete-node/ &vspd0; +/delete-node/ &vspd1; +/delete-node/ &vspd2; +/delete-node/ &vspi0; + +/ { + /delete-node/ hdmi0-out; +}; + +/ { + soc { + /delete-node/ fdp1@fe940000; + }; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 07f607dd9d..2290be725f 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -4,6 +4,8 @@ menu "Select Target SoC"

config R8A774A1 bool "Renesas SoC R8A774A1" + imply CLK_R8A774A1 + imply PINCTRL_PFC_R8A774A1

config R8A7795 bool "Renesas SoC R8A7795" @@ -51,6 +53,15 @@ config TARGET_BEACON_RZG2M select R8A774A1 select PINCTRL_PFC_R8A774A1

+config TARGET_HIHOPE_RZG2 + bool "HiHope RZ/G2 board" + imply R8A774A1 + imply SYS_MALLOC_F + imply MULTI_DTB_FIT + imply MULTI_DTB_FIT_USER_DEFINED_AREA + help + Support for RZG2 HiHope platform + config TARGET_CONDOR bool "Condor board" imply R8A77980 @@ -109,12 +120,15 @@ source "board/renesas/ebisu/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" source "board/beacon/beacon-rzg2m/Kconfig" +source "board/hoperun/hihope-rzg2/Kconfig"

config MULTI_DTB_FIT_UNCOMPRESS_SZ + default 0x80000 if TARGET_HIHOPE_RZG2 default 0x80000 if TARGET_SALVATOR_X default 0x80000 if TARGET_ULCB

config MULTI_DTB_FIT_USER_DEF_ADDR + default 0x49000000 if TARGET_HIHOPE_RZG2 default 0x49000000 if TARGET_SALVATOR_X default 0x49000000 if TARGET_ULCB

diff --git a/board/hoperun/hihope-rzg2/Kconfig b/board/hoperun/hihope-rzg2/Kconfig new file mode 100644 index 0000000000..ee422ba6c8 --- /dev/null +++ b/board/hoperun/hihope-rzg2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_HIHOPE_RZG2 + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "hihope-rzg2" + +config SYS_VENDOR + default "hoperun" + +config SYS_CONFIG_NAME + default "hihope-rzg2" + +endif diff --git a/board/hoperun/hihope-rzg2/MAINTAINERS b/board/hoperun/hihope-rzg2/MAINTAINERS new file mode 100644 index 0000000000..e3702fd12e --- /dev/null +++ b/board/hoperun/hihope-rzg2/MAINTAINERS @@ -0,0 +1,6 @@ +HIHOPE_RZG2 BOARD +M: Biju Das biju.das.jz@bp.renesas.com +S: Maintained +F: board/hoperun/hihope-rzg2/ +F: include/configs/hihope-rzg2.h +F: configs/hihope_rzg2_defconfig diff --git a/board/hoperun/hihope-rzg2/Makefile b/board/hoperun/hihope-rzg2/Makefile new file mode 100644 index 0000000000..5313031109 --- /dev/null +++ b/board/hoperun/hihope-rzg2/Makefile @@ -0,0 +1,9 @@ +# +# board/hoperun/hihope-rzg2/Makefile +# +# Copyright (C) 2020 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := hihope-rzg2.o diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c new file mode 100644 index 0000000000..826a403178 --- /dev/null +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * board/hoperun/hihope-rzg2/hihope-rzg2.c + * This file is HiHope RZ/G2M board support. + * + * Copyright (C) 2020 Renesas Electronics Corporation + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <linux/libfdt.h> + +#define HSUSB_MSTP704 BIT(4) +#define HSUSB_REG_LPSTS 0xE6590102 +#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) +#define HSUSB_REG_UGCTRL2 0xE6590184 +#define HSUSB_REG_UGCTRL2_USB0SEL 0x30 +#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 + +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CODE 0xA5A5000F + +/* If the firmware passed a device tree use it for U-Boot DRAM setup. */ +extern u64 rcar_atf_boot_args[]; + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) +{ +} + +/* + * Routine: get_board_revision for RZ/G2 + * Description: GP5_19 and GP5_21 are used to detect board revision for + * HiHope RZ/G2 rev3.0+ boards. + * + * Rev GP5_19 GP5_21 + * ============================== + * Rev.3.0 0 0 + * Rev.4.0 0 1 + * + */ +static int get_board_revision_for_rzg2(void) +{ + int revision = 3; + struct gpio_desc rev_bit0, rev_bit1; + char *rev_bit0_gpio = "gpio@e605500021"; + char *rev_bit1_gpio = "gpio@e605500019"; + + if (dm_gpio_lookup_name(rev_bit0_gpio, &rev_bit0) || + dm_gpio_request(&rev_bit0, "rev_bit0")) { + printf("Cannot get GPIO5_21\n"); + return revision; + } + + if (dm_gpio_lookup_name(rev_bit1_gpio, &rev_bit1) || + dm_gpio_request(&rev_bit1, "rev_bit1")) { + printf("Cannot get GPIO5_19\n"); + return revision; + } + + dm_gpio_set_dir_flags(&rev_bit1, GPIOD_IS_IN); + dm_gpio_set_dir_flags(&rev_bit0, GPIOD_IS_IN); + revision = 0x03 + ((dm_gpio_get_value(&rev_bit1) << 1) | + dm_gpio_get_value(&rev_bit0)); + return revision; +} + +static int get_board_revision(void) +{ + u32 cpu_type = rmobile_get_cpu_type(); + int revision = 2; + + if (cpu_type == RMOBILE_CPU_TYPE_R8A774A1) { + if (rmobile_get_cpu_rev_integer() == 1 && + rmobile_get_cpu_rev_fraction() == 3) + revision = get_board_revision_for_rzg2(); + } + + return revision; +} + +void clear_wlan_bt_reg_on(void) +{ + struct gpio_desc bt_power, wifi_power; + char *bt_power_gpio = "gpio@e605300013"; /* GP3_13 */ + char *wifi_power_gpio = "gpio@e60540006"; /* GP4_06 */ + + if (get_board_revision() > 2) { + if (!dm_gpio_lookup_name(bt_power_gpio, &bt_power) && + !dm_gpio_request(&bt_power, "bt_power")) { + dm_gpio_set_dir_flags(&bt_power, GPIOD_IS_OUT); + dm_gpio_set_value(&bt_power, 0); + } else { + printf("Cannot get BT Power GPIO3_13\n"); + } + + if (!dm_gpio_lookup_name(wifi_power_gpio, &wifi_power) && + !dm_gpio_request(&wifi_power, "wifi_power")) { + dm_gpio_set_dir_flags(&wifi_power, GPIOD_IS_OUT); + dm_gpio_set_value(&wifi_power, 0); + } else { + printf("Cannot get WIFI Power GPIO4_06\n"); + } + } +} + +/* Kconfig forces this on, so just return 0 */ +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + /* USB1 pull-up */ + setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); + + /* Configure the HSUSB block */ + mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); + /* Choice USB0SEL */ + clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, + HSUSB_REG_UGCTRL2_USB0SEL_EHCI); + /* low power status */ + setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); + + clear_wlan_bt_reg_on(); + + return 0; +} + +int fdtdec_board_setup(const void *fdt_blob) +{ + void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); + + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + fdt_overlay_apply_node((void *)fdt_blob, 0, atf_fdt_blob, 0); + + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +void reset_cpu(ulong addr) +{ + writel(RST_CODE, RST_CA57RESCNT); +} + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + /* PRR driver is not available yet */ + u32 cpu_type = rmobile_get_cpu_type(); + + if (cpu_type == RMOBILE_CPU_TYPE_R8A774A1 && + !strcmp(name, "r8a774a1-hihope-rzg2m-u-boot")) + return 0; + + return -1; +} +#endif diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig new file mode 100644 index 0000000000..1a77e140f7 --- /dev/null +++ b/configs/hihope_rzg2_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0xFFFE0000 +CONFIG_DM_GPIO=y +CONFIG_RCAR_GEN3=y +CONFIG_TARGET_HIHOPE_RZG2=y +# CONFIG_SPL is not set +CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-hihope-rzg2m-u-boot" +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb" +CONFIG_VERSION_VARIABLE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot" +CONFIG_MULTI_DTB_FIT_LZO=y +CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_BITBANGMII=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_SCIF_CONSOLE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SMBIOS_MANUFACTURER="" diff --git a/include/configs/hihope-rzg2.h b/include/configs/hihope-rzg2.h new file mode 100644 index 0000000000..68a51176e3 --- /dev/null +++ b/include/configs/hihope-rzg2.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/hihope-rzg2.h + * This file is HOPERUN HiHope RZ/G2 board configuration. + * + * Copyright (C) 2020 Renesas Electronics Corporation + */ + +#ifndef __HIHOPE_RZG2_H +#define __HIHOPE_RZG2_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII_MULTI + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +#endif /* __HIHOPE_RZG2_H */