Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode.

Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.

Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/atum8548/atum8548.c | 6 +- board/freescale/mpc8536ds/mpc8536ds.c | 15 +- board/freescale/mpc8544ds/mpc8544ds.c | 14 +- board/freescale/mpc8548cds/mpc8548cds.c | 6 +- board/freescale/mpc8568mds/mpc8568mds.c | 4 +- board/freescale/mpc8569mds/mpc8569mds.c | 4 +- board/freescale/mpc8572ds/mpc8572ds.c | 17 +-- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 12 +- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 5 +- board/freescale/p1_p2_rdb/pci.c | 10 +- board/freescale/p2020ds/p2020ds.c | 14 +- board/sbc8548/sbc8548.c | 6 +- board/tqc/tqm85xx/tqm85xx.c | 8 +- cpu/mpc8xxx/Makefile | 1 + cpu/mpc8xxx/pci_cfg.c | 225 +++++++++++++++++++++++++++++ include/asm-ppc/fsl_pci.h | 5 + 16 files changed, 284 insertions(+), 68 deletions(-) create mode 100644 cpu/mpc8xxx/pci_cfg.c

diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 85c0adc..a220ad4 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -202,8 +202,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 5); - int pcie_configured = io_sel & 6; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -262,7 +262,7 @@ pci_init_board(void) struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions;

- uint pci_agent = (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 032d732..da72916 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -216,8 +216,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; - int pcie_ep = (host_agent == 1); - int pcie_configured = (io_sel == 7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); struct pci_region *r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -265,9 +265,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 5); - int pcie_configured = (io_sel == 2 || io_sel == 3 - || io_sel == 5 || io_sel == 7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -323,8 +322,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; - int pcie_ep = (host_agent == 3); - int pcie_configured = (io_sel == 5 || io_sel == 7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); struct pci_region *r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -381,7 +380,7 @@ pci_init_board(void) struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions;

- uint pci_agent = (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = 1; uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 5a47d0a..244a197 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -125,8 +125,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; - int pcie_ep = (host_agent == 1); - int pcie_configured = io_sel >= 6; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); struct pci_region *r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -188,8 +188,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 5); - int pcie_configured = io_sel >= 2; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -246,8 +246,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; - int pcie_ep = (host_agent == 3); - int pcie_configured = io_sel >= 4; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); struct pci_region *r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -306,7 +306,7 @@ pci_init_board(void) struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions;

- uint pci_agent = (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = 1; uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 9df5f82..80de6f8 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -283,7 +283,7 @@ pci_init_board(void) uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */

- uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);

uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */

@@ -361,10 +361,10 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions;

- int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);

if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index fe505b0..e2dc69e 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -422,10 +422,10 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions;

- int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);

if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 63c21dd..cc88731 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -331,9 +331,9 @@ pci_init_board(void)

pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; hose = &pcie1_hose; - pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); r = hose->regions; - pcie_configured = io_sel >= 1; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);

if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 7da70fe..c69934c 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -186,9 +186,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 3) || - (host_agent == 5) || (host_agent == 6); - int pcie_configured = (io_sel == 0x7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); struct pci_region *r = hose->regions; u32 temp32;

@@ -252,9 +251,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; - int pcie_ep = (host_agent == 2) || (host_agent == 4) || - (host_agent == 6) || (host_agent == 0); - int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); struct pci_region *r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ @@ -301,11 +299,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent <= 1) || (host_agent == 4) || - (host_agent == 5); - int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) || - (io_sel == 0x7) || (io_sel == 0xb) || - (io_sel == 0xc) || (io_sel == 0xf); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 45000d9..98111eb 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -248,9 +248,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_configured = (io_sel == 1) || (io_sel == 4); - int pcie_ep = (host_agent == 0) || (host_agent == 2) || - (host_agent == 5); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions;

if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { @@ -298,9 +297,8 @@ void pci_init_board(void) struct pci_controller *hose = &pcie2_hose; struct pci_region *r = hose->regions;

- int pcie_configured = (io_sel == 0) || (io_sel == 4); - int pcie_ep = (host_agent == 0) || (host_agent == 1) || - (host_agent == 4); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);

if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { printf(" PCI-Express 2 connected to slot as %s" \ @@ -345,7 +343,7 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; - int pci_agent = (host_agent >= 4) && (host_agent <= 6); + int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); struct pci_region *r = hose->regions;

if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index fab4fae..1a08afa 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -155,15 +155,14 @@ void pci_init_board(void) uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) >> MPC8641_PORDEVSR_IO_SEL_SHIFT; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);

#ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) >> MPC8641_PORBMSR_HA_SHIFT; uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); #endif - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); if (pci->pme_msg_det) { diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 174a8a7..a3617d5 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -59,9 +59,8 @@ void pci_init_board(void)

#ifdef CONFIG_PCIE2 SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = (host_agent == 2) || (host_agent == 4) || - (host_agent == 6) || (host_agent == 0); - pcie_configured = (io_sel == 0xE); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ puts ("\n PCIE2 connected to Slot 1 as "); @@ -80,9 +79,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE1 SET_STD_PCIE_INFO(pci_info[num], 1);

- pcie_ep = (host_agent <= 1) || (host_agent == 4) || - (host_agent == 5); - pcie_configured = (io_sel == 0xE); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ puts ("\n PCIE1 connected to Slot 2 as "); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 3fe72cd..7ad9be8 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -219,9 +219,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE2 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; hose = &pcie2_hose; - pcie_ep = (host_agent == 2) || (host_agent == 4) || - (host_agent == 6) || (host_agent == 0); - pcie_configured = (io_sel == 0x2) || (io_sel == 0xe); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { @@ -287,9 +286,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE3 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; hose = &pcie3_hose; - pcie_ep = (host_agent == 0) || (host_agent == 3) || - (host_agent == 5) || (host_agent == 6); - pcie_configured = (io_sel == 0x2) || (io_sel == 0x4); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { @@ -336,8 +334,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE1 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; hose = &pcie1_hose; - pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5); - pcie_configured = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); r = hose->regions;

if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 1ae4cda..e5b21b5 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -363,7 +363,7 @@ pci_init_board(void) uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */

- uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);

uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */

@@ -441,10 +441,10 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions;

- int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);

if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 277edcd..3931ec5 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -561,8 +561,7 @@ static inline void init_pci1(void) /* PORPLLSR[16] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

- uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || - (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);

uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */

@@ -630,11 +629,10 @@ static inline void init_pcie1(void) uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || - (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions;

- int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);

if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("PCIe: %s, base address %x", diff --git a/cpu/mpc8xxx/Makefile b/cpu/mpc8xxx/Makefile index 430a75f..5cb6814 100644 --- a/cpu/mpc8xxx/Makefile +++ b/cpu/mpc8xxx/Makefile @@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.a

COBJS-y += cpu.o +COBJS-$(CONFIG_PCI) += pci_cfg.o

SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c new file mode 100644 index 0000000..9c7d92c --- /dev/null +++ b/cpu/mpc8xxx/pci_cfg.c @@ -0,0 +1,225 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <pci.h> + +struct pci_info { + u16 agent; + u16 cfg; +}; + +/* The agent field is a bit mask in which each bit represents the value of + * cfg_host_agt[] signal and the bit is set of the given interface would be + * in agent/end-point mode for the given interface. + * + * The same idea is true of the cfg field. The bit will be set if the + * interface would be enabled based on the value of cfg_IO_ports[] signal + * + * On MPC86xx/PQ3 based systems: + * we extract cfg_host_agt from GUTS register PORBMSR + * we extract cfg_IO_ports from GUTS register PORDEVSR + * + * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems + * without PCIe) + */ + +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0) | (1 << 2), + .cfg = 0, + }, +}; +#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0), + .cfg = 0, + }, +}; +#elif defined(CONFIG_MPC8536) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 3), + .cfg = (1 << 5) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 1), + .cfg = (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8544) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | + (1 << 6) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 3), + .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 1), + .cfg = (1 << 6) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8548) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI_1] = { + .agent = (1 << 4) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCI_2] = { + .agent = (1 << 4) | (1 << 6), + .cfg = 0, + }, + /* PCI_2 is always host and we dont use iosel to determine enable/disable */ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2), + .cfg = (1 << 3) | (1 << 4) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8568) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0) | (1 << 4) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4), + .cfg = (1 << 3) | (1 << 4) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8569) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 6), + .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | + (1 << 8) | (1 << 0xc) | (1 << 0xf), + }, +}; +#elif defined(CONFIG_MPC8572) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 7) | + (1 << 0xb) | (1 << 0xc) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), + .cfg = (1 << 3) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), + .cfg = (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8610) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI_1] = { + .agent = (1 << 4) | (1 << 5) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2) | (1 << 5), + .cfg = (1 << 1) | (1 << 4), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4), + .cfg = (1 << 0) | (1 << 4), + }, +}; +#elif defined(CONFIG_MPC8641) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = 0, /* we dont use agent on 8641 */ + .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | + (1 << 7) | (1 << 0xe) | (1 << 0xf), + }, +}; +#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1), + .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2), + .cfg = (1 << 0xe), + }, +}; +#elif defined(CONFIG_P2010) || defined(CONFIG_P2020) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), + .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | + (1 << 0xd) | (1 << 0xe) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), + .cfg = (1 << 2) | (1 << 0xe), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), + .cfg = (1 << 2) | (1 << 4), + }, +}; +#else +#error Need to define pci_config_info for processor +#endif + +int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent) +{ + return ((1 << host_agent) & pci_config_info[trgt].agent); +} + +int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) +{ + return ((1 << io_sel) & pci_config_info[trgt].cfg); +} diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index f625d19..b9972da 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -20,6 +20,11 @@ #ifndef __FSL_PCI_H_ #define __FSL_PCI_H_

+#include <asm/fsl_law.h> + +int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent); +int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel); + void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); void ft_fsl_pci_setup(void *blob, const char *pci_alias,