From: Marcel Ziswiler marcel.ziswiler@toradex.com

The following commit introduced per-SoC pllinfo tables but unfortunately there were two generic issues (e.g. mask vs. shift mixed up and wrongly used parenthesis) plus two each masks being wrong in the pllinfo tables for T20/T30 which this patch fixes.

commit aeea4204b340afe063ea38c36a0a60ce33015e7d Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.

Tested both on Colibri T20 as well as Colibri T30.

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com --- Please note that this patch applies to the next branch of the u-boot-tegra custodian tree.

arch/arm/mach-tegra/clock.c | 4 ++-- arch/arm/mach-tegra/tegra20/clock.c | 4 ++-- arch/arm/mach-tegra/tegra30/clock.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 0c5ae83..6f4dcc6 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -474,7 +474,7 @@ unsigned clock_get_rate(enum clock_id clkid) * PLLU uses p_mask/p_shift for VCO on all but T210, * T210 uses normal DIVP. Handled in pllinfo table. */ - divm <<= (base >> pllinfo->p_mask) & pllinfo->p_shift; + divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; do_div(rate, divm); return rate; } @@ -535,7 +535,7 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)

/* Set cpcon (KCP) to PLL_MISC */ misc_reg = readl(&pll->pll_misc); - misc_reg &= ~(pllinfo->kcp_mask) << pllinfo->kcp_shift; + misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); misc_reg |= cpcon << pllinfo->kcp_shift; writel(misc_reg, &pll->pll_misc);

diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index 0de5365..41e19a6 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -366,9 +366,9 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { * If lock_ena or lock_det are >31, they're not used in that PLL. */

- { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ - { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0, .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 23496b0..3710a50 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -415,9 +415,9 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { * If lock_ena or lock_det are >31, they're not used in that PLL. */

- { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ - { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0, .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */