[U-Boot] [PATCH 1/3] fpga: zynqpl: Add dcache flush support
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com
Buffers must be cache and dma aligned.
Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com --- drivers/fpga/zynqpl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 717c039..f2f49b5 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -177,8 +177,8 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; }
- if ((u32)buf_start & 0x3) { - u32 *new_buf = (u32 *)((u32)buf & ~0x3); + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { + u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, (u32)buf_start, (u32)new_buf, swap); @@ -284,6 +284,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: Source = 0x%08X\n", __func__, (u32)buf); debug("%s: Size = %zu\n", __func__, bsize);
+ /* flush(clean & invalidate) d-cache range buf */ + flush_dcache_range((u32)buf, (u32)buf + + roundup(bsize, ARCH_DMA_MINALIGN)); + /* Set up the transfer */ writel((u32)buf | 1, &devcfg_base->dma_src_addr); writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); -- 1.8.2.3
DMA doesn't work when src is placed below 1MB limit.
Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com --- drivers/fpga/zynqpl.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index f2f49b5..1effbad 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/io.h> #include <zynqpl.h> +#include <asm/sizes.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h>
@@ -177,6 +178,12 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; }
+ if ((u32)buf < SZ_1M) { + printf("%s: Bitstream has to be placed up to 1MB (%x)\n", + __func__, (u32)buf); + return FPGA_FAIL; + } + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
-- 1.8.2.3
Here is the set of command which has been performed to proof this feature.
gzip < fpga.bin > fpga.bin.gz mkimage -A arm -O u-boot -T firmware -C gzip \ -a 20000000 -n "zc702_fpga_bin" -d fpga.bin.gz fpga.bin.gz.ub
tftp 100000 fpga.bin.gz.ub fpga loadmk 0 100000
This flow should speedup loading bitstream data from external memory and save image footprint in non volatile memory.
Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com --- common/cmd_fpga.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index c4b3c8f..010cd24 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -160,9 +160,25 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) image_header_t *hdr = (image_header_t *)fpga_data; ulong data; - - data = (ulong)image_get_data(hdr); - data_size = image_get_data_size(hdr); + uint8_t comp; + + comp = image_get_comp(hdr); + if (comp == IH_COMP_GZIP) { + ulong image_buf = image_get_data(hdr); + data = image_get_load(hdr); + ulong image_size = ~0UL; + + if (gunzip((void *)data, ~0UL, + (void *)image_buf, + &image_size) != 0) { + puts("GUNZIP: error\n"); + return 1; + } + data_size = image_size; + } else { + data = (ulong)image_get_data(hdr); + data_size = image_get_data_size(hdr); + } rc = fpga_load(dev, (void *)data, data_size); } break; -- 1.8.2.3
participants (1)
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Michal Simek