[U-Boot] [PATCH v7 0/9] Add support for ThunderX 88xx SoC family
This patch series adds support for Cavium ThunderX 88xx SoC family (http://cavium.com/ThunderX_ARM_Processors.html)
This is the version 6 of the series I posted at http://lists.denx.de/pipermail/u-boot/2015-September/228716.html http://lists.denx.de/pipermail/u-boot/2015-September/227088.html http://lists.denx.de/pipermail/u-boot/2015-August/224324.html http://lists.denx.de/pipermail/u-boot/2015-August/223618.html
Changes in v7: - Removed stale board.c changes - Removed rebase/merge residue - Added CONFIG_CMD_ATF - Updated defconfig - Fixed typo in the 'uboot,skip-init' preperty
Changes in v6: - Fixed lack of protection in global_data.h - Changed the 'PL0X_PREINITIALIZED' flag to the 'skip-init' bool - Added /chosen node - Added 'u-boot,skip-init' property to the FDT
Changes in v5: - Allow setting of different memory attributes in the memory map - Added OF control support - Added FDT for ThunderX 88xx series - Added CONFIG_OF_CONTROL support - Changed memory attributes - Moved dram_init() from a separate file to thunderx.c
Changes in v4: - Use ALIGN macro for address alignment - Document FW calls - Fixed build warnings - Moved to DM_SERIAL - Moved CONFIG_SYS_PROMPT to configs/thunderx_88xx_defconfig - Added proper DM_SERIAL definitions
Changes in v3: - Reduced code duplication - Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS - Moved 'reset_sctrl' call to the 'reset' label - Rebased to the actual upstream tree - Documented newly added config options - Fixed clobber lists (thanks to Corey) - Added __used keyword - Fixed formatting - Added MAINTAINERS - Moved command definitions to defconfig
Changes in v2: - Changed code licensing - Completed the patchset
Sergey Temerkhanov (9): armv8: Add read_mpidr() function armv8: New MMU setup code allowing to use 48+ bits PA/VA armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure armv8: Add psci.h from the Linux kernel arm: serial: Add ability to use pre-initialized UARTs armv8: cavium: Add the device tree for ThunderX armv8: cavium: Add ThunderX 88xx board definition armv8: cavium: Add an implementation of ATF calling functions armv8: cavium: Get DRAM size from ATF
arch/arm/Kconfig | 5 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/cache_v8.c | 79 +++++++ arch/arm/cpu/armv8/fwcall.c | 75 ++++++ arch/arm/cpu/armv8/start.S | 36 +++ arch/arm/dts/Makefile | 1 + arch/arm/dts/thunderx-88xx.dts | 31 +++ arch/arm/dts/thunderx-88xx.dtsi | 363 ++++++++++++++++++++++++++++++ arch/arm/include/asm/armv8/mmu.h | 82 ++++++- arch/arm/include/asm/global_data.h | 3 + arch/arm/include/asm/system.h | 39 ++++ board/cavium/thunderx/Kconfig | 27 +++ board/cavium/thunderx/MAINTAINERS | 6 + board/cavium/thunderx/Makefile | 8 + board/cavium/thunderx/atf.c | 312 +++++++++++++++++++++++++ board/cavium/thunderx/thunderx.c | 102 +++++++++ configs/thunderx_88xx_defconfig | 24 ++ doc/README.arm64 | 35 ++- doc/device-tree-bindings/serial/pl01x.txt | 3 + drivers/serial/serial_pl01x.c | 14 +- include/cavium/atf.h | 22 ++ include/cavium/atf_part.h | 26 +++ include/cavium/thunderx_svc.h | 67 ++++++ include/configs/thunderx_88xx.h | 147 ++++++++++++ include/dm/platform_data/serial_pl01x.h | 2 + include/linux/psci.h | 90 ++++++++ 26 files changed, 1582 insertions(+), 18 deletions(-) create mode 100644 arch/arm/cpu/armv8/fwcall.c create mode 100644 arch/arm/dts/thunderx-88xx.dts create mode 100644 arch/arm/dts/thunderx-88xx.dtsi create mode 100644 board/cavium/thunderx/Kconfig create mode 100644 board/cavium/thunderx/MAINTAINERS create mode 100644 board/cavium/thunderx/Makefile create mode 100644 board/cavium/thunderx/atf.c create mode 100644 board/cavium/thunderx/thunderx.c create mode 100644 configs/thunderx_88xx_defconfig create mode 100644 include/cavium/atf.h create mode 100644 include/cavium/atf_part.h create mode 100644 include/cavium/thunderx_svc.h create mode 100644 include/configs/thunderx_88xx.h create mode 100644 include/linux/psci.h
This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org ---
Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/include/asm/system.h | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 868ea54..323c43e 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -71,6 +71,17 @@ static inline void set_sctlr(unsigned int val) asm volatile("isb"); }
+static inline unsigned long read_mpidr(void) +{ + unsigned long val; + + asm volatile("mrs %0, mpidr_el1" : "=r" (val)); + + return val; +} + +#define BSP_COREID 0 + void __asm_flush_dcache_all(void); void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end);
On Wed, Oct 14, 2015 at 09:55:44AM -0700, Sergey Temerkhanov wrote:
This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot/master, thanks!
This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc.
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
---
Changes in v7: - Removed stale board.c changes
Changes in v6: - Fixed lack of protection in global_data.h
Changes in v5: - Allow setting of different memory attributes in the memory map
Changes in v4: - Use ALIGN macro for address alignment
Changes in v3: - Reduced code duplication - Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS - Moved 'reset_sctrl' call to the 'reset' label - Rebased to the actual upstream tree - Documented newly added config options
Changes in v2: - Changed code licensing - Completed the patchset
arch/arm/cpu/armv8/cache_v8.c | 79 ++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/start.S | 36 +++++++++++++++++ arch/arm/include/asm/armv8/mmu.h | 82 +++++++++++++++++++++++++++++++++++--- arch/arm/include/asm/global_data.h | 3 ++ arch/arm/include/asm/system.h | 7 ++++ doc/README.arm64 | 35 +++++++++++++--- 6 files changed, 230 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6bde1cf..989b17e 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -12,6 +12,69 @@ DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF + +#ifdef CONFIG_SYS_FULL_VA +static void set_ptl1_entry(u64 index, u64 ptl2_entry) +{ + u64 *pgd = (u64 *)gd->arch.tlb_addr; + u64 value; + + value = ptl2_entry | PTL1_TYPE_TABLE; + pgd[index] = value; +} + +static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_attrs) +{ + u64 *pmd = (u64 *)ptl1; + u64 value; + + value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF; + value |= memory_attrs; + pmd[bfn] = value; +} + +static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP; + +#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES +#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES + +static void setup_pgtables(void) +{ + int l1_e, l2_e; + unsigned long pmd = 0; + unsigned long address; + + /* Setup the PMD pointers */ + for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) { + gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr + + PTL1_ENTRIES * sizeof(u64); + gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e; + gd->arch.pmd_addr[l1_e] = ALIGN(gd->arch.pmd_addr[l1_e], + 0x10000UL); + } + + /* Setup the page tables */ + for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) { + if (mem_map[pmd].base == + (uintptr_t)l1_e << PTL2_BITS) { + set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]); + + for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) { + address = mem_map[pmd].base + + (uintptr_t)l2_e * BLOCK_SIZE; + set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e, + address, mem_map[pmd].attrs); + } + + pmd++; + } else { + set_ptl1_entry(l1_e, 0); + } + } +} + +#else + inline void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, u64 share) { @@ -31,13 +94,25 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) page_table[index] = value; }
+#endif + + /* to activate the MMU we need to set up virtual memory */ static void mmu_setup(void) { +#ifndef CONFIG_SYS_FULL_VA bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; +#endif int el;
+#ifdef CONFIG_SYS_FULL_VA + unsigned long coreid = read_mpidr() & CONFIG_COREID_MASK; + + /* Set up page tables only on BSP */ + if (coreid == BSP_COREID) + setup_pgtables(); +#else /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { set_pgtable_section(page_table, i, i << SECTION_SHIFT, @@ -55,6 +130,7 @@ static void mmu_setup(void) } }
+#endif /* load TTBR0 */ el = current_el(); if (el == 1) { @@ -154,6 +230,7 @@ u64 *__weak arch_get_page_table(void) { return NULL; }
+#ifndef CONFIG_SYS_FULL_VA void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { @@ -179,6 +256,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, flush_dcache_range(start, end); asm volatile("dsb sy"); } +#endif + #else /* CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index da45d98..2ee60d6 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -43,6 +43,9 @@ _bss_end_ofs: .quad __bss_end - _start
reset: +#ifdef CONFIG_SYS_RESET_SCTRL + bl reset_sctrl +#endif /* * Could be EL3/EL2/EL1, Initial State: * Little Endian, MMU Disabled, i/dCache Disabled @@ -99,6 +102,39 @@ master_cpu:
bl _main
+#ifdef CONFIG_SYS_RESET_SCTRL +reset_sctrl: + switch_el x1, 3f, 2f, 1f +3: + mrs x0, sctlr_el3 + b 0f +2: + mrs x0, sctlr_el2 + b 0f +1: + mrs x0, sctlr_el1 + +0: + ldr x1, =0xfdfffffa + and x0, x0, x1 + + switch_el x1, 6f, 5f, 4f +6: + msr sctlr_el3, x0 + b 7f +5: + msr sctlr_el2, x0 + b 7f +4: + msr sctlr_el1, x0 + +7: + dsb sy + isb + b __asm_invalidate_tlb_all + ret +#endif + /*-----------------------------------------------------------------------*/
WEAK(apply_core_errata) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 0c928d4..94426d9 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -21,7 +21,13 @@ * The following definitions are related each other, shoud be * calculated specifically. */ + +#ifndef CONFIG_SYS_FULL_VA #define VA_BITS (42) /* 42 bits virtual address */ +#else +#define VA_BITS CONFIG_SYS_VA_BITS +#define PTL2_BITS CONFIG_SYS_PTL2_BITS +#endif
/* PAGE_SHIFT determines the page size */ #undef PAGE_SIZE @@ -30,11 +36,18 @@ #define PAGE_MASK (~(PAGE_SIZE-1))
/* - * section address mask and size definitions. + * block/section address mask and size definitions. */ +#ifndef CONFIG_SYS_FULL_VA #define SECTION_SHIFT 29 #define SECTION_SIZE (UL(1) << SECTION_SHIFT) #define SECTION_MASK (~(SECTION_SIZE-1)) +#else +#define BLOCK_SHIFT CONFIG_SYS_BLOCK_SHIFT +#define BLOCK_SIZE (UL(1) << BLOCK_SHIFT) +#define BLOCK_MASK (~(BLOCK_SIZE-1)) +#endif + /***************************************************************/
/* @@ -46,15 +59,54 @@ #define MT_NORMAL_NC 3 #define MT_NORMAL 4
-#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \ - (0x04 << (MT_DEVICE_NGNRE*8)) | \ - (0x0c << (MT_DEVICE_GRE*8)) | \ - (0x44 << (MT_NORMAL_NC*8)) | \ - (UL(0xff) << (MT_NORMAL*8))) +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ + (0x04 << (MT_DEVICE_NGNRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (UL(0xff) << (MT_NORMAL * 8)))
/* * Hardware page table definitions. * + */ + +#ifdef CONFIG_SYS_FULL_VA +/* + * Level 1 descriptor (PGD). + */ + +#define PTL1_TYPE_MASK (3 << 0) +#define PTL1_TYPE_TABLE (3 << 0) + +#define PTL1_TABLE_PXN (1UL << 59) +#define PTL1_TABLE_XN (1UL << 60) +#define PTL1_TABLE_AP (1UL << 61) +#define PTL1_TABLE_NS (1UL << 63) + + +/* + * Level 2 descriptor (PMD). + */ + +#define PTL2_TYPE_MASK (3 << 0) +#define PTL2_TYPE_FAULT (0 << 0) +#define PTL2_TYPE_TABLE (3 << 0) +#define PTL2_TYPE_BLOCK (1 << 0) + +/* + * Block + */ +#define PTL2_MEMTYPE(x) ((x) << 2) +#define PTL2_BLOCK_NON_SHARE (0 << 8) +#define PTL2_BLOCK_OUTER_SHARE (2 << 8) +#define PTL2_BLOCK_INNER_SHARE (3 << 8) +#define PTL2_BLOCK_AF (1 << 10) +#define PTL2_BLOCK_NG (1 << 11) +#define PTL2_BLOCK_PXN (UL(1) << 53) +#define PTL2_BLOCK_UXN (UL(1) << 54) + +#else +/* * Level 2 descriptor (PMD). */ #define PMD_TYPE_MASK (3 << 0) @@ -73,6 +125,8 @@ #define PMD_SECT_PXN (UL(1) << 53) #define PMD_SECT_UXN (UL(1) << 54)
+#endif + /* * AttrIndx[2:0] */ @@ -99,9 +153,16 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) + +#ifndef CONFIG_SYS_FULL_VA #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ +#else +#define TCR_EL1_IPS_BITS CONFIG_SYS_TCR_EL1_IPS_BITS +#define TCR_EL2_IPS_BITS CONFIG_SYS_TCR_EL2_IPS_BITS +#define TCR_EL3_IPS_BITS CONFIG_SYS_TCR_EL3_IPS_BITS +#endif
/* PTWs cacheable, inner/outer WBWA and non-shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ @@ -111,6 +172,7 @@ TCR_T0SZ(VA_BITS))
#ifndef __ASSEMBLY__ +#ifndef CONFIG_SYS_FULL_VA
void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, @@ -118,6 +180,7 @@ void set_pgtable_section(u64 *page_table, u64 index, void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr);
+#endif static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); @@ -138,5 +201,12 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) } asm volatile("isb"); } + +struct mm_region { + u64 base; + u64 size; + u64 attrs; +}; #endif + #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 4e3ea55..4d5c976 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -38,6 +38,9 @@ struct arch_global_data { unsigned long long timer_reset_value; #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; +#if defined(CONFIG_SYS_FULL_VA) + unsigned long pmd_addr[CONFIG_SYS_PTL1_ENTRIES]; +#endif unsigned long tlb_size; #endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 323c43e..9288541 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -14,7 +14,12 @@ #define CR_WXN (1 << 19) /* Write Permision Imply XN */ #define CR_EE (1 << 25) /* Exception (Big) Endian */
+#ifndef CONFIG_SYS_FULL_VA #define PGTABLE_SIZE (0x10000) +#else +#define PGTABLE_SIZE CONFIG_SYS_PGTABLE_SIZE +#endif + /* 2MB granularity */ #define MMU_SECTION_SHIFT 21
@@ -147,7 +152,9 @@ void flush_l3_cache(void); #define CR_AFE (1 << 29) /* Access flag enable */ #define CR_TE (1 << 30) /* Thumb exception enable */
+#ifndef PGTABLE_SIZE #define PGTABLE_SIZE (4096 * 4) +#endif
/* * This is used to ensure the compiler did actually allocate the register we diff --git a/doc/README.arm64 b/doc/README.arm64 index 75586db..f32108f 100644 --- a/doc/README.arm64 +++ b/doc/README.arm64 @@ -36,11 +36,34 @@ Notes 6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and aarch32 specific codes.
+7. CONFIG_SYS_FULL_VA is used to enable 2-level page tables. For cores + supporting 64k pages it allows usage of full 48+ virtual/physical addresses + + Enabling this option requires the following ones to be defined: + - CONFIG_SYS_MEM_MAP - an array of 'struct mm_region' describing the + system memory map (start, length, attributes) + - CONFIG_SYS_MEM_MAP_SIZE - number of entries in CONFIG_SYS_MEM_MAP + - CONFIG_SYS_PTL1_ENTRIES - number of 1st level page table entries + - CONFIG_SYS_PTL2_ENTRIES - number of 1nd level page table entries + for the largest CONFIG_SYS_MEM_MAP entry + - CONFIG_COREID_MASK - the mask value used to get the core from the + MPIDR_EL1 register + - CONFIG_SYS_PTL2_BITS - number of bits addressed by the 2nd level + page tables + - CONFIG_SYS_BLOCK_SHIFT - number of bits addressed by a single block + entry from L2 page tables + - CONFIG_SYS_PGTABLE_SIZE - total size of the page table + - CONFIG_SYS_TCR_EL{1,2,3}_IPS_BITS - the IPS field of the TCR_EL{1,2,3} + + + + Contributor =========== - Tom Rini trini@ti.com - Scott Wood scottwood@freescale.com - York Sun yorksun@freescale.com - Simon Glass sjg@chromium.org - Sharma Bhupesh bhupesh.sharma@freescale.com - Rob Herring robherring2@gmail.com + Tom Rini trini@ti.com + Scott Wood scottwood@freescale.com + York Sun yorksun@freescale.com + Simon Glass sjg@chromium.org + Sharma Bhupesh bhupesh.sharma@freescale.com + Rob Herring robherring2@gmail.com + Sergey Temerkhanov s.temerkhanov@gmail.com
On Wed, Oct 14, 2015 at 09:55:45AM -0700, Sergey Temerkhanov wrote:
This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc.
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Applied to u-boot/master, thanks!
This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF)
The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Corey Minyard cminyard@mvista.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: - Document FW calls
Changes in v3: - Fixed clobber lists (thanks to Corey)
Changes in v2: None
arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/fwcall.c | 75 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/system.h | 21 ++++++++++++ 3 files changed, 97 insertions(+) create mode 100644 arch/arm/cpu/armv8/fwcall.c
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index adb11b3..7579ea7 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -14,6 +14,7 @@ obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o obj-y += transition.o +obj-y += fwcall.o
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c new file mode 100644 index 0000000..9efcc5a --- /dev/null +++ b/arch/arm/cpu/armv8/fwcall.c @@ -0,0 +1,75 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <asm-offsets.h> +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/system.h> + +/* + * Issue the hypervisor call + * + * x0~x7: input arguments + * x0~x3: output arguments + */ +void hvc_call(struct pt_regs *args) +{ + asm volatile( + "ldr x0, %0\n" + "ldr x1, %1\n" + "ldr x2, %2\n" + "ldr x3, %3\n" + "ldr x4, %4\n" + "ldr x5, %5\n" + "ldr x6, %6\n" + "ldr x7, %7\n" + "hvc #0\n" + "str x0, %0\n" + "str x1, %1\n" + "str x2, %2\n" + "str x3, %3\n" + : "+m" (args->regs[0]), "+m" (args->regs[1]), + "+m" (args->regs[2]), "+m" (args->regs[3]) + : "m" (args->regs[4]), "m" (args->regs[5]), + "m" (args->regs[6]), "m" (args->regs[7]) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17"); +} + +/* + * void smc_call(arg0, arg1...arg7) + * + * issue the secure monitor call + * + * x0~x7: input arguments + * x0~x3: output arguments + */ + +void smc_call(struct pt_regs *args) +{ + asm volatile( + "ldr x0, %0\n" + "ldr x1, %1\n" + "ldr x2, %2\n" + "ldr x3, %3\n" + "ldr x4, %4\n" + "ldr x5, %5\n" + "ldr x6, %6\n" + "smc #0\n" + "str x0, %0\n" + "str x1, %1\n" + "str x2, %2\n" + "str x3, %3\n" + : "+m" (args->regs[0]), "+m" (args->regs[1]), + "+m" (args->regs[2]), "+m" (args->regs[3]) + : "m" (args->regs[4]), "m" (args->regs[5]), + "m" (args->regs[6]) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17"); +} diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9288541..f3e2d1b 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -1,6 +1,9 @@ #ifndef __ASM_ARM_SYSTEM_H #define __ASM_ARM_SYSTEM_H
+#include <common.h> +#include <linux/compiler.h> + #ifdef CONFIG_ARM64
/* @@ -104,6 +107,24 @@ void smp_kick_all_cpus(void);
void flush_l3_cache(void);
+/* + *Issue a hypervisor call in accordance with ARM "SMC Calling convention", + * DEN0028A + * + * @args: input and output arguments + * + */ +void hvc_call(struct pt_regs *args); + +/* + *Issue a secure monitor call in accordance with ARM "SMC Calling convention", + * DEN0028A + * + * @args: input and output arguments + * + */ +void smc_call(struct pt_regs *args); + #endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256
On 14.10.2015 18:55, Sergey Temerkhanov wrote:
This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF)
The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Corey Minyard cminyard@mvista.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Reviewed-by: Simon Glass sjg@chromium.org
+1 (I may need it as well)
Tested-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com
Tested on: Hikey Methodology:
Hacked smc handler in arm trusted firmware (x0=x0+x1, x1=x2+x3, x2=x4+x5, x3=x6+2) +new u-boot command (smc/hvc) using functions from this patch;
I didn't tested hvc code (would need to make some fake hypervisor), but it's basically the same.
Idea: perhaps after this series is merged we can add 2 new commands to u-boot (SMC/HVC) to play with hypervisors/secure monitors (and perhaps use some simple functionality if needed).
@Sergey - you probably need to rebase the patch as it doesn't apply to master cleanly
Regards, Mateusz
Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4:
- Document FW calls
Changes in v3:
- Fixed clobber lists (thanks to Corey)
Changes in v2: None
arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/fwcall.c | 75 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/system.h | 21 ++++++++++++ 3 files changed, 97 insertions(+) create mode 100644 arch/arm/cpu/armv8/fwcall.c
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index adb11b3..7579ea7 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -14,6 +14,7 @@ obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o obj-y += transition.o +obj-y += fwcall.o
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c new file mode 100644 index 0000000..9efcc5a --- /dev/null +++ b/arch/arm/cpu/armv8/fwcall.c @@ -0,0 +1,75 @@ +/**
- (C) Copyright 2014, Cavium Inc.
- SPDX-License-Identifier: GPL-2.0+
+**/
+#include <asm-offsets.h> +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/system.h>
+/*
- Issue the hypervisor call
- x0~x7: input arguments
- x0~x3: output arguments
- */
+void hvc_call(struct pt_regs *args) +{
- asm volatile(
"ldr x0, %0\n""ldr x1, %1\n""ldr x2, %2\n""ldr x3, %3\n""ldr x4, %4\n""ldr x5, %5\n""ldr x6, %6\n""ldr x7, %7\n""hvc #0\n""str x0, %0\n""str x1, %1\n""str x2, %2\n""str x3, %3\n": "+m" (args->regs[0]), "+m" (args->regs[1]),"+m" (args->regs[2]), "+m" (args->regs[3]): "m" (args->regs[4]), "m" (args->regs[5]),"m" (args->regs[6]), "m" (args->regs[7]): "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7","x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15","x16", "x17");+}
+/*
- void smc_call(arg0, arg1...arg7)
- issue the secure monitor call
- x0~x7: input arguments
- x0~x3: output arguments
- */
+void smc_call(struct pt_regs *args) +{
- asm volatile(
"ldr x0, %0\n""ldr x1, %1\n""ldr x2, %2\n""ldr x3, %3\n""ldr x4, %4\n""ldr x5, %5\n""ldr x6, %6\n""smc #0\n""str x0, %0\n""str x1, %1\n""str x2, %2\n""str x3, %3\n": "+m" (args->regs[0]), "+m" (args->regs[1]),"+m" (args->regs[2]), "+m" (args->regs[3]): "m" (args->regs[4]), "m" (args->regs[5]),"m" (args->regs[6]): "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7","x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15","x16", "x17");+} diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9288541..f3e2d1b 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -1,6 +1,9 @@ #ifndef __ASM_ARM_SYSTEM_H #define __ASM_ARM_SYSTEM_H
+#include <common.h> +#include <linux/compiler.h>
#ifdef CONFIG_ARM64
/* @@ -104,6 +107,24 @@ void smp_kick_all_cpus(void);
void flush_l3_cache(void);
+/*
- *Issue a hypervisor call in accordance with ARM "SMC Calling convention",
- DEN0028A
- @args: input and output arguments
- */
+void hvc_call(struct pt_regs *args);
+/*
- *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
- DEN0028A
- @args: input and output arguments
- */
+void smc_call(struct pt_regs *args);
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
On 6.1.2016 14:04, Mateusz Kulikowski wrote:
On 14.10.2015 18:55, Sergey Temerkhanov wrote:
This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF)
The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Corey Minyard cminyard@mvista.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Reviewed-by: Simon Glass sjg@chromium.org
+1 (I may need it as well)
Tested-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com
Tested on: Hikey Methodology:
Hacked smc handler in arm trusted firmware (x0=x0+x1, x1=x2+x3, x2=x4+x5, x3=x6+2) +new u-boot command (smc/hvc) using functions from this patch;
I didn't tested hvc code (would need to make some fake hypervisor), but it's basically the same.
Idea: perhaps after this series is merged we can add 2 new commands to u-boot (SMC/HVC) to play with hypervisors/secure monitors (and perhaps use some simple functionality if needed).
How this should look like?
Definitely I would like to see this code in mainline because we have code which needs to call SMCs.
Thanks, Michal
On Thu, Jan 07, 2016 at 04:06:55PM +0100, Michal Simek wrote:
On 6.1.2016 14:04, Mateusz Kulikowski wrote:
On 14.10.2015 18:55, Sergey Temerkhanov wrote:
This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF)
The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Corey Minyard cminyard@mvista.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Reviewed-by: Simon Glass sjg@chromium.org
+1 (I may need it as well)
Tested-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com
Tested on: Hikey Methodology:
Hacked smc handler in arm trusted firmware (x0=x0+x1, x1=x2+x3, x2=x4+x5, x3=x6+2) +new u-boot command (smc/hvc) using functions from this patch;
I didn't tested hvc code (would need to make some fake hypervisor), but it's basically the same.
Idea: perhaps after this series is merged we can add 2 new commands to u-boot (SMC/HVC) to play with hypervisors/secure monitors (and perhaps use some simple functionality if needed).
How this should look like?
Definitely I would like to see this code in mainline because we have code which needs to call SMCs.
I guess the answer is we either need the cavium board series re-posted without the device-tree binding change that is causing consternation elsewhere or come up with something else there, or I just pull parts of the series. I'm not quite sure which is best at this point..
On 7.1.2016 17:26, Tom Rini wrote:
On Thu, Jan 07, 2016 at 04:06:55PM +0100, Michal Simek wrote:
On 6.1.2016 14:04, Mateusz Kulikowski wrote:
On 14.10.2015 18:55, Sergey Temerkhanov wrote:
This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF)
The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Corey Minyard cminyard@mvista.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Reviewed-by: Simon Glass sjg@chromium.org
+1 (I may need it as well)
Tested-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com
Tested on: Hikey Methodology:
Hacked smc handler in arm trusted firmware (x0=x0+x1, x1=x2+x3, x2=x4+x5, x3=x6+2) +new u-boot command (smc/hvc) using functions from this patch;
I didn't tested hvc code (would need to make some fake hypervisor), but it's basically the same.
Idea: perhaps after this series is merged we can add 2 new commands to u-boot (SMC/HVC) to play with hypervisors/secure monitors (and perhaps use some simple functionality if needed).
How this should look like?
Definitely I would like to see this code in mainline because we have code which needs to call SMCs.
I guess the answer is we either need the cavium board series re-posted without the device-tree binding change that is causing consternation elsewhere or come up with something else there, or I just pull parts of the series. I'm not quite sure which is best at this point..
This patch can go standalone I believe. Should it go via Albert or directly through you? I think that make sense to add it in merge window. I am happy to test it on zynqmp.
Thanks, Michal
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256
On 07.01.2016 16:06, Michal Simek wrote:
On 6.1.2016 14:04, Mateusz Kulikowski wrote:
On 14.10.2015 18:55, Sergey Temerkhanov wrote:
[...]
Idea: perhaps after this series is merged we can add 2 new commands to u-boot (SMC/HVC) to play with hypervisors/secure monitors (and perhaps use some simple functionality if needed).
How this should look like?
I thought of something like this (I did such code few times):
u-boot> smc 42 42 42 42 42 42 ret => (0x1, 0x2, 0x3, 0x4)
Or something similar (perhaps setting env variables so return value can be used in scripts)
Regards, Mateusz
On 7.1.2016 22:39, Mateusz Kulikowski wrote:
On 07.01.2016 16:06, Michal Simek wrote:
On 6.1.2016 14:04, Mateusz Kulikowski wrote:
On 14.10.2015 18:55, Sergey Temerkhanov wrote:
[...]
Idea: perhaps after this series is merged we can add 2 new commands to u-boot (SMC/HVC) to play with hypervisors/secure monitors (and perhaps use some simple functionality if needed).
How this should look like?
I thought of something like this (I did such code few times):
u-boot> smc 42 42 42 42 42 42 ret => (0x1, 0x2, 0x3, 0x4)
Or something similar (perhaps setting env variables so return value can be used in scripts)
I have no problem with that.
M
Hi Mateusz,
On 07.01.2016 22:39, Mateusz Kulikowski wrote:
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256
On 07.01.2016 16:06, Michal Simek wrote:
On 6.1.2016 14:04, Mateusz Kulikowski wrote:
On 14.10.2015 18:55, Sergey Temerkhanov wrote:
[...]
Idea: perhaps after this series is merged we can add 2 new commands to u-boot (SMC/HVC) to play with hypervisors/secure monitors (and perhaps use some simple functionality if needed).
How this should look like?
I thought of something like this (I did such code few times):
u-boot> smc 42 42 42 42 42 42 ret => (0x1, 0x2, 0x3, 0x4)
Could you share any (example?) code you have for such an smc/hvc U-Boot command?
Best regards
Dirk
Hi Dirk,
On 23.06.2016 13:33, Dirk Behme wrote: [...]
Idea: perhaps after this series is merged we can add 2 new commands to u-boot (SMC/HVC) to play with hypervisors/secure monitors (and perhaps use some simple functionality if needed).
How this should look like?
I thought of something like this (I did such code few times):
u-boot> smc 42 42 42 42 42 42 ret => (0x1, 0x2, 0x3, 0x4)
Could you share any (example?) code you have for such an smc/hvc U-Boot command?
I'm afraid I don't have it anymore :(
SMC call itself is trivial, you can use smc_call @ u-boot: arch/arm/cpu/armv8/fwcall.c (this is code for armv8 in 64-bit mode, but you can easily port it to armv7)
As for adding custom commands - just use any existing as template (sleep may be a good idea :) ).
Regards, Mateusz
On 25.06.2016 21:04, Mateusz Kulikowski wrote:
Hi Dirk,
On 23.06.2016 13:33, Dirk Behme wrote: [...]
Idea: perhaps after this series is merged we can add 2 new commands to u-boot (SMC/HVC) to play with hypervisors/secure monitors (and perhaps use some simple functionality if needed).
How this should look like?
I thought of something like this (I did such code few times):
u-boot> smc 42 42 42 42 42 42 ret => (0x1, 0x2, 0x3, 0x4)
Could you share any (example?) code you have for such an smc/hvc U-Boot command?
I'm afraid I don't have it anymore :(
SMC call itself is trivial, you can use smc_call @ u-boot: arch/arm/cpu/armv8/fwcall.c (this is code for armv8 in 64-bit mode, but you can easily port it to armv7)
As for adding custom commands - just use any existing as template (sleep may be a good idea :) ).
Anything like below [1]?
Best regards
Dirk
[1]
From f5fb9bdab3054fdc37ca3fed44703f0dc5c8b083 Mon Sep 17 00:00:00 2001 From: Dirk Behme dirk.behme@de.bosch.com Date: Mon, 27 Jun 2016 12:39:35 +0200 Subject: [PATCH] common: Add ARMv8 smc command
Add a command line interface to do ARMv8 secure monitor calls (smc).
Signed-off-by: Dirk Behme dirk.behme@de.bosch.com --- common/Makefile | 2 + common/cmd_armv8svchvc.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 0 deletions(-) create mode 100644 common/cmd_armv8svchvc.c
diff --git a/common/Makefile b/common/Makefile index 252fbf1..5a8dad0 100644 --- a/common/Makefile +++ b/common/Makefile @@ -191,6 +191,8 @@ obj-$(CONFIG_CMD_SPL) += cmd_spl.o obj-$(CONFIG_CMD_ZIP) += cmd_zip.o obj-$(CONFIG_CMD_ZFS) += cmd_zfs.o
+obj-$(CONFIG_ARM64) += cmd_armv8svchvc.o + # others obj-$(CONFIG_BOOTSTAGE) += bootstage.o obj-$(CONFIG_CONSOLE_MUX) += iomux.o diff --git a/common/cmd_armv8svchvc.c b/common/cmd_armv8svchvc.c new file mode 100644 index 0000000..6491704 --- /dev/null +++ b/common/cmd_armv8svchvc.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2016 + * Robert Bosch Car Multimedia GmbH + * Dirk Behme dirk.behme@de.bosch.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> + +static int do_smc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct pt_regs regs; + + memset(®s, 0, sizeof(struct pt_regs)); + + switch (argc) { + case 9: + regs.regs[7] = simple_strtoul(argv[8], NULL, 16); + /* fall through */ + case 8: + regs.regs[6] = simple_strtoul(argv[7], NULL, 16); + /* fall through */ + case 7: + regs.regs[5] = simple_strtoul(argv[6], NULL, 16); + /* fall through */ + case 6: + regs.regs[4] = simple_strtoul(argv[5], NULL, 16); + /* fall through */ + case 5: + regs.regs[3] = simple_strtoul(argv[4], NULL, 16); + /* fall through */ + case 4: + regs.regs[2] = simple_strtoul(argv[3], NULL, 16); + /* fall through */ + case 3: + regs.regs[1] = simple_strtoul(argv[2], NULL, 16); + /* fall through */ + case 2: + regs.regs[0] = simple_strtoul(argv[1], NULL, 16); + break; + default: + return CMD_RET_USAGE; + } + + smc_call(®s); + + printf("ret: x0: 0x%016luX\n x1: 0x%016luX\n x2: 0x%016luX x3: 0x%016lX\n", + regs.regs[0], regs.regs[1], regs.regs[2], regs.regs[3]); + + return 0; +} + +U_BOOT_CMD( + smc , 9, 0, do_smc, + "do ARMv8 hypervisor call (SMC)", + "x0 [x1 x2 x3 x4 x5 x6 x7]\n" + " - 8 SMC parameters for the registers x0 - x7" +);
On Wed, Oct 14, 2015 at 09:55:46AM -0700, Sergey Temerkhanov wrote:
This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF)
The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Corey Minyard cminyard@mvista.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Reviewed-by: Simon Glass sjg@chromium.org Tested-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com
Applied to u-boot/master, thanks!
This commit adds the psci.h header file from Linux kernel which contains definitions related to the PSCI interface provided by firmware
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com ---
Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
include/linux/psci.h | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 include/linux/psci.h
diff --git a/include/linux/psci.h b/include/linux/psci.h new file mode 100644 index 0000000..310d83e --- /dev/null +++ b/include/linux/psci.h @@ -0,0 +1,90 @@ +/* + * ARM Power State and Coordination Interface (PSCI) header + * + * This header holds common PSCI defines and macros shared + * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space. + * + * Copyright (C) 2014 Linaro Ltd. + * Author: Anup Patel anup.patel@linaro.org + */ + +#ifndef _UAPI_LINUX_PSCI_H +#define _UAPI_LINUX_PSCI_H + +/* + * PSCI v0.1 interface + * + * The PSCI v0.1 function numbers are implementation defined. + * + * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED, + * INVALID_PARAMS, and DENIED defined below are applicable + * to PSCI v0.1. + */ + +/* PSCI v0.2 interface */ +#define PSCI_0_2_FN_BASE 0x84000000 +#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) +#define PSCI_0_2_64BIT 0x40000000 +#define PSCI_0_2_FN64_BASE \ + (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) +#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) + +#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) +#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) +#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) +#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) +#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) +#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) +#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) +#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) +#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) +#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) +#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) +#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) + +/* PSCI v0.2 power state encoding for CPU_SUSPEND function */ +#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff +#define PSCI_0_2_POWER_STATE_ID_SHIFT 0 +#define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16 +#define PSCI_0_2_POWER_STATE_TYPE_MASK \ + (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT) +#define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24 +#define PSCI_0_2_POWER_STATE_AFFL_MASK \ + (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) + +/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ +#define PSCI_0_2_AFFINITY_LEVEL_ON 0 +#define PSCI_0_2_AFFINITY_LEVEL_OFF 1 +#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2 + +/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */ +#define PSCI_0_2_TOS_UP_MIGRATE 0 +#define PSCI_0_2_TOS_UP_NO_MIGRATE 1 +#define PSCI_0_2_TOS_MP 2 + +/* PSCI version decoding (independent of PSCI version) */ +#define PSCI_VERSION_MAJOR_SHIFT 16 +#define PSCI_VERSION_MINOR_MASK \ + ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1) +#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK +#define PSCI_VERSION_MAJOR(ver) \ + (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) +#define PSCI_VERSION_MINOR(ver) \ + ((ver) & PSCI_VERSION_MINOR_MASK) + +/* PSCI return values (inclusive of all PSCI versions) */ +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_NOT_SUPPORTED -1 +#define PSCI_RET_INVALID_PARAMS -2 +#define PSCI_RET_DENIED -3 +#define PSCI_RET_ALREADY_ON -4 +#define PSCI_RET_ON_PENDING -5 +#define PSCI_RET_INTERNAL_FAILURE -6 +#define PSCI_RET_NOT_PRESENT -7 +#define PSCI_RET_DISABLED -8 + +#endif /* _UAPI_LINUX_PSCI_H */
On Wed, Oct 14, 2015 at 09:55:47AM -0700, Sergey Temerkhanov wrote:
This commit adds the psci.h header file from Linux kernel which contains definitions related to the PSCI interface provided by firmware
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Applied to u-boot/master, thanks!
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v7: None Changes in v6: - Changed the 'PL0X_PREINITIALIZED' flag to the 'skip-init' bool
Changes in v5: - Added OF control support
Changes in v4: - Fixed build warnings - Moved to DM_SERIAL
Changes in v3: - Added __used keyword
Changes in v2: None
doc/device-tree-bindings/serial/pl01x.txt | 3 +++ drivers/serial/serial_pl01x.c | 14 ++++++++------ include/dm/platform_data/serial_pl01x.h | 2 ++ 3 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties: - reg: exactly one register range with length 0x1000 - clock: input clock frequency for the UART (used to calculate the baud rate divisor) + +Optional properties: +- u-boot,skip-init: skip UART initialization at start. diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 18c02ab..ebfa4fb 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -103,7 +103,7 @@ static int pl011_set_line_control(struct pl01x_regs *regs) }
static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, - int clock, int baudrate) + int clock, int baudrate) { switch (type) { case TYPE_PL010: { @@ -273,7 +273,6 @@ __weak struct serial_device *default_serial_console(void) #endif /* nCONFIG_DM_SERIAL */
#ifdef CONFIG_DM_SERIAL - struct pl01x_priv { struct pl01x_regs *regs; enum pl01x_type type; @@ -284,9 +283,9 @@ static int pl01x_serial_setbrg(struct udevice *dev, int baudrate) struct pl01x_serial_platdata *plat = dev_get_platdata(dev); struct pl01x_priv *priv = dev_get_priv(dev);
- pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate); - - return 0; + return plat->skip_init ? 0 : + pl01x_generic_setbrg(priv->regs, priv->type, + plat->clock, baudrate); }
static int pl01x_serial_probe(struct udevice *dev) @@ -296,7 +295,8 @@ static int pl01x_serial_probe(struct udevice *dev)
priv->regs = (struct pl01x_regs *)plat->base; priv->type = plat->type; - return pl01x_generic_serial_init(priv->regs, priv->type); + return plat->skip_init ? 0 : + pl01x_generic_serial_init(priv->regs, priv->type); }
static int pl01x_serial_getc(struct udevice *dev) @@ -350,6 +350,8 @@ static int pl01x_serial_ofdata_to_platdata(struct udevice *dev) plat->base = addr; plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1); plat->type = dev_get_driver_data(dev); + plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, + "uboot,skip-init"); return 0; } #endif diff --git a/include/dm/platform_data/serial_pl01x.h b/include/dm/platform_data/serial_pl01x.h index 5e068f3..10e9572 100644 --- a/include/dm/platform_data/serial_pl01x.h +++ b/include/dm/platform_data/serial_pl01x.h @@ -17,11 +17,13 @@ enum pl01x_type { * @base: Register base address * @type: Port type * @clock: Input clock rate, used for calculating the baud rate divisor + * @flags: Port flags */ struct pl01x_serial_platdata { unsigned long base; enum pl01x_type type; unsigned int clock; + bool skip_init; };
#endif
On Wed, Oct 14, 2015 at 6:55 PM, Sergey Temerkhanov s.temerkhanov@gmail.com wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
(...)
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties:
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud rate divisor)
+Optional properties: +- u-boot,skip-init: skip UART initialization at start.
Again: get this merged in the Linux kernel FIRST. Is it?
Yours, Linus Walleij
Hi Linus,
On 16 October 2015 at 15:23, Linus Walleij linus.walleij@linaro.org wrote:
On Wed, Oct 14, 2015 at 6:55 PM, Sergey Temerkhanov s.temerkhanov@gmail.com wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
(...)
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties:
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud rate divisor)
+Optional properties: +- u-boot,skip-init: skip UART initialization at start.
Again: get this merged in the Linux kernel FIRST. Is it?
We had a little bit of a chat about this at ELCE. It would be great to get these changes merged with the kernel but the amount of push-back/energy it requires is still excessive IMO. Any thoughts?
Regards, Simon
On Fri, Oct 16, 2015 at 04:27:31PM -0600, Simon Glass wrote:
Hi Linus,
On 16 October 2015 at 15:23, Linus Walleij linus.walleij@linaro.org wrote:
On Wed, Oct 14, 2015 at 6:55 PM, Sergey Temerkhanov s.temerkhanov@gmail.com wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
(...)
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties:
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud rate divisor)
+Optional properties: +- u-boot,skip-init: skip UART initialization at start.
Again: get this merged in the Linux kernel FIRST. Is it?
We had a little bit of a chat about this at ELCE. It would be great to get these changes merged with the kernel but the amount of push-back/energy it requires is still excessive IMO. Any thoughts?
But it also requires that we try. Did we try here? My first thought is that there's a number of things it would be nice to say "don't re-init stuff" to the kernel as well.
Hi Tom,
On 16 October 2015 at 18:23, Tom Rini trini@konsulko.com wrote:
On Fri, Oct 16, 2015 at 04:27:31PM -0600, Simon Glass wrote:
Hi Linus,
On 16 October 2015 at 15:23, Linus Walleij linus.walleij@linaro.org wrote:
On Wed, Oct 14, 2015 at 6:55 PM, Sergey Temerkhanov s.temerkhanov@gmail.com wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
(...)
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties:
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud rate divisor)
+Optional properties: +- u-boot,skip-init: skip UART initialization at start.
Again: get this merged in the Linux kernel FIRST. Is it?
We had a little bit of a chat about this at ELCE. It would be great to get these changes merged with the kernel but the amount of push-back/energy it requires is still excessive IMO. Any thoughts?
But it also requires that we try. Did we try here? My first thought is that there's a number of things it would be nice to say "don't re-init stuff" to the kernel as well.
See the thread that ends here:
http://lists.denx.de/pipermail/u-boot/2015-July/219283.html
Regards, Simon
On Sun, Oct 18, 2015 at 08:41:59PM -0600, Simon Glass wrote:
Hi Tom,
On 16 October 2015 at 18:23, Tom Rini trini@konsulko.com wrote:
On Fri, Oct 16, 2015 at 04:27:31PM -0600, Simon Glass wrote:
Hi Linus,
On 16 October 2015 at 15:23, Linus Walleij linus.walleij@linaro.org wrote:
On Wed, Oct 14, 2015 at 6:55 PM, Sergey Temerkhanov s.temerkhanov@gmail.com wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
(...)
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties:
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud rate divisor)
+Optional properties: +- u-boot,skip-init: skip UART initialization at start.
Again: get this merged in the Linux kernel FIRST. Is it?
We had a little bit of a chat about this at ELCE. It would be great to get these changes merged with the kernel but the amount of push-back/energy it requires is still excessive IMO. Any thoughts?
But it also requires that we try. Did we try here? My first thought is that there's a number of things it would be nice to say "don't re-init stuff" to the kernel as well.
See the thread that ends here:
Yes, I think maybe Geert was waiting for a reply or respin?
On Sat, Oct 17, 2015 at 12:27 AM, Simon Glass sjg@chromium.org wrote:
On 16 October 2015 at 15:23, Linus Walleij linus.walleij@linaro.org wrote:
Again: get this merged in the Linux kernel FIRST. Is it?
We had a little bit of a chat about this at ELCE. It would be great to get these changes merged with the kernel but the amount of push-back/energy it requires is still excessive IMO. Any thoughts?
I'm sorry but DT is standardization, and while I know how stinky it is to be first somewhere and having to pave the road for everyone else, in the long run it's worth it. I think when we switched the entire kernel to DT it was to get "more order", and this is the cost that comes with that order: more review.
I will go in and answer the comment on the DT mailing list so there is some push atleast.
Yours, Linus Walleij
Hi Linus,
On 19 October 2015 at 01:15, Linus Walleij linus.walleij@linaro.org wrote:
On Sat, Oct 17, 2015 at 12:27 AM, Simon Glass sjg@chromium.org wrote:
On 16 October 2015 at 15:23, Linus Walleij linus.walleij@linaro.org wrote:
Again: get this merged in the Linux kernel FIRST. Is it?
We had a little bit of a chat about this at ELCE. It would be great to get these changes merged with the kernel but the amount of push-back/energy it requires is still excessive IMO. Any thoughts?
I'm sorry but DT is standardization, and while I know how stinky it is to be first somewhere and having to pave the road for everyone else, in the long run it's worth it. I think when we switched the entire kernel to DT it was to get "more order", and this is the cost that comes with that order: more review.
I will go in and answer the comment on the DT mailing list so there is some push atleast.
Perhaps if we could see some movement then it would provide encouragement to continue. So far I cannot recall seeing a single U-Boot device tree change accepted in the 4 years I've been involved. That's not to say it hasn't happened, and I hope it is just a reflection on my memory rather than the difficulty level.
Regards, Simon
Jon & Grant especially:
On Mon, Oct 19, 2015 at 2:44 PM, Simon Glass sjg@chromium.org wrote:
Me
I will go in and answer the comment on the DT mailing list so there is some push atleast.
Perhaps if we could see some movement then it would provide encouragement to continue. So far I cannot recall seeing a single U-Boot device tree change accepted in the 4 years I've been involved. That's not to say it hasn't happened, and I hope it is just a reflection on my memory rather than the difficulty level.
OK this isn't working.
I think the problem is that DT bindings have traditionally been merged to the kernel by different subsystem maintainers. That means mailing them and their mailing lists and this is IMO too complex for U-Boot people (or other external people) to have to deal with. As subsystem maintainer I'm not very happy about being the one responsible either.
The MAINTAINERS entry for device tree bindings does not state a git tree and I've never seen any of the maintainers send a pull request for DT binding files. (Beat me up properly if you have, guys.) I've seen Grant send some at times.
I suggest sending U-Boot DT bindings to not only devicetree@vger.kernel.org but also, as indicated, to Jon Corbet and linux-doc.
If noone cares to comment in two weeks, Jon can merge them, breaking the status quo on external DT bindings.
The DT bindings maintainance has sadly been a very sad story and if the Linux kernel should be the canon repository for them, we need to find a simple way for external projects to contribute. Just mailing them to devicetree@vger obviously stands the risk of just ending up in the memory hole.
Jon, are you OK with taking on this or do we need to find another way of funneling external DT bindings? Or do you want to do this Grant?
Yours, Linus Walleij
On Mon, Oct 19, 2015 at 02:57:22PM +0200, Linus Walleij wrote:
Jon & Grant especially:
On Mon, Oct 19, 2015 at 2:44 PM, Simon Glass sjg@chromium.org wrote:
Me
I will go in and answer the comment on the DT mailing list so there is some push atleast.
Perhaps if we could see some movement then it would provide encouragement to continue. So far I cannot recall seeing a single U-Boot device tree change accepted in the 4 years I've been involved. That's not to say it hasn't happened, and I hope it is just a reflection on my memory rather than the difficulty level.
OK this isn't working.
I think the problem is that DT bindings have traditionally been merged to the kernel by different subsystem maintainers. That means mailing them and their mailing lists and this is IMO too complex for U-Boot people (or other external people) to have to deal with. As subsystem maintainer I'm not very happy about being the one responsible either.
The MAINTAINERS entry for device tree bindings does not state a git tree and I've never seen any of the maintainers send a pull request for DT binding files. (Beat me up properly if you have, guys.) I've seen Grant send some at times.
From Rob Herring Date Tue, 1 Sep 2015 16:20:13 -0500 Subject [GIT PULL] DeviceTree for 4.3
https://lkml.org/lkml/2015/9/1/526
I suggest sending U-Boot DT bindings to not only devicetree@vger.kernel.org but also, as indicated, to Jon Corbet and linux-doc.
I have no problem with patches going to an extended set of lists.
If noone cares to comment in two weeks, Jon can merge them, breaking the status quo on external DT bindings.
The DT bindings maintainance has sadly been a very sad story and if the Linux kernel should be the canon repository for them, we need to find a simple way for external projects to contribute. Just mailing them to devicetree@vger obviously stands the risk of just ending up in the memory hole.
Rob, we should organise rotating the reponsibility of picking things up.
I'd been meaning to organise something official previously, and this is a good kick to do so.
Thanks, Mark.
On Mon, Oct 19, 2015 at 7:57 AM, Linus Walleij linus.walleij@linaro.org wrote:
Jon & Grant especially:
On Mon, Oct 19, 2015 at 2:44 PM, Simon Glass sjg@chromium.org wrote:
Me
I will go in and answer the comment on the DT mailing list so there is some push atleast.
Perhaps if we could see some movement then it would provide encouragement to continue. So far I cannot recall seeing a single U-Boot device tree change accepted in the 4 years I've been involved. That's not to say it hasn't happened, and I hope it is just a reflection on my memory rather than the difficulty level.
Sorry, but anything is with "uboot,*" is going to be an uphill battle. The same is true for "linux,*" properties. There's only 2-3 linux ones that have gone in that timeframe and not without much discussion.
OK this isn't working.
I think the problem is that DT bindings have traditionally been merged to the kernel by different subsystem maintainers. That means mailing them and their mailing lists and this is IMO too complex for U-Boot people (or other external people) to have to deal with. As subsystem maintainer I'm not very happy about being the one responsible either.
The MAINTAINERS entry for device tree bindings does not state a git tree and I've never seen any of the maintainers send a pull request for DT binding files. (Beat me up properly if you have, guys.) I've seen Grant send some at times.
Err, what?
$ git log --merges --grep='Pull.*(Herring|Likely)' --oneline Documentation/devicetree/ 4401555 Merge tag 'devicetree-fixes-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux f1a3c0b Merge tag 'devicetree-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 4da3064 Merge tag 'devicetree-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux d56a669 Merge tag 'devicetree-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 7505256 Merge tag 'devicetree-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux 3d52c5b Merge tag 'devicetree-fixes-for-4.0' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux cdd3054 Merge tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux b8de08d Merge tag 'devicetree-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux 7ef58b3 Merge tag 'devicetree-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux 2e29a6d Merge tag 'devicetree-fixes-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux e98d6e7 Merge tag 'devicetree-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux 4d3afba Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux ae36e95 Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux d270506 Merge tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next 345ef87 Merge tag 'dt-fixes-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux b9f2b21 Merge tag 'dt-for-linus' of git://git.secretlab.ca/git/linux bbb1955 Merge tag 'dt-fixes-for-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 4d8880a Merge tag 'devicetree-for-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 24cb412 Merge tag 'dt-fixes-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 10d0c97 Merge tag 'devicetree-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 31f7c3a Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux 74b9272 Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux ff9129b Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux 30c67e9 Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux b3cdda2 Merge tag 'dt-for-linus' of git://git.secretlab.ca/git/linux 3aad3f0 Merge tag 'spi-for-linus' of git://git.secretlab.ca/git/linux e327955 Merge tags 'dt-for-linus', 'gpio-for-linus' and 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6 d3b43e1 Merge tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6 b0885d0 Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6 b58ed04 Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux-2.6 a54dfb1 Merge tag 'dt-for-3.7' of git://sources.calxeda.com/kernel/linux 7fe0b14 Merge tag 'spi-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc f14121a Merge tag 'dt-for-3.6' of git://sources.calxeda.com/kernel/linux b1bf7d4 Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6 0708500 Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux-2.6 e152c38 Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux-2.6 7bf97e1 Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6 5f0e685 Merge tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6 f8974cb Merge tag 'dt-for-linus' of git://git.secretlab.ca/git/linux-2.6
The DT core code and bindings (which don't go thru subsystem trees) go together. The maintainer issues with DT are on binding review bandwidth, not so much on there is no one applying them. I'm sure we've missed things though.
I suggest sending U-Boot DT bindings to not only devicetree@vger.kernel.org but also, as indicated, to Jon Corbet and linux-doc.
I'd suggest devicetree-spec@vger for common things. Perhaps we need a better name, but the whole point of this was to separate the common issues from the firehose and have multiple OS participation.
If noone cares to comment in two weeks, Jon can merge them, breaking the status quo on external DT bindings.
Did someone tell Jon to drink from that firehose?
The DT bindings maintainance has sadly been a very sad story and if the Linux kernel should be the canon repository for them, we need to find a simple way for external projects to contribute. Just mailing them to devicetree@vger obviously stands the risk of just ending up in the memory hole.
Jon, are you OK with taking on this or do we need to find another way of funneling external DT bindings? Or do you want to do this Grant?
Grant is stepping away from maintainer duties.
In any case, I don't think the problem here is bindings not getting picked up. The instances I'm aware of the bindings were reviewed and commented on.
Rob
Yours, Linus Walleij _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Mon, Oct 19, 2015 at 9:21 PM, Rob Herring robh@kernel.org wrote:
On Mon, Oct 19, 2015 at 7:57 AM, Linus Walleij linus.walleij@linaro.org wrote:
The MAINTAINERS entry for device tree bindings does not state a git tree and I've never seen any of the maintainers send a pull request for DT binding files. (Beat me up properly if you have, guys.) I've seen Grant send some at times.
Err, what?
$ git log --merges --grep='Pull.*(Herring|Likely)' --oneline Documentation/devicetree/
OK nice, bad research from me. My sloppy statement was based on this:
OPEN FIRMWARE AND FLATTENED DEVICE TREE M: Rob Herring robh+dt@kernel.org M: Frank Rowand frowand.list@gmail.com M: Grant Likely grant.likely@linaro.org L: devicetree@vger.kernel.org W: http://www.devicetree.org/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux.git S: Maintained F: drivers/of/ F: include/linux/of*.h F: scripts/dtc/
The DT core code and bindings (which don't go thru subsystem trees) go together.
I guess I should just send a patch adding
F: Documentation/devicetree/*
...and hope things get better from that.
I suggest sending U-Boot DT bindings to not only devicetree@vger.kernel.org but also, as indicated, to Jon Corbet and linux-doc.
I'd suggest devicetree-spec@vger for common things. Perhaps we need a better name, but the whole point of this was to separate the common issues from the firehose and have multiple OS participation.
Hm, wasn't devicetree@vger.kernel.org supposed to be for that?
If noone cares to comment in two weeks, Jon can merge them, breaking the status quo on external DT bindings.
Did someone tell Jon to drink from that firehose?
I'm sorry, I guess this whole mail was something I wrote in light panic over the increasing threat from the separatists.
Yours, Linus Walleij
On Tue, Oct 20, 2015 at 10:10 AM, Linus Walleij linus.walleij@linaro.org wrote:
On Mon, Oct 19, 2015 at 9:21 PM, Rob Herring robh@kernel.org wrote:
On Mon, Oct 19, 2015 at 7:57 AM, Linus Walleij linus.walleij@linaro.org wrote:
Err, what?
$ git log --merges --grep='Pull.*(Herring|Likely)' --oneline Documentation/devicetree/
OK nice, bad research from me. My sloppy statement was based on this:
OPEN FIRMWARE AND FLATTENED DEVICE TREE M: Rob Herring robh+dt@kernel.org M: Frank Rowand frowand.list@gmail.com M: Grant Likely grant.likely@linaro.org L: devicetree@vger.kernel.org W: http://www.devicetree.org/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux.git S: Maintained F: drivers/of/ F: include/linux/of*.h F: scripts/dtc/
The DT core code and bindings (which don't go thru subsystem trees) go together.
I guess I should just send a patch adding
F: Documentation/devicetree/*
...and hope things get better from that.
Ah yeah now I also woke up properly... so there is a special group of people listed under another heading for this, and I should know that, mea culpa.
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS M: Rob Herring robh+dt@kernel.org M: Pawel Moll pawel.moll@arm.com M: Mark Rutland mark.rutland@arm.com M: Ian Campbell ijc+devicetree@hellion.org.uk M: Kumar Gala galak@codeaurora.org L: devicetree@vger.kernel.org S: Maintained F: Documentation/devicetree/ F: arch/*/boot/dts/ F: include/dt-bindings/
So can we add your git tree as T: here and replace Grant's tree in the overall DT entry above it?
Yours, Linus Walleij
On Tue, Oct 20, 2015 at 3:15 AM, Linus Walleij linus.walleij@linaro.org wrote:
On Tue, Oct 20, 2015 at 10:10 AM, Linus Walleij linus.walleij@linaro.org wrote:
On Mon, Oct 19, 2015 at 9:21 PM, Rob Herring robh@kernel.org wrote:
On Mon, Oct 19, 2015 at 7:57 AM, Linus Walleij linus.walleij@linaro.org wrote:
Err, what?
$ git log --merges --grep='Pull.*(Herring|Likely)' --oneline Documentation/devicetree/
OK nice, bad research from me. My sloppy statement was based on this:
OPEN FIRMWARE AND FLATTENED DEVICE TREE M: Rob Herring robh+dt@kernel.org M: Frank Rowand frowand.list@gmail.com M: Grant Likely grant.likely@linaro.org L: devicetree@vger.kernel.org W: http://www.devicetree.org/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux.git S: Maintained F: drivers/of/ F: include/linux/of*.h F: scripts/dtc/
The DT core code and bindings (which don't go thru subsystem trees) go together.
I guess I should just send a patch adding
F: Documentation/devicetree/*
...and hope things get better from that.
Ah yeah now I also woke up properly... so there is a special group of people listed under another heading for this, and I should know that, mea culpa.
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS M: Rob Herring robh+dt@kernel.org M: Pawel Moll pawel.moll@arm.com M: Mark Rutland mark.rutland@arm.com M: Ian Campbell ijc+devicetree@hellion.org.uk M: Kumar Gala galak@codeaurora.org L: devicetree@vger.kernel.org S: Maintained F: Documentation/devicetree/ F: arch/*/boot/dts/ F: include/dt-bindings/
So can we add your git tree as T: here and replace Grant's tree in the overall DT entry above it?
I would hold off. We've not sorted out our workflow yet and may move to a shared repo.
Rob
Hi,
On 20 October 2015 at 07:05, Rob Herring robh@kernel.org wrote:
On Tue, Oct 20, 2015 at 3:15 AM, Linus Walleij linus.walleij@linaro.org wrote:
On Tue, Oct 20, 2015 at 10:10 AM, Linus Walleij linus.walleij@linaro.org wrote:
On Mon, Oct 19, 2015 at 9:21 PM, Rob Herring robh@kernel.org wrote:
On Mon, Oct 19, 2015 at 7:57 AM, Linus Walleij linus.walleij@linaro.org wrote:
Err, what?
$ git log --merges --grep='Pull.*(Herring|Likely)' --oneline Documentation/devicetree/
OK nice, bad research from me. My sloppy statement was based on this:
OPEN FIRMWARE AND FLATTENED DEVICE TREE M: Rob Herring robh+dt@kernel.org M: Frank Rowand frowand.list@gmail.com M: Grant Likely grant.likely@linaro.org L: devicetree@vger.kernel.org W: http://www.devicetree.org/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux.git S: Maintained F: drivers/of/ F: include/linux/of*.h F: scripts/dtc/
The DT core code and bindings (which don't go thru subsystem trees) go together.
I guess I should just send a patch adding
F: Documentation/devicetree/*
...and hope things get better from that.
Ah yeah now I also woke up properly... so there is a special group of people listed under another heading for this, and I should know that, mea culpa.
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS M: Rob Herring robh+dt@kernel.org M: Pawel Moll pawel.moll@arm.com M: Mark Rutland mark.rutland@arm.com M: Ian Campbell ijc+devicetree@hellion.org.uk M: Kumar Gala galak@codeaurora.org L: devicetree@vger.kernel.org S: Maintained F: Documentation/devicetree/ F: arch/*/boot/dts/ F: include/dt-bindings/
So can we add your git tree as T: here and replace Grant's tree in the overall DT entry above it?
I would hold off. We've not sorted out our workflow yet and may move to a shared repo.
With respect to this patch, I wonder if someone in the 'circle of trust' might draw up a patch to handle skipping init and specifying the input the clock speed? A little bit of progress might go a long way.
Regards, Simon
On Wed, Oct 21, 2015 at 02:49:20PM -0600, Simon Glass wrote:
Hi,
On 20 October 2015 at 07:05, Rob Herring robh@kernel.org wrote:
On Tue, Oct 20, 2015 at 3:15 AM, Linus Walleij linus.walleij@linaro.org wrote:
On Tue, Oct 20, 2015 at 10:10 AM, Linus Walleij linus.walleij@linaro.org wrote:
On Mon, Oct 19, 2015 at 9:21 PM, Rob Herring robh@kernel.org wrote:
On Mon, Oct 19, 2015 at 7:57 AM, Linus Walleij linus.walleij@linaro.org wrote:
Err, what?
$ git log --merges --grep='Pull.*(Herring|Likely)' --oneline Documentation/devicetree/
OK nice, bad research from me. My sloppy statement was based on this:
OPEN FIRMWARE AND FLATTENED DEVICE TREE M: Rob Herring robh+dt@kernel.org M: Frank Rowand frowand.list@gmail.com M: Grant Likely grant.likely@linaro.org L: devicetree@vger.kernel.org W: http://www.devicetree.org/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux.git S: Maintained F: drivers/of/ F: include/linux/of*.h F: scripts/dtc/
The DT core code and bindings (which don't go thru subsystem trees) go together.
I guess I should just send a patch adding
F: Documentation/devicetree/*
...and hope things get better from that.
Ah yeah now I also woke up properly... so there is a special group of people listed under another heading for this, and I should know that, mea culpa.
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS M: Rob Herring robh+dt@kernel.org M: Pawel Moll pawel.moll@arm.com M: Mark Rutland mark.rutland@arm.com M: Ian Campbell ijc+devicetree@hellion.org.uk M: Kumar Gala galak@codeaurora.org L: devicetree@vger.kernel.org S: Maintained F: Documentation/devicetree/ F: arch/*/boot/dts/ F: include/dt-bindings/
So can we add your git tree as T: here and replace Grant's tree in the overall DT entry above it?
I would hold off. We've not sorted out our workflow yet and may move to a shared repo.
With respect to this patch, I wonder if someone in the 'circle of trust' might draw up a patch to handle skipping init and specifying the input the clock speed? A little bit of progress might go a long way.
Or at least "yes, if you do it $this way, we'll take it".. ?
On Tue, Oct 20, 2015 at 3:10 AM, Linus Walleij linus.walleij@linaro.org wrote:
On Mon, Oct 19, 2015 at 9:21 PM, Rob Herring robh@kernel.org wrote:
On Mon, Oct 19, 2015 at 7:57 AM, Linus Walleij linus.walleij@linaro.org wrote:
The MAINTAINERS entry for device tree bindings does not state a git tree and I've never seen any of the maintainers send a pull request for DT binding files. (Beat me up properly if you have, guys.) I've seen Grant send some at times.
Err, what?
$ git log --merges --grep='Pull.*(Herring|Likely)' --oneline Documentation/devicetree/
OK nice, bad research from me. My sloppy statement was based on this:
OPEN FIRMWARE AND FLATTENED DEVICE TREE M: Rob Herring robh+dt@kernel.org M: Frank Rowand frowand.list@gmail.com M: Grant Likely grant.likely@linaro.org L: devicetree@vger.kernel.org W: http://www.devicetree.org/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux.git S: Maintained F: drivers/of/ F: include/linux/of*.h F: scripts/dtc/
The DT core code and bindings (which don't go thru subsystem trees) go together.
I guess I should just send a patch adding
F: Documentation/devicetree/*
I see you found it is already there...
...and hope things get better from that.
I suggest sending U-Boot DT bindings to not only devicetree@vger.kernel.org but also, as indicated, to Jon Corbet and linux-doc.
I'd suggest devicetree-spec@vger for common things. Perhaps we need a better name, but the whole point of this was to separate the common issues from the firehose and have multiple OS participation.
Hm, wasn't devicetree@vger.kernel.org supposed to be for that?
Yes, but BSD developers complained about all the Linux driver patches, so devicetree-spec was created as was devicetree-compiler to try to separate out the lower volume stuff. We need to do more with MAINTAINERS so that common bindings go to devicetree-spec.
Rob
On Mon, Oct 19, 2015 at 06:44:25AM -0600, Simon Glass wrote:
Hi Linus,
On 19 October 2015 at 01:15, Linus Walleij linus.walleij@linaro.org wrote:
On Sat, Oct 17, 2015 at 12:27 AM, Simon Glass sjg@chromium.org wrote:
On 16 October 2015 at 15:23, Linus Walleij linus.walleij@linaro.org wrote:
Again: get this merged in the Linux kernel FIRST. Is it?
We had a little bit of a chat about this at ELCE. It would be great to get these changes merged with the kernel but the amount of push-back/energy it requires is still excessive IMO. Any thoughts?
I'm sorry but DT is standardization, and while I know how stinky it is to be first somewhere and having to pave the road for everyone else, in the long run it's worth it. I think when we switched the entire kernel to DT it was to get "more order", and this is the cost that comes with that order: more review.
I will go in and answer the comment on the DT mailing list so there is some push atleast.
Perhaps if we could see some movement then it would provide encouragement to continue. So far I cannot recall seeing a single U-Boot device tree change accepted in the 4 years I've been involved. That's not to say it hasn't happened, and I hope it is just a reflection on my memory rather than the difficulty level.
I think there's a few things that need to be kept in mind. First, the DT world is changing compared to where it was a year ago, and even more so since August or so (LPC?). There should be less of a stuck in limbo problem. The second is that since we aren't using DT as free-form replacement for values shoved in a C header, it is a lot more work to get things agreed to and merged with our upstream here. And third (and maybe this is where devicetree-spec@vger.kernel.org comes in) is that if this is really going to be some useful and OS-agnostic description of the hardware then yes, we do need some way to say 'here is what the clock freq is once released from ROM'.
All of that said, maybe "no re-init of console port" is not quite right for the UART node (maybe a property of the stdout-path to note this condition as Rob suggests).
On Wed, Oct 14, 2015 at 11:55 AM, Sergey Temerkhanov s.temerkhanov@gmail.com wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
I'll comment on this now that I'm here, but as the rest of the thread said, please send to DT list.
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties:
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud rate divisor)
+Optional properties: +- u-boot,skip-init: skip UART initialization at start.
What are you trying to accomplish by skipping?
stdout-path can take options now, so what about making it an option there:
stdout-path = &serial0:no-init
I have similar concerns with this as I did with the early init flag. This requires the dtb and u-boot to be in sync. For example, you have this option in the dtb, but then you add clock initialization to your platform which changes the default clock frequency of the UART. Now if you boot with an older dtb and new u-boot, then it will break because the UART is at the wrong baudrate.
Rob
Hi Rob,
On 19 October 2015 at 14:14, Rob Herring robherring2@gmail.com wrote:
On Wed, Oct 14, 2015 at 11:55 AM, Sergey Temerkhanov s.temerkhanov@gmail.com wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
I'll comment on this now that I'm here, but as the rest of the thread said, please send to DT list.
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties:
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud rate divisor)
+Optional properties: +- u-boot,skip-init: skip UART initialization at start.
What are you trying to accomplish by skipping?
stdout-path can take options now, so what about making it an option there:
stdout-path = &serial0:no-init
I have similar concerns with this as I did with the early init flag. This requires the dtb and u-boot to be in sync. For example, you have this option in the dtb, but then you add clock initialization to your platform which changes the default clock frequency of the UART. Now if you boot with an older dtb and new u-boot, then it will break because the UART is at the wrong baudrate.
If you are saying what I think you are saying, U-Boot expects the device tree that IT uses for configuration to come from the same commit as the source code. It doesn't support anything else as the DTB is bundled with (and replaced at the same time as) U-Boot.. You would be on your own in that case.
Regards, Simon
On Mon, Oct 19, 2015 at 5:09 PM, Simon Glass sjg@chromium.org wrote:
Hi Rob,
On 19 October 2015 at 14:14, Rob Herring robherring2@gmail.com wrote:
On Wed, Oct 14, 2015 at 11:55 AM, Sergey Temerkhanov s.temerkhanov@gmail.com wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
I'll comment on this now that I'm here, but as the rest of the thread said, please send to DT list.
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties:
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud rate divisor)
+Optional properties: +- u-boot,skip-init: skip UART initialization at start.
What are you trying to accomplish by skipping?
stdout-path can take options now, so what about making it an option there:
stdout-path = &serial0:no-init
I have similar concerns with this as I did with the early init flag. This requires the dtb and u-boot to be in sync. For example, you have this option in the dtb, but then you add clock initialization to your platform which changes the default clock frequency of the UART. Now if you boot with an older dtb and new u-boot, then it will break because the UART is at the wrong baudrate.
If you are saying what I think you are saying, U-Boot expects the device tree that IT uses for configuration to come from the same commit as the source code. It doesn't support anything else as the DTB is bundled with (and replaced at the same time as) U-Boot.. You would be on your own in that case.
You can have that expectation, but that is generally not how DT works. Bindings are an ABI. You may not care for some usecases or boards, but we generally can't assume a DTB and its user whether u-boot, kernel, BSD, etc. are linked together. The rule is new s/w version should work with old DTB.
How is it going to work when/if we put dts files in a standalone repository?
What I want to see WRT u-boot and DTB handling is that they are independently updateable. That is already the case on some platforms such as highbank. The way it works is the management processor put both u-boot and the DTB into memory and then boots the cores. u-boot does minor tweaks and then passes the DTB on to the OS. I was working some to add u-boot DT config support for highbank before Calxeda's demise. IIRC, the main problems I hit were telling u-boot where the dtb is and then having it pass the same DTB on to the kernel. I doubt I'm the only one that would like things to work that way.
Rob
Hi Rob,
On 23 October 2015 at 12:35, Rob Herring robherring2@gmail.com wrote:
On Mon, Oct 19, 2015 at 5:09 PM, Simon Glass sjg@chromium.org wrote:
Hi Rob,
On 19 October 2015 at 14:14, Rob Herring robherring2@gmail.com wrote:
On Wed, Oct 14, 2015 at 11:55 AM, Sergey Temerkhanov s.temerkhanov@gmail.com wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
I'll comment on this now that I'm here, but as the rest of the thread said, please send to DT list.
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties:
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud rate divisor)
+Optional properties: +- u-boot,skip-init: skip UART initialization at start.
What are you trying to accomplish by skipping?
stdout-path can take options now, so what about making it an option there:
stdout-path = &serial0:no-init
I have similar concerns with this as I did with the early init flag. This requires the dtb and u-boot to be in sync. For example, you have this option in the dtb, but then you add clock initialization to your platform which changes the default clock frequency of the UART. Now if you boot with an older dtb and new u-boot, then it will break because the UART is at the wrong baudrate.
If you are saying what I think you are saying, U-Boot expects the device tree that IT uses for configuration to come from the same commit as the source code. It doesn't support anything else as the DTB is bundled with (and replaced at the same time as) U-Boot.. You would be on your own in that case.
You can have that expectation, but that is generally not how DT works. Bindings are an ABI. You may not care for some usecases or boards, but we generally can't assume a DTB and its user whether u-boot, kernel, BSD, etc. are linked together. The rule is new s/w version should work with old DTB.
How is it going to work when/if we put dts files in a standalone repository?
What I want to see WRT u-boot and DTB handling is that they are independently updateable. That is already the case on some platforms such as highbank. The way it works is the management processor put both u-boot and the DTB into memory and then boots the cores. u-boot does minor tweaks and then passes the DTB on to the OS. I was working some to add u-boot DT config support for highbank before Calxeda's demise. IIRC, the main problems I hit were telling u-boot where the dtb is and then having it pass the same DTB on to the kernel. I doubt I'm the only one that would like things to work that way.
I don't see that this is a requirement. Also I don't think it makes sense.
U-Boot and Linux have quite different field-upgrade cycles. It is quite common to update the kernel without updating U-Boot, and vice versa. Some platforms will never update U-Boot. Some platforms have U-Boot in one medium (sometimes even read-only) and Linux in another. When updating the kernel I would expect the kernel device tree to be updated also - e.g. a new FIT image containing the kernel and device tree files. This is because we may have new drivers or enhanced features there were not defined in the earlier device tre.
When updating U-Boot I would expect U-Boot's device tree to update also, without affecting the one passed to the kernel. Similar to the above there may be new features or enhancements that require this.
If there is ever a stand-alone repository then we can revisit this discussion, but I doubt it makes much different for U-Boot at least, which requires the device tree to complete its build. Maybe something has changed recently to suggest things will go that way, but as far as I recall it has been talked about for 4 years.
It should be possible for the U-Boot project to decide how it uses device tree.
Regards, Simon
On Mon, Oct 19, 2015 at 1:14 PM, Rob Herring robherring2@gmail.com wrote:
On Wed, Oct 14, 2015 at 11:55 AM, Sergey Temerkhanov s.temerkhanov@gmail.com wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
I'll comment on this now that I'm here, but as the rest of the thread said, please send to DT list.
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties:
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud rate divisor)
+Optional properties: +- u-boot,skip-init: skip UART initialization at start.
What are you trying to accomplish by skipping?
stdout-path can take options now, so what about making it an option there:
stdout-path = &serial0:no-init
It's not about a single UART but all UARTs present in the platform. Some of them might have different reference clocks/PLL settings/whatever which can be tricky to support with FDT editing/rebuilding/etc. Especially if those reference clocks can be reprogrammed between runs.
I have similar concerns with this as I did with the early init flag. This requires the dtb and u-boot to be in sync. For example, you have this option in the dtb, but then you add clock initialization to your platform which changes the default clock frequency of the UART. Now if you boot with an older dtb and new u-boot, then it will break because the UART is at the wrong baudrate.
It's not a problem at all since the U-Boot image with an attached DTB is being used. And that DTB comes from the U-Boot source tree.
Rob
On Wed, Oct 14, 2015 at 09:55:48AM -0700, Sergey Temerkhanov wrote:
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Reviewed-by: Simon Glass sjg@chromium.org
In the end, this appears to have become mired in a lack of getting a device tree binding for this functionality in particular to be accepted upstream from us. I'm deferring on this particular version until someone with the time and desire to resolve the binding does so.
This commit adds the FDT for the ThunderX family of SoCs
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v7: None Changes in v6: - Added /chosen node
Changes in v5: - Added FDT for ThunderX 88xx series
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/dts/Makefile | 1 + arch/arm/dts/thunderx-88xx.dts | 31 ++++ arch/arm/dts/thunderx-88xx.dtsi | 363 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 395 insertions(+) create mode 100644 arch/arm/dts/thunderx-88xx.dts create mode 100644 arch/arm/dts/thunderx-88xx.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 65b4230..9fb8dee 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb +dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ diff --git a/arch/arm/dts/thunderx-88xx.dts b/arch/arm/dts/thunderx-88xx.dts new file mode 100644 index 0000000..08f2678 --- /dev/null +++ b/arch/arm/dts/thunderx-88xx.dts @@ -0,0 +1,31 @@ +/* + * Cavium Thunder DTS file - Thunder board description + * + * Copyright (C) 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + */ + +/dts-v1/; + +/include/ "thunderx-88xx.dtsi" + +/ { + model = "Cavium ThunderX CN88XX board"; + compatible = "cavium,thunder-88xx"; + + aliases { + serial0 = &uaa0; + serial1 = &uaa1; + }; + + chosen { + stdout-path = &uaa0; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x80000000>; + }; +}; diff --git a/arch/arm/dts/thunderx-88xx.dtsi b/arch/arm/dts/thunderx-88xx.dtsi new file mode 100644 index 0000000..086652f --- /dev/null +++ b/arch/arm/dts/thunderx-88xx.dtsi @@ -0,0 +1,363 @@ +/* + * Cavium Thunder DTS file - Thunder SoC description + * + * Copyright (C) 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + */ + +/ { + compatible = "cavium,thunder-88xx"; + interrupt-parent = <&gic0>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@000 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; + }; + cpu@001 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "psci"; + }; + cpu@002 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "psci"; + }; + cpu@003 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "psci"; + }; + cpu@004 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x004>; + enable-method = "psci"; + }; + cpu@005 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x005>; + enable-method = "psci"; + }; + cpu@006 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x006>; + enable-method = "psci"; + }; + cpu@007 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x007>; + enable-method = "psci"; + }; + cpu@008 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x008>; + enable-method = "psci"; + }; + cpu@009 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x009>; + enable-method = "psci"; + }; + cpu@00a { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00a>; + enable-method = "psci"; + }; + cpu@00b { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00b>; + enable-method = "psci"; + }; + cpu@00c { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00c>; + enable-method = "psci"; + }; + cpu@00d { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00d>; + enable-method = "psci"; + }; + cpu@00e { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00e>; + enable-method = "psci"; + }; + cpu@00f { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x00f>; + enable-method = "psci"; + }; + cpu@100 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + cpu@101 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + cpu@102 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + cpu@103 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + cpu@104 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x104>; + enable-method = "psci"; + }; + cpu@105 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x105>; + enable-method = "psci"; + }; + cpu@106 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x106>; + enable-method = "psci"; + }; + cpu@107 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x107>; + enable-method = "psci"; + }; + cpu@108 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x108>; + enable-method = "psci"; + }; + cpu@109 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x109>; + enable-method = "psci"; + }; + cpu@10a { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10a>; + enable-method = "psci"; + }; + cpu@10b { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10b>; + enable-method = "psci"; + }; + cpu@10c { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10c>; + enable-method = "psci"; + }; + cpu@10d { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10d>; + enable-method = "psci"; + }; + cpu@10e { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10e>; + enable-method = "psci"; + }; + cpu@10f { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x10f>; + enable-method = "psci"; + }; + cpu@200 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + }; + cpu@201 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + }; + cpu@202 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x202>; + enable-method = "psci"; + }; + cpu@203 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x203>; + enable-method = "psci"; + }; + cpu@204 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x204>; + enable-method = "psci"; + }; + cpu@205 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x205>; + enable-method = "psci"; + }; + cpu@206 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x206>; + enable-method = "psci"; + }; + cpu@207 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x207>; + enable-method = "psci"; + }; + cpu@208 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x208>; + enable-method = "psci"; + }; + cpu@209 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x209>; + enable-method = "psci"; + }; + cpu@20a { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20a>; + enable-method = "psci"; + }; + cpu@20b { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20b>; + enable-method = "psci"; + }; + cpu@20c { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20c>; + enable-method = "psci"; + }; + cpu@20d { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20d>; + enable-method = "psci"; + }; + cpu@20e { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20e>; + enable-method = "psci"; + }; + cpu@20f { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x20f>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "refclk50mhz"; + }; + + gic0: interrupt-controller@8010,00000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */ + <0x8010 0x80000000 0x0 0x600000>; /* GICR */ + interrupts = <1 9 0xf04>; + }; + + uaa0: serial@87e0,24000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x24000000 0x0 0x1000>; + interrupts = <1 21 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk"; + flags = <1>; + }; + + uaa1: serial@87e0,25000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x25000000 0x0 0x1000>; + interrupts = <1 22 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk"; + flags = <1>; + }; + }; +};
On Wed, Oct 14, 2015 at 09:55:49AM -0700, Sergey Temerkhanov wrote:
This commit adds the FDT for the ThunderX family of SoCs
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot/master, thanks!
This commit adds basic Cavium ThunderX 88xx board definitions and support.
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
---
Changes in v7: - Removed rebase/merge residue - Added CONFIG_CMD_ATF - Updated defconfig - Fixed typo in the 'uboot,skip-init' preperty
Changes in v6: - Added 'u-boot,skip-init' property to the FDT
Changes in v5: - Added CONFIG_OF_CONTROL support - Changed memory attributes
Changes in v4: - Moved CONFIG_SYS_PROMPT to configs/thunderx_88xx_defconfig - Added proper DM_SERIAL definitions
Changes in v3: - Fixed formatting - Added MAINTAINERS - Moved command definitions to defconfig
Changes in v2: None
arch/arm/Kconfig | 5 ++ arch/arm/dts/thunderx-88xx.dtsi | 4 +- board/cavium/thunderx/Kconfig | 27 +++++++ board/cavium/thunderx/MAINTAINERS | 6 ++ board/cavium/thunderx/Makefile | 8 +++ board/cavium/thunderx/thunderx.c | 75 ++++++++++++++++++++ configs/thunderx_88xx_defconfig | 24 +++++++ include/configs/thunderx_88xx.h | 145 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 292 insertions(+), 2 deletions(-) create mode 100644 board/cavium/thunderx/Kconfig create mode 100644 board/cavium/thunderx/MAINTAINERS create mode 100644 board/cavium/thunderx/Makefile create mode 100644 board/cavium/thunderx/thunderx.c create mode 100644 configs/thunderx_88xx_defconfig create mode 100644 include/configs/thunderx_88xx.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7981355..a90f9db 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -666,6 +666,10 @@ config ARCH_ROCKCHIP select CPU_V7 select DM
+config TARGET_THUNDERX_88XX + bool "Support ThunderX 88xx" + select OF_CONTROL + endchoice
source "arch/arm/mach-at91/Kconfig" @@ -734,6 +738,7 @@ source "board/bluegiga/apx4devkit/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" +source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" diff --git a/arch/arm/dts/thunderx-88xx.dtsi b/arch/arm/dts/thunderx-88xx.dtsi index 086652f..6e9230b 100644 --- a/arch/arm/dts/thunderx-88xx.dtsi +++ b/arch/arm/dts/thunderx-88xx.dtsi @@ -348,7 +348,7 @@ interrupts = <1 21 4>; clocks = <&refclk50mhz>; clock-names = "apb_pclk"; - flags = <1>; + uboot,skip-init; };
uaa1: serial@87e0,25000000 { @@ -357,7 +357,7 @@ interrupts = <1 22 4>; clocks = <&refclk50mhz>; clock-names = "apb_pclk"; - flags = <1>; + uboot,skip-init; }; }; }; diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig new file mode 100644 index 0000000..927d876 --- /dev/null +++ b/board/cavium/thunderx/Kconfig @@ -0,0 +1,27 @@ +if TARGET_THUNDERX_88XX + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "thunderx" + +config SYS_VENDOR + string + default "cavium" + +config SYS_CONFIG_NAME + string + default "thunderx_88xx" + +config CMD_ATF + bool "Enable ATF query commands" + default y + help + Enable vendor specific ATF query commands such as SPI and SD/MMC + devices access, low level environment query, boot device layout + and node count. + +endif diff --git a/board/cavium/thunderx/MAINTAINERS b/board/cavium/thunderx/MAINTAINERS new file mode 100644 index 0000000..c84d3b5 --- /dev/null +++ b/board/cavium/thunderx/MAINTAINERS @@ -0,0 +1,6 @@ +THUNDERX BOARD +M: Sergey Temerkhanov s.temerkhanov@gmail.com +S: Maintained +F: board/cavium/thunderx/ +F: include/configs/thunderx_88xx.h +F: configs/thunderx_88xx_defconfig diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile new file mode 100644 index 0000000..306044a --- /dev/null +++ b/board/cavium/thunderx/Makefile @@ -0,0 +1,8 @@ +# +# +# (C) Copyright 2014, Cavium Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := thunderx.o diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c new file mode 100644 index 0000000..486374e --- /dev/null +++ b/board/cavium/thunderx/thunderx.c @@ -0,0 +1,75 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <linux/compiler.h> + +#if !CONFIG_IS_ENABLED(OF_CONTROL) +#include <dm/platdata.h> +#include <dm/platform_data/serial_pl01x.h> + +static const struct pl01x_serial_platdata serial0 = { + .base = CONFIG_SYS_SERIAL0, + .type = TYPE_PL011, + .clock = 0, + .skip_init = true, +}; + +U_BOOT_DEVICE(thunderx_serial0) = { + .name = "serial_pl01x", + .platdata = &serial0, +}; + +static const struct pl01x_serial_platdata serial1 = { + .base = CONFIG_SYS_SERIAL1, + .type = TYPE_PL011, + .clock = 0, + .skip_init = true, +}; + +U_BOOT_DEVICE(thunderx_serial1) = { + .name = "serial_pl01x", + .platdata = &serial1, +}; +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int timer_init(void) +{ + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +/* + * Board specific ethernet initialization routine. + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + return rc; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + printf("DEBUG: PCI Init TODO *****\n"); +} +#endif diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig new file mode 100644 index 0000000..b7078e0 --- /dev/null +++ b/configs/thunderx_88xx_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_TARGET_THUNDERX_88XX=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx" +CONFIG_SYS_EXTRA_OPTIONS="ARM64" +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="ThunderX_88XX> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_DM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_PL011=y +CONFIG_DEBUG_UART_BASE=0x87e024000000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_REGEX=y diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h new file mode 100644 index 0000000..7b4cd9b --- /dev/null +++ b/include/configs/thunderx_88xx.h @@ -0,0 +1,145 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#ifndef __THUNDERX_88XX_H__ +#define __THUNDERX_88XX_H__ + +#define CONFIG_REMAKE_ELF + +#define CONFIG_THUNDERX + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_64BIT + +#define CONFIG_SYS_NO_FLASH + + +#define CONFIG_IDENT_STRING \ + " for Cavium Thunder CN88XX ARM v8 Multi-Core" +#define CONFIG_BOOTP_VCI_STRING "Diagnostics" + +#define MEM_BASE 0x00500000 + +#define CONFIG_COREID_MASK 0xffffff + +#define CONFIG_SYS_FULL_VA + +#define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ + PTL2_MEMTYPE(MT_NORMAL) | \ + PTL2_BLOCK_NON_SHARE}, \ + {0x800000000000UL, 0x40000000000UL, \ + PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ + PTL2_BLOCK_NON_SHARE}, \ + {0x840000000000UL, 0x40000000000UL, \ + PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \ + PTL2_BLOCK_NON_SHARE}, \ + } + +#define CONFIG_SYS_MEM_MAP_SIZE 3 + +#define CONFIG_SYS_VA_BITS 48 +#define CONFIG_SYS_PTL2_BITS 42 +#define CONFIG_SYS_BLOCK_SHIFT 29 +#define CONFIG_SYS_PTL1_ENTRIES 64 +#define CONFIG_SYS_PTL2_ENTRIES 8192 + +#define CONFIG_SYS_PGTABLE_SIZE \ + ((CONFIG_SYS_PTL1_ENTRIES + \ + CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8) +#define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32) +#define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16) +#define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16) + +/* Link Definitions */ +#define CONFIG_SYS_TEXT_BASE 0x00500000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +/* SMP Spin Table Definitions */ +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + + +#define CONFIG_SYS_MEMTEST_START MEM_BASE +#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* PL011 Serial Configuration */ + +#define CONFIG_PL01X_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_CONS_INDEX 1 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0x801000000000) +#define GICR_BASE (0x801000002000) +#define CONFIG_SYS_SERIAL0 0x87e024000000 +#define CONFIG_SYS_SERIAL1 0x87e025000000 + +#define CONFIG_BAUDRATE 115200 + +/* Command line configuration */ +#define CONFIG_MENU + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (MEM_BASE) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Initial environment variables */ +#define UBOOT_IMG_HEAD_SIZE 0x40 +/* C80000 - 0x40 */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=08007ffc0\0" \ + "fdt_addr=0x94C00000\0" \ + "fdt_high=0x9fffffff\0" + +#define CONFIG_BOOTARGS \ + "console=ttyAMA0,115200n8 " \ + "earlycon=pl011,0x87e024000000 " \ + "debug maxcpus=48 rootwait rw "\ + "root=/dev/sda2 coherent_pool=16M" +#define CONFIG_BOOTDELAY 5 + +/* Do not preserve environment */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ +#define CONFIG_NO_RELOCATION 1 +#define CONFIG_LIB_RAND +#define PLL_REF_CLK 50000000 /* 50 MHz */ +#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) + +#endif /* __THUNDERX_88XX_H__ */
On Wed, Oct 14, 2015 at 09:55:50AM -0700, Sergey Temerkhanov wrote:
This commit adds basic Cavium ThunderX 88xx board definitions and support.
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
With a minor change for current API, applied to u-boot/master, thanks!
This commit adds functions issuing calls to the product-specific ATF services
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com ---
Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
board/cavium/thunderx/Makefile | 2 +- board/cavium/thunderx/atf.c | 312 ++++++++++++++++++++++++++++++++++++++++ include/cavium/atf.h | 22 +++ include/cavium/atf_part.h | 26 ++++ include/cavium/thunderx_svc.h | 67 +++++++++ include/configs/thunderx_88xx.h | 2 + 6 files changed, 430 insertions(+), 1 deletion(-) create mode 100644 board/cavium/thunderx/atf.c create mode 100644 include/cavium/atf.h create mode 100644 include/cavium/atf_part.h create mode 100644 include/cavium/thunderx_svc.h
diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile index 306044a..c78c414 100644 --- a/board/cavium/thunderx/Makefile +++ b/board/cavium/thunderx/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y := thunderx.o +obj-y := thunderx.o atf.o diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c new file mode 100644 index 0000000..6ab9de9 --- /dev/null +++ b/board/cavium/thunderx/atf.c @@ -0,0 +1,312 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <common.h> +#include <asm/io.h> + +#include <asm/system.h> +#include <cavium/thunderx_svc.h> +#include <cavium/atf.h> +#include <cavium/atf_part.h> + +#include <asm/psci.h> + +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_MMC_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_NOR_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_get_pcount(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_PART_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_get_part(struct storage_partition *part, unsigned int index) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_GET_PART; + regs.regs[1] = (uintptr_t)part; + regs.regs[2] = index; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_erase_nor(uintptr_t offset, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_NOR_ERASE; + regs.regs[1] = offset; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_NOR_WRITE; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_MMC_WRITE; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_dram_size(unsigned int node) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_DRAM_SIZE; + regs.regs[1] = node; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_node_count(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_NODE_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_env_count(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_ENV_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_env_string(size_t index, char *str) +{ + uint64_t *buf = (void *)str; + struct pt_regs regs; + regs.regs[0] = THUNDERX_ENV_STRING; + regs.regs[1] = index; + + smc_call(®s); + + if (regs.regs > 0) { + buf[0] = regs.regs[0]; + buf[1] = regs.regs[1]; + buf[2] = regs.regs[2]; + buf[3] = regs.regs[3]; + + return 1; + } else { + return regs.regs[0]; + } +} + +#ifdef CONFIG_CMD_ATF + +static void atf_print_ver(void) +{ + struct pt_regs regs; + regs.regs[0] = ARM_STD_SVC_VERSION; + + smc_call(®s); + + printf("ARM Std FW version: %ld.%ld\n", regs.regs[0], regs.regs[1]); + + regs.regs[0] = THUNDERX_SVC_VERSION; + + smc_call(®s); + + printf("ThunderX OEM ver: %ld.%ld\n", regs.regs[0], regs.regs[1]); +} + +static void atf_print_uid(void) +{ +} + +static void atf_print_part_table(void) +{ + size_t pcount; + unsigned long i; + int ret; + char *ptype; + + struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE; + + pcount = atf_get_pcount(); + + printf("Partition count: %lu\n\n", pcount); + printf("%10s %10s %10s\n", "Type", "Size", "Offset"); + + for (i = 0; i < pcount; i++) { + ret = atf_get_part(part, i); + + if (ret < 0) { + printf("Uknown error while reading partition: %d\n", + ret); + return; + } + + switch (part->type) { + case PARTITION_NBL1FW_REST: + ptype = "NBL1FW"; + break; + case PARTITION_BL2_BL31: + ptype = "BL2_BL31"; + break; + case PARTITION_UBOOT: + ptype = "BOOTLDR"; + break; + case PARTITION_KERNEL: + ptype = "KERNEL"; + break; + case PARTITION_DEVICE_TREE: + ptype = "DEVTREE"; + break; + default: + ptype = "UNKNOWN"; + } + printf("%10s %10d %10lx\n", ptype, part->size, part->offset); + } +} + +int do_atf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ssize_t ret; + size_t size, offset; + void *buffer = 0; + unsigned int index, node; + char str[4 * sizeof(uint64_t)]; + + if ((argc == 5) && !strcmp(argv[1], "readmmc")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_read_mmc(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "readnor")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_read_nor(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "writemmc")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_write_mmc(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "writenor")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_write_nor(offset, buffer, size); + } else if ((argc == 2) && !strcmp(argv[1], "part")) { + atf_print_part_table(); + } else if ((argc == 4) && !strcmp(argv[1], "erasenor")) { + offset = simple_strtoul(argv[2], NULL, 10); + size = simple_strtoul(argv[3], NULL, 10); + + ret = atf_erase_nor(offset, size); + } else if ((argc == 2) && !strcmp(argv[1], "envcount")) { + ret = atf_env_count(); + printf("Number of environment strings: %zd\n", ret); + } else if ((argc == 3) && !strcmp(argv[1], "envstring")) { + index = simple_strtoul(argv[2], NULL, 10); + ret = atf_env_string(index, str); + if (ret > 0) + printf("Environment string %d: %s\n", index, str); + else + printf("Return code: %zd\n", ret); + } else if ((argc == 3) && !strcmp(argv[1], "dramsize")) { + node = simple_strtoul(argv[2], NULL, 10); + ret = atf_dram_size(node); + printf("DRAM size: %zd Mbytes\n", ret >> 20); + } else if ((argc == 2) && !strcmp(argv[1], "nodes")) { + ret = atf_node_count(); + printf("Nodes count: %zd\n", ret); + } else if ((argc == 2) && !strcmp(argv[1], "ver")) { + atf_print_ver(); + } else if ((argc == 2) && !strcmp(argv[1], "uid")) { + atf_print_uid(); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + atf, 10, 1, do_atf, + "issue calls to ATF", + "\t readmmc addr offset size - read MMC card\n" + "\t readnor addr offset size - read NOR flash\n" + "\t writemmc addr offset size - write MMC card\n" + "\t writenor addr offset size - write NOR flash\n" + "\t erasenor offset size - erase NOR flash\n" + "\t nodes - number of nodes\n" + "\t dramsize node - size of DRAM attached to node\n" + "\t envcount - number of environment strings\n" + "\t envstring index - print the environment string\n" + "\t part - print MMC partition table\n" + "\t ver - print ATF call set versions\n" +); + +#endif diff --git a/include/cavium/atf.h b/include/cavium/atf.h new file mode 100644 index 0000000..0a53c2f --- /dev/null +++ b/include/cavium/atf.h @@ -0,0 +1,22 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ +#ifndef __ATF_H__ +#define __ATF_H__ +#include <cavium/atf_part.h> + +ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size); +ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size); +ssize_t atf_get_pcount(void); +ssize_t atf_get_part(struct storage_partition *part, unsigned int index); +ssize_t atf_erase_nor(uintptr_t offset, size_t size); +ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size); +ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size); +ssize_t atf_dram_size(unsigned int node); +ssize_t atf_node_count(void); +ssize_t atf_env_count(void); +ssize_t atf_env_string(size_t index, char *str); + +#endif diff --git a/include/cavium/atf_part.h b/include/cavium/atf_part.h new file mode 100644 index 0000000..182f6f4 --- /dev/null +++ b/include/cavium/atf_part.h @@ -0,0 +1,26 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#ifndef __ATF_PART_H__ +#define __ATF_PART_H__ + +struct storage_partition { + unsigned int type; + unsigned int size; + unsigned long offset; +}; + +enum { + PARTITION_NBL1FW_REST = 0, + PARTITION_BL2_BL31 = 1, + PARTITION_UBOOT = 2, + PARTITION_UEFI = 2, + PARTITION_KERNEL = 3, + PARTITION_DEVICE_TREE = 4, + PARTITION_LAST, +}; + +#endif diff --git a/include/cavium/thunderx_svc.h b/include/cavium/thunderx_svc.h new file mode 100644 index 0000000..416ce3c --- /dev/null +++ b/include/cavium/thunderx_svc.h @@ -0,0 +1,67 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#ifndef __THUNDERX_SVC_H__ +#define __THUNDERX_SVC_H__ + +/* SMC function IDs for general purpose queries */ + +#define THUNDERX_SVC_CALL_COUNT 0x4300ff00 +#define THUNDERX_SVC_UID 0x4300ff01 + +#define THUNDERX_SVC_VERSION 0x4300ff03 + +#define ARM_STD_SVC_VERSION 0x8400ff03 + +/* ThunderX Service Calls version numbers */ +#define THUNDERX_VERSION_MAJOR 0x0 +#define THUNDERX_VERSION_MINOR 0x1 + +#define THUNDERX_MMC_READ 0x43000101 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_MMC_WRITE 0x43000102 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ + +#define THUNDERX_NOR_READ 0x43000111 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_NOR_WRITE 0x43000112 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_NOR_ERASE 0x43000113 +/* x1 - block address + */ + +#define THUNDERX_PART_COUNT 0x43000201 +#define THUNDERX_GET_PART 0x43000202 +/* x1 - pointer to the buffer + * x2 - index + */ + +#define THUNDERX_DRAM_SIZE 0x43000301 +/* x1 - node number + */ + +#define THUNDERX_GTI_SYNC 0x43000401 + +#define THUNDERX_ENV_COUNT 0x43000501 +#define THUNDERX_ENV_STRING 0x43000502 +/* x1 - index + */ + +#define THUNDERX_NODE_COUNT 0x43000601 + +#endif /* __THUNDERX_SVC_H__ */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 7b4cd9b..1416f4d 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -28,6 +28,8 @@
#define CONFIG_SYS_FULL_VA
+#define CONFIG_SYS_LOWMEM_BASE MEM_BASE + #define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ PTL2_MEMTYPE(MT_NORMAL) | \ PTL2_BLOCK_NON_SHARE}, \
On Wed, Oct 14, 2015 at 09:55:51AM -0700, Sergey Temerkhanov wrote:
This commit adds functions issuing calls to the product-specific ATF services
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Applied to u-boot/master, thanks!
Change the dram_init() function on ThunderX to query ATF services for the real installed DRAM size
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com ---
Changes in v7: None Changes in v6: None Changes in v5: - Moved dram_init() from a separate file to thunderx.c
Changes in v4: None Changes in v3: None Changes in v2: None
board/cavium/thunderx/thunderx.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index 486374e..b926767 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -9,6 +9,8 @@ #include <errno.h> #include <linux/compiler.h>
+#include <cavium/atf.h> + #if !CONFIG_IS_ENABLED(OF_CONTROL) #include <dm/platdata.h> #include <dm/platform_data/serial_pl01x.h> @@ -50,6 +52,31 @@ int timer_init(void) return 0; }
+int dram_init(void) +{ + ssize_t node_count = atf_node_count(); + ssize_t dram_size; + int node; + + printf("Initializing\nNodes in system: %zd\n", node_count); + + gd->ram_size = 0; + + for (node = 0; node < node_count; node++) { + dram_size = atf_dram_size(node); + printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20); + gd->ram_size += dram_size; + } + + gd->ram_size -= MEM_BASE; + + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + puts("DRAM size:"); + + return 0; +} + /* * Board specific reset that is system reset. */
On Wed, Oct 14, 2015 at 09:55:52AM -0700, Sergey Temerkhanov wrote:
Change the dram_init() function on ThunderX to query ATF services for the real installed DRAM size
Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com
Applied to u-boot/master, thanks!
participants (11)
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Dirk Behme -
Linus Walleij -
Mark Rutland -
Mateusz Kulikowski -
Michal Simek -
Rob Herring -
Rob Herring -
Sergei Temerkhanov -
Sergey Temerkhanov
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Simon Glass -
Tom Rini