The default cache operations defined in arch/arm/lib/cache.c do not perform any real cache operation, and instead a WARNING will be emitted.

Signed-off-by: Hong Xu hong.xu@atmel.com Tested-by: Elen Song elen.song@atmel.com CC: Albert Aribaud albert.u.boot@aribaud.net --- arch/arm/lib/cache.c | 55 ++++++++++++++++++++++++++++--------------------- 1 files changed, 31 insertions(+), 24 deletions(-)

diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 92b61a2..6af05ec 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -20,36 +20,43 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +#include <linux/compiler.h> +#include <common.h>

-/* for now: just dummy functions to satisfy the linker */ +#define EMIT_WARNING printf("WARNING: %s - CPU cache operation is not " \ +"implemented!\n", __func__)

-#include <common.h> +/* + * Default implementations + * + * Warn user if CPU code does not implement necessary cache functions + */ +void __weak flush_cache(unsigned long start, unsigned long size) +{ + EMIT_WARNING; +}

-void __flush_cache(unsigned long start, unsigned long size) +void __weak flush_dcache_all(void) { -#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136) - void arm1136_cache_flush(void); + EMIT_WARNING; +}

- arm1136_cache_flush(); -#endif -#ifdef CONFIG_ARM926EJS - /* test and clean, page 2-23 of arm926ejs manual */ - asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); - /* disable write buffer as well (page 2-22) */ - asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); -#endif - return; +void __weak flush_dcache_range(unsigned long start, unsigned long stop) +{ + EMIT_WARNING; } -void flush_cache(unsigned long start, unsigned long size) - __attribute__((weak, alias("__flush_cache")));

-/* - * Default implementation: - * do a range flush for the entire range - */ -void __flush_dcache_all(void) +void __weak invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + EMIT_WARNING; +} + +void __weak invalidate_dcache_all(void) +{ + EMIT_WARNING; +} + +void __weak invalidate_icache_all(void) { - flush_cache(0, ~0); + EMIT_WARNING; } -void flush_dcache_all(void) - __attribute__((weak, alias("__flush_dcache_all")));

arch/arm/lib/cache.c is cleaned and no real cache operation will be defined in this file. So a new file arch/arm/cpu/arm1136/cache.c is created. This file will define the real cache operations.

Signed-off-by: Hong Xu hong.xu@atmel.com Tested-by: Elen Song elen.song@atmel.com CC: Albert Aribaud albert.u.boot@aribaud.net CC: Aneesh V aneesh@ti.com CC: Marek Vasut marek.vasut@gmail.com CC: Reinhard Meyer u-boot@emk-elektronik.de CC: Heiko Schocher hs@denx.de --- arch/arm/cpu/arm1136/Makefile | 2 +- arch/arm/cpu/arm1136/cache.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/arm1136/cache.c

diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile index 930e0d1..5b5f330 100644 --- a/arch/arm/cpu/arm1136/Makefile +++ b/arch/arm/cpu/arm1136/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o

START = start.o -COBJS = cpu.o +COBJS = cpu.o cache.o

SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/arm1136/cache.c b/arch/arm/cpu/arm1136/cache.c new file mode 100644 index 0000000..02aa266 --- /dev/null +++ b/arch/arm/cpu/arm1136/cache.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +void flush_cache(unsigned long start, unsigned long size) +{ +#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136) + void arm1136_cache_flush(void); + + arm1136_cache_flush(); +#endif +}

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

Signed-off-by: Hong Xu hong.xu@atmel.com Tested-by: Elen Song elen.song@atmel.com CC: Albert Aribaud albert.u.boot@aribaud.net CC: Aneesh V aneesh@ti.com CC: Marek Vasut marek.vasut@gmail.com CC: Reinhard Meyer u-boot@emk-elektronik.de CC: Heiko Schocher hs@denx.de --- arch/arm/cpu/arm926ejs/Makefile | 2 +- arch/arm/cpu/arm926ejs/cache.c | 142 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/cache.c

diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 930e0d1..5b5f330 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o

START = start.o -COBJS = cpu.o +COBJS = cpu.o cache.o

SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c new file mode 100644 index 0000000..99a73c6 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#define FLUSH_CACHE_OP 0 +#define INVALIDATE_CACHE_OP 1 + +#ifndef CONFIG_SYS_DCACHE_OFF +/* + * Flush or Invalidate DCache respectively + */ +static void cache_range_op(unsigned long start, unsigned long stop, int op) +{ + int cache_line_len; + unsigned long mva; + char *func_name; + + if (op == FLUSH_CACHE_OP) + func_name = "flush_dcache_range"; + else if (op == INVALIDATE_CACHE_OP) + func_name = "invalidate_dcache_range"; + else { + printf("WARNING: %s - Invalid cache operation!\n", __func__); + return; + } + +#ifdef CONFIG_SYS_CACHELINE_SIZE + cache_line_len = CONFIG_SYS_CACHELINE_SIZE; +#else + /* + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9 + * only b'10, aka. 32 bytes cache line len is valid + */ + cache_line_len = 32; +#endif + mva = start; + if ((mva & (cache_line_len - 1)) != 0) { + printf("WARNING: %s - start address 0x%08x not aligned to" + "cache line size(%d bytes)\n", func_name, start, + cache_line_len); + /* Round up starting address */ + mva = (mva | (cache_line_len - 1)) + 1; + } + if ((stop & (cache_line_len - 1)) != 0) { + printf("WARNING: %s - stop address 0x%08x not aligned to" + "cache line size(%d bytes)\n", func_name, stop, + cache_line_len); + /* Round down ending address */ + stop &= ~(cache_line_len - 1); + } + + while (mva < stop) { + if (op == FLUSH_CACHE_OP) + asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva)); + else + asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva)); + + mva += cache_line_len; + } + + /* Drain WB if necessary */ + if (op == FLUSH_CACHE_OP) + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0)); +} + +/* + * The buffer range to be flushed is [start, stop) + */ +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + cache_range_op(start, stop, FLUSH_CACHE_OP); +} + +void flush_dcache_all(void) +{ + /* + * ARM926EJ-S Technical Reference Manual, Chap 2.3.8 + * Clean & Invalidate the entire DCache + */ + asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory"); + /* Drain WB */ + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0)); +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} + +/* + * The buffer range to be invalidated is [start, stop) + */ +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + cache_range_op(start, stop, INVALIDATE_CACHE_OP); +} + +void invalidate_dcache_all(void) +{ + asm("mcr p15, 0, %0, c7, c6, 0\n" : : "r" (0)); +} + +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ + +void flush_cache(unsigned long, unsigned long) {} +void flush_dcache_all(void) {} +void flush_dcache_range(unsigned long start, unsigned long stop) {} +void invalidate_dcache_range(unsigned long start, unsigned long stop) {} +void invalidate_dcache_all(void) {} +#endif + +#ifndef CONFIG_SYS_ICACHE_OFF +void invalidate_icache_all(void) +{ + asm("mcr p15, 0, %0, c7, c5, 0\n" : : "r" (0)); +} + +#else /* #ifndef CONFIG_SYS_ICACHE_OFF */ + +void invalidate_icache_all(void) {} +#endif